3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
6 * Juergen Beisert, EuroDesign embedded technologies, info@eurodsn.de
7 * Derived from walnut.c
10 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * Revision 1.1.5.1 2011-02-28 14:41:31 lothar
32 * imported Freescale specific U-Boot additions for i.MX28,... release L2.6.31_10.08.01
37 #include <asm/processor.h>
47 #define writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
48 #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
50 /* write only register to configure things in our CPLD */
51 #define CPLD_CONTROL_1 0x79000102
52 #define CPLD_VERSION 0x79000103
54 #define IS_CAMERON ((*(unsigned char *)(CPLD_VERSION)== 0x32) ? 1 : 0)
56 static struct pci_controller hose={0,};
58 /************************************************************
60 ************************************************************/
62 /* CPC0_CR0 Function ISA bus
64 - GPIO1 -> Output: NAND-Command Latch Enable
65 - GPIO2 -> Output: NAND Address Latch Enable
66 - GPIO3 -> IRQ input ISA-IRQ #5 (through CPLD)
67 - GPIO4 -> Output: NAND-Chip Enable
68 - GPIO5 -> IRQ input ISA-IRQ#7 (through CPLD)
69 - GPIO6 -> IRQ input ISA-IRQ#9 (through CPLD)
70 - GPIO7 -> IRQ input ISA-IRQ#10 (through CPLD)
71 - GPIO8 -> IRQ input ISA-IRQ#11 (through CPLD)
72 - GPIO9 -> IRQ input ISA-IRQ#12 (through CPLD)
73 - GPIO10/CS1# -> CS1# NAND ISA-CS#0
74 - GPIO11/CS2# -> CS2# ISA emulation ISA-CS#1
75 - GPIO12/CS3# -> CS3# 2nd Flash-Bank ISA-CS#2 or ISA-CS#7
76 - GPIO13/CS4# -> CS4# USB HC or ISA emulation ISA-CS#3
77 - GPIO14/CS5# -> CS5# Boosted IDE access ISA-CS#4
78 - GPIO15/CS6# -> CS6# ISA emulation ISA-CS#5
79 - GPIO16/CS7# -> CS7# ISA emulation ISA-CS#6
80 - GPIO17/IRQ0 -> GPIO, in, NAND-Ready/Busy# line ISA-IRQ#3
81 - GPIO18/IRQ1 -> IRQ input ISA-IRQ#14
82 - GPIO19/IRQ2 -> IRQ input or USB ISA-IRQ#4
83 - GPIO20/IRQ3 -> IRQ input PCI-IRQ#D
84 - GPIO21/IRQ4 -> IRQ input PCI-IRQ#C
85 - GPIO22/IRQ5 -> IRQ input PCI-IRQ#B
86 - GPIO23/IRQ6 -> IRQ input PCI-IRQ#A
87 - GPIO24 -> if GPIO output: 0=JTAG CPLD activ, 1=JTAG CPLD inactiv
90 | CPLD register: io-space at offset 0x102 (write only)
93 | 2 0=CS#4 USB CS#, 1=ISA or GP bus
97 | 6 1=enable faster IDE access
100 #define USB_CHIP_ENABLE 0x04
101 #define IDE_BOOSTING 0x40
103 /* --------------- USB stuff ------------------------------------- */
104 #ifdef CONFIG_ISP1161_PRESENT
106 * initUsbHost- Initialize the Philips isp1161 HC part if present
107 * @cpldConfig: Pointer to value in write only CPLD register
109 * Initialize the USB host controller if present and fills the
110 * scratch register to inform the driver about used resources
113 static void initUsbHost (unsigned char *cpldConfig)
116 unsigned long usbBase;
118 * Read back where init.S has located the USB chip
121 usbBase = mfdcr (0x013);
122 if (!(usbBase & 0x18000)) /* enabled? */
124 usbBase &= 0xFFF00000;
127 * to test for the USB controller enable using of CS#4 and DMA 3 for USB access
129 writeb (*cpldConfig | USB_CHIP_ENABLE,CPLD_CONTROL_1);
132 * first check: is the controller assembled?
134 hcWriteWord (usbBase, 0x5555, HcScratch);
135 if (hcReadWord (usbBase, HcScratch) == 0x5555) {
136 hcWriteWord (usbBase, 0xAAAA, HcScratch);
137 if (hcReadWord (usbBase, HcScratch) == 0xAAAA) {
138 if ((hcReadWord (usbBase, HcChipID) & 0xFF00) != 0x6100)
139 return; /* this is not our controller */
141 * try a software reset. This needs up to 10 seconds (see datasheet)
143 hcWriteDWord (usbBase, 0x00000001, HcCommandStatus);
144 for (i = 1000; i > 0; i--) { /* loop up to 10 seconds */
146 if (!(hcReadDWord (usbBase, HcCommandStatus) & 0x01))
151 return; /* the controller doesn't responding. Broken? */
153 * OK. USB controller is ready. Initialize it in such way the later driver
154 * can us it (without any knowing about specific implementation)
156 hcWriteDWord (usbBase, 0x00000000, HcControl);
158 * disable all interrupt sources. Because we
159 * don't know where we come from (hard reset, cold start, soft reset...)
161 hcWriteDWord (usbBase, 0x8000007D, HcInterruptDisable);
163 * our current setup hardware configuration
164 * - every port power supply can switched indepently
165 * - every port can signal overcurrent
166 * - every port is "outside" and the devices are removeable
168 hcWriteDWord (usbBase, 0x32000902, HcRhDescriptorA);
169 hcWriteDWord (usbBase, 0x00060000, HcRhDescriptorB);
171 * don't forget to switch off power supply of each port
172 * The later running driver can reenable them to find and use
173 * the (maybe) connected devices.
176 hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus1);
177 hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus2);
178 hcWriteWord (usbBase, 0x0428, HcHardwareConfiguration);
179 hcWriteWord (usbBase, 0x0040, HcDMAConfiguration);
180 hcWriteWord (usbBase, 0x0000, HcuPInterruptEnable);
181 hcWriteWord (usbBase, 0xA000 | (0x03 << 8) | 27, HcScratch);
183 * controller is present and usable
185 *cpldConfig |= USB_CHIP_ENABLE;
191 #if defined(CONFIG_START_IDE)
192 int board_start_ide(void)
195 puts ("no IDE on cameron board.\n");
202 static int sc3_cameron_init (void)
204 /* Set up the Memory Controller for the CAMERON version */
205 mtebc (pb4ap, 0x01805940);
206 mtebc (pb4cr, 0x7401a000);
207 mtebc (pb5ap, 0x01805940);
208 mtebc (pb5cr, 0x7401a000);
216 void sc3_read_eeprom (void)
218 uchar i2c_buffer[18];
220 i2c_read (0x50, 0x03, 1, i2c_buffer, 9);
222 setenv ("serial#", (char *)i2c_buffer);
224 /* read mac-address from eeprom */
225 i2c_read (0x50, 0x11, 1, i2c_buffer, 15);
227 i2c_buffer[16] = i2c_buffer[14];
228 i2c_buffer[15] = i2c_buffer[13];
229 i2c_buffer[14] = ':';
230 i2c_buffer[13] = i2c_buffer[12];
231 i2c_buffer[12] = i2c_buffer[11];
232 i2c_buffer[11] = ':';
236 setenv ("ethaddr", (char *)i2c_buffer);
239 int board_early_init_f (void)
241 /* write only register to configure things in our CPLD */
242 unsigned char cpldConfig_1=0x00;
244 /*-------------------------------------------------------------------------+
245 | Interrupt controller setup for the SolidCard III CPU card (plus Evaluation board).
247 | Note: IRQ 0 UART 0, active high; level sensitive
248 | IRQ 1 UART 1, active high; level sensitive
249 | IRQ 2 IIC, active high; level sensitive
250 | IRQ 3 Ext. master, rising edge, edge sensitive
251 | IRQ 4 PCI, active high; level sensitive
252 | IRQ 5 DMA Channel 0, active high; level sensitive
253 | IRQ 6 DMA Channel 1, active high; level sensitive
254 | IRQ 7 DMA Channel 2, active high; level sensitive
255 | IRQ 8 DMA Channel 3, active high; level sensitive
256 | IRQ 9 Ethernet Wakeup, active high; level sensitive
257 | IRQ 10 MAL System Error (SERR), active high; level sensitive
258 | IRQ 11 MAL Tx End of Buffer, active high; level sensitive
259 | IRQ 12 MAL Rx End of Buffer, active high; level sensitive
260 | IRQ 13 MAL Tx Descriptor Error, active high; level sensitive
261 | IRQ 14 MAL Rx Descriptor Error, active high; level sensitive
262 | IRQ 15 Ethernet, active high; level sensitive
263 | IRQ 16 External PCI SERR, active high; level sensitive
264 | IRQ 17 ECC Correctable Error, active high; level sensitive
265 | IRQ 18 PCI Power Management, active high; level sensitive
267 | IRQ 19 (EXT IRQ7 405GPr only)
268 | IRQ 20 (EXT IRQ8 405GPr only)
269 | IRQ 21 (EXT IRQ9 405GPr only)
270 | IRQ 22 (EXT IRQ10 405GPr only)
271 | IRQ 23 (EXT IRQ11 405GPr only)
272 | IRQ 24 (EXT IRQ12 405GPr only)
274 | IRQ 25 (EXT IRQ 0) NAND-Flash R/B# (raising edge means flash is ready)
275 | IRQ 26 (EXT IRQ 1) IDE0 interrupt (x86 = IRQ14). Active high (edge sensitive)
276 | IRQ 27 (EXT IRQ 2) USB controller
277 | IRQ 28 (EXT IRQ 3) INT D, VGA; active low; level sensitive
278 | IRQ 29 (EXT IRQ 4) INT C, Ethernet; active low; level sensitive
279 | IRQ 30 (EXT IRQ 5) INT B, PC104+ SLOT; active low; level sensitive
280 | IRQ 31 (EXT IRQ 6) INT A, PC104+ SLOT; active low; level sensitive
282 | Direct Memory Access Controller Signal Polarities
283 | DRQ0 active high (like ISA)
284 | ACK0 active low (like ISA)
285 | EOT0 active high (like ISA)
286 | DRQ1 active high (like ISA)
287 | ACK1 active low (like ISA)
288 | EOT1 active high (like ISA)
289 | DRQ2 active high (like ISA)
290 | ACK2 active low (like ISA)
291 | EOT2 active high (like ISA)
292 | DRQ3 active high (like ISA)
293 | ACK3 active low (like ISA)
294 | EOT3 active high (like ISA)
296 +-------------------------------------------------------------------------*/
298 writeb (cpldConfig_1, CPLD_CONTROL_1); /* disable everything in CPLD */
300 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
301 mtdcr (uicer, 0x00000000); /* disable all ints */
302 mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
306 mtdcr (0x0B6, 0x18000000);
307 mtdcr (uicpr, 0xFFFFFFF0);
308 mtdcr (uictr, 0x10001030);
310 mtdcr (0x0B6, 0x0000000);
311 mtdcr (uicpr, 0xFFFFFFE0);
312 mtdcr (uictr, 0x10000020);
314 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
315 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
317 /* setup other implementation specific details */
318 mtdcr (ecr, 0x60606000);
320 mtdcr (cntrl1, 0x000042C0);
323 mtdcr (cntrl0, 0x01380000);
324 /* Setup the GPIOs */
325 writel (0x08008000, 0xEF600700); /* Output states */
326 writel (0x00000000, 0xEF600718); /* Open Drain control */
327 writel (0x68098000, 0xEF600704); /* Output control */
329 mtdcr (cntrl0,0x00080000);
330 /* Setup the GPIOs */
331 writel (0x08000000, 0xEF600700); /* Output states */
332 writel (0x14000000, 0xEF600718); /* Open Drain control */
333 writel (0x7C000000, 0xEF600704); /* Output control */
336 /* Code decompression disabled */
340 /* CPC0_ER: enable sleep mode of (currently) unused components */
341 /* CPC0_FR: force unused components into sleep mode */
342 mtdcr (cpmer, 0x3F800000);
343 mtdcr (cpmfr, 0x14000000);
345 /* set PLB priority */
346 mtdcr (0x87, 0x08000000);
348 /* --------------- DMA stuff ------------------------------------- */
349 mtdcr (0x126, 0x49200000);
351 #ifndef IDE_USES_ISA_EMULATION
352 cpldConfig_1 |= IDE_BOOSTING; /* enable faster IDE */
353 /* cpldConfig |= 0x01; */ /* enable 8.33MHz output, if *not* present on your baseboard */
354 writeb (cpldConfig_1, CPLD_CONTROL_1);
357 #ifdef CONFIG_ISP1161_PRESENT
358 initUsbHost (&cpldConfig_1);
359 writeb (cpldConfig_1, CPLD_CONTROL_1);
361 /* FIXME: for what must we do this */
362 *(unsigned long *)0x79000080 = 0x0001;
366 int misc_init_r (void)
370 volatile char *xilinx_adr;
371 xilinx_adr = (char *)0x79000102;
375 /* customer settings ***************************************** */
377 s1 = getenv ("function");
379 if (!strcmp (s1, "Rosho")) {
380 printf ("function 'Rosho' activated\n");
384 printf (">>>>>>>>>> function %s not recognized\n",s1);
389 /* individual settings ***************************************** */
390 if ((s1 = getenv ("xilinx"))) {
393 while (i < 3 && s1[i]) {
394 if (s1[i] >= '0' && s1[i] <= '9')
395 xilinx_val = (xilinx_val << 4) + s1[i] - '0';
397 if (s1[i] >= 'A' && s1[i] <= 'F')
398 xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10;
400 if (s1[i] >= 'a' && s1[i] <= 'f')
401 xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10;
408 if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) {
409 printf ("Xilinx: set to %s\n", s1);
410 *xilinx_adr = (unsigned char) xilinx_val;
412 printf ("Xilinx: rejected value %s\n", s1);
417 /* -------------------------------------------------------------------------
420 * Print some informations about chips select configurations
421 * Only used while debugging.
430 ------------------------------------------------------------------------- */
433 static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
435 const char *bsize[4] = {"8","16","32","?"};
436 const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128};
437 const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"};
439 #define CYCLE 30 /* time of one clock (based on 33MHz) */
441 printf("\nCS#%d",reg);
442 if (!(cr & 0x00018000))
445 if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20)))
446 puts(" Address is not multiple of bank size!");
448 printf("\n -%s bit device",
449 bsize[(cr & 0x00006000) >> 13]);
450 printf(" at 0x%08lX", cr & 0xFFF00000U);
451 printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]);
452 printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]);
453 if (ap & 0x80000000) {
454 printf("\n -Burst device (%luns/%luns)",
455 (((ap & 0x7C000000) >> 26) + 1) * CYCLE,
456 (((ap & 0x03800000) >> 23) + 1) * CYCLE);
458 printf("\n -Non burst device, active cycle %luns",
459 (((ap & 0x7F800000) >> 23) + 1) * CYCLE);
460 printf("\n -Address setup %luns",
461 ((ap & 0xC0000) >> 18) * CYCLE);
462 printf("\n -CS active to RD %luns/WR %luns",
463 ((ap & 0x30000) >> 16) * CYCLE,
464 ((ap & 0xC000) >> 14) * CYCLE);
465 printf("\n -WR to CS inactive %luns",
466 ((ap & 0x3000) >> 12) * CYCLE);
467 printf("\n -Hold after access %luns",
468 ((ap & 0xE00) >> 9) * CYCLE);
469 printf("\n -Ready is %sabled",
470 ap & 0x100 ? "en" : "dis");
478 static unsigned int ap[] = {pb0ap, pb1ap, pb2ap, pb3ap, pb4ap,
479 pb5ap, pb6ap, pb7ap};
480 static unsigned int cr[] = {pb0cr, pb1cr, pb2cr, pb3cr, pb4cr,
481 pb5cr, pb6cr, pb7cr};
483 static int show_reg (int nr)
485 unsigned long ul1, ul2;
487 mtdcr (ebccfga, ap[nr]);
488 ul1 = mfdcr (ebccfgd);
489 mtdcr (ebccfga, cr[nr]);
490 ul2 = mfdcr(ebccfgd);
491 printCSConfig(nr, ul1, ul2);
496 int checkboard (void)
502 for (i = 0; i < 8; i++) {
506 mtdcr (ebccfga, epcr);
507 ul1 = mfdcr (ebccfgd);
509 puts ("\nGeneral configuration:\n");
511 if (ul1 & 0x80000000)
512 printf(" -External Bus is always driven\n");
515 printf(" -CS signals are always driven\n");
518 printf(" -PowerDown after %lu clocks\n",
519 (ul1 & 0x1F000) >> 7);
521 switch (ul1 & 0xC0000)
524 printf(" -No external master present\n");
527 printf(" -8 bit external master present\n");
530 printf(" -16 bit external master present\n");
533 printf(" -32 bit external master present\n");
537 switch (ul1 & 0x300000)
540 printf(" -Prefetch: Illegal setting!\n");
543 printf(" -1 doubleword prefetch\n");
546 printf(" -2 doublewords prefetch\n");
549 printf(" -4 doublewords prefetch\n");
554 printf("Board: SolidCard III %s %s version.\n",
555 (IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION);
559 static int printSDRAMConfig(char reg, unsigned long cr)
561 const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0};
563 const char *basize[8]=
564 {"4", "8", "16", "32", "64", "128", "256", "Reserved"};
566 printf("SDRAM bank %d",reg);
571 printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]);
572 printf(" mode %lu\n",((cr & 0xE000)>>13)+1);
577 return(bisize[(cr & 0xE0000) >> 17]);
583 static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf};
586 phys_size_t initdram (int board_type)
595 puts("\nSDRAM configuration:\n");
597 mtdcr (memcfga, mem_mcopt1);
598 ul1 = mfdcr(memcfgd);
600 if (!(ul1 & 0x80000000)) {
601 puts(" Controller disabled\n");
604 for (i = 0; i < 4; i++) {
605 mtdcr (memcfga, mbcf[i]);
606 ul1 = mfdcr (memcfgd);
607 mems += printSDRAMConfig (i, ul1);
610 mtdcr (memcfga, mem_sdtr1);
611 ul1 = mfdcr(memcfgd);
613 printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
614 printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
615 printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1);
616 printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1);
617 printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
618 printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
620 mtdcr (memcfga, mem_rtr);
621 ul1 = mfdcr(memcfgd);
622 printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
624 mtdcr(memcfga,mem_pmit);
627 mtdcr(memcfga,mem_mcopt1);
630 if (ul1 & 0x20000000)
631 printf(" -Power Down after: %luns\n",
632 ((ul2 & 0xFFC00000) >> 22) * 7);
634 puts(" -Power Down disabled\n");
636 if (ul1 & 0x40000000)
637 printf(" -Self refresh feature active\n");
639 puts(" -Self refresh disabled\n");
641 if (ul1 & 0x10000000)
642 puts(" -ECC enabled\n");
644 puts(" -ECC disabled\n");
647 puts(" -Using registered SDRAM\n");
649 if (!(ul1 & 0x6000000))
650 puts(" -Using 32 bit data width\n");
652 puts(" -Illegal data width!\n");
655 puts(" -ECC drivers inactive\n");
657 puts(" -ECC drivers active\n");
660 puts(" -Memory lines always active outputs\n");
662 puts(" -Memory lines only at write cycles active outputs\n");
664 mtdcr (memcfga, mem_status);
665 ul1 = mfdcr (memcfgd);
666 if (ul1 & 0x80000000)
667 puts(" -SDRAM Controller ready\n");
669 puts(" -SDRAM Controller not ready\n");
672 puts(" -SDRAM in self refresh mode!\n");
674 return (mems * 1024 * 1024);
676 mtdcr (memcfga, mem_mb0cf);
677 ul1 = mfdcr (memcfgd);
678 mems = printSDRAMConfig (0, ul1);
680 mtdcr (memcfga, mem_mb1cf);
681 ul1 = mfdcr (memcfgd);
682 mems += printSDRAMConfig (1, ul1);
684 mtdcr (memcfga, mem_mb2cf);
685 ul1 = mfdcr(memcfgd);
686 mems += printSDRAMConfig (2, ul1);
688 mtdcr (memcfga, mem_mb3cf);
689 ul1 = mfdcr(memcfgd);
690 mems += printSDRAMConfig (3, ul1);
692 return (mems * 1024 * 1024);
696 static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
698 /*-------------------------------------------------------------------------+
699 | ,-. ,-. ,-. ,-. ,-.
700 | INTD# ----|B|-----|P|-. ,-|P|-. ,-| |-. ,-|G|
701 | |R| |C| \ / |C| \ / |E| \ / |r|
702 | INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a|
703 | |D| |0| \/ |0| \/ |h| \/ |f|
704 | INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i|
705 | |E| |+| /\ |+| /\ |r| /\ |k|
706 | INTA# ----| |-----| |- `----| |- `----| |- `----| |
707 | `-' `-' `-' `-' `-'
711 +-------------------------------------------------------------------------*/
712 unsigned char int_line = 0xff;
714 switch (PCI_DEV(dev)) {
716 int_line = 31; /* INT A */
721 int_line = 30; /* INT B */
726 int_line = 29; /* INT C */
731 int_line = 28; /* INT D */
735 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
738 extern void pci_405gp_init(struct pci_controller *hose);
739 extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
740 extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry);
742 * The following table is used when there is a special need to setup a PCI device.
743 * For every PCI device found in this table is called the given init function with given
744 * parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same
748 static struct pci_config_table pci_solidcard3_config_table[] =
750 /* Host to PCI Bridge device (405GP) */
754 class: PCI_CLASS_BRIDGE_HOST,
758 config_device: pci_405gp_setup_bridge
763 /*-------------------------------------------------------------------------+
764 | pci_init_board (Called from pci_init() in drivers/pci/pci.c)
766 | Init the PCI part of the SolidCard III
769 * - Pointer to current PCI hose
774 +-------------------------------------------------------------------------*/
776 void pci_init_board(void)
780 * we want the ptrs to RAM not flash (ie don't use init list)
782 hose.fixup_irq = pci_solidcard3_fixup_irq;
783 hose.config_table = pci_solidcard3_config_table;
784 pci_405gp_init(&hose);
787 int board_eth_init(bd_t *bis)
789 return pci_eth_init(bis);