board/siemens/pxm2/board.c

   1 /*
   2  * Board functions for TI AM335X based pxm2 board
   3  * (C) Copyright 2013 Siemens Schweiz AG
   4  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * u-boot:/board/ti/am335x/board.c
   8  *
   9  * Board functions for TI AM335X based boards
  10  *
  11  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <errno.h>
  18 #include <spl.h>
  19 #include <asm/arch/cpu.h>
  20 #include <asm/arch/hardware.h>
  21 #include <asm/arch/omap.h>
  22 #include <asm/arch/ddr_defs.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/mmc_host_def.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include "../../../drivers/video/da8xx-fb.h"
  28 #include <asm/io.h>
  29 #include <asm/emif.h>
  30 #include <asm/gpio.h>
  31 #include <i2c.h>
  32 #include <miiphy.h>
  33 #include <cpsw.h>
  34 #include <watchdog.h>
  35 #include "board.h"
  36 #include "../common/factoryset.h"
  37 #include "pmic.h"
  38 #include <nand.h>
  39 #include <bmp_layout.h>
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #ifdef CONFIG_SPL_BUILD
  44 static void board_init_ddr(void)
  45 {
  46 struct emif_regs pxm2_ddr3_emif_reg_data = {
  47         .sdram_config = 0x41805332,
  48         .sdram_tim1 = 0x666b3c9,
  49         .sdram_tim2 = 0x243631ca,
  50         .sdram_tim3 = 0x33f,
  51         .emif_ddr_phy_ctlr_1 = 0x100005,
  52         .zq_config = 0,
  53         .ref_ctrl = 0x81a,
  54 };
  55
  56 struct ddr_data pxm2_ddr3_data = {
  57         .datardsratio0 = 0x81204812,
  58         .datawdsratio0 = 0,
  59         .datafwsratio0 = 0x8020080,
  60         .datawrsratio0 = 0x4010040,
  61 };
  62
  63 struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
  64         .cmd0csratio = 0x80,
  65         .cmd0iclkout = 0,
  66         .cmd1csratio = 0x80,
  67         .cmd1iclkout = 0,
  68         .cmd2csratio = 0x80,
  69         .cmd2iclkout = 0,
  70 };
  71
  72         config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
  73                    &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
  74 }
  75
  76 /*
  77  * voltage switching for MPU frequency switching.
  78  * @module = mpu - 0, core - 1
  79  * @vddx_op_vol_sel = vdd voltage to set
  80  */
  81
  82 #define MPU     0
  83 #define CORE    1
  84
  85 int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
  86 {
  87         uchar buf[4];
  88         unsigned int reg_offset;
  89
  90         if (module == MPU)
  91                 reg_offset = PMIC_VDD1_OP_REG;
  92         else
  93                 reg_offset = PMIC_VDD2_OP_REG;
  94
  95         /* Select VDDx OP   */
  96         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
  97                 return 1;
  98
  99         buf[0] &= ~PMIC_OP_REG_CMD_MASK;
 100
 101         if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 102                 return 1;
 103
 104         /* Configure VDDx OP  Voltage */
 105         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 106                 return 1;
 107
 108         buf[0] &= ~PMIC_OP_REG_SEL_MASK;
 109         buf[0] |= vddx_op_vol_sel;
 110
 111         if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 112                 return 1;
 113
 114         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 115                 return 1;
 116
 117         if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
 118                 return 1;
 119
 120         return 0;
 121 }
 122
 123 #define OSC     (V_OSCK/1000000)
 124
 125 const struct dpll_params dpll_mpu_pxm2 = {
 126                 720, OSC-1, 1, -1, -1, -1, -1};
 127
 128 void spl_siemens_board_init(void)
 129 {
 130         uchar buf[4];
 131         /*
 132          * pxm2 PMIC code.  All boards currently want an MPU voltage
 133          * of 1.2625V and CORE voltage of 1.1375V to operate at
 134          * 720MHz.
 135          */
 136         if (i2c_probe(PMIC_CTRL_I2C_ADDR))
 137                 return;
 138
 139         /* VDD1/2 voltage selection register access by control i/f */
 140         if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
 141                 return;
 142
 143         buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
 144
 145         if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
 146                 return;
 147
 148         /* Frequency switching for OPP 120 */
 149         if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
 150             voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
 151                 printf("voltage update failed\n");
 152         }
 153 }
 154 #endif /* if def CONFIG_SPL_BUILD */
 155
 156 int read_eeprom(void)
 157 {
 158         /* nothing ToDo here for this board */
 159
 160         return 0;
 161 }
 162
 163 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 164         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 165 static void cpsw_control(int enabled)
 166 {
 167         /* VTP can be added here */
 168
 169         return;
 170 }
 171
 172 static struct cpsw_slave_data cpsw_slaves[] = {
 173         {
 174                 .slave_reg_ofs  = 0x208,
 175                 .sliver_reg_ofs = 0xd80,
 176                 .phy_id         = 0,
 177                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 178         },
 179         {
 180                 .slave_reg_ofs  = 0x308,
 181                 .sliver_reg_ofs = 0xdc0,
 182                 .phy_id         = 1,
 183                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 184         },
 185 };
 186
 187 static struct cpsw_platform_data cpsw_data = {
 188         .mdio_base              = CPSW_MDIO_BASE,
 189         .cpsw_base              = CPSW_BASE,
 190         .mdio_div               = 0xff,
 191         .channels               = 4,
 192         .cpdma_reg_ofs          = 0x800,
 193         .slaves                 = 1,
 194         .slave_data             = cpsw_slaves,
 195         .ale_reg_ofs            = 0xd00,
 196         .ale_entries            = 1024,
 197         .host_port_reg_ofs      = 0x108,
 198         .hw_stats_reg_ofs       = 0x900,
 199         .bd_ram_ofs             = 0x2000,
 200         .mac_control            = (1 << 5),
 201         .control                = cpsw_control,
 202         .host_port_num          = 0,
 203         .version                = CPSW_CTRL_VERSION_2,
 204 };
 205 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 206
 207 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 208         (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
 209 int board_eth_init(bd_t *bis)
 210 {
 211         int n = 0;
 212 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 213         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 214         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 215 #ifdef CONFIG_FACTORYSET
 216         int rv;
 217         if (!is_valid_ether_addr(factory_dat.mac))
 218                 printf("Error: no valid mac address\n");
 219         else
 220                 eth_setenv_enetaddr("ethaddr", factory_dat.mac);
 221 #endif /* #ifdef CONFIG_FACTORYSET */
 222
 223         /* Set rgmii mode and enable rmii clock to be sourced from chip */
 224         writel(RGMII_MODE_ENABLE , &cdev->miisel);
 225
 226         rv = cpsw_register(&cpsw_data);
 227         if (rv < 0)
 228                 printf("Error %d registering CPSW switch\n", rv);
 229         else
 230                 n += rv;
 231 #endif
 232         return n;
 233 }
 234 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 235
 236 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
 237 static struct da8xx_panel lcd_panels[] = {
 238         /* AUO G156XW01 V1 */
 239         [0] = {
 240                 .name = "AUO_G156XW01_V1",
 241                 .width = 1376,
 242                 .height = 768,
 243                 .hfp = 14,
 244                 .hbp = 64,
 245                 .hsw = 56,
 246                 .vfp = 1,
 247                 .vbp = 28,
 248                 .vsw = 3,
 249                 .pxl_clk = 60000000,
 250                 .invert_pxl_clk = 0,
 251         },
 252         /* AUO B101EVN06 V0 */
 253         [1] = {
 254                 .name = "AUO_B101EVN06_V0",
 255                 .width = 1280,
 256                 .height = 800,
 257                 .hfp = 52,
 258                 .hbp = 84,
 259                 .hsw = 36,
 260                 .vfp = 3,
 261                 .vbp = 14,
 262                 .vsw = 6,
 263                 .pxl_clk = 60000000,
 264                 .invert_pxl_clk = 0,
 265         },
 266         /*
 267          * Settings from factoryset
 268          * stored in EEPROM
 269          */
 270         [2] = {
 271                 .name = "factoryset",
 272                 .width = 0,
 273                 .height = 0,
 274                 .hfp = 0,
 275                 .hbp = 0,
 276                 .hsw = 0,
 277                 .vfp = 0,
 278                 .vbp = 0,
 279                 .vsw = 0,
 280                 .pxl_clk = 60000000,
 281                 .invert_pxl_clk = 0,
 282         },
 283 };
 284
 285 static const struct display_panel disp_panel = {
 286         WVGA,
 287         32,
 288         16,
 289         COLOR_ACTIVE,
 290 };
 291
 292 static const struct lcd_ctrl_config lcd_cfg = {
 293         &disp_panel,
 294         .ac_bias                = 255,
 295         .ac_bias_intrpt         = 0,
 296         .dma_burst_sz           = 16,
 297         .bpp                    = 32,
 298         .fdd                    = 0x80,
 299         .tft_alt_mode           = 0,
 300         .stn_565_mode           = 0,
 301         .mono_8bit_mode         = 0,
 302         .invert_line_clock      = 1,
 303         .invert_frm_clock       = 1,
 304         .sync_edge              = 0,
 305         .sync_ctrl              = 1,
 306         .raster_order           = 0,
 307 };
 308
 309 static int set_gpio(int gpio, int state)
 310 {
 311         gpio_request(gpio, "temp");
 312         gpio_direction_output(gpio, state);
 313         gpio_set_value(gpio, state);
 314         gpio_free(gpio);
 315         return 0;
 316 }
 317
 318 static int enable_backlight(void)
 319 {
 320         set_gpio(BOARD_LCD_POWER, 1);
 321         set_gpio(BOARD_BACK_LIGHT, 1);
 322         set_gpio(BOARD_TOUCH_POWER, 1);
 323         return 0;
 324 }
 325
 326 static int enable_pwm(void)
 327 {
 328         struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
 329         struct pwmss_ecap_regs *ecap;
 330         int ticks = PWM_TICKS;
 331         int duty = PWM_DUTY;
 332
 333         ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
 334         /* enable clock */
 335         setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
 336         /* TimeStam Counter register */
 337         writel(0xdb9, &ecap->tsctr);
 338         /* config period */
 339         writel(ticks - 1, &ecap->cap3);
 340         writel(ticks - 1, &ecap->cap1);
 341         setbits_le16(&ecap->ecctl2,
 342                      (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
 343         /* config duty */
 344         writel(duty, &ecap->cap2);
 345         writel(duty, &ecap->cap4);
 346         /* start */
 347         setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
 348         return 0;
 349 }
 350
 351 static struct dpll_regs dpll_lcd_regs = {
 352         .cm_clkmode_dpll = CM_WKUP + 0x98,
 353         .cm_idlest_dpll = CM_WKUP + 0x48,
 354         .cm_clksel_dpll = CM_WKUP + 0x54,
 355 };
 356
 357 /* no console on this board */
 358 int board_cfb_skip(void)
 359 {
 360         return 1;
 361 }
 362
 363 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
 364 #define PLL_GET_N(v) (v & 0x7f)
 365
 366 static int get_clk(struct dpll_regs *dpll_regs)
 367 {
 368         unsigned int val;
 369         unsigned int m, n;
 370         int f = 0;
 371
 372         val = readl(dpll_regs->cm_clksel_dpll);
 373         m = PLL_GET_M(val);
 374         n = PLL_GET_N(val);
 375         f = (m * V_OSCK) / n;
 376
 377         return f;
 378 };
 379
 380 int clk_get(int clk)
 381 {
 382         return get_clk(&dpll_lcd_regs);
 383 };
 384
 385 static int conf_disp_pll(int m, int n)
 386 {
 387         struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 388         struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
 389         struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
 390
 391         u32 *const clk_domains[] = {
 392                 &cmper->lcdclkctrl,
 393                 0
 394         };
 395         u32 *const clk_modules_explicit_en[] = {
 396                 &cmper->lcdclkctrl,
 397                 &cmper->lcdcclkstctrl,
 398                 &cmper->epwmss0clkctrl,
 399                 0
 400         };
 401         do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 402         writel(0x0, &cmdpll->clklcdcpixelclk);
 403
 404         do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
 405
 406         return 0;
 407 }
 408
 409 static int board_video_init(void)
 410 {
 411         conf_disp_pll(24, 1);
 412         if (factory_dat.pxm50)
 413                 da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
 414         else
 415                 da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
 416
 417         enable_pwm();
 418         enable_backlight();
 419
 420         return 0;
 421 }
 422 #endif
 423 #include "../common/board.c"