board/stxgp3/init.S

   1 /*
   2  * Copyright (C) 2004 Embedded Edge, LLC
   3  * Dan Malek <dan@embeddededge.com>
   4  * Copied from ADS85xx.
   5  * Updates for Silicon Tx GP3 8560.  We only support 32-bit flash
   6  * and DDR with SPD EEPROM configuration.
   7  *
   8  * Copyright 2004 Freescale Semiconductor.
   9  * Copyright (C) 2002,2003, Motorola Inc.
  10  * Xianghua Xiao <X.Xiao@motorola.com>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <ppc_asm.tmpl>
  32 #include <ppc_defs.h>
  33 #include <asm/cache.h>
  34 #include <asm/mmu.h>
  35 #include <config.h>
  36 #include <mpc85xx.h>
  37
  38
  39 /*
  40  * TLB0 and TLB1 Entries
  41  *
  42  * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
  43  * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
  44  * these TLB entries are established.
  45  *
  46  * The TLB entries for DDR are dynamically setup in spd_sdram()
  47  * and use TLB1 Entries 8 through 15 as needed according to the
  48  * size of DDR memory.
  49  *
  50  * MAS0: tlbsel, esel, nv
  51  * MAS1: valid, iprot, tid, ts, tsize
  52  * MAS2: epn, sharen, x0, x1, w, i, m, g, e
  53  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  54  */
  55
  56 #define entry_start \
  57         mflr    r1      ;       \
  58         bl      0f      ;
  59
  60 #define entry_end \
  61 0:      mflr    r0      ;       \
  62         mtlr    r1      ;       \
  63         blr             ;
  64
  65
  66         .section        .bootpg, "ax"
  67         .globl  tlb1_entry
  68 tlb1_entry:
  69         entry_start
  70
  71         /*
  72          * Number of TLB0 and TLB1 entries in the following table
  73          */
  74         .long 13
  75
  76 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
  77         /*
  78          * TLB0         4K      Non-cacheable, guarded
  79          * 0xff700000   4K      Initial CCSRBAR mapping
  80          *
  81          * This ends up at a TLB0 Index==0 entry, and must not collide
  82          * with other TLB0 Entries.
  83          */
  84         .long TLB1_MAS0(0, 0, 0)
  85         .long TLB1_MAS1(1, 0, 0, 0, 0)
  86         .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
  87         .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
  88 #else
  89 #error("Update the number of table entries in tlb1_entry")
  90 #endif
  91
  92         /*
  93          * TLB0         16K     Cacheable, non-guarded
  94          * 0xd001_0000  16K     Temporary Global data for initialization
  95          *
  96          * Use four 4K TLB0 entries.  These entries must be cacheable
  97          * as they provide the bootstrap memory before the memory
  98          * controler and real memory have been configured.
  99          *
 100          * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
 101          * and must not collide with other TLB0 entries.
 102          */
 103         .long TLB1_MAS0(0, 0, 0)
 104         .long TLB1_MAS1(1, 0, 0, 0, 0)
 105         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \
 106                         0,0,0,0,0,0,0,0)
 107         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \
 108                         0,0,0,0,0,1,0,1,0,1)
 109
 110         .long TLB1_MAS0(0, 0, 0)
 111         .long TLB1_MAS1(1, 0, 0, 0, 0)
 112         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
 113                         0,0,0,0,0,0,0,0)
 114         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
 115                         0,0,0,0,0,1,0,1,0,1)
 116
 117         .long TLB1_MAS0(0, 0, 0)
 118         .long TLB1_MAS1(1, 0, 0, 0, 0)
 119         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
 120                         0,0,0,0,0,0,0,0)
 121         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
 122                         0,0,0,0,0,1,0,1,0,1)
 123
 124         .long TLB1_MAS0(0, 0, 0)
 125         .long TLB1_MAS1(1, 0, 0, 0, 0)
 126         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
 127                         0,0,0,0,0,0,0,0)
 128         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
 129                         0,0,0,0,0,1,0,1,0,1)
 130
 131
 132         /*
 133          * TLB 0:       16M     Non-cacheable, guarded
 134          * 0xff000000   16M     FLASH
 135          * Out of reset this entry is only 4K.
 136          */
 137         .long TLB1_MAS0(1, 0, 0)
 138         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
 139         .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
 140         .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
 141
 142         /*
 143          * TLB 1:       256M    Non-cacheable, guarded
 144          * 0x80000000   256M    PCI1 MEM First half
 145          */
 146         .long TLB1_MAS0(1, 1, 0)
 147         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 148         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
 149         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
 150
 151         /*
 152          * TLB 2:       256M    Non-cacheable, guarded
 153          * 0x90000000   256M    PCI1 MEM Second half
 154          */
 155         .long TLB1_MAS0(1, 2, 0)
 156         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 157         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \
 158                         0,0,0,0,1,0,1,0)
 159         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \
 160                         0,0,0,0,0,1,0,1,0,1)
 161
 162         /*
 163          * TLB 3:       256M    Non-cacheable, guarded
 164          * 0xc0000000   256M    Rapid IO MEM First half
 165          */
 166         .long TLB1_MAS0(1, 3, 0)
 167         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 168         .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
 169         .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
 170
 171         /*
 172          * TLB 4:       256M    Non-cacheable, guarded
 173          * 0xd0000000   256M    Rapid IO MEM Second half
 174          */
 175         .long TLB1_MAS0(1, 4, 0)
 176         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 177         .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), \
 178                         0,0,0,0,1,0,1,0)
 179         .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), \
 180                         0,0,0,0,0,1,0,1,0,1)
 181
 182         /*
 183          * TLB 5:       64M     Non-cacheable, guarded
 184          * 0xe000_0000  1M      CCSRBAR
 185          * 0xe200_0000  16M     PCI1 IO
 186          */
 187         .long TLB1_MAS0(1, 5, 0)
 188         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 189         .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
 190         .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
 191
 192         /*
 193          * TLB 6:       64M     Cacheable, non-guarded
 194          * 0xf000_0000  64M     LBC SDRAM
 195          */
 196         .long TLB1_MAS0(1, 6, 0)
 197         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 198         .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
 199         .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
 200
 201         /*
 202          * TLB 7:       16K     Non-cacheable, guarded
 203          * 0xfc000000   16K     Configuration Latch register
 204          */
 205         .long TLB1_MAS0(1, 7, 0)
 206         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K)
 207         .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,1,0,1,0)
 208         .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,0,1,0,1,0,1)
 209
 210 #if !defined(CONFIG_SPD_EEPROM)
 211         /*
 212          * TLB 8, 9:    128M    DDR
 213          * 0x00000000   64M     DDR System memory
 214          * 0x04000000   64M     DDR System memory
 215          * Without SPD EEPROM configured DDR, this must be setup manually.
 216          * Make sure the TLB count at the top of this table is correct.
 217          * Likely it needs to be increased by two for these entries.
 218          */
 219 #error("Update the number of table entries in tlb1_entry")
 220         .long TLB1_MAS0(1, 8, 0)
 221         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 222         .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
 223         .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
 224
 225         .long TLB1_MAS0(1, 9, 0)
 226         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 227         .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
 228                         0,0,0,0,0,0,0,0)
 229         .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
 230                         0,0,0,0,0,1,0,1,0,1)
 231 #endif
 232
 233         entry_end
 234
 235 /*
 236  * LAW(Local Access Window) configuration:
 237  *
 238  * 0x0000_0000     0x7fff_ffff     DDR                     2G
 239  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
 240  * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
 241  * 0xe000_0000     0xe000_ffff     CCSR                    1M
 242  * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
 243  * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
 244  * 0xfc00_0000     0xfc00_ffff     Config Latch            64K
 245  * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
 246  *
 247  * Notes:
 248  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
 249  *    If flash is 8M at default position (last 8M), no LAW needed.
 250  */
 251
 252 #if !defined(CONFIG_SPD_EEPROM)
 253 #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
 254 #define LAWAR0  (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
 255 #else
 256 #define LAWBAR0 0
 257 #define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
 258 #endif
 259
 260 #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
 261 #define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
 262
 263 /*
 264  * This is not so much the SDRAM map as it is the whole localbus map.
 265  */
 266 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
 267 #define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
 268
 269 #define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
 270 #define LAWAR3  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
 271
 272 /*
 273  * Rapid IO at 0xc000_0000 for 512 M
 274  */
 275 #define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
 276 #define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
 277
 278
 279         .section .bootpg, "ax"
 280         .globl  law_entry
 281 law_entry:
 282         entry_start
 283         .long 0x05
 284         .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
 285         .long LAWBAR4,LAWAR4
 286         entry_end