3 # Note only one of these may be selected at a time! But hidden choices are
4 # not supported by Kconfig
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
11 config SUNXI_GEN_SUN6I
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
20 prompt "Sunxi SoC Variant"
24 bool "sun4i (Allwinner A10)"
26 select SUNXI_GEN_SUN4I
30 bool "sun5i (Allwinner A13)"
32 select SUNXI_GEN_SUN4I
36 bool "sun6i (Allwinner A31)"
38 select SUNXI_GEN_SUN6I
42 bool "sun7i (Allwinner A20)"
44 select CPU_V7_HAS_NONSEC
45 select CPU_V7_HAS_VIRT
46 select SUNXI_GEN_SUN4I
48 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
51 bool "sun8i (Allwinner A23)"
53 select SUNXI_GEN_SUN6I
57 bool "sun8i (Allwinner A33)"
59 select SUNXI_GEN_SUN6I
63 bool "sun9i (Allwinner A80)"
65 select SUNXI_GEN_SUN6I
69 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
72 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
76 int "sunxi dram clock speed"
77 default 312 if MACH_SUN6I || MACH_SUN8I
78 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
80 Set the dram clock speed, valid range 240 - 480, must be a multiple
83 if MACH_SUN5I || MACH_SUN7I
85 int "sunxi mbus clock speed"
88 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
93 int "sunxi dram zq value"
94 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
95 default 127 if MACH_SUN7I
97 Set the dram zq value.
100 bool "sunxi dram odt enable"
101 default n if !MACH_SUN8I_A23
102 default y if MACH_SUN8I_A23
104 Select this to enable dram odt (on die termination).
106 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
108 int "sunxi dram emr1 value"
109 default 0 if MACH_SUN4I
110 default 4 if MACH_SUN5I || MACH_SUN7I
112 Set the dram controller emr1 value.
115 hex "sunxi dram tpr3 value"
118 Set the dram controller tpr3 parameter. This parameter configures
119 the delay on the command lane and also phase shifts, which are
120 applied for sampling incoming read data. The default value 0
121 means that no phase/delay adjustments are necessary. Properly
122 configuring this parameter increases reliability at high DRAM
125 config DRAM_DQS_GATING_DELAY
126 hex "sunxi dram dqs_gating_delay value"
129 Set the dram controller dqs_gating_delay parmeter. Each byte
130 encodes the DQS gating delay for each byte lane. The delay
131 granularity is 1/4 cycle. For example, the value 0x05060606
132 means that the delay is 5 quarter-cycles for one lane (1.25
133 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
134 The default value 0 means autodetection. The results of hardware
135 autodetection are not very reliable and depend on the chip
136 temperature (sometimes producing different results on cold start
137 and warm reboot). But the accuracy of hardware autodetection
138 is usually good enough, unless running at really high DRAM
139 clocks speeds (up to 600MHz). If unsure, keep as 0.
142 prompt "sunxi dram timings"
143 default DRAM_TIMINGS_VENDOR_MAGIC
145 Select the timings of the DDR3 chips.
147 config DRAM_TIMINGS_VENDOR_MAGIC
148 bool "Magic vendor timings from Android"
150 The same DRAM timings as in the Allwinner boot0 bootloader.
152 config DRAM_TIMINGS_DDR3_1066F_1333H
153 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
155 Use the timings of the standard JEDEC DDR3-1066F speed bin for
156 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
157 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
158 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
159 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
160 that down binning to DDR3-1066F is supported (because DDR3-1066F
161 uses a bit faster timings than DDR3-1333H).
163 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
164 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
166 Use the timings of the slowest possible JEDEC speed bin for the
167 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
168 DDR3-800E, DDR3-1066G or DDR3-1333J.
175 config DRAM_ODT_CORRECTION
176 int "sunxi dram odt correction value"
179 Set the dram odt correction value (range -255 - 255). In allwinner
180 fex files, this option is found in bits 8-15 of the u32 odt_en variable
181 in the [dram] section. When bit 31 of the odt_en variable is set
182 then the correction is negative. Usually the value for this is 0.
186 default 912000000 if MACH_SUN7I
187 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
189 config SYS_CONFIG_NAME
190 default "sun4i" if MACH_SUN4I
191 default "sun5i" if MACH_SUN5I
192 default "sun6i" if MACH_SUN6I
193 default "sun7i" if MACH_SUN7I
194 default "sun8i" if MACH_SUN8I
195 default "sun9i" if MACH_SUN9I
204 bool "UART0 on MicroSD breakout board"
207 Repurpose the SD card slot for getting access to the UART0 serial
208 console. Primarily useful only for low level u-boot debugging on
209 tablets, where normal UART0 is difficult to access and requires
210 device disassembly and/or soldering. As the SD card can't be used
211 at the same time, the system can be only booted in the FEL mode.
212 Only enable this if you really know what you are doing.
214 config OLD_SUNXI_KERNEL_COMPAT
215 boolean "Enable workarounds for booting old kernels"
218 Set this to enable various workarounds for old kernels, this results in
219 sub-optimal settings for newer kernels, only enable if needed.
222 string "Card detect pin for mmc0"
225 Set the card detect pin for mmc0, leave empty to not use cd. This
226 takes a string in the format understood by sunxi_name_to_gpio, e.g.
227 PH1 for pin 1 of port H.
230 string "Card detect pin for mmc1"
233 See MMC0_CD_PIN help text.
236 string "Card detect pin for mmc2"
239 See MMC0_CD_PIN help text.
242 string "Card detect pin for mmc3"
245 See MMC0_CD_PIN help text.
248 string "Pins for mmc1"
251 Set the pins used for mmc1, when applicable. This takes a string in the
252 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
255 string "Pins for mmc2"
258 See MMC1_PINS help text.
261 string "Pins for mmc3"
264 See MMC1_PINS help text.
266 config MMC_SUNXI_SLOT_EXTRA
267 int "mmc extra slot number"
270 sunxi builds always enable mmc0, some boards also have a second sdcard
271 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
274 config SPL_NAND_SUPPORT
275 bool "SPL/NAND mode support"
279 This enables support for booting from NAND internal
280 memory. U-Boot SPL doesn't detect where is it load from,
281 therefore this option is needed to properly load image from
282 flash. Option also disables MMC functionality on U-Boot due to
283 initialization errors encountered, when both controllers are
287 string "Vbus enable pin for usb0 (otg)"
290 Set the Vbus enable pin for usb0 (otg). This takes a string in the
291 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
294 string "Vbus detect pin for usb0 (otg)"
297 Set the Vbus detect pin for usb0 (otg). This takes a string in the
298 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
301 string "Vbus enable pin for usb1 (ehci0)"
302 default "PH6" if MACH_SUN4I || MACH_SUN7I
303 default "PH27" if MACH_SUN6I
305 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
306 a string in the format understood by sunxi_name_to_gpio, e.g.
307 PH1 for pin 1 of port H.
310 string "Vbus enable pin for usb2 (ehci1)"
311 default "PH3" if MACH_SUN4I || MACH_SUN7I
312 default "PH24" if MACH_SUN6I
314 See USB1_VBUS_PIN help text.
317 bool "Enable I2C/TWI controller 0"
318 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
319 default n if MACH_SUN6I || MACH_SUN8I
321 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
322 its clock and setting up the bus. This is especially useful on devices
323 with slaves connected to the bus or with pins exposed through e.g. an
324 expansion port/header.
327 bool "Enable I2C/TWI controller 1"
330 See I2C0_ENABLE help text.
333 bool "Enable I2C/TWI controller 2"
336 See I2C0_ENABLE help text.
338 if MACH_SUN6I || MACH_SUN7I
340 bool "Enable I2C/TWI controller 3"
343 See I2C0_ENABLE help text.
348 bool "Enable I2C/TWI controller 4"
351 See I2C0_ENABLE help text.
355 boolean "Enable support for gpio-s on axp PMICs"
358 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
361 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
364 Say Y here to add support for using a cfb console on the HDMI, LCD
365 or VGA output found on most sunxi devices. See doc/README.video for
366 info on how to select the video output and mode.
369 boolean "HDMI output support"
370 depends on VIDEO && !MACH_SUN8I
373 Say Y here to add support for outputting video over HDMI.
376 boolean "VGA output support"
377 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
380 Say Y here to add support for outputting video over VGA.
382 config VIDEO_VGA_VIA_LCD
383 boolean "VGA via LCD controller support"
384 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
387 Say Y here to add support for external DACs connected to the parallel
388 LCD interface driving a VGA connector, such as found on the
391 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
392 boolean "Force sync active high for VGA via LCD controller support"
393 depends on VIDEO_VGA_VIA_LCD
396 Say Y here if you've a board which uses opendrain drivers for the vga
397 hsync and vsync signals. Opendrain drivers cannot generate steep enough
398 positive edges for a stable video output, so on boards with opendrain
399 drivers the sync signals must always be active high.
401 config VIDEO_VGA_EXTERNAL_DAC_EN
402 string "LCD panel power enable pin"
403 depends on VIDEO_VGA_VIA_LCD
406 Set the enable pin for the external VGA DAC. This takes a string in the
407 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
409 config VIDEO_LCD_MODE
410 string "LCD panel timing details"
414 LCD panel timing details string, leave empty if there is no LCD panel.
415 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
416 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
418 config VIDEO_LCD_DCLK_PHASE
419 int "LCD panel display clock phase"
423 Select LCD panel display clock phase shift, range 0-3.
425 config VIDEO_LCD_POWER
426 string "LCD panel power enable pin"
430 Set the power enable pin for the LCD panel. This takes a string in the
431 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
433 config VIDEO_LCD_RESET
434 string "LCD panel reset pin"
438 Set the reset pin for the LCD panel. This takes a string in the format
439 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
441 config VIDEO_LCD_BL_EN
442 string "LCD panel backlight enable pin"
446 Set the backlight enable pin for the LCD panel. This takes a string in the
447 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
450 config VIDEO_LCD_BL_PWM
451 string "LCD panel backlight pwm pin"
455 Set the backlight pwm pin for the LCD panel. This takes a string in the
456 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
458 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
459 bool "LCD panel backlight pwm is inverted"
463 Set this if the backlight pwm output is active low.
465 config VIDEO_LCD_PANEL_I2C
466 bool "LCD panel needs to be configured via i2c"
470 Say y here if the LCD panel needs to be configured via i2c. This
471 will add a bitbang i2c controller using gpios to talk to the LCD.
473 config VIDEO_LCD_PANEL_I2C_SDA
474 string "LCD panel i2c interface SDA pin"
475 depends on VIDEO_LCD_PANEL_I2C
478 Set the SDA pin for the LCD i2c interface. This takes a string in the
479 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
481 config VIDEO_LCD_PANEL_I2C_SCL
482 string "LCD panel i2c interface SCL pin"
483 depends on VIDEO_LCD_PANEL_I2C
486 Set the SCL pin for the LCD i2c interface. This takes a string in the
487 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
490 # Note only one of these may be selected at a time! But hidden choices are
491 # not supported by Kconfig
492 config VIDEO_LCD_IF_PARALLEL
495 config VIDEO_LCD_IF_LVDS
500 prompt "LCD panel support"
503 Select which type of LCD panel to support.
505 config VIDEO_LCD_PANEL_PARALLEL
506 bool "Generic parallel interface LCD panel"
507 select VIDEO_LCD_IF_PARALLEL
509 config VIDEO_LCD_PANEL_LVDS
510 bool "Generic lvds interface LCD panel"
511 select VIDEO_LCD_IF_LVDS
513 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
514 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
515 select VIDEO_LCD_SSD2828
516 select VIDEO_LCD_IF_PARALLEL
518 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
520 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
521 bool "Hitachi tx18d42vm LCD panel"
522 select VIDEO_LCD_HITACHI_TX18D42VM
523 select VIDEO_LCD_IF_LVDS
525 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
527 config VIDEO_LCD_TL059WV5C0
528 bool "tl059wv5c0 LCD panel"
529 select VIDEO_LCD_PANEL_I2C
530 select VIDEO_LCD_IF_PARALLEL
532 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
533 Aigo M60/M608/M606 tablets.
538 config USB_MUSB_SUNXI
539 bool "Enable sunxi OTG / DRC USB controller in host mode"
542 Say y here to enable support for the sunxi OTG / DRC USB controller
543 used on almost all sunxi boards. Note currently u-boot can only have
544 one usb host controller enabled at a time, so enabling this on boards
545 which also use the ehci host controller will result in build errors.
548 boolean "Enable USB keyboard support"
551 Say Y here to add support for using a USB keyboard (typically used
552 in combination with a graphical console).
555 int "GMAC Transmit Clock Delay Chain"
558 Set the GMAC Transmit Clock Delay Chain value.
560 config SYS_MALLOC_CLEAR_ON_INIT
576 default y if !USB_MUSB_SUNXI