board/ti/dra7xx/evm.c

   1 /*
   2  * (C) Copyright 2013
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  *
   5  * Lokesh Vutla <lokeshvutla@ti.com>
   6  *
   7  * Based on previous work by:
   8  * Aneesh V       <aneesh@ti.com>
   9  * Steve Sakoman  <steve@sakoman.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13 #include <common.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <asm/gpio.h>
  17 #include <usb.h>
  18 #include <linux/usb/gadget.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/dra7xx_iodelay.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sata.h>
  24 #include <environment.h>
  25 #include <dwc3-uboot.h>
  26 #include <dwc3-omap-uboot.h>
  27 #include <ti-usb-phy-uboot.h>
  28
  29 #include "mux_data.h"
  30
  31 #ifdef CONFIG_DRIVER_TI_CPSW
  32 #include <cpsw.h>
  33 #endif
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 /* GPIO 7_11 */
  38 #define GPIO_DDR_VTT_EN 203
  39
  40 const struct omap_sysinfo sysinfo = {
  41         "Board: DRA7xx\n"
  42 };
  43
  44 /*
  45  * Adjust I/O delays on the Tx control and data lines of each MAC port. This
  46  * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
  47  * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
  48  * essentially need to counteract the DRA7xx internal delay, and we do this
  49  * by delaying the control and data lines. If not using this PHY, you probably
  50  * don't need to do this stuff!
  51  */
  52 static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
  53 {
  54         int i = 0;
  55         u32 reg_val;
  56         u32 delta;
  57         u32 coarse;
  58         u32 fine;
  59
  60         writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
  61
  62         while(io_dly[i].addr) {
  63                 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
  64                        io_dly[i].addr);
  65                 delta = io_dly[i].dly;
  66                 reg_val = readl(io_dly[i].addr) & 0x3ff;
  67                 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
  68                 coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
  69                 fine = (reg_val & 0x1F) + (delta & 0x1F);
  70                 fine = (fine > 0x1F) ? (0x1F) : (fine);
  71                 reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
  72                                 CFG_IO_DELAY_LOCK_MASK |
  73                                 ((coarse << 5) | (fine));
  74                 writel(reg_val, io_dly[i].addr);
  75                 i++;
  76         }
  77
  78         writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
  79 }
  80
  81 /**
  82  * @brief board_init
  83  *
  84  * @return 0
  85  */
  86 int board_init(void)
  87 {
  88         gpmc_init();
  89         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
  90
  91         return 0;
  92 }
  93
  94 int board_late_init(void)
  95 {
  96 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  97         u32 id[4];
  98
  99         if (omap_revision() == DRA722_ES1_0)
 100                 setenv("board_name", "dra72x");
 101         else
 102                 setenv("board_name", "dra7xx");
 103
 104         id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
 105         id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
 106         usb_set_serial_num_from_die_id(id);
 107 #endif
 108         return 0;
 109 }
 110
 111 void set_muxconf_regs_essential(void)
 112 {
 113         do_set_mux32((*ctrl)->control_padconf_core_base,
 114                      early_padconf, ARRAY_SIZE(early_padconf));
 115 }
 116
 117 #ifdef CONFIG_IODELAY_RECALIBRATION
 118 void recalibrate_iodelay(void)
 119 {
 120         if (is_dra72x()) {
 121                 __recalibrate_iodelay(core_padconf_array_essential,
 122                                       ARRAY_SIZE(core_padconf_array_essential),
 123                                       iodelay_cfg_array,
 124                                       ARRAY_SIZE(iodelay_cfg_array));
 125         } else {
 126                 __recalibrate_iodelay(dra74x_core_padconf_array,
 127                                       ARRAY_SIZE(dra74x_core_padconf_array),
 128                                       dra742_iodelay_cfg_array,
 129                                       ARRAY_SIZE(dra742_iodelay_cfg_array));
 130         }
 131 }
 132 #endif
 133
 134 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 135 int board_mmc_init(bd_t *bis)
 136 {
 137         omap_mmc_init(0, 0, 0, -1, -1);
 138         omap_mmc_init(1, 0, 0, -1, -1);
 139         return 0;
 140 }
 141 #endif
 142
 143 #ifdef CONFIG_USB_DWC3
 144 static struct dwc3_device usb_otg_ss1 = {
 145         .maximum_speed = USB_SPEED_SUPER,
 146         .base = DRA7_USB_OTG_SS1_BASE,
 147         .tx_fifo_resize = false,
 148         .index = 0,
 149 };
 150
 151 static struct dwc3_omap_device usb_otg_ss1_glue = {
 152         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 153         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 154         .vbus_id_status = OMAP_DWC3_VBUS_VALID,
 155         .index = 0,
 156 };
 157
 158 static struct ti_usb_phy_device usb_phy1_device = {
 159         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 160         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 161         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 162         .index = 0,
 163 };
 164
 165 static struct dwc3_device usb_otg_ss2 = {
 166         .maximum_speed = USB_SPEED_SUPER,
 167         .base = DRA7_USB_OTG_SS2_BASE,
 168         .tx_fifo_resize = false,
 169         .index = 1,
 170 };
 171
 172 static struct dwc3_omap_device usb_otg_ss2_glue = {
 173         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 174         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 175         .vbus_id_status = OMAP_DWC3_VBUS_VALID,
 176         .index = 1,
 177 };
 178
 179 static struct ti_usb_phy_device usb_phy2_device = {
 180         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 181         .index = 1,
 182 };
 183
 184 int board_usb_init(int index, enum usb_init_type init)
 185 {
 186         switch (index) {
 187         case 0:
 188                 if (init == USB_INIT_DEVICE) {
 189                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 190                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 191                 } else {
 192                         usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
 193                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 194                 }
 195
 196                 ti_usb_phy_uboot_init(&usb_phy1_device);
 197                 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 198                 dwc3_uboot_init(&usb_otg_ss1);
 199                 break;
 200         case 1:
 201                 if (init == USB_INIT_DEVICE) {
 202                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 203                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 204                 } else {
 205                         usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
 206                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 207                 }
 208
 209                 ti_usb_phy_uboot_init(&usb_phy2_device);
 210                 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 211                 dwc3_uboot_init(&usb_otg_ss2);
 212                 break;
 213         default:
 214                 printf("Invalid Controller Index\n");
 215         }
 216
 217         return 0;
 218 }
 219
 220 int board_usb_cleanup(int index, enum usb_init_type init)
 221 {
 222         switch (index) {
 223         case 0:
 224         case 1:
 225                 ti_usb_phy_uboot_exit(index);
 226                 dwc3_uboot_exit(index);
 227                 dwc3_omap_uboot_exit(index);
 228                 break;
 229         default:
 230                 printf("Invalid Controller Index\n");
 231         }
 232         return 0;
 233 }
 234
 235 int usb_gadget_handle_interrupts(int index)
 236 {
 237         u32 status;
 238
 239         status = dwc3_omap_uboot_interrupt_status(index);
 240         if (status)
 241                 dwc3_uboot_handle_interrupt(index);
 242
 243         return 0;
 244 }
 245 #endif
 246
 247 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 248 int spl_start_uboot(void)
 249 {
 250         /* break into full u-boot on 'c' */
 251         if (serial_tstc() && serial_getc() == 'c')
 252                 return 1;
 253
 254 #ifdef CONFIG_SPL_ENV_SUPPORT
 255         env_init();
 256         env_relocate_spec();
 257         if (getenv_yesno("boot_os") != 1)
 258                 return 1;
 259 #endif
 260
 261         return 0;
 262 }
 263 #endif
 264
 265 #ifdef CONFIG_DRIVER_TI_CPSW
 266
 267 /* Delay value to add to calibrated value */
 268 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 269 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 270 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 271 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 272 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 273 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 274 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 275 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 276 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 277 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 278
 279 extern u32 *const omap_si_rev;
 280
 281 static void cpsw_control(int enabled)
 282 {
 283         /* VTP can be added here */
 284
 285         return;
 286 }
 287
 288 static struct cpsw_slave_data cpsw_slaves[] = {
 289         {
 290                 .slave_reg_ofs  = 0x208,
 291                 .sliver_reg_ofs = 0xd80,
 292                 .phy_addr       = 2,
 293         },
 294         {
 295                 .slave_reg_ofs  = 0x308,
 296                 .sliver_reg_ofs = 0xdc0,
 297                 .phy_addr       = 3,
 298         },
 299 };
 300
 301 static struct cpsw_platform_data cpsw_data = {
 302         .mdio_base              = CPSW_MDIO_BASE,
 303         .cpsw_base              = CPSW_BASE,
 304         .mdio_div               = 0xff,
 305         .channels               = 8,
 306         .cpdma_reg_ofs          = 0x800,
 307         .slaves                 = 2,
 308         .slave_data             = cpsw_slaves,
 309         .ale_reg_ofs            = 0xd00,
 310         .ale_entries            = 1024,
 311         .host_port_reg_ofs      = 0x108,
 312         .hw_stats_reg_ofs       = 0x900,
 313         .bd_ram_ofs             = 0x2000,
 314         .mac_control            = (1 << 5),
 315         .control                = cpsw_control,
 316         .host_port_num          = 0,
 317         .version                = CPSW_CTRL_VERSION_2,
 318 };
 319
 320 int board_eth_init(bd_t *bis)
 321 {
 322         int ret;
 323         uint8_t mac_addr[6];
 324         uint32_t mac_hi, mac_lo;
 325         uint32_t ctrl_val;
 326         const struct io_delay io_dly[] = {
 327                 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
 328                 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
 329                 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
 330                 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
 331                 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
 332                 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
 333                 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
 334                 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
 335                 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
 336                 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
 337                 {0}
 338         };
 339
 340         /* Adjust IO delay for RGMII tx path */
 341         dra7xx_adj_io_delay(io_dly);
 342
 343         /* try reading mac address from efuse */
 344         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 345         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 346         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 347         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 348         mac_addr[2] = mac_hi & 0xFF;
 349         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 350         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 351         mac_addr[5] = mac_lo & 0xFF;
 352
 353         if (!getenv("ethaddr")) {
 354                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 355
 356                 if (is_valid_ethaddr(mac_addr))
 357                         eth_setenv_enetaddr("ethaddr", mac_addr);
 358         }
 359
 360         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 361         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 362         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 363         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 364         mac_addr[2] = mac_hi & 0xFF;
 365         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 366         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 367         mac_addr[5] = mac_lo & 0xFF;
 368
 369         if (!getenv("eth1addr")) {
 370                 if (is_valid_ethaddr(mac_addr))
 371                         eth_setenv_enetaddr("eth1addr", mac_addr);
 372         }
 373
 374         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 375         ctrl_val |= 0x22;
 376         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 377
 378         if (*omap_si_rev == DRA722_ES1_0)
 379                 cpsw_data.active_slave = 1;
 380
 381         ret = cpsw_register(&cpsw_data);
 382         if (ret < 0)
 383                 printf("Error %d registering CPSW switch\n", ret);
 384
 385         return ret;
 386 }
 387 #endif
 388
 389 #ifdef CONFIG_BOARD_EARLY_INIT_F
 390 /* VTT regulator enable */
 391 static inline void vtt_regulator_enable(void)
 392 {
 393         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 394                 return;
 395
 396         /* Do not enable VTT for DRA722 */
 397         if (omap_revision() == DRA722_ES1_0)
 398                 return;
 399
 400         /*
 401          * EVM Rev G and later use gpio7_11 for DDR3 termination.
 402          * This is safe enough to do on older revs.
 403          */
 404         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 405         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 406 }
 407
 408 int board_early_init_f(void)
 409 {
 410         vtt_regulator_enable();
 411         return 0;
 412 }
 413 #endif