board/voiceblue/setup.S

   1 /*
   2  * Board specific setup info
   3  *
   4  * (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
   5  * (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * version 2 published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <version.h>
  27
  28 _TEXT_BASE:
  29         .word   TEXT_BASE       /* SDRAM load addr from config.mk */
  30
  31 OMAP5910_LPG1_BASE:             .word 0xfffbd000
  32 OMAP5910_TIPB_SWITCHES_BASE:    .word 0xfffbc800
  33 OMAP5910_MPU_TC_BASE:           .word 0xfffecc00
  34 OMAP5910_MPU_CLKM_BASE:         .word 0xfffece00
  35 OMAP5910_ULPD_PWR_MNG_BASE:     .word 0xfffe0800
  36 OMAP5910_DPLL1_BASE:            .word 0xfffecf00
  37 OMAP5910_GPIO_BASE:             .word 0xfffce000
  38 OMAP5910_MPU_WD_TIMER_BASE:     .word 0xfffec800
  39 OMAP5910_MPUI_BASE:             .word 0xfffec900
  40
  41 _OMAP5910_ARM_CKCTL:            .word OMAP5910_ARM_CKCTL
  42 _OMAP5910_ARM_EN_CLK:           .word OMAP5910_ARM_EN_CLK
  43
  44 OMAP5910_MPUI_CTRL:             .word 0x0000ff1b
  45
  46 VAL_EMIFS_CS0_CONFIG:           .word 0x00009090
  47 VAL_EMIFS_CS1_CONFIG:           .word 0x00003031
  48 VAL_EMIFS_CS2_CONFIG:           .word 0x00003031
  49 VAL_EMIFS_CS3_CONFIG:           .word 0x0000c0c0
  50 VAL_EMIFS_DYN_WAIT:             .word 0x00000000
  51 /* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
  52                                 /*     SLRF       SD_RET     ARE        SDRAM_TYPE   ARCV           SDRAM_FREQUENCY PWD     CLK */
  53 VAL_EMIFF_SDRAM_CONFIG:         .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
  54 VAL_EMIFF_SDRAM_CONFIG2:        .word 0x00000003
  55 VAL_EMIFF_MRS:                  .word 0x00000037
  56
  57 /*
  58  * GPIO04 - D4 (Onboard LED)
  59  * GPIO07 - LAN91C111 reset
  60  */
  61 GPIO_DIRECTION:
  62         .word 0x0000ff6f
  63 /*
  64  * Disable everything, but D4 LED (connected through invertor)
  65  */
  66 GPIO_OUTPUT:
  67         .word 0x00000010
  68
  69 MUX_CONFIG_BASE:
  70         .word 0xfffe1000
  71
  72 MUX_CONFIG_VALUES:
  73         .align 4
  74         .word 0x00000000        @ FUNC_MUX_CTRL_0
  75         .word 0x00000000        @ FUNC_MUX_CTRL_1
  76         .word 0x00000000        @ FUNC_MUX_CTRL_2
  77         .word 0x00000000        @ FUNC_MUX_CTRL_3
  78         .word 0x00000000        @ FUNC_MUX_CTRL_4
  79         .word 0x12082480        @ FUNC_MUX_CTRL_5
  80         .word 0x0000001c        @ FUNC_MUX_CTRL_6
  81         .word 0x00000003        @ FUNC_MUX_CTRL_7
  82         .word 0x10001200        @ FUNC_MUX_CTRL_8
  83         .word 0x01201012        @ FUNC_MUX_CTRL_9
  84         .word 0x02081248        @ FUNC_MUX_CTRL_A
  85         .word 0x00001248        @ FUNC_MUX_CTRL_B
  86         .word 0x12240000        @ FUNC_MUX_CTRL_C
  87         .word 0x00002000        @ FUNC_MUX_CTRL_D
  88         .word 0x00000000        @ PULL_DWN_CTRL_0
  89         .word 0x0000085f        @ PULL_DWN_CTRL_1
  90         .word 0x01001000        @ PULL_DWN_CTRL_2
  91         .word 0x00000000        @ PULL_DWN_CTRL_3
  92         .word 0x00000000        @ GATE_INH_CTRL_0
  93         .word 0x00000000        @ VOLTAGE_CTRL_0
  94         .word 0x00000000        @ TEST_DBG_CTRL_0
  95         .word 0x00000006        @ MOD_CONF_CTRL_0
  96         .word 0x0000eaef        @ COMP_MODE_CTRL_0
  97
  98 MUX_CONFIG_OFFSETS:
  99         .align 1
 100         .byte 0x00              @ FUNC_MUX_CTRL_0
 101         .byte 0x04              @ FUNC_MUX_CTRL_1
 102         .byte 0x08              @ FUNC_MUX_CTRL_2
 103         .byte 0x10              @ FUNC_MUX_CTRL_3
 104         .byte 0x14              @ FUNC_MUX_CTRL_4
 105         .byte 0x18              @ FUNC_MUX_CTRL_5
 106         .byte 0x1c              @ FUNC_MUX_CTRL_6
 107         .byte 0x20              @ FUNC_MUX_CTRL_7
 108         .byte 0x24              @ FUNC_MUX_CTRL_8
 109         .byte 0x28              @ FUNC_MUX_CTRL_9
 110         .byte 0x2c              @ FUNC_MUX_CTRL_A
 111         .byte 0x30              @ FUNC_MUX_CTRL_B
 112         .byte 0x34              @ FUNC_MUX_CTRL_C
 113         .byte 0x38              @ FUNC_MUX_CTRL_D
 114         .byte 0x40              @ PULL_DWN_CTRL_0
 115         .byte 0x44              @ PULL_DWN_CTRL_1
 116         .byte 0x48              @ PULL_DWN_CTRL_2
 117         .byte 0x4c              @ PULL_DWN_CTRL_3
 118         .byte 0x50              @ GATE_INH_CTRL_0
 119         .byte 0x60              @ VOLTAGE_CTRL_0
 120         .byte 0x70              @ TEST_DBG_CTRL_0
 121         .byte 0x80              @ MOD_CONF_CTRL_0
 122         .byte 0x0c              @ COMP_MODE_CTRL_0
 123         .byte 0xff
 124
 125 .globl lowlevel_init
 126 lowlevel_init:
 127         /* Improve performance a bit... */
 128         mrc     p15, 0, r1, c0, c0, 0           @ read C15 ID register
 129         mrc     p15, 0, r1, c0, c0, 1           @ read C15 Cache information register
 130         mrc     p15, 0, r1, c1, c0, 0           @ read C15 Control register
 131         orr     r1, r1, #0x1000                 @ enable I-cache, map interrupt vector 0xffff0000
 132         mcr     p15, 0, r1, c1, c0, 0           @ write C15 Control register
 133         mov     r1, #0x00
 134         mcr     p15, 0, r1, c7, c5, 0           @ Flush I-cache
 135         nop
 136         nop
 137         nop
 138         nop
 139
 140         /* Setup clocking mode */
 141         ldr     r0, OMAP5910_MPU_CLKM_BASE      @ prepare base of CLOCK unit
 142         ldrh    r1, [r0, #0x18]                 @ get reset status
 143         bic     r1, r1, #(7 << 11)              @ clear clock select
 144         orr     r1, r1, #(2 << 11)              @ set synchronous scalable
 145         mov     r2, #0                          @ set wait counter to 100 clock cycles
 146
 147 icache_loop:
 148         cmp     r2, #0x01
 149         streqh  r1, [r0, #0x18]
 150         add     r2, r2, #0x01
 151         cmp     r2, #0x10
 152         bne     icache_loop
 153         nop
 154
 155         /* Setup clock divisors */
 156         ldr     r0, OMAP5910_MPU_CLKM_BASE      @ base of CLOCK unit
 157         ldr     r1, _OMAP5910_ARM_CKCTL
 158         orr     r1, r1, #0x2000                 @ enable DSP clock
 159         strh    r1, [r0, #0x00]                 @ setup clock divisors
 160
 161         /* Setup DPLL to generate requested freq */
 162         ldr     r0, OMAP5910_DPLL1_BASE         @ base of DPLL1 register
 163         mov     r1, #0x0010                     @ set PLL_ENABLE
 164         orr     r1, r1, #0x2000                 @ set IOB to new locking
 165         orr     r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
 166         orr     r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
 167         strh    r1, [r0]                        @ write
 168
 169 locking:
 170         ldrh    r1, [r0]                        @ get DPLL value
 171         tst     r1, #0x01
 172         beq     locking                         @ while LOCK not set
 173
 174         /* Enable clock */
 175         ldr     r0, OMAP5910_MPU_CLKM_BASE      @ base of CLOCK unit
 176         mov     r1, #(1 << 10)                  @ disable idle mode do not check
 177                                                 @ nWAKEUP pin, other remain active
 178         strh    r1, [r0, #0x04]
 179         ldr     r1, _OMAP5910_ARM_EN_CLK
 180         strh    r1, [r0, #0x08]
 181         mov     r1, #0x003f                     @ FLASH.RP not enabled in idle and
 182                                                 @ max delayed ( 32 x CLKIN )
 183         strh    r1, [r0, #0x0c]
 184
 185         /* Configure 5910 pins functions to match our board. */
 186         ldr     r0, MUX_CONFIG_BASE
 187         adr     r1, MUX_CONFIG_VALUES
 188         adr     r2, MUX_CONFIG_OFFSETS
 189 next_mux_cfg:
 190         ldrb    r3, [r2], #1
 191         ldr     r4, [r1], #4
 192         cmp     r3, #0xff
 193         strne   r4, [r0, r3]
 194         bne     next_mux_cfg
 195
 196         /* Configure GPIO pins (also enables onboard LED) */
 197         ldr     r0, OMAP5910_GPIO_BASE
 198         ldr     r1, GPIO_OUTPUT
 199         strh    r1, [r0, #0x04]
 200         ldr     r1, GPIO_DIRECTION
 201         strh    r1, [r0, #0x08]
 202
 203         /* EnablePeripherals */
 204         ldr     r0, OMAP5910_MPU_CLKM_BASE      @ CLOCK unit
 205         mov     r1, #0x0001                     @ Peripheral enable
 206         strh    r1, [r0, #0x14]
 207
 208         /* Program LED Pulse Generator */
 209         ldr     r0, OMAP5910_LPG1_BASE          @ 1st LED Pulse Generator
 210         mov     r1, #0x7F                       @ Set obscure frequency in
 211         strb    r1, [r0, #0x00]                 @ LCR
 212         mov     r1, #0x01                       @ Enable clock (CLK_EN) in
 213         strb    r1, [r0, #0x04]                 @ PMR
 214
 215         /* TIPB Lock UART1 */
 216         ldr     r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches
 217         mov     r1, #1                          @ ARM allocated
 218         strh    r1, [r0,#0x04]                  @ clear IRQ line and status bits
 219         strh    r1, [r0,#0x00]
 220         ldrh    r1, [r0,#0x04]
 221
 222         /* Disable watchdog */
 223         ldr     r0, OMAP5910_MPU_WD_TIMER_BASE
 224         mov     r1, #0xf5
 225         strh    r1, [r0, #0x8]
 226         mov     r1, #0xa0
 227         strh    r1, [r0, #0x8]
 228
 229         /* Enable MCLK */
 230         ldr     r0, OMAP5910_ULPD_PWR_MNG_BASE
 231         mov     r1, #0x6
 232         strh    r1, [r0, #0x34]
 233         strh    r1, [r0, #0x34]
 234
 235         /* Setup clock divisors */
 236         ldr     r0, OMAP5910_ULPD_PWR_MNG_BASE  @ base of ULDPL DPLL1 register
 237
 238         mov     r1, #0x0010                     @ set PLL_ENABLE
 239         orr     r1, r1, #0x2000                 @ set IOB to new locking
 240         strh    r1, [r0]                        @ write
 241
 242 ulocking:
 243         ldrh    r1, [r0]                        @ get DPLL value
 244         tst     r1, #1
 245         beq     ulocking                        @ while LOCK not set
 246
 247         /* EMIF init */
 248         ldr     r0, OMAP5910_MPU_TC_BASE
 249         ldrh    r1, [r0, #0x0c]                 @ EMIFS_CONFIG_REG
 250         bic     r1, r1, #0x0c                   @ pwr down disabled, flash WP
 251         orr     r1, r1, #0x01
 252         str     r1, [r0, #0x0c]
 253
 254         ldr     r1, VAL_EMIFS_CS0_CONFIG
 255         str     r1, [r0, #0x10]                 @ EMIFS_CS0_CONFIG
 256         ldr     r1, VAL_EMIFS_CS1_CONFIG
 257         str     r1, [r0, #0x14]                 @ EMIFS_CS1_CONFIG
 258         ldr     r1, VAL_EMIFS_CS2_CONFIG
 259         str     r1, [r0, #0x18]                 @ EMIFS_CS2_CONFIG
 260         ldr     r1, VAL_EMIFS_CS3_CONFIG
 261         str     r1, [r0, #0x1c]                 @ EMIFS_CS3_CONFIG
 262         ldr     r1, VAL_EMIFS_DYN_WAIT
 263         str     r1, [r0, #0x40]                 @ EMIFS_CFG_DYN_WAIT
 264
 265         /* Setup SDRAM */
 266         ldr     r1, VAL_EMIFF_SDRAM_CONFIG
 267         str     r1, [r0, #0x20]                 @ EMIFF_SDRAM_CONFIG
 268         ldr     r1, VAL_EMIFF_SDRAM_CONFIG2
 269         str     r1, [r0, #0x3c]                 @ EMIFF_SDRAM_CONFIG2
 270         ldr     r1, VAL_EMIFF_MRS
 271         str     r1, [r0, #0x24]                 @ EMIFF_MRS
 272         /* SDRAM needs 100us to stabilize */
 273         mov     r0, #0x4000
 274 sdelay:
 275         subs    r0, r0, #0x1
 276         bne     sdelay
 277
 278         /* back to arch calling code */
 279         mov     pc, lr
 280 .end