board/vpac270/vpac270.c

   1 /*
   2  * Voipac PXA270 Support
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/regs-mmc.h>
  12 #include <asm/arch/pxa.h>
  13 #include <netdev.h>
  14 #include <serial.h>
  15 #include <asm/io.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 /*
  20  * Miscelaneous platform dependent initialisations
  21  */
  22 int board_init(void)
  23 {
  24         /* We have RAM, disable cache */
  25         dcache_disable();
  26         icache_disable();
  27
  28         /* memory and cpu-speed are setup before relocation */
  29         /* so we do _nothing_ here */
  30
  31         /* Arch number of vpac270 */
  32         gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
  33
  34         /* adress of boot parameters */
  35         gd->bd->bi_boot_params = 0xa0000100;
  36
  37         return 0;
  38 }
  39
  40 int dram_init(void)
  41 {
  42 #ifndef CONFIG_ONENAND
  43         pxa2xx_dram_init();
  44 #endif
  45         gd->ram_size = PHYS_SDRAM_1_SIZE;
  46         return 0;
  47 }
  48
  49 void dram_init_banksize(void)
  50 {
  51         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  52         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  53
  54 #ifdef  CONFIG_RAM_256M
  55         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  56         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  57 #endif
  58 }
  59
  60 #ifdef  CONFIG_CMD_MMC
  61 int board_mmc_init(bd_t *bis)
  62 {
  63         pxa_mmc_register(0);
  64         return 0;
  65 }
  66 #endif
  67
  68 #ifdef  CONFIG_CMD_USB
  69 int usb_board_init(void)
  70 {
  71         writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
  72                 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  73                 UHCHR);
  74
  75         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  76
  77         while (readl(UHCHR) & UHCHR_FSBIR)
  78                 ;
  79
  80         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  81         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  82
  83         /* Clear any OTG Pin Hold */
  84         if (readl(PSSR) & PSSR_OTGPH)
  85                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  86
  87         writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
  88         writel(readl(UHCRHDA) | 0x100, UHCRHDA);
  89
  90         /* Set port power control mask bits, only 3 ports. */
  91         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  92
  93         /* enable port 2 */
  94         writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
  95                 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
  96
  97         return 0;
  98 }
  99
 100 void usb_board_init_fail(void)
 101 {
 102         return;
 103 }
 104
 105 void usb_board_stop(void)
 106 {
 107         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 108         udelay(11);
 109         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 110
 111         writel(readl(UHCCOMS) | 1, UHCCOMS);
 112         udelay(10);
 113
 114         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 115
 116         return;
 117 }
 118 #endif
 119
 120 #ifdef CONFIG_DRIVER_DM9000
 121 int board_eth_init(bd_t *bis)
 122 {
 123         return dm9000_initialize(bis);
 124 }
 125 #endif