board/vpac270/vpac270.c

   1 /*
   2  * Voipac PXA270 Support
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/regs-mmc.h>
  12 #include <asm/arch/pxa.h>
  13 #include <netdev.h>
  14 #include <serial.h>
  15 #include <asm/io.h>
  16 #include <usb.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 /*
  21  * Miscelaneous platform dependent initialisations
  22  */
  23 int board_init(void)
  24 {
  25         /* We have RAM, disable cache */
  26         dcache_disable();
  27         icache_disable();
  28
  29         /* memory and cpu-speed are setup before relocation */
  30         /* so we do _nothing_ here */
  31
  32         /* Arch number of vpac270 */
  33         gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
  34
  35         /* adress of boot parameters */
  36         gd->bd->bi_boot_params = 0xa0000100;
  37
  38         return 0;
  39 }
  40
  41 int dram_init(void)
  42 {
  43 #ifndef CONFIG_ONENAND
  44         pxa2xx_dram_init();
  45 #endif
  46         gd->ram_size = PHYS_SDRAM_1_SIZE;
  47         return 0;
  48 }
  49
  50 void dram_init_banksize(void)
  51 {
  52         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  53         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  54
  55 #ifdef  CONFIG_RAM_256M
  56         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  57         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  58 #endif
  59 }
  60
  61 #ifdef  CONFIG_CMD_MMC
  62 int board_mmc_init(bd_t *bis)
  63 {
  64         pxa_mmc_register(0);
  65         return 0;
  66 }
  67 #endif
  68
  69 #ifdef  CONFIG_CMD_USB
  70 int board_usb_init(int index, enum usb_init_type init)
  71 {
  72         writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
  73                 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  74                 UHCHR);
  75
  76         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  77
  78         while (readl(UHCHR) & UHCHR_FSBIR)
  79                 ;
  80
  81         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  82         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  83
  84         /* Clear any OTG Pin Hold */
  85         if (readl(PSSR) & PSSR_OTGPH)
  86                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  87
  88         writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
  89         writel(readl(UHCRHDA) | 0x100, UHCRHDA);
  90
  91         /* Set port power control mask bits, only 3 ports. */
  92         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  93
  94         /* enable port 2 */
  95         writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
  96                 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
  97
  98         return 0;
  99 }
 100
 101 int board_usb_cleanup(int index, enum usb_init_type init)
 102 {
 103         return 0;
 104 }
 105
 106 void usb_board_stop(void)
 107 {
 108         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 109         udelay(11);
 110         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 111
 112         writel(readl(UHCCOMS) | 1, UHCCOMS);
 113         udelay(10);
 114
 115         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 116
 117         return;
 118 }
 119 #endif
 120
 121 #ifdef CONFIG_DRIVER_DM9000
 122 int board_eth_init(bd_t *bis)
 123 {
 124         return dm9000_initialize(bis);
 125 }
 126 #endif