2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 *************************************************************************
35 * Jump vector table as in table 3.1 in [1]
37 *************************************************************************
43 ldr pc, _undefined_instruction
44 ldr pc, _software_interrupt
45 ldr pc, _prefetch_abort
51 _undefined_instruction: .word undefined_instruction
52 _software_interrupt: .word software_interrupt
53 _prefetch_abort: .word prefetch_abort
54 _data_abort: .word data_abort
55 _not_used: .word not_used
59 .balignl 16,0xdeadbeef
63 *************************************************************************
65 * Startup Code (reset vector)
67 * do important init only if we don't start from memory!
68 * relocate armboot to ram
70 * jump to second stage
72 *************************************************************************
76 * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
86 * Note: _armboot_end_data and _armboot_end are defined
87 * by the (board-dependent) linker script.
88 * _armboot_end_data is the first usable FLASH address after armboot
90 .globl _armboot_end_data
92 .word armboot_end_data
98 * _armboot_real_end is the first usable RAM address behind armboot
99 * and the various stacks
101 .globl _armboot_real_end
105 #ifdef CONFIG_USE_IRQ
106 /* IRQ stack memory (calculated at run-time) */
107 .globl IRQ_STACK_START
111 /* IRQ stack memory (calculated at run-time) */
112 .globl FIQ_STACK_START
119 * the actual reset code
124 * set the cpu to SVC32 mode
132 * we do sys-critical inits only at reboot,
133 * not when booting from ram!
135 #ifdef CONFIG_INIT_CRITICAL
141 * relocate armboot to RAM
143 adr r0, _start /* r0 <- current position of code */
144 ldr r2, _armboot_start
146 sub r2, r3, r2 /* r2 <- size of armboot */
147 ldr r1, _TEXT_BASE /* r1 <- destination address */
148 add r2, r0, r2 /* r2 <- source end address */
151 * r0 = source address
152 * r1 = target address
153 * r2 = source end address
161 /* set up the stack */
163 add r0, r0, #CONFIG_STACKSIZE
164 sub sp, r0, #12 /* leave 3 words for abort-stack */
166 ldr pc, _start_armboot
168 _start_armboot: .word start_armboot
172 *************************************************************************
174 * CPU_init_critical registers
176 * setup important registers
177 * setup memory timing
179 *************************************************************************
183 /* Interupt-Controller base addresses */
184 INTMR1: .word 0x80000280 @ 32 bit size
185 INTMR2: .word 0x80001280 @ 16 bit size
186 INTMR3: .word 0x80002280 @ 8 bit size
189 SYSCON1: .word 0x80000100
190 SYSCON2: .word 0x80001100
191 SYSCON3: .word 0x80002200
193 #define CLKCTL 0x6 /* mask */
194 #define CLKCTL_18 0x0 /* 18.432 MHz */
195 #define CLKCTL_36 0x2 /* 36.864 MHz */
196 #define CLKCTL_49 0x4 /* 49.152 MHz */
197 #define CLKCTL_73 0x6 /* 73.728 MHz */
201 * mask all IRQs by clearing all bits in the INTMRs
212 * flush v4 I/D caches
215 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
216 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
219 * disable MMU stuff and caches
222 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
223 bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
224 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
227 #ifdef CONFIG_ARM7_REVD
228 /* set clock speed */
229 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
230 /* !!! not doing DRAM refresh properly! */
234 orr r1, r1, #CLKCTL_36
239 * before relocating, we have to setup RAM timing
240 * because memory timing is board-dependend, you will
241 * find a memsetup.S in your board directory.
253 *************************************************************************
257 *************************************************************************
263 #define S_FRAME_SIZE 72
285 #define MODE_SVC 0x13
289 * use bad_save_user_regs for abort/prefetch/undef/swi ...
290 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
293 .macro bad_save_user_regs
294 sub sp, sp, #S_FRAME_SIZE
295 stmia sp, {r0 - r12} @ Calling r0-r12
299 add r2, r2, #CONFIG_STACKSIZE
301 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
302 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
306 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
310 .macro irq_save_user_regs
311 sub sp, sp, #S_FRAME_SIZE
312 stmia sp, {r0 - r12} @ Calling r0-r12
314 stmdb r8, {sp, lr}^ @ Calling SP, LR
315 str lr, [r8, #0] @ Save calling PC
317 str r6, [r8, #4] @ Save CPSR
318 str r0, [r8, #8] @ Save OLD_R0
322 .macro irq_restore_user_regs
323 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
325 ldr lr, [sp, #S_PC] @ Get PC
326 add sp, sp, #S_FRAME_SIZE
327 subs pc, lr, #4 @ return & move spsr_svc into cpsr
331 ldr r13, _armboot_end @ setup our mode stack
332 add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
335 str lr, [r13] @ save caller lr / spsr
339 mov r13, #MODE_SVC @ prepare SVC-Mode
345 .macro get_irq_stack @ setup IRQ stack
346 ldr sp, IRQ_STACK_START
349 .macro get_fiq_stack @ setup FIQ stack
350 ldr sp, FIQ_STACK_START
357 undefined_instruction:
360 bl do_undefined_instruction
366 bl do_software_interrupt
386 #ifdef CONFIG_USE_IRQ
393 irq_restore_user_regs
398 /* someone ought to write a more effiction fiq_save_user_regs */
401 irq_restore_user_regs
423 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
424 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
425 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
426 bic ip, ip, #0x000f @ ............wcam
427 bic ip, ip, #0x2100 @ ..v....s........
428 mcr p15, 0, ip, c1, c0, 0 @ ctrl register