3 * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <asm/arch/regs-pinctrl.h>
21 #include <asm/arch/pinctrl.h>
23 void pin_gpio_direction(u32 id, u32 output)
26 u32 bank = PINID_2_BANK(id);
27 u32 pin = PINID_2_PIN(id);
29 addr = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0;
32 REG_SET_ADDR(addr, 1 << pin);
34 REG_CLR_ADDR(addr, 1 << pin);
37 u32 pin_gpio_get(u32 id)
40 u32 bank = PINID_2_BANK(id);
41 u32 pin = PINID_2_PIN(id);
43 addr = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0;
45 val = REG_RD_ADDR(addr);
47 return !!(val & (1 << pin));
50 void pin_gpio_set(u32 id, u32 val)
53 u32 bank = PINID_2_BANK(id);
54 u32 pin = PINID_2_PIN(id);
56 addr = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0;
59 REG_SET_ADDR(addr, 1 << pin);
61 REG_CLR_ADDR(addr, 1 << pin);
64 void pin_set_strength(u32 id, enum pad_strength strength)
67 u32 bank = PINID_2_BANK(id);
68 u32 pin = PINID_2_PIN(id);
71 addr = REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0;
72 addr += 0x40 * bank + 0x10 * (pin >> 3);
75 /* Don't use REG_CLR_ADDR/REG_SET_ADDR to prevent unwanted pin state transitions */
76 val = REG_RD_ADDR(addr);
77 val &= ~(0x7 << (pin * 4));
78 val |= (strength & 0x7) << (pin * 4);
79 REG_WR_ADDR(addr, val);
82 void pin_set_voltage(u32 id, enum pad_voltage volt)
85 u32 bank = PINID_2_BANK(id);
86 u32 pin = PINID_2_PIN(id);
88 addr = REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0;
89 addr += 0x40 * bank + 0x10 * (pin >> 3);
92 REG_CLR_ADDR(addr, 1 << (pin * 4 + 2));
94 REG_SET_ADDR(addr, 1 << (pin * 4 + 2));
97 void pin_set_pullup(u32 id, u32 pullup)
100 u32 bank = PINID_2_BANK(id);
101 u32 pin = PINID_2_PIN(id);
103 addr = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0;
106 REG_SET_ADDR(addr, 1 << pin);
108 REG_CLR_ADDR(addr, 1 << pin);
111 void pin_set_type(u32 id, enum pin_fun cfg)
114 u32 bank = PINID_2_BANK(id);
115 u32 pin = PINID_2_PIN(id);
118 addr = REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0;
119 addr += 0x20 * bank + 0x10 * (pin >> 4);
122 /* Don't use _CLR/_SET to prevent unwanted pin state transitions */
123 val = REG_RD_ADDR(addr);
124 val &= ~(0x3 << (pin * 2));
125 val |= (cfg & 0x3) << (pin * 2);
126 REG_WR_ADDR(addr, val);
129 void pin_set_group(struct pin_group *pin_group)
132 struct pin_desc *pin;
134 for (p = 0; p < pin_group->nr_pins; p++) {
135 pin = &pin_group->pins[p];
136 pin_set_type(pin->id, pin->fun);
137 pin_set_strength(pin->id, pin->strength);
138 pin_set_voltage(pin->id, pin->voltage);
139 pin_set_pullup(pin->id, pin->pullup);