2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
13 #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
14 #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
16 #define MXC_CCM_BASE CCM_BASE_ADDR
17 #define MXC_DPLL1_BASE PLL1_BASE_ADDR
18 #define MXC_DPLL2_BASE PLL2_BASE_ADDR
19 #define MXC_DPLL3_BASE PLL3_BASE_ADDR
21 /* PLL Register Offsets */
22 #define MXC_PLL_DP_CTL 0x00
23 #define MXC_PLL_DP_CONFIG 0x04
24 #define MXC_PLL_DP_OP 0x08
25 #define MXC_PLL_DP_MFD 0x0C
26 #define MXC_PLL_DP_MFN 0x10
27 #define MXC_PLL_DP_MFNMINUS 0x14
28 #define MXC_PLL_DP_MFNPLUS 0x18
29 #define MXC_PLL_DP_HFS_OP 0x1C
30 #define MXC_PLL_DP_HFS_MFD 0x20
31 #define MXC_PLL_DP_HFS_MFN 0x24
32 #define MXC_PLL_DP_MFN_TOGC 0x28
33 #define MXC_PLL_DP_DESTAT 0x2c
35 /* PLL Register Bit definitions */
36 #define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
37 #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
38 #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
39 #define MXC_PLL_DP_CTL_ADE 0x800
40 #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
41 #define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
42 #define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
43 #define MXC_PLL_DP_CTL_HFSM 0x80
44 #define MXC_PLL_DP_CTL_PRE 0x40
45 #define MXC_PLL_DP_CTL_UPEN 0x20
46 #define MXC_PLL_DP_CTL_RST 0x10
47 #define MXC_PLL_DP_CTL_RCP 0x8
48 #define MXC_PLL_DP_CTL_PLM 0x4
49 #define MXC_PLL_DP_CTL_BRM0 0x2
50 #define MXC_PLL_DP_CTL_LRF 0x1
52 #define MXC_PLL_DP_CONFIG_BIST 0x8
53 #define MXC_PLL_DP_CONFIG_SJC_CE 0x4
54 #define MXC_PLL_DP_CONFIG_AREN 0x2
55 #define MXC_PLL_DP_CONFIG_LDREQ 0x1
57 #define MXC_PLL_DP_OP_MFI_OFFSET 4
58 #define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
59 #define MXC_PLL_DP_OP_PDF_OFFSET 0
60 #define MXC_PLL_DP_OP_PDF_MASK 0xF
62 #define MXC_PLL_DP_MFD_OFFSET 0
63 #define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
65 #define MXC_PLL_DP_MFN_OFFSET 0x0
66 #define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
68 #define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
69 #define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
70 #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
71 #define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
73 #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
74 #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
76 /* Register addresses of CCM*/
77 #define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
78 #define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
79 #define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
80 #define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
81 #define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
82 #define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
83 #define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
84 #define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
85 #define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
86 #define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
87 #define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
88 #define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
89 #define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
90 #define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
91 #define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
92 #define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
93 #define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
94 #define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
95 #define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
96 #define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
97 #define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
98 #define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
99 #define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
100 #define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
101 #define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
102 #define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
103 #define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
104 #define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
105 #define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
106 #define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
107 #define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
108 #define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
109 #define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
110 #define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x84)
112 /* Define the bits in register CCR */
113 #define MXC_CCM_CCR_COSC_EN (1 << 12)
114 #define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
115 #define MXC_CCM_CCR_CAMP2_EN (1 << 10)
116 #define MXC_CCM_CCR_CAMP1_EN (1 << 9)
117 #define MXC_CCM_CCR_FPM_EN (1 << 8)
118 #define MXC_CCM_CCR_OSCNT_OFFSET (0)
119 #define MXC_CCM_CCR_OSCNT_MASK (0xFF)
121 /* Define the bits in register CCDR */
122 #define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
123 #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
124 #define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
126 /* Define the bits in register CSR */
127 #define MXC_CCM_CSR_COSR_READY (1 << 5)
128 #define MXC_CCM_CSR_LVS_VALUE (1 << 4)
129 #define MXC_CCM_CSR_CAMP2_READY (1 << 3)
130 #define MXC_CCM_CSR_CAMP1_READY (1 << 2)
131 #define MXC_CCM_CSR_FPM_READY (1 << 1)
132 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
134 /* Define the bits in register CCSR */
135 #define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
136 #define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
137 #define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
138 #define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
139 #define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
140 #define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
141 #define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
142 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
143 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
144 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
146 /* Define the bits in register CACRR */
147 #define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
148 #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
150 /* Define the bits in register CBCDR */
151 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
152 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
153 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
154 #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
155 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
156 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
157 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
158 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
159 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
160 #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
161 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
162 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
163 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
164 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
165 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
166 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
167 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
168 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
169 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
170 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
172 /* Define the bits in register CBCMR */
173 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
174 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
175 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
176 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
177 #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
178 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
179 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
180 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
181 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
182 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
183 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
184 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
185 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
186 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
188 /* Define the bits in register CSCMR1 */
189 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
190 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
191 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
192 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
193 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
194 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
195 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
196 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
197 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
198 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
199 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
200 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
201 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
202 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
203 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
204 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
205 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
206 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
207 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
208 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
209 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
210 #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
211 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
212 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
213 #define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
214 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
215 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
216 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
217 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
218 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
219 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
220 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
222 /* Define the bits in register CSCMR2 */
223 #define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET (26)
224 #define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK (0x7 << 26)
225 #define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
226 #define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
227 #define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
228 #define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
229 #define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
230 #define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
231 #define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
232 #define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
233 #define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
234 #define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
235 #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
236 #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
237 #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
238 #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
239 #define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
240 #define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
241 #define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
242 #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
243 #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
244 #define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
245 #define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
246 #define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
247 #define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
248 #define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
249 #define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
251 /* Define the bits in register CSCDR1 */
252 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
253 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
254 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
255 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
256 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
257 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
258 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
259 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
260 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
261 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
262 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
263 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
264 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
265 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
266 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
267 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
268 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
269 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
271 /* Define the bits in register CS1CDR and CS2CDR */
272 #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
273 #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
274 #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
275 #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
276 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
277 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
278 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
279 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
281 #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
282 #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
283 #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
284 #define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
285 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
286 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
287 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
288 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
290 /* Define the bits in register CDCDR */
291 #define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
292 #define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
293 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
294 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
295 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
296 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
297 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
298 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
299 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
300 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
301 #define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
302 #define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
303 #define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
304 #define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
305 #define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
306 #define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
308 /* Define the bits in register CHSCCDR */
309 #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
310 #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
311 #define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
312 #define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
313 #define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
314 #define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
315 #define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
316 #define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
318 /* Define the bits in register CSCDR2 */
319 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
320 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
321 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
322 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
323 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
324 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
325 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
326 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
327 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
328 #define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
329 #define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
330 #define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
332 /* Define the bits in register CSCDR3 */
333 #define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
334 #define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
335 #define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
336 #define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
337 #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
338 #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
339 #define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
340 #define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
342 /* Define the bits in register CSCDR4 */
343 #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
344 #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
345 #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
346 #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
347 #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
348 #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
349 #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
350 #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
352 /* Define the bits in register CDHIPR */
353 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
354 #define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
355 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
356 #define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
357 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
358 #define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
359 #define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
360 #define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
362 /* Define the bits in register CDCR */
363 #define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
364 #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
365 #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
367 /* Define the bits in register CLPCR */
368 #define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
369 #define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
370 #define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
371 #define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
372 #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
373 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
374 #define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
375 #define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
376 #define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
377 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
378 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
379 #define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
380 #define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
381 #define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
382 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
383 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
384 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
385 #define MXC_CCM_CLPCR_LPM_OFFSET (0)
386 #define MXC_CCM_CLPCR_LPM_MASK (0x3)
388 /* Define the bits in register CISR */
389 #define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
390 #define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
391 #define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
392 #define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
393 #define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
394 #define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
395 #define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
396 #define MXC_CCM_CISR_COSC_READY (0x1 << 6)
397 #define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
398 #define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
399 #define MXC_CCM_CISR_FPM_READY (0x1 << 3)
400 #define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
401 #define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
402 #define MXC_CCM_CISR_LRF_PLL1 (0x1)
404 /* Define the bits in register CIMR */
405 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
406 #define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
407 #define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
408 #define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
409 #define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
410 #define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
411 #define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
412 #define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
413 #define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
414 #define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
415 #define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
416 #define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
417 #define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
419 /* Define the bits in register CCOSR */
420 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
421 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
422 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
423 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
424 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
425 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
426 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
427 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
428 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
429 #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
431 /* Define the bits in registers CGPR */
432 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
433 #define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
434 #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
435 #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
437 /* Define the bits in registers CCGRx */
438 #define MXC_CCM_CCGR_CG_MASK 0x3
440 #define MXC_CCM_CCGR0_CG15_OFFSET 30
441 #define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
442 #define MXC_CCM_CCGR0_CG14_OFFSET 28
443 #define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
444 #define MXC_CCM_CCGR0_CG13_OFFSET 26
445 #define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
446 #define MXC_CCM_CCGR0_CG12_OFFSET 24
447 #define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
448 #define MXC_CCM_CCGR0_CG11_OFFSET 22
449 #define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
450 #define MXC_CCM_CCGR0_CG10_OFFSET 20
451 #define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
452 #define MXC_CCM_CCGR0_CG9_OFFSET 18
453 #define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
454 #define MXC_CCM_CCGR0_CG8_OFFSET 16
455 #define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
456 #define MXC_CCM_CCGR0_CG7_OFFSET 14
457 #define MXC_CCM_CCGR0_CG6_OFFSET 12
458 #define MXC_CCM_CCGR0_CG5_OFFSET 10
459 #define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
460 #define MXC_CCM_CCGR0_CG4_OFFSET 8
461 #define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
462 #define MXC_CCM_CCGR0_CG3_OFFSET 6
463 #define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
464 #define MXC_CCM_CCGR0_CG2_OFFSET 4
465 #define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
466 #define MXC_CCM_CCGR0_CG1_OFFSET 2
467 #define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
468 #define MXC_CCM_CCGR0_CG0_OFFSET 0
469 #define MXC_CCM_CCGR0_CG0_MASK 0x3
471 #define MXC_CCM_CCGR1_CG15_OFFSET 30
472 #define MXC_CCM_CCGR1_CG14_OFFSET 28
473 #define MXC_CCM_CCGR1_CG13_OFFSET 26
474 #define MXC_CCM_CCGR1_CG12_OFFSET 24
475 #define MXC_CCM_CCGR1_CG11_OFFSET 22
476 #define MXC_CCM_CCGR1_CG10_OFFSET 20
477 #define MXC_CCM_CCGR1_CG9_OFFSET 18
478 #define MXC_CCM_CCGR1_CG8_OFFSET 16
479 #define MXC_CCM_CCGR1_CG7_OFFSET 14
480 #define MXC_CCM_CCGR1_CG6_OFFSET 12
481 #define MXC_CCM_CCGR1_CG5_OFFSET 10
482 #define MXC_CCM_CCGR1_CG4_OFFSET 8
483 #define MXC_CCM_CCGR1_CG3_OFFSET 6
484 #define MXC_CCM_CCGR1_CG2_OFFSET 4
485 #define MXC_CCM_CCGR1_CG1_OFFSET 2
486 #define MXC_CCM_CCGR1_CG0_OFFSET 0
488 #define MXC_CCM_CCGR2_CG15_OFFSET 30
489 #define MXC_CCM_CCGR2_CG14_OFFSET 28
490 #define MXC_CCM_CCGR2_CG13_OFFSET 26
491 #define MXC_CCM_CCGR2_CG12_OFFSET 24
492 #define MXC_CCM_CCGR2_CG11_OFFSET 22
493 #define MXC_CCM_CCGR2_CG10_OFFSET 20
494 #define MXC_CCM_CCGR2_CG9_OFFSET 18
495 #define MXC_CCM_CCGR2_CG8_OFFSET 16
496 #define MXC_CCM_CCGR2_CG7_OFFSET 14
497 #define MXC_CCM_CCGR2_CG6_OFFSET 12
498 #define MXC_CCM_CCGR2_CG5_OFFSET 10
499 #define MXC_CCM_CCGR2_CG4_OFFSET 8
500 #define MXC_CCM_CCGR2_CG3_OFFSET 6
501 #define MXC_CCM_CCGR2_CG2_OFFSET 4
502 #define MXC_CCM_CCGR2_CG1_OFFSET 2
503 #define MXC_CCM_CCGR2_CG0_OFFSET 0
505 #define MXC_CCM_CCGR3_CG15_OFFSET 30
506 #define MXC_CCM_CCGR3_CG14_OFFSET 28
507 #define MXC_CCM_CCGR3_CG13_OFFSET 26
508 #define MXC_CCM_CCGR3_CG12_OFFSET 24
509 #define MXC_CCM_CCGR3_CG11_OFFSET 22
510 #define MXC_CCM_CCGR3_CG10_OFFSET 20
511 #define MXC_CCM_CCGR3_CG9_OFFSET 18
512 #define MXC_CCM_CCGR3_CG8_OFFSET 16
513 #define MXC_CCM_CCGR3_CG7_OFFSET 14
514 #define MXC_CCM_CCGR3_CG6_OFFSET 12
515 #define MXC_CCM_CCGR3_CG5_OFFSET 10
516 #define MXC_CCM_CCGR3_CG4_OFFSET 8
517 #define MXC_CCM_CCGR3_CG3_OFFSET 6
518 #define MXC_CCM_CCGR3_CG2_OFFSET 4
519 #define MXC_CCM_CCGR3_CG1_OFFSET 2
520 #define MXC_CCM_CCGR3_CG0_OFFSET 0
522 #define MXC_CCM_CCGR4_CG15_OFFSET 30
523 #define MXC_CCM_CCGR4_CG14_OFFSET 28
524 #define MXC_CCM_CCGR4_CG13_OFFSET 26
525 #define MXC_CCM_CCGR4_CG12_OFFSET 24
526 #define MXC_CCM_CCGR4_CG11_OFFSET 22
527 #define MXC_CCM_CCGR4_CG10_OFFSET 20
528 #define MXC_CCM_CCGR4_CG9_OFFSET 18
529 #define MXC_CCM_CCGR4_CG8_OFFSET 16
530 #define MXC_CCM_CCGR4_CG7_OFFSET 14
531 #define MXC_CCM_CCGR4_CG6_OFFSET 12
532 #define MXC_CCM_CCGR4_CG5_OFFSET 10
533 #define MXC_CCM_CCGR4_CG4_OFFSET 8
534 #define MXC_CCM_CCGR4_CG3_OFFSET 6
535 #define MXC_CCM_CCGR4_CG2_OFFSET 4
536 #define MXC_CCM_CCGR4_CG1_OFFSET 2
537 #define MXC_CCM_CCGR4_CG0_OFFSET 0
539 #define MXC_CCM_CCGR5_CG15_OFFSET 30
540 #define MXC_CCM_CCGR5_CG14_OFFSET 28
541 #define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
542 #define MXC_CCM_CCGR5_CG13_OFFSET 26
543 #define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
544 #define MXC_CCM_CCGR5_CG12_OFFSET 24
545 #define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
546 #define MXC_CCM_CCGR5_CG11_OFFSET 22
547 #define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
548 #define MXC_CCM_CCGR5_CG10_OFFSET 20
549 #define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
550 #define MXC_CCM_CCGR5_CG9_OFFSET 18
551 #define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
552 #define MXC_CCM_CCGR5_CG8_OFFSET 16
553 #define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
554 #define MXC_CCM_CCGR5_CG7_OFFSET 14
555 #define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
556 #define MXC_CCM_CCGR5_CG6_OFFSET 12
557 #define MXC_CCM_CCGR5_CG5_OFFSET 10
558 #define MXC_CCM_CCGR5_CG4_OFFSET 8
559 #define MXC_CCM_CCGR5_CG3_OFFSET 6
560 #define MXC_CCM_CCGR5_CG2_OFFSET 4
561 #define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
562 #define MXC_CCM_CCGR5_CG1_OFFSET 2
563 #define MXC_CCM_CCGR5_CG0_OFFSET 0
565 #define MXC_CCM_CCGR6_CG4_OFFSET 8
566 #define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8)
567 #define MXC_CCM_CCGR6_CG3_OFFSET 6
568 #define MXC_CCM_CCGR6_CG2_OFFSET 4
569 #define MXC_CCM_CCGR6_CG1_OFFSET 2
570 #define MXC_CCM_CCGR6_CG0_OFFSET 0
572 #define MXC_CORTEXA8_BASE ARM_BASE_ADDR
573 #define MXC_GPC_BASE GPC_BASE_ADDR
574 #define MXC_DPTC_LP_BASE (GPC_BASE_ADDR + 0x80)
575 #define MXC_DPTC_GP_BASE (GPC_BASE_ADDR + 0x100)
576 #define MXC_DVFS_CORE_BASE (GPC_BASE_ADDR + 0x180)
577 #define MXC_DPTC_PER_BASE (GPC_BASE_ADDR + 0x1C0)
578 #define MXC_PGC_IPU_BASE (GPC_BASE_ADDR + 0x220)
579 #define MXC_PGC_VPU_BASE (GPC_BASE_ADDR + 0x240)
580 #define MXC_PGC_GPU_BASE (GPC_BASE_ADDR + 0x260)
581 #define MXC_SRPG_NEON_BASE (GPC_BASE_ADDR + 0x280)
582 #define MXC_SRPG_ARM_BASE (GPC_BASE_ADDR + 0x2A0)
583 #define MXC_SRPG_EMPGC0_BASE (GPC_BASE_ADDR + 0x2C0)
584 #define MXC_SRPG_EMPGC1_BASE (GPC_BASE_ADDR + 0x2D0)
585 #define MXC_SRPG_MEGAMIX_BASE (GPC_BASE_ADDR + 0x2E0)
586 #define MXC_SRPG_EMI_BASE (GPC_BASE_ADDR + 0x300)
588 /* CORTEXA8 platform */
589 #define MXC_CORTEXA8_PLAT_PVID (MXC_CORTEXA8_BASE + 0x0)
590 #define MXC_CORTEXA8_PLAT_GPC (MXC_CORTEXA8_BASE + 0x4)
591 #define MXC_CORTEXA8_PLAT_PIC (MXC_CORTEXA8_BASE + 0x8)
592 #define MXC_CORTEXA8_PLAT_LPC (MXC_CORTEXA8_BASE + 0xC)
593 #define MXC_CORTEXA8_PLAT_NEON_LPC (MXC_CORTEXA8_BASE + 0x10)
594 #define MXC_CORTEXA8_PLAT_ICGC (MXC_CORTEXA8_BASE + 0x14)
595 #define MXC_CORTEXA8_PLAT_AMC (MXC_CORTEXA8_BASE + 0x18)
596 #define MXC_CORTEXA8_PLAT_NMC (MXC_CORTEXA8_BASE + 0x20)
597 #define MXC_CORTEXA8_PLAT_NMS (MXC_CORTEXA8_BASE + 0x24)
600 #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
601 #define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
602 #define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
603 #define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
604 #define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
605 #define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
606 #define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
607 #define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
608 #define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
609 #define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
610 #define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
611 #define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
612 #define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
613 #define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
614 #define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
615 #define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
616 #define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
619 #define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0)
620 #define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
621 #define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
622 #define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC)
623 #define MXC_GPC_NEON (MXC_GPC_BASE + 0x10)
624 #define MXC_GPC_PGR_ARMPG_OFFSET 8
625 #define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
628 #define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
629 #define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
630 #define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
631 #define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
632 #define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
633 #define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
635 #define MXC_PGCR_PCR 1
636 #define MXC_SRPGCR_PCR 1
637 #define MXC_EMPGCR_PCR 1
638 #define MXC_PGSR_PSR 1
641 #define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
642 #define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
645 #define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
646 #define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
647 #define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
649 #define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
650 #define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
651 #define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
653 #define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
654 #define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
655 #define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
657 #define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
658 #define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
659 #define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
661 #define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
662 #define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
663 #define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
665 #define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
666 #define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
667 #define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
669 #endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */