2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
15 * @defgroup GPIO_MX51 Board GPIO and Muxing Setup
19 * @file mach-mx51/iomux.c
21 * @brief I/O Muxing control functions
27 #include <asm/arch/mx51.h>
28 #include <asm/arch/mx51_pins.h>
29 #include <asm/arch/iomux.h>
32 * IOMUX register (base) addresses
35 IOMUXGPR0 = IOMUXC_BASE_ADDR,
36 IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
37 IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
38 IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
39 IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
40 IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
43 #define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
45 static inline u32 _get_mux_reg(iomux_pin_name_t pin)
47 u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
49 if (is_soc_rev(CHIP_REV_2_0) < 0) {
50 if ((pin == MX51_PIN_NANDF_RB5) ||
51 (pin == MX51_PIN_NANDF_RB6) ||
52 (pin == MX51_PIN_NANDF_RB7))
54 else if (mux_reg >= 0x2FC)
56 else if (mux_reg >= 0x130)
59 mux_reg += IOMUXSW_MUX_CTL;
63 static inline u32 _get_pad_reg(iomux_pin_name_t pin)
65 u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
67 if (is_soc_rev(CHIP_REV_2_0) < 0) {
68 if ((pin == MX51_PIN_NANDF_RB5) ||
69 (pin == MX51_PIN_NANDF_RB6) ||
70 (pin == MX51_PIN_NANDF_RB7))
72 else if (pad_reg == 0x4D0 - PAD_I_START)
74 else if (pad_reg == 0x860 - PAD_I_START)
76 else if (pad_reg >= 0x804 - PAD_I_START)
78 else if (pad_reg >= 0x7FC - PAD_I_START)
80 else if (pad_reg >= 0x4E4 - PAD_I_START)
85 pad_reg += IOMUXSW_PAD_CTL;
89 static inline u32 _get_mux_end()
91 if (is_soc_rev(CHIP_REV_2_0) < 0)
92 return IOMUXC_BASE_ADDR + (0x3F8 - 4);
94 return IOMUXC_BASE_ADDR + (0x3F0 - 4);
98 * This function is used to configure a pin through the IOMUX module.
99 * FIXED ME: for backward compatible. Will be static function!
100 * @param pin a pin number as defined in \b #iomux_pin_name_t
101 * @param cfg an output function as defined in \b #iomux_pin_cfg_t
103 * @return 0 if successful; Non-zero otherwise
105 static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
107 u32 mux_reg = _get_mux_reg(pin);
109 if ((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
111 if (cfg == IOMUX_CONFIG_GPIO)
112 writel(PIN_TO_ALT_GPIO(pin), mux_reg);
114 writel(cfg, mux_reg);
120 * Request ownership for an IO pin. This function has to be the first one
121 * being called before that pin is used. The caller has to check the
122 * return value to make sure it returns 0.
124 * @param pin a name defined by \b iomux_pin_name_t
125 * @param cfg an input function as defined in \b #iomux_pin_cfg_t
127 * @return 0 if successful; Non-zero otherwise
129 int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
131 int ret = iomux_config_mux(pin, cfg);
136 * Release ownership for an IO pin
138 * @param pin a name defined by \b iomux_pin_name_t
139 * @param cfg an input function as defined in \b #iomux_pin_cfg_t
141 void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
146 * This function configures the pad value for a IOMUX pin.
148 * @param pin a pin number as defined in \b #iomux_pin_name_t
149 * @param config the ORed value of elements defined in \b #iomux_pad_config_t
151 void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
153 u32 pad_reg = _get_pad_reg(pin);
154 writel(config, pad_reg);
157 unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
159 u32 pad_reg = _get_pad_reg(pin);
160 return readl(pad_reg);
163 * This function configures input path.
165 * @param input index of input select register as defined in \b
166 * #iomux_input_select_t
167 * @param config the binary value of elements defined in \b
168 * #iomux_input_config_t
170 void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
172 u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
174 if (is_soc_rev(CHIP_REV_2_0) < 0) {
175 if (input == MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT)
178 MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT)
180 else if (input >= MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT)
183 MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT)
186 MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT)
188 else if (input >= MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT)
190 else if (input >= MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT)
193 reg += INPUT_CTL_START_TO1;
195 reg += INPUT_CTL_START;