cpu/mpc8260/i2c.c

   1 /*
   2  * (C) Copyright 2000
   3  * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
   4  *
   5  * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   6  * Marius Groeger <mgroeger@sysgo.de>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28
  29 #if defined(CONFIG_HARD_I2C)
  30
  31 #include <asm/cpm_8260.h>
  32 #include <i2c.h>
  33
  34 /* define to enable debug messages */
  35 #undef  DEBUG_I2C
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #if defined(CONFIG_I2C_MULTI_BUS)
  40 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
  41 #endif /* CONFIG_I2C_MULTI_BUS */
  42
  43 /* uSec to wait between polls of the i2c */
  44 #define DELAY_US        100
  45 /* uSec to wait for the CPM to start processing the buffer */
  46 #define START_DELAY_US  1000
  47
  48 /*
  49  * tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the
  50  * timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP
  51  */
  52 #define TOUT_LOOP 5
  53
  54 /*-----------------------------------------------------------------------
  55  * Set default values
  56  */
  57 #ifndef CONFIG_SYS_I2C_SPEED
  58 #define CONFIG_SYS_I2C_SPEED    50000
  59 #endif
  60
  61 #ifndef CONFIG_SYS_I2C_SLAVE
  62 #define CONFIG_SYS_I2C_SLAVE    0xFE
  63 #endif
  64 /*-----------------------------------------------------------------------
  65  */
  66
  67 typedef void (*i2c_ecb_t)(int, int, void *);    /* error callback function */
  68
  69 /* This structure keeps track of the bd and buffer space usage. */
  70 typedef struct i2c_state {
  71         int             rx_idx;         /* index   to next free Rx BD */
  72         int             tx_idx;         /* index   to next free Tx BD */
  73         void            *rxbd;          /* pointer to next free Rx BD */
  74         void            *txbd;          /* pointer to next free Tx BD */
  75         int             tx_space;       /* number  of Tx bytes left   */
  76         unsigned char   *tx_buf;        /* pointer to free Tx area    */
  77         i2c_ecb_t       err_cb;         /* error callback function    */
  78         void            *cb_data;       /* private data to be passed  */
  79 } i2c_state_t;
  80
  81 /* flags for i2c_send() and i2c_receive() */
  82 #define I2CF_ENABLE_SECONDARY   0x01    /* secondary_address is valid   */
  83 #define I2CF_START_COND         0x02    /* tx: generate start condition */
  84 #define I2CF_STOP_COND          0x04    /* tx: generate stop  condition */
  85
  86 /* return codes */
  87 #define I2CERR_NO_BUFFERS       1       /* no more BDs or buffer space  */
  88 #define I2CERR_MSG_TOO_LONG     2       /* tried to send/receive to much data   */
  89 #define I2CERR_TIMEOUT          3       /* timeout in i2c_doio()        */
  90 #define I2CERR_QUEUE_EMPTY      4       /* i2c_doio called without send/receive */
  91 #define I2CERR_IO_ERROR         5       /* had an error during comms    */
  92
  93 /* error callback flags */
  94 #define I2CECB_RX_ERR           0x10    /* this is a receive error      */
  95 #define     I2CECB_RX_OV        0x02    /* receive overrun error        */
  96 #define     I2CECB_RX_MASK      0x0f    /* mask for error bits          */
  97 #define I2CECB_TX_ERR           0x20    /* this is a transmit error     */
  98 #define     I2CECB_TX_CL        0x01    /* transmit collision error     */
  99 #define     I2CECB_TX_UN        0x02    /* transmit underflow error     */
 100 #define     I2CECB_TX_NAK       0x04    /* transmit no ack error        */
 101 #define     I2CECB_TX_MASK      0x0f    /* mask for error bits          */
 102 #define I2CECB_TIMEOUT          0x40    /* this is a timeout error      */
 103
 104 #define ERROR_I2C_NONE          0
 105 #define ERROR_I2C_LENGTH        1
 106
 107 #define I2C_WRITE_BIT           0x00
 108 #define I2C_READ_BIT            0x01
 109
 110 #define I2C_RXTX_LEN    128     /* maximum tx/rx buffer length */
 111
 112
 113 #define NUM_RX_BDS 4
 114 #define NUM_TX_BDS 4
 115 #define MAX_TX_SPACE 256
 116
 117 typedef struct I2C_BD
 118 {
 119   unsigned short status;
 120   unsigned short length;
 121   unsigned char *addr;
 122 } I2C_BD;
 123 #define BD_I2C_TX_START 0x0400  /* special status for i2c: Start condition */
 124
 125 #define BD_I2C_TX_CL    0x0001  /* collision error */
 126 #define BD_I2C_TX_UN    0x0002  /* underflow error */
 127 #define BD_I2C_TX_NAK   0x0004  /* no acknowledge error */
 128 #define BD_I2C_TX_ERR   (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
 129
 130 #define BD_I2C_RX_ERR   BD_SC_OV
 131
 132 #ifdef DEBUG_I2C
 133 #define PRINTD(x) printf x
 134 #else
 135 #define PRINTD(x)
 136 #endif
 137
 138 /*
 139  * Returns the best value of I2BRG to meet desired clock speed of I2C with
 140  * input parameters (clock speed, filter, and predivider value).
 141  * It returns computer speed value and the difference between it and desired
 142  * speed.
 143  */
 144 static inline int
 145 i2c_roundrate(int hz, int speed, int filter, int modval,
 146                 int *brgval, int *totspeed)
 147 {
 148     int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
 149
 150     PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
 151         hz, speed, filter, modval));
 152
 153     div = moddiv * speed;
 154     brgdiv = (hz + div - 1) / div;
 155
 156     PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
 157
 158     *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter);
 159
 160     if ((*brgval < 0) || (*brgval > 255)) {
 161           PRINTD(("\t\trejected brgval=%d\n", *brgval));
 162           return -1;
 163     }
 164
 165     brgdiv = 2 * (*brgval + 3 + (2 * filter));
 166     div = moddiv * brgdiv ;
 167     *totspeed = hz / div;
 168
 169     PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
 170
 171     return  0;
 172 }
 173
 174 /*
 175  * Sets the I2C clock predivider and divider to meet required clock speed.
 176  */
 177 static int i2c_setrate(int hz, int speed)
 178 {
 179     immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR ;
 180     volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
 181     int brgval,
 182           modval,       /* 0-3 */
 183           bestspeed_diff = speed,
 184           bestspeed_brgval=0,
 185           bestspeed_modval=0,
 186           bestspeed_filter=0,
 187           totspeed,
 188           filter = 0; /* Use this fixed value */
 189
 190         for (modval = 0; modval < 4; modval++)
 191         {
 192                 if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0)
 193                 {
 194                         int diff = speed - totspeed ;
 195
 196                         if ((diff >= 0) && (diff < bestspeed_diff))
 197                         {
 198                                 bestspeed_diff  = diff ;
 199                                 bestspeed_modval        = modval;
 200                                 bestspeed_brgval        = brgval;
 201                                 bestspeed_filter        = filter;
 202                         }
 203                 }
 204         }
 205
 206     PRINTD(("[I2C] Best is:\n"));
 207     PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
 208                    hz, speed,
 209                    bestspeed_filter, bestspeed_modval, bestspeed_brgval,
 210                    bestspeed_diff));
 211
 212     i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
 213     i2c->i2c_i2brg = bestspeed_brgval & 0xff;
 214
 215     PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg));
 216
 217     return 1 ;
 218 }
 219
 220 void i2c_init(int speed, int slaveadd)
 221 {
 222         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
 223         volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
 224         volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
 225         volatile iic_t *iip;
 226         ulong rbase, tbase;
 227         volatile I2C_BD *rxbd, *txbd;
 228         uint dpaddr;
 229
 230 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 231         /* call board specific i2c bus reset routine before accessing the   */
 232         /* environment, which might be in a chip on that bus. For details   */
 233         /* about this problem see doc/I2C_Edge_Conditions.                  */
 234         i2c_init_board();
 235 #endif
 236
 237         dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
 238         if (dpaddr == 0) {
 239             /* need to allocate dual port ram */
 240             dpaddr = m8260_cpm_dpalloc(64 +
 241                 (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
 242                 MAX_TX_SPACE, 64);
 243             *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])) = dpaddr;
 244         }
 245
 246         /*
 247          * initialise data in dual port ram:
 248          *
 249          *        dpaddr -> parameter ram (64 bytes)
 250          *         rbase -> rx BD         (NUM_RX_BDS * sizeof(I2C_BD) bytes)
 251          *         tbase -> tx BD         (NUM_TX_BDS * sizeof(I2C_BD) bytes)
 252          *                  tx buffer     (MAX_TX_SPACE bytes)
 253          */
 254
 255         iip = (iic_t *)&immap->im_dprambase[dpaddr];
 256         memset((void*)iip, 0, sizeof(iic_t));
 257
 258         rbase = dpaddr + 64;
 259         tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
 260
 261         /* Disable interrupts */
 262         i2c->i2c_i2mod = 0x00;
 263         i2c->i2c_i2cmr = 0x00;
 264         i2c->i2c_i2cer = 0xff;
 265         i2c->i2c_i2add = slaveadd;
 266
 267         /*
 268          * Set the I2C BRG Clock division factor from desired i2c rate
 269          * and current CPU rate (we assume sccr dfbgr field is 0;
 270          * divide BRGCLK by 1)
 271          */
 272         PRINTD(("[I2C] Setting rate...\n"));
 273         i2c_setrate (gd->brg_clk, CONFIG_SYS_I2C_SPEED) ;
 274
 275         /* Set I2C controller in master mode */
 276         i2c->i2c_i2com = 0x01;
 277
 278         /* Initialize Tx/Rx parameters */
 279         iip->iic_rbase = rbase;
 280         iip->iic_tbase = tbase;
 281         rxbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_rbase]);
 282         txbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_tbase]);
 283
 284         PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
 285         PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
 286         PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
 287         PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
 288
 289         /* Set big endian byte order */
 290         iip->iic_tfcr = 0x10;
 291         iip->iic_rfcr = 0x10;
 292
 293         /* Set maximum receive size. */
 294         iip->iic_mrblr = I2C_RXTX_LEN;
 295
 296     cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
 297                                                         CPM_CR_I2C_SBLOCK,
 298                                                         0x00,
 299                                                         CPM_CR_INIT_TRX) | CPM_CR_FLG;
 300     do {
 301                 __asm__ __volatile__ ("eieio");
 302     } while (cp->cp_cpcr & CPM_CR_FLG);
 303
 304         /* Clear events and interrupts */
 305         i2c->i2c_i2cer = 0xff;
 306         i2c->i2c_i2cmr = 0x00;
 307 }
 308
 309 static
 310 void i2c_newio(i2c_state_t *state)
 311 {
 312         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
 313         volatile iic_t *iip;
 314         uint dpaddr;
 315
 316         PRINTD(("[I2C] i2c_newio\n"));
 317
 318         dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
 319         iip = (iic_t *)&immap->im_dprambase[dpaddr];
 320         state->rx_idx = 0;
 321         state->tx_idx = 0;
 322         state->rxbd = (void*)&immap->im_dprambase[iip->iic_rbase];
 323         state->txbd = (void*)&immap->im_dprambase[iip->iic_tbase];
 324         state->tx_space = MAX_TX_SPACE;
 325         state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
 326         state->err_cb = NULL;
 327         state->cb_data = NULL;
 328
 329         PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
 330         PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
 331         PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
 332
 333         /* clear the buffer memory */
 334         memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
 335 }
 336
 337 static
 338 int i2c_send(i2c_state_t *state,
 339                          unsigned char address,
 340                          unsigned char secondary_address,
 341                          unsigned int flags,
 342                          unsigned short size,
 343                          unsigned char *dataout)
 344 {
 345         volatile I2C_BD *txbd;
 346         int i,j;
 347
 348         PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
 349                         address, secondary_address, flags, size));
 350
 351         /* trying to send message larger than BD */
 352         if (size > I2C_RXTX_LEN)
 353           return I2CERR_MSG_TOO_LONG;
 354
 355         /* no more free bds */
 356         if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
 357           return I2CERR_NO_BUFFERS;
 358
 359         txbd = (I2C_BD *)state->txbd;
 360         txbd->addr = state->tx_buf;
 361
 362         PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
 363
 364     if (flags & I2CF_START_COND)
 365     {
 366         PRINTD(("[I2C] Formatting addresses...\n"));
 367         if (flags & I2CF_ENABLE_SECONDARY)
 368         {
 369                 txbd->length = size + 2;  /* Length of message plus dest addresses */
 370                 txbd->addr[0] = address << 1;
 371                 txbd->addr[1] = secondary_address;
 372                 i = 2;
 373         }
 374         else
 375         {
 376                 txbd->length = size + 1;  /* Length of message plus dest address */
 377                 txbd->addr[0] = address << 1;  /* Write destination address to BD */
 378                 i = 1;
 379         }
 380     }
 381     else
 382     {
 383         txbd->length = size;  /* Length of message */
 384         i = 0;
 385     }
 386
 387         /* set up txbd */
 388         txbd->status = BD_SC_READY;
 389         if (flags & I2CF_START_COND)
 390           txbd->status |= BD_I2C_TX_START;
 391         if (flags & I2CF_STOP_COND)
 392           txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 393
 394         /* Copy data to send into buffer */
 395         PRINTD(("[I2C] copy data...\n"));
 396         for(j = 0; j < size; i++, j++)
 397           txbd->addr[i] = dataout[j];
 398
 399         PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 400                    txbd->length,
 401                    txbd->status,
 402                    txbd->addr[0],
 403                    txbd->addr[1]));
 404
 405         /* advance state */
 406         state->tx_buf += txbd->length;
 407         state->tx_space -= txbd->length;
 408         state->tx_idx++;
 409         state->txbd = (void*)(txbd + 1);
 410
 411         return 0;
 412 }
 413
 414 static
 415 int i2c_receive(i2c_state_t *state,
 416                                 unsigned char address,
 417                                 unsigned char secondary_address,
 418                                 unsigned int flags,
 419                                 unsigned short size_to_expect,
 420                                 unsigned char *datain)
 421 {
 422         volatile I2C_BD *rxbd, *txbd;
 423
 424         PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
 425
 426         /* Expected to receive too much */
 427         if (size_to_expect > I2C_RXTX_LEN)
 428           return I2CERR_MSG_TOO_LONG;
 429
 430         /* no more free bds */
 431         if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
 432                  || state->tx_space < 2)
 433           return I2CERR_NO_BUFFERS;
 434
 435         rxbd = (I2C_BD *)state->rxbd;
 436         txbd = (I2C_BD *)state->txbd;
 437
 438         PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
 439         PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
 440
 441         txbd->addr = state->tx_buf;
 442
 443         /* set up TXBD for destination address */
 444         if (flags & I2CF_ENABLE_SECONDARY)
 445         {
 446                 txbd->length = 2;
 447                 txbd->addr[0] = address << 1;   /* Write data */
 448                 txbd->addr[1] = secondary_address;  /* Internal address */
 449                 txbd->status = BD_SC_READY;
 450         }
 451         else
 452         {
 453                 txbd->length = 1 + size_to_expect;
 454                 txbd->addr[0] = (address << 1) | 0x01;
 455                 txbd->status = BD_SC_READY;
 456                 memset(&txbd->addr[1], 0, txbd->length);
 457         }
 458
 459         /* set up rxbd for reception */
 460         rxbd->status = BD_SC_EMPTY;
 461         rxbd->length = size_to_expect;
 462         rxbd->addr = datain;
 463
 464         txbd->status |= BD_I2C_TX_START;
 465         if (flags & I2CF_STOP_COND)
 466         {
 467                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 468                 rxbd->status |= BD_SC_WRAP;
 469         }
 470
 471         PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 472                    txbd->length,
 473                    txbd->status,
 474                    txbd->addr[0],
 475                    txbd->addr[1]));
 476         PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 477                    rxbd->length,
 478                    rxbd->status,
 479                    rxbd->addr[0],
 480                    rxbd->addr[1]));
 481
 482         /* advance state */
 483         state->tx_buf += txbd->length;
 484         state->tx_space -= txbd->length;
 485         state->tx_idx++;
 486         state->txbd = (void*)(txbd + 1);
 487         state->rx_idx++;
 488         state->rxbd = (void*)(rxbd + 1);
 489
 490         return 0;
 491 }
 492
 493
 494 static
 495 int i2c_doio(i2c_state_t *state)
 496 {
 497         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
 498         volatile iic_t *iip;
 499         volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
 500         volatile I2C_BD *txbd, *rxbd;
 501         int  n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
 502         uint dpaddr;
 503
 504         PRINTD(("[I2C] i2c_doio\n"));
 505
 506         if (state->tx_idx <= 0 && state->rx_idx <= 0) {
 507                 PRINTD(("[I2C] No I/O is queued\n"));
 508                 return I2CERR_QUEUE_EMPTY;
 509         }
 510
 511         dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
 512         iip = (iic_t *)&immap->im_dprambase[dpaddr];
 513         iip->iic_rbptr = iip->iic_rbase;
 514         iip->iic_tbptr = iip->iic_tbase;
 515
 516         /* Enable I2C */
 517         PRINTD(("[I2C] Enabling I2C...\n"));
 518         i2c->i2c_i2mod |= 0x01;
 519
 520         /* Begin transmission */
 521         i2c->i2c_i2com |= 0x80;
 522
 523         /* Loop until transmit & receive completed */
 524
 525         if ((n = state->tx_idx) > 0) {
 526
 527                 txbd = ((I2C_BD*)state->txbd) - n;
 528                 for (i = 0; i < n; i++) {
 529                         txtimeo += TOUT_LOOP * txbd->length;
 530                         txbd++;
 531                 }
 532
 533                 txbd--; /* wait until last in list is done */
 534
 535                 PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
 536
 537                 udelay(START_DELAY_US); /* give it time to start */
 538                 while((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) {
 539                         udelay(DELAY_US);
 540                         if (ctrlc())
 541                                 return (-1);
 542                         __asm__ __volatile__ ("eieio");
 543                 }
 544         }
 545
 546         if (txcnt < txtimeo && (n = state->rx_idx) > 0) {
 547
 548                 rxbd = ((I2C_BD*)state->rxbd) - n;
 549                 for (i = 0; i < n; i++) {
 550                         rxtimeo += TOUT_LOOP * rxbd->length;
 551                         rxbd++;
 552                 }
 553
 554                 rxbd--; /* wait until last in list is done */
 555
 556                 PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
 557
 558                 udelay(START_DELAY_US); /* give it time to start */
 559                 while((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) {
 560                         udelay(DELAY_US);
 561                         if (ctrlc())
 562                                 return (-1);
 563                         __asm__ __volatile__ ("eieio");
 564                 }
 565         }
 566
 567         /* Turn off I2C */
 568         i2c->i2c_i2mod &= ~0x01;
 569
 570         if ((n = state->tx_idx) > 0) {
 571                 for (i = 0; i < n; i++) {
 572                         txbd = ((I2C_BD*)state->txbd) - (n - i);
 573                         if ((b = txbd->status & BD_I2C_TX_ERR) != 0) {
 574                                 if (state->err_cb != NULL)
 575                                         (*state->err_cb)(I2CECB_TX_ERR|b, i,
 576                                                 state->cb_data);
 577                                 if (rc == 0)
 578                                         rc = I2CERR_IO_ERROR;
 579                         }
 580                 }
 581         }
 582
 583         if ((n = state->rx_idx) > 0) {
 584                 for (i = 0; i < n; i++) {
 585                         rxbd = ((I2C_BD*)state->rxbd) - (n - i);
 586                         if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) {
 587                                 if (state->err_cb != NULL)
 588                                         (*state->err_cb)(I2CECB_RX_ERR|b, i,
 589                                                 state->cb_data);
 590                                 if (rc == 0)
 591                                         rc = I2CERR_IO_ERROR;
 592                         }
 593                 }
 594         }
 595
 596         if ((txtimeo > 0 && txcnt >= txtimeo) || \
 597             (rxtimeo > 0 && rxcnt >= rxtimeo)) {
 598                 if (state->err_cb != NULL)
 599                         (*state->err_cb)(I2CECB_TIMEOUT, -1, state->cb_data);
 600                 if (rc == 0)
 601                         rc = I2CERR_TIMEOUT;
 602         }
 603
 604         return (rc);
 605 }
 606
 607 static void
 608 i2c_probe_callback(int flags, int xnum, void *data)
 609 {
 610         /*
 611          * the only acceptable errors are a transmit NAK or a receive
 612          * overrun - tx NAK means the device does not exist, rx OV
 613          * means the device must have responded to the slave address
 614          * even though the transfer failed
 615          */
 616         if (flags == (I2CECB_TX_ERR|I2CECB_TX_NAK))
 617                 *(int *)data |= 1;
 618         if (flags == (I2CECB_RX_ERR|I2CECB_RX_OV))
 619                 *(int *)data |= 2;
 620 }
 621
 622 int
 623 i2c_probe(uchar chip)
 624 {
 625         i2c_state_t state;
 626         int rc, err_flag;
 627         uchar buf[1];
 628
 629         i2c_newio(&state);
 630
 631         state.err_cb = i2c_probe_callback;
 632         state.cb_data = (void *) &err_flag;
 633         err_flag = 0;
 634
 635         rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);
 636
 637         if (rc != 0)
 638                 return (rc);    /* probe failed */
 639
 640         rc = i2c_doio(&state);
 641
 642         if (rc == 0)
 643                 return (0);     /* device exists - read succeeded */
 644
 645         if (rc == I2CERR_TIMEOUT)
 646                 return (-1);    /* device does not exist - timeout */
 647
 648         if (rc != I2CERR_IO_ERROR || err_flag == 0)
 649                 return (rc);    /* probe failed */
 650
 651         if (err_flag & 1)
 652                 return (-1);    /* device does not exist - had transmit NAK */
 653
 654         return (0);     /* device exists - had receive overrun */
 655 }
 656
 657
 658 int
 659 i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 660 {
 661         i2c_state_t state;
 662         uchar xaddr[4];
 663         int rc;
 664
 665         xaddr[0] = (addr >> 24) & 0xFF;
 666         xaddr[1] = (addr >> 16) & 0xFF;
 667         xaddr[2] = (addr >>  8) & 0xFF;
 668         xaddr[3] =  addr        & 0xFF;
 669
 670 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 671          /*
 672           * EEPROM chips that implement "address overflow" are ones
 673           * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
 674           * and the extra bits end up in the "chip address" bit slots.
 675           * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
 676           * chips.
 677           *
 678           * Note that we consider the length of the address field to still
 679           * be one byte because the extra address bits are hidden in the
 680           * chip address.
 681           */
 682         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 683 #endif
 684
 685         i2c_newio(&state);
 686
 687         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
 688         if (rc != 0) {
 689                 printf("i2c_read: i2c_send failed (%d)\n", rc);
 690                 return 1;
 691         }
 692
 693         rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
 694         if (rc != 0) {
 695                 printf("i2c_read: i2c_receive failed (%d)\n", rc);
 696                 return 1;
 697         }
 698
 699         rc = i2c_doio(&state);
 700         if (rc != 0) {
 701                 printf("i2c_read: i2c_doio failed (%d)\n", rc);
 702                 return 1;
 703         }
 704         return 0;
 705 }
 706
 707 int
 708 i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 709 {
 710         i2c_state_t state;
 711         uchar xaddr[4];
 712         int rc;
 713
 714         xaddr[0] = (addr >> 24) & 0xFF;
 715         xaddr[1] = (addr >> 16) & 0xFF;
 716         xaddr[2] = (addr >>  8) & 0xFF;
 717         xaddr[3] =  addr        & 0xFF;
 718
 719 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 720          /*
 721           * EEPROM chips that implement "address overflow" are ones
 722           * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
 723           * and the extra bits end up in the "chip address" bit slots.
 724           * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
 725           * chips.
 726           *
 727           * Note that we consider the length of the address field to still
 728           * be one byte because the extra address bits are hidden in the
 729           * chip address.
 730           */
 731         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 732 #endif
 733
 734         i2c_newio(&state);
 735
 736         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
 737         if (rc != 0) {
 738                 printf("i2c_write: first i2c_send failed (%d)\n", rc);
 739                 return 1;
 740         }
 741
 742         rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
 743         if (rc != 0) {
 744                 printf("i2c_write: second i2c_send failed (%d)\n", rc);
 745                 return 1;
 746         }
 747
 748         rc = i2c_doio(&state);
 749         if (rc != 0) {
 750                 printf("i2c_write: i2c_doio failed (%d)\n", rc);
 751                 return 1;
 752         }
 753         return 0;
 754 }
 755
 756 uchar
 757 i2c_reg_read(uchar chip, uchar reg)
 758 {
 759         uchar buf;
 760
 761         i2c_read(chip, reg, 1, &buf, 1);
 762
 763         return (buf);
 764 }
 765
 766 void
 767 i2c_reg_write(uchar chip, uchar reg, uchar val)
 768 {
 769         i2c_write(chip, reg, 1, &val, 1);
 770 }
 771
 772 #if defined(CONFIG_I2C_MULTI_BUS)
 773 /*
 774  * Functions for multiple I2C bus handling
 775  */
 776 unsigned int i2c_get_bus_num(void)
 777 {
 778         return i2c_bus_num;
 779 }
 780
 781 int i2c_set_bus_num(unsigned int bus)
 782 {
 783 #if defined(CONFIG_I2C_MUX)
 784         if (bus < CONFIG_SYS_MAX_I2C_BUS) {
 785                 i2c_bus_num = bus;
 786         } else {
 787                 int     ret;
 788
 789                 ret = i2x_mux_select_mux(bus);
 790                 if (ret == 0)
 791                         i2c_bus_num = bus;
 792                 else
 793                         return ret;
 794         }
 795 #else
 796         if (bus >= CONFIG_SYS_MAX_I2C_BUS)
 797                 return -1;
 798         i2c_bus_num = bus;
 799 #endif
 800         return 0;
 801 }
 802 /* TODO: add 100/400k switching */
 803 unsigned int i2c_get_bus_speed(void)
 804 {
 805         return CONFIG_SYS_I2C_SPEED;
 806 }
 807
 808 int i2c_set_bus_speed(unsigned int speed)
 809 {
 810         if (speed != CONFIG_SYS_I2C_SPEED)
 811                 return -1;
 812
 813         return 0;
 814 }
 815
 816 #endif  /* CONFIG_I2C_MULTI_BUS */
 817 #endif  /* CONFIG_HARD_I2C */