cpu/mpc8xxx/ddr/util.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/fsl_law.h>
  11
  12 #include "ddr.h"
  13
  14 unsigned int fsl_ddr_get_mem_data_rate(void);
  15
  16 /*
  17  * Round mclk_ps to nearest 10 ps in memory controller code.
  18  *
  19  * If an imprecise data rate is too high due to rounding error
  20  * propagation, compute a suitably rounded mclk_ps to compute
  21  * a working memory controller configuration.
  22  */
  23 unsigned int get_memory_clk_period_ps(void)
  24 {
  25         unsigned int mclk_ps;
  26
  27         mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate();
  28         /* round to nearest 10 ps */
  29         return 10 * ((mclk_ps + 5) / 10);
  30 }
  31
  32 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
  33 unsigned int picos_to_mclk(unsigned int picos)
  34 {
  35         const unsigned long long ULL_2e12 = 2000000000000ULL;
  36         const unsigned long long ULL_8Fs = 0xFFFFFFFFULL;
  37         unsigned long long clks;
  38         unsigned long long clks_temp;
  39
  40         if (!picos)
  41                 return 0;
  42
  43         clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos;
  44         clks_temp = clks;
  45         clks = clks / ULL_2e12;
  46         if (clks_temp % ULL_2e12) {
  47                 clks++;
  48         }
  49
  50         if (clks > ULL_8Fs) {
  51                 clks = ULL_8Fs;
  52         }
  53
  54         return (unsigned int) clks;
  55 }
  56
  57 unsigned int mclk_to_picos(unsigned int mclk)
  58 {
  59         return get_memory_clk_period_ps() * mclk;
  60 }
  61
  62 void
  63 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
  64                            unsigned int memctl_interleaved,
  65                            unsigned int ctrl_num)
  66 {
  67         unsigned long long base = memctl_common_params->base_address;
  68         unsigned long long size = memctl_common_params->total_mem;
  69
  70         /*
  71          * If no DIMMs on this controller, do not proceed any further.
  72          */
  73         if (!memctl_common_params->ndimms_present) {
  74                 return;
  75         }
  76
  77 #if !defined(CONFIG_PHYS_64BIT)
  78         if (base >= CONFIG_MAX_MEM_MAPPED)
  79                 return;
  80         if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
  81                 size = CONFIG_MAX_MEM_MAPPED - base;
  82 #endif
  83
  84         if (ctrl_num == 0) {
  85                 /*
  86                  * Set up LAW for DDR controller 1 space.
  87                  */
  88                 unsigned int lawbar1_target_id = memctl_interleaved
  89                         ? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
  90
  91                 if (set_ddr_laws(base, size, lawbar1_target_id) < 0) {
  92                         printf("ERROR\n");
  93                         return ;
  94                 }
  95         } else if (ctrl_num == 1) {
  96                 if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) < 0) {
  97                         printf("ERROR\n");
  98                         return ;
  99                 }
 100         } else {
 101                 printf("unexpected controller number %u in %s\n",
 102                         ctrl_num, __FUNCTION__);
 103         }
 104 }
 105
 106 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
 107 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 108                          unsigned int memctl_interleaved,
 109                          unsigned int ctrl_num);
 110
 111 void board_add_ram_info(int use_default)
 112 {
 113 #if defined(CONFIG_MPC85xx)
 114         volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 115 #elif defined(CONFIG_MPC86xx)
 116         volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
 117 #endif
 118 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 119         uint32_t cs0_config = in_be32(&ddr->cs0_config);
 120 #endif
 121         uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
 122         int cas_lat;
 123
 124         puts(" (DDR");
 125         switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
 126                 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
 127         case SDRAM_TYPE_DDR1:
 128                 puts("1");
 129                 break;
 130         case SDRAM_TYPE_DDR2:
 131                 puts("2");
 132                 break;
 133         case SDRAM_TYPE_DDR3:
 134                 puts("3");
 135                 break;
 136         default:
 137                 puts("?");
 138                 break;
 139         }
 140
 141         if (sdram_cfg & SDRAM_CFG_32_BE)
 142                 puts(", 32-bit");
 143         else
 144                 puts(", 64-bit");
 145
 146         /* Calculate CAS latency based on timing cfg values */
 147         cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
 148         if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
 149                 cas_lat += (8 << 1);
 150         printf(", CL=%d", cas_lat >> 1);
 151         if (cas_lat & 0x1)
 152                 puts(".5");
 153
 154         if (sdram_cfg & SDRAM_CFG_ECC_EN)
 155                 puts(", ECC on)");
 156         else
 157                 puts(", ECC off)");
 158
 159 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 160         if (cs0_config & 0x20000000) {
 161                 puts("\n");
 162                 puts("       DDR Controller Interleaving Mode: ");
 163
 164                 switch ((cs0_config >> 24) & 0xf) {
 165                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 166                         puts("cache line");
 167                         break;
 168                 case FSL_DDR_PAGE_INTERLEAVING:
 169                         puts("page");
 170                         break;
 171                 case FSL_DDR_BANK_INTERLEAVING:
 172                         puts("bank");
 173                         break;
 174                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 175                         puts("super-bank");
 176                         break;
 177                 default:
 178                         puts("invalid");
 179                         break;
 180                 }
 181         }
 182 #endif
 183
 184         if ((sdram_cfg >> 8) & 0x7f) {
 185                 puts("\n");
 186                 puts("       DDR Chip-Select Interleaving Mode: ");
 187                 switch(sdram_cfg >> 8 & 0x7f) {
 188                 case FSL_DDR_CS0_CS1_CS2_CS3:
 189                         puts("CS0+CS1+CS2+CS3");
 190                         break;
 191                 case FSL_DDR_CS0_CS1:
 192                         puts("CS0+CS1");
 193                         break;
 194                 case FSL_DDR_CS2_CS3:
 195                         puts("CS2+CS3");
 196                         break;
 197                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 198                         puts("CS0+CS1 and CS2+CS3");
 199                         break;
 200                 default:
 201                         puts("invalid");
 202                         break;
 203                 }
 204         }
 205 }