cpu/ppc4xx/44x_spd_ddr.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr.c
   3  * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
   4  * DDR controller. Those are 440GP/GX/EP/GR.
   5  *
   6  * (C) Copyright 2001
   7  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
   8  *
   9  * Based on code by:
  10  *
  11  * Kenneth Johansson ,Ericsson AB.
  12  * kenneth.johansson@etx.ericsson.se
  13  *
  14  * hacked up by bill hunter. fixed so we could run before
  15  * serial_init and console_init. previous version avoided this by
  16  * running out of cache memory during serial/console init, then running
  17  * this code later.
  18  *
  19  * (C) Copyright 2002
  20  * Jun Gu, Artesyn Technology, jung@artesyncp.com
  21  * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
  22  *
  23  * (C) Copyright 2005-2007
  24  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  25  *
  26  * See file CREDITS for list of people who contributed to this
  27  * project.
  28  *
  29  * This program is free software; you can redistribute it and/or
  30  * modify it under the terms of the GNU General Public License as
  31  * published by the Free Software Foundation; either version 2 of
  32  * the License, or (at your option) any later version.
  33  *
  34  * This program is distributed in the hope that it will be useful,
  35  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  36  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  37  * GNU General Public License for more details.
  38  *
  39  * You should have received a copy of the GNU General Public License
  40  * along with this program; if not, write to the Free Software
  41  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  42  * MA 02111-1307 USA
  43  */
  44
  45 /* define DEBUG for debugging output (obviously ;-)) */
  46 #if 0
  47 #define DEBUG
  48 #endif
  49
  50 #include <common.h>
  51 #include <asm/processor.h>
  52 #include <i2c.h>
  53 #include <ppc4xx.h>
  54 #include <asm/mmu.h>
  55
  56 #include "ecc.h"
  57
  58 #if defined(CONFIG_SPD_EEPROM) &&                                       \
  59         (defined(CONFIG_440GP) || defined(CONFIG_440GX) ||              \
  60          defined(CONFIG_440EP) || defined(CONFIG_440GR))
  61
  62 /*
  63  * Set default values
  64  */
  65 #ifndef CONFIG_SYS_I2C_SPEED
  66 #define CONFIG_SYS_I2C_SPEED    50000
  67 #endif
  68
  69 #ifndef CONFIG_SYS_I2C_SLAVE
  70 #define CONFIG_SYS_I2C_SLAVE    0xFE
  71 #endif
  72
  73 #define ONE_BILLION     1000000000
  74
  75 /*
  76  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
  77  */
  78 void __spd_ddr_init_hang (void)
  79 {
  80         hang ();
  81 }
  82 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
  83
  84 /*-----------------------------------------------------------------------------+
  85   |  General Definition
  86   +-----------------------------------------------------------------------------*/
  87 #define DEFAULT_SPD_ADDR1       0x53
  88 #define DEFAULT_SPD_ADDR2       0x52
  89 #define MAXBANKS                4               /* at most 4 dimm banks */
  90 #define MAX_SPD_BYTES           256
  91 #define NUMHALFCYCLES           4
  92 #define NUMMEMTESTS             8
  93 #define NUMMEMWORDS             8
  94 #define MAXBXCR                 4
  95 #define TRUE                    1
  96 #define FALSE                   0
  97
  98 /*
  99  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
 100  * region. Right now the cache should still be disabled in U-Boot because of the
 101  * EMAC driver, that need it's buffer descriptor to be located in non cached
 102  * memory.
 103  *
 104  * If at some time this restriction doesn't apply anymore, just define
 105  * CONFIG_4xx_DCACHE in the board config file and this code should setup
 106  * everything correctly.
 107  */
 108 #ifdef CONFIG_4xx_DCACHE
 109 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
 110 #else
 111 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 112 #endif
 113
 114 /* bank_parms is used to sort the bank sizes by descending order */
 115 struct bank_param {
 116         unsigned long cr;
 117         unsigned long bank_size_bytes;
 118 };
 119
 120 typedef struct bank_param BANKPARMS;
 121
 122 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
 123 extern const unsigned char cfg_simulate_spd_eeprom[128];
 124 #endif
 125
 126 static unsigned char spd_read(uchar chip, uint addr);
 127 static void get_spd_info(unsigned long *dimm_populated,
 128                          unsigned char *iic0_dimm_addr,
 129                          unsigned long num_dimm_banks);
 130 static void check_mem_type(unsigned long *dimm_populated,
 131                            unsigned char *iic0_dimm_addr,
 132                            unsigned long num_dimm_banks);
 133 static void check_volt_type(unsigned long *dimm_populated,
 134                             unsigned char *iic0_dimm_addr,
 135                             unsigned long num_dimm_banks);
 136 static void program_cfg0(unsigned long *dimm_populated,
 137                          unsigned char *iic0_dimm_addr,
 138                          unsigned long  num_dimm_banks);
 139 static void program_cfg1(unsigned long *dimm_populated,
 140                          unsigned char *iic0_dimm_addr,
 141                          unsigned long num_dimm_banks);
 142 static void program_rtr(unsigned long *dimm_populated,
 143                         unsigned char *iic0_dimm_addr,
 144                         unsigned long num_dimm_banks);
 145 static void program_tr0(unsigned long *dimm_populated,
 146                         unsigned char *iic0_dimm_addr,
 147                         unsigned long num_dimm_banks);
 148 static void program_tr1(void);
 149
 150 static unsigned long program_bxcr(unsigned long *dimm_populated,
 151                                   unsigned char *iic0_dimm_addr,
 152                                   unsigned long num_dimm_banks);
 153
 154 /*
 155  * This function is reading data from the DIMM module EEPROM over the SPD bus
 156  * and uses that to program the sdram controller.
 157  *
 158  * This works on boards that has the same schematics that the AMCC walnut has.
 159  *
 160  * BUG: Don't handle ECC memory
 161  * BUG: A few values in the TR register is currently hardcoded
 162  */
 163 long int spd_sdram(void) {
 164         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 165         unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
 166         unsigned long total_size;
 167         unsigned long cfg0;
 168         unsigned long mcsts;
 169         unsigned long num_dimm_banks;               /* on board dimm banks */
 170
 171         num_dimm_banks = sizeof(iic0_dimm_addr);
 172
 173         /*
 174          * Make sure I2C controller is initialized
 175          * before continuing.
 176          */
 177         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 178
 179         /*
 180          * Read the SPD information using I2C interface. Check to see if the
 181          * DIMM slots are populated.
 182          */
 183         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 184
 185         /*
 186          * Check the memory type for the dimms plugged.
 187          */
 188         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 189
 190         /*
 191          * Check the voltage type for the dimms plugged.
 192          */
 193         check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 194
 195 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 196         /*
 197          * Soft-reset SDRAM controller.
 198          */
 199         mtsdr(sdr_srst, SDR0_SRST_DMC);
 200         mtsdr(sdr_srst, 0x00000000);
 201 #endif
 202
 203         /*
 204          * program 440GP SDRAM controller options (SDRAM0_CFG0)
 205          */
 206         program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 207
 208         /*
 209          * program 440GP SDRAM controller options (SDRAM0_CFG1)
 210          */
 211         program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 212
 213         /*
 214          * program SDRAM refresh register (SDRAM0_RTR)
 215          */
 216         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 217
 218         /*
 219          * program SDRAM Timing Register 0 (SDRAM0_TR0)
 220          */
 221         program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 222
 223         /*
 224          * program the BxCR registers to find out total sdram installed
 225          */
 226         total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
 227                                   num_dimm_banks);
 228
 229 #ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
 230         /* and program tlb entries for this size (dynamic) */
 231         program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE);
 232 #endif
 233
 234         /*
 235          * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
 236          */
 237         mtsdram(mem_clktr, 0x40000000);
 238
 239         /*
 240          * delay to ensure 200 usec has elapsed
 241          */
 242         udelay(400);
 243
 244         /*
 245          * enable the memory controller
 246          */
 247         mfsdram(mem_cfg0, cfg0);
 248         mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
 249
 250         /*
 251          * wait for SDRAM_CFG0_DC_EN to complete
 252          */
 253         while (1) {
 254                 mfsdram(mem_mcsts, mcsts);
 255                 if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
 256                         break;
 257         }
 258
 259         /*
 260          * program SDRAM Timing Register 1, adding some delays
 261          */
 262         program_tr1();
 263
 264 #ifdef CONFIG_DDR_ECC
 265         /*
 266          * If ecc is enabled, initialize the parity bits.
 267          */
 268         ecc_init(CONFIG_SYS_SDRAM_BASE, total_size);
 269 #endif
 270
 271         return total_size;
 272 }
 273
 274 static unsigned char spd_read(uchar chip, uint addr)
 275 {
 276         unsigned char data[2];
 277
 278 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
 279         if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) {
 280                 /*
 281                  * Onboard spd eeprom requested -> simulate values
 282                  */
 283                 return cfg_simulate_spd_eeprom[addr];
 284         }
 285 #endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */
 286
 287         if (i2c_probe(chip) == 0) {
 288                 if (i2c_read(chip, addr, 1, data, 1) == 0) {
 289                         return data[0];
 290                 }
 291         }
 292
 293         return 0;
 294 }
 295
 296 static void get_spd_info(unsigned long *dimm_populated,
 297                          unsigned char *iic0_dimm_addr,
 298                          unsigned long num_dimm_banks)
 299 {
 300         unsigned long dimm_num;
 301         unsigned long dimm_found;
 302         unsigned char num_of_bytes;
 303         unsigned char total_size;
 304
 305         dimm_found = FALSE;
 306         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 307                 num_of_bytes = 0;
 308                 total_size = 0;
 309
 310                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 311                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 312
 313                 if ((num_of_bytes != 0) && (total_size != 0)) {
 314                         dimm_populated[dimm_num] = TRUE;
 315                         dimm_found = TRUE;
 316                         debug("DIMM slot %lu: populated\n", dimm_num);
 317                 } else {
 318                         dimm_populated[dimm_num] = FALSE;
 319                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 320                 }
 321         }
 322
 323         if (dimm_found == FALSE) {
 324                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 325                 spd_ddr_init_hang ();
 326         }
 327 }
 328
 329 static void check_mem_type(unsigned long *dimm_populated,
 330                            unsigned char *iic0_dimm_addr,
 331                            unsigned long num_dimm_banks)
 332 {
 333         unsigned long dimm_num;
 334         unsigned char dimm_type;
 335
 336         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 337                 if (dimm_populated[dimm_num] == TRUE) {
 338                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 339                         switch (dimm_type) {
 340                         case 7:
 341                                 debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
 342                                 break;
 343                         default:
 344                                 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
 345                                        dimm_num);
 346                                 printf("Only DDR SDRAM DIMMs are supported.\n");
 347                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 348                                 spd_ddr_init_hang ();
 349                                 break;
 350                         }
 351                 }
 352         }
 353 }
 354
 355 static void check_volt_type(unsigned long *dimm_populated,
 356                             unsigned char *iic0_dimm_addr,
 357                             unsigned long num_dimm_banks)
 358 {
 359         unsigned long dimm_num;
 360         unsigned long voltage_type;
 361
 362         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 363                 if (dimm_populated[dimm_num] == TRUE) {
 364                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 365                         if (voltage_type != 0x04) {
 366                                 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
 367                                        dimm_num);
 368                                 spd_ddr_init_hang ();
 369                         } else {
 370                                 debug("DIMM %lu voltage level supported.\n", dimm_num);
 371                         }
 372                         break;
 373                 }
 374         }
 375 }
 376
 377 static void program_cfg0(unsigned long *dimm_populated,
 378                          unsigned char *iic0_dimm_addr,
 379                          unsigned long num_dimm_banks)
 380 {
 381         unsigned long dimm_num;
 382         unsigned long cfg0;
 383         unsigned long ecc_enabled;
 384         unsigned char ecc;
 385         unsigned char attributes;
 386         unsigned long data_width;
 387         unsigned long dimm_32bit;
 388         unsigned long dimm_64bit;
 389
 390         /*
 391          * get Memory Controller Options 0 data
 392          */
 393         mfsdram(mem_cfg0, cfg0);
 394
 395         /*
 396          * clear bits
 397          */
 398         cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
 399                   SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
 400                   SDRAM_CFG0_DMWD_MASK |
 401                   SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
 402
 403
 404         /*
 405          * FIXME: assume the DDR SDRAMs in both banks are the same
 406          */
 407         ecc_enabled = TRUE;
 408         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 409                 if (dimm_populated[dimm_num] == TRUE) {
 410                         ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
 411                         if (ecc != 0x02) {
 412                                 ecc_enabled = FALSE;
 413                         }
 414
 415                         /*
 416                          * program Registered DIMM Enable
 417                          */
 418                         attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
 419                         if ((attributes & 0x02) != 0x00) {
 420                                 cfg0 |= SDRAM_CFG0_RDEN;
 421                         }
 422
 423                         /*
 424                          * program DDR SDRAM Data Width
 425                          */
 426                         data_width =
 427                                 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
 428                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
 429                         if (data_width == 64 || data_width == 72) {
 430                                 dimm_64bit = TRUE;
 431                                 cfg0 |= SDRAM_CFG0_DMWD_64;
 432                         } else if (data_width == 32 || data_width == 40) {
 433                                 dimm_32bit = TRUE;
 434                                 cfg0 |= SDRAM_CFG0_DMWD_32;
 435                         } else {
 436                                 printf("WARNING: DIMM with datawidth of %lu bits.\n",
 437                                        data_width);
 438                                 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
 439                                 spd_ddr_init_hang ();
 440                         }
 441                         break;
 442                 }
 443         }
 444
 445         /*
 446          * program Memory Data Error Checking
 447          */
 448         if (ecc_enabled == TRUE) {
 449                 cfg0 |= SDRAM_CFG0_MCHK_GEN;
 450         } else {
 451                 cfg0 |= SDRAM_CFG0_MCHK_NON;
 452         }
 453
 454         /*
 455          * program Page Management Unit (0 == enabled)
 456          */
 457         cfg0 &= ~SDRAM_CFG0_PMUD;
 458
 459         /*
 460          * program Memory Controller Options 0
 461          * Note: DCEN must be enabled after all DDR SDRAM controller
 462          * configuration registers get initialized.
 463          */
 464         mtsdram(mem_cfg0, cfg0);
 465 }
 466
 467 static void program_cfg1(unsigned long *dimm_populated,
 468                          unsigned char *iic0_dimm_addr,
 469                          unsigned long num_dimm_banks)
 470 {
 471         unsigned long cfg1;
 472         mfsdram(mem_cfg1, cfg1);
 473
 474         /*
 475          * Self-refresh exit, disable PM
 476          */
 477         cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
 478
 479         /*
 480          * program Memory Controller Options 1
 481          */
 482         mtsdram(mem_cfg1, cfg1);
 483 }
 484
 485 static void program_rtr(unsigned long *dimm_populated,
 486                         unsigned char *iic0_dimm_addr,
 487                         unsigned long num_dimm_banks)
 488 {
 489         unsigned long dimm_num;
 490         unsigned long bus_period_x_10;
 491         unsigned long refresh_rate = 0;
 492         unsigned char refresh_rate_type;
 493         unsigned long refresh_interval;
 494         unsigned long sdram_rtr;
 495         PPC4xx_SYS_INFO sys_info;
 496
 497         /*
 498          * get the board info
 499          */
 500         get_sys_info(&sys_info);
 501         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 502
 503         for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
 504                 if (dimm_populated[dimm_num] == TRUE) {
 505                         refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
 506                         switch (refresh_rate_type) {
 507                         case 0x00:
 508                                 refresh_rate = 15625;
 509                                 break;
 510                         case 0x01:
 511                                 refresh_rate = 15625/4;
 512                                 break;
 513                         case 0x02:
 514                                 refresh_rate = 15625/2;
 515                                 break;
 516                         case 0x03:
 517                                 refresh_rate = 15626*2;
 518                                 break;
 519                         case 0x04:
 520                                 refresh_rate = 15625*4;
 521                                 break;
 522                         case 0x05:
 523                                 refresh_rate = 15625*8;
 524                                 break;
 525                         default:
 526                                 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
 527                                        dimm_num);
 528                                 printf("Replace the DIMM module with a supported DIMM.\n");
 529                                 break;
 530                         }
 531
 532                         break;
 533                 }
 534         }
 535
 536         refresh_interval = refresh_rate * 10 / bus_period_x_10;
 537         sdram_rtr = (refresh_interval & 0x3ff8) <<  16;
 538
 539         /*
 540          * program Refresh Timer Register (SDRAM0_RTR)
 541          */
 542         mtsdram(mem_rtr, sdram_rtr);
 543 }
 544
 545 static void program_tr0(unsigned long *dimm_populated,
 546                          unsigned char *iic0_dimm_addr,
 547                          unsigned long num_dimm_banks)
 548 {
 549         unsigned long dimm_num;
 550         unsigned long tr0;
 551         unsigned char wcsbc;
 552         unsigned char t_rp_ns;
 553         unsigned char t_rcd_ns;
 554         unsigned char t_ras_ns;
 555         unsigned long t_rp_clk;
 556         unsigned long t_ras_rcd_clk;
 557         unsigned long t_rcd_clk;
 558         unsigned long t_rfc_clk;
 559         unsigned long plb_check;
 560         unsigned char cas_bit;
 561         unsigned long cas_index;
 562         unsigned char cas_2_0_available;
 563         unsigned char cas_2_5_available;
 564         unsigned char cas_3_0_available;
 565         unsigned long cycle_time_ns_x_10[3];
 566         unsigned long tcyc_3_0_ns_x_10;
 567         unsigned long tcyc_2_5_ns_x_10;
 568         unsigned long tcyc_2_0_ns_x_10;
 569         unsigned long tcyc_reg;
 570         unsigned long bus_period_x_10;
 571         PPC4xx_SYS_INFO sys_info;
 572         unsigned long residue;
 573
 574         /*
 575          * get the board info
 576          */
 577         get_sys_info(&sys_info);
 578         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 579
 580         /*
 581          * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
 582          */
 583         mfsdram(mem_tr0, tr0);
 584         tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
 585                  SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
 586                  SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
 587                  SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
 588
 589         /*
 590          * initialization
 591          */
 592         wcsbc = 0;
 593         t_rp_ns = 0;
 594         t_rcd_ns = 0;
 595         t_ras_ns = 0;
 596         cas_2_0_available = TRUE;
 597         cas_2_5_available = TRUE;
 598         cas_3_0_available = TRUE;
 599         tcyc_2_0_ns_x_10 = 0;
 600         tcyc_2_5_ns_x_10 = 0;
 601         tcyc_3_0_ns_x_10 = 0;
 602
 603         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 604                 if (dimm_populated[dimm_num] == TRUE) {
 605                         wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
 606                         t_rp_ns  = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
 607                         t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
 608                         t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
 609                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
 610
 611                         for (cas_index = 0; cas_index < 3; cas_index++) {
 612                                 switch (cas_index) {
 613                                 case 0:
 614                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 615                                         break;
 616                                 case 1:
 617                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
 618                                         break;
 619                                 default:
 620                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
 621                                         break;
 622                                 }
 623
 624                                 if ((tcyc_reg & 0x0F) >= 10) {
 625                                         printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
 626                                                dimm_num);
 627                                         spd_ddr_init_hang ();
 628                                 }
 629
 630                                 cycle_time_ns_x_10[cas_index] =
 631                                         (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
 632                         }
 633
 634                         cas_index = 0;
 635
 636                         if ((cas_bit & 0x80) != 0) {
 637                                 cas_index += 3;
 638                         } else if ((cas_bit & 0x40) != 0) {
 639                                 cas_index += 2;
 640                         } else if ((cas_bit & 0x20) != 0) {
 641                                 cas_index += 1;
 642                         }
 643
 644                         if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
 645                                 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
 646                                 cas_index++;
 647                         } else {
 648                                 if (cas_index != 0) {
 649                                         cas_index++;
 650                                 }
 651                                 cas_3_0_available = FALSE;
 652                         }
 653
 654                         if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
 655                                 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
 656                                 cas_index++;
 657                         } else {
 658                                 if (cas_index != 0) {
 659                                         cas_index++;
 660                                 }
 661                                 cas_2_5_available = FALSE;
 662                         }
 663
 664                         if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
 665                                 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
 666                                 cas_index++;
 667                         } else {
 668                                 if (cas_index != 0) {
 669                                         cas_index++;
 670                                 }
 671                                 cas_2_0_available = FALSE;
 672                         }
 673
 674                         break;
 675                 }
 676         }
 677
 678         /*
 679          * Program SD_WR and SD_WCSBC fields
 680          */
 681         tr0 |= SDRAM_TR0_SDWR_2_CLK;                /* Write Recovery: 2 CLK */
 682         switch (wcsbc) {
 683         case 0:
 684                 tr0 |= SDRAM_TR0_SDWD_0_CLK;
 685                 break;
 686         default:
 687                 tr0 |= SDRAM_TR0_SDWD_1_CLK;
 688                 break;
 689         }
 690
 691         /*
 692          * Program SD_CASL field
 693          */
 694         if ((cas_2_0_available == TRUE) &&
 695             (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
 696                 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
 697         } else if ((cas_2_5_available == TRUE) &&
 698                  (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
 699                 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
 700         } else if ((cas_3_0_available == TRUE) &&
 701                  (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
 702                 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
 703         } else {
 704                 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
 705                 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
 706                 printf("Make sure the PLB speed is within the supported range.\n");
 707                 spd_ddr_init_hang ();
 708         }
 709
 710         /*
 711          * Calculate Trp in clock cycles and round up if necessary
 712          * Program SD_PTA field
 713          */
 714         t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
 715         plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
 716         if (sys_info.freqPLB != plb_check) {
 717                 t_rp_clk++;
 718         }
 719         switch ((unsigned long)t_rp_clk) {
 720         case 0:
 721         case 1:
 722         case 2:
 723                 tr0 |= SDRAM_TR0_SDPA_2_CLK;
 724                 break;
 725         case 3:
 726                 tr0 |= SDRAM_TR0_SDPA_3_CLK;
 727                 break;
 728         default:
 729                 tr0 |= SDRAM_TR0_SDPA_4_CLK;
 730                 break;
 731         }
 732
 733         /*
 734          * Program SD_CTP field
 735          */
 736         t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
 737         plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
 738         if (sys_info.freqPLB != plb_check) {
 739                 t_ras_rcd_clk++;
 740         }
 741         switch (t_ras_rcd_clk) {
 742         case 0:
 743         case 1:
 744         case 2:
 745                 tr0 |= SDRAM_TR0_SDCP_2_CLK;
 746                 break;
 747         case 3:
 748                 tr0 |= SDRAM_TR0_SDCP_3_CLK;
 749                 break;
 750         case 4:
 751                 tr0 |= SDRAM_TR0_SDCP_4_CLK;
 752                 break;
 753         default:
 754                 tr0 |= SDRAM_TR0_SDCP_5_CLK;
 755                 break;
 756         }
 757
 758         /*
 759          * Program SD_LDF field
 760          */
 761         tr0 |= SDRAM_TR0_SDLD_2_CLK;
 762
 763         /*
 764          * Program SD_RFTA field
 765          * FIXME tRFC hardcoded as 75 nanoseconds
 766          */
 767         t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
 768         residue = sys_info.freqPLB % (ONE_BILLION / 75);
 769         if (residue >= (ONE_BILLION / 150)) {
 770                 t_rfc_clk++;
 771         }
 772         switch (t_rfc_clk) {
 773         case 0:
 774         case 1:
 775         case 2:
 776         case 3:
 777         case 4:
 778         case 5:
 779         case 6:
 780                 tr0 |= SDRAM_TR0_SDRA_6_CLK;
 781                 break;
 782         case 7:
 783                 tr0 |= SDRAM_TR0_SDRA_7_CLK;
 784                 break;
 785         case 8:
 786                 tr0 |= SDRAM_TR0_SDRA_8_CLK;
 787                 break;
 788         case 9:
 789                 tr0 |= SDRAM_TR0_SDRA_9_CLK;
 790                 break;
 791         case 10:
 792                 tr0 |= SDRAM_TR0_SDRA_10_CLK;
 793                 break;
 794         case 11:
 795                 tr0 |= SDRAM_TR0_SDRA_11_CLK;
 796                 break;
 797         case 12:
 798                 tr0 |= SDRAM_TR0_SDRA_12_CLK;
 799                 break;
 800         default:
 801                 tr0 |= SDRAM_TR0_SDRA_13_CLK;
 802                 break;
 803         }
 804
 805         /*
 806          * Program SD_RCD field
 807          */
 808         t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
 809         plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
 810         if (sys_info.freqPLB != plb_check) {
 811                 t_rcd_clk++;
 812         }
 813         switch (t_rcd_clk) {
 814         case 0:
 815         case 1:
 816         case 2:
 817                 tr0 |= SDRAM_TR0_SDRD_2_CLK;
 818                 break;
 819         case 3:
 820                 tr0 |= SDRAM_TR0_SDRD_3_CLK;
 821                 break;
 822         default:
 823                 tr0 |= SDRAM_TR0_SDRD_4_CLK;
 824                 break;
 825         }
 826
 827         debug("tr0: %x\n", tr0);
 828         mtsdram(mem_tr0, tr0);
 829 }
 830
 831 static int short_mem_test(void)
 832 {
 833         unsigned long i, j;
 834         unsigned long bxcr_num;
 835         unsigned long *membase;
 836         const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
 837                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 838                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
 839                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 840                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
 841                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 842                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
 843                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 844                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
 845                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 846                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
 847                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 848                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
 849                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 850                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
 851                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 852                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
 853
 854         for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
 855                 mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
 856                 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
 857                         /* Bank is enabled */
 858                         membase = (unsigned long*)
 859                                 (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
 860
 861                         /*
 862                          * Run the short memory test
 863                          */
 864                         for (i = 0; i < NUMMEMTESTS; i++) {
 865                                 for (j = 0; j < NUMMEMWORDS; j++) {
 866                                         /* printf("bank enabled base:%x\n", &membase[j]); */
 867                                         membase[j] = test[i][j];
 868                                         ppcDcbf((unsigned long)&(membase[j]));
 869                                 }
 870
 871                                 for (j = 0; j < NUMMEMWORDS; j++) {
 872                                         if (membase[j] != test[i][j]) {
 873                                                 ppcDcbf((unsigned long)&(membase[j]));
 874                                                 return 0;
 875                                         }
 876                                         ppcDcbf((unsigned long)&(membase[j]));
 877                                 }
 878
 879                                 if (j < NUMMEMWORDS)
 880                                         return 0;
 881                         }
 882
 883                         /*
 884                          * see if the rdclt value passed
 885                          */
 886                         if (i < NUMMEMTESTS)
 887                                 return 0;
 888                 }
 889         }
 890
 891         return 1;
 892 }
 893
 894 static void program_tr1(void)
 895 {
 896         unsigned long tr0;
 897         unsigned long tr1;
 898         unsigned long cfg0;
 899         unsigned long ecc_temp;
 900         unsigned long dlycal;
 901         unsigned long dly_val;
 902         unsigned long k;
 903         unsigned long max_pass_length;
 904         unsigned long current_pass_length;
 905         unsigned long current_fail_length;
 906         unsigned long current_start;
 907         unsigned long rdclt;
 908         unsigned long rdclt_offset;
 909         long max_start;
 910         long max_end;
 911         long rdclt_average;
 912         unsigned char window_found;
 913         unsigned char fail_found;
 914         unsigned char pass_found;
 915         PPC4xx_SYS_INFO sys_info;
 916
 917         /*
 918          * get the board info
 919          */
 920         get_sys_info(&sys_info);
 921
 922         /*
 923          * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
 924          */
 925         mfsdram(mem_tr1, tr1);
 926         tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
 927                  SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
 928
 929         mfsdram(mem_tr0, tr0);
 930         if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
 931             (sys_info.freqPLB > 100000000)) {
 932                 tr1 |= SDRAM_TR1_RDSS_TR2;
 933                 tr1 |= SDRAM_TR1_RDSL_STAGE3;
 934                 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
 935         } else {
 936                 tr1 |= SDRAM_TR1_RDSS_TR1;
 937                 tr1 |= SDRAM_TR1_RDSL_STAGE2;
 938                 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
 939         }
 940
 941         /*
 942          * save CFG0 ECC setting to a temporary variable and turn ECC off
 943          */
 944         mfsdram(mem_cfg0, cfg0);
 945         ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
 946         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
 947
 948         /*
 949          * get the delay line calibration register value
 950          */
 951         mfsdram(mem_dlycal, dlycal);
 952         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
 953
 954         max_pass_length = 0;
 955         max_start = 0;
 956         max_end = 0;
 957         current_pass_length = 0;
 958         current_fail_length = 0;
 959         current_start = 0;
 960         rdclt_offset = 0;
 961         window_found = FALSE;
 962         fail_found = FALSE;
 963         pass_found = FALSE;
 964         debug("Starting memory test ");
 965
 966         for (k = 0; k < NUMHALFCYCLES; k++) {
 967                 for (rdclt = 0; rdclt < dly_val; rdclt++) {
 968                         /*
 969                          * Set the timing reg for the test.
 970                          */
 971                         mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
 972
 973                         if (short_mem_test()) {
 974                                 if (fail_found == TRUE) {
 975                                         pass_found = TRUE;
 976                                         if (current_pass_length == 0) {
 977                                                 current_start = rdclt_offset + rdclt;
 978                                         }
 979
 980                                         current_fail_length = 0;
 981                                         current_pass_length++;
 982
 983                                         if (current_pass_length > max_pass_length) {
 984                                                 max_pass_length = current_pass_length;
 985                                                 max_start = current_start;
 986                                                 max_end = rdclt_offset + rdclt;
 987                                         }
 988                                 }
 989                         } else {
 990                                 current_pass_length = 0;
 991                                 current_fail_length++;
 992
 993                                 if (current_fail_length >= (dly_val>>2)) {
 994                                         if (fail_found == FALSE) {
 995                                                 fail_found = TRUE;
 996                                         } else if (pass_found == TRUE) {
 997                                                 window_found = TRUE;
 998                                                 break;
 999                                         }
1000                                 }
1001                         }
1002                 }
1003                 debug(".");
1004
1005                 if (window_found == TRUE) {
1006                         break;
1007                 }
1008
1009                 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1010                 rdclt_offset += dly_val;
1011         }
1012         debug("\n");
1013
1014         /*
1015          * make sure we find the window
1016          */
1017         if (window_found == FALSE) {
1018                 printf("ERROR: Cannot determine a common read delay.\n");
1019                 spd_ddr_init_hang ();
1020         }
1021
1022         /*
1023          * restore the orignal ECC setting
1024          */
1025         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1026
1027         /*
1028          * set the SDRAM TR1 RDCD value
1029          */
1030         tr1 &= ~SDRAM_TR1_RDCD_MASK;
1031         if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1032                 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1033         } else {
1034                 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1035         }
1036
1037         /*
1038          * set the SDRAM TR1 RDCLT value
1039          */
1040         tr1 &= ~SDRAM_TR1_RDCT_MASK;
1041         while (max_end >= (dly_val << 1)) {
1042                 max_end -= (dly_val << 1);
1043                 max_start -= (dly_val << 1);
1044         }
1045
1046         rdclt_average = ((max_start + max_end) >> 1);
1047
1048         if (rdclt_average < 0) {
1049                 rdclt_average = 0;
1050         }
1051
1052         if (rdclt_average >= dly_val) {
1053                 rdclt_average -= dly_val;
1054                 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1055         }
1056         tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1057
1058         debug("tr1: %x\n", tr1);
1059
1060         /*
1061          * program SDRAM Timing Register 1 TR1
1062          */
1063         mtsdram(mem_tr1, tr1);
1064 }
1065
1066 static unsigned long program_bxcr(unsigned long *dimm_populated,
1067                                   unsigned char *iic0_dimm_addr,
1068                                   unsigned long num_dimm_banks)
1069 {
1070         unsigned long dimm_num;
1071         unsigned long bank_base_addr;
1072         unsigned long cr;
1073         unsigned long i;
1074         unsigned long j;
1075         unsigned long temp;
1076         unsigned char num_row_addr;
1077         unsigned char num_col_addr;
1078         unsigned char num_banks;
1079         unsigned char bank_size_id;
1080         unsigned long ctrl_bank_num[MAXBANKS];
1081         unsigned long bx_cr_num;
1082         unsigned long largest_size_index;
1083         unsigned long largest_size;
1084         unsigned long current_size_index;
1085         BANKPARMS bank_parms[MAXBXCR];
1086         unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
1087         unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
1088
1089         /*
1090          * Set the BxCR regs.  First, wipe out the bank config registers.
1091          */
1092         for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1093                 mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2));
1094                 mtdcr(memcfgd, 0x00000000);
1095                 bank_parms[bx_cr_num].bank_size_bytes = 0;
1096         }
1097
1098 #ifdef CONFIG_BAMBOO
1099         /*
1100          * This next section is hardware dependent and must be programmed
1101          * to match the hardware.  For bamboo, the following holds...
1102          * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard)
1103          * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
1104          * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
1105          * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
1106          * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
1107          */
1108         ctrl_bank_num[0] = 0;
1109         ctrl_bank_num[1] = 1;
1110         ctrl_bank_num[2] = 3;
1111 #else
1112         /*
1113          * Ocotea, Ebony and the other IBM/AMCC eval boards have
1114          * 2 DIMM slots with each max 2 banks
1115          */
1116         ctrl_bank_num[0] = 0;
1117         ctrl_bank_num[1] = 2;
1118 #endif
1119
1120         /*
1121          * reset the bank_base address
1122          */
1123         bank_base_addr = CONFIG_SYS_SDRAM_BASE;
1124
1125         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1126                 if (dimm_populated[dimm_num] == TRUE) {
1127                         num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1128                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1129                         num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
1130                         bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1131                         debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num,
1132                               num_row_addr, num_col_addr, num_banks);
1133
1134                         /*
1135                          * Set the SDRAM0_BxCR regs
1136                          */
1137                         cr = 0;
1138                         switch (bank_size_id) {
1139                         case 0x02:
1140                                 cr |= SDRAM_BXCR_SDSZ_8;
1141                                 break;
1142                         case 0x04:
1143                                 cr |= SDRAM_BXCR_SDSZ_16;
1144                                 break;
1145                         case 0x08:
1146                                 cr |= SDRAM_BXCR_SDSZ_32;
1147                                 break;
1148                         case 0x10:
1149                                 cr |= SDRAM_BXCR_SDSZ_64;
1150                                 break;
1151                         case 0x20:
1152                                 cr |= SDRAM_BXCR_SDSZ_128;
1153                                 break;
1154                         case 0x40:
1155                                 cr |= SDRAM_BXCR_SDSZ_256;
1156                                 break;
1157                         case 0x80:
1158                                 cr |= SDRAM_BXCR_SDSZ_512;
1159                                 break;
1160                         default:
1161                                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1162                                        dimm_num);
1163                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
1164                                        bank_size_id);
1165                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1166                                 spd_ddr_init_hang ();
1167                         }
1168
1169                         switch (num_col_addr) {
1170                         case 0x08:
1171                                 cr |= SDRAM_BXCR_SDAM_1;
1172                                 break;
1173                         case 0x09:
1174                                 cr |= SDRAM_BXCR_SDAM_2;
1175                                 break;
1176                         case 0x0A:
1177                                 cr |= SDRAM_BXCR_SDAM_3;
1178                                 break;
1179                         case 0x0B:
1180                                 cr |= SDRAM_BXCR_SDAM_4;
1181                                 break;
1182                         default:
1183                                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1184                                        dimm_num);
1185                                 printf("ERROR: Unsupported value for number of "
1186                                        "column addresses: %d.\n", num_col_addr);
1187                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1188                                 spd_ddr_init_hang ();
1189                         }
1190
1191                         /*
1192                          * enable the bank
1193                          */
1194                         cr |= SDRAM_BXCR_SDBE;
1195
1196                         for (i = 0; i < num_banks; i++) {
1197                                 bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
1198                                         (4 << 20) * bank_size_id;
1199                                 bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
1200                                 debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
1201                                       dimm_num, i, ctrl_bank_num[dimm_num]+i,
1202                                       bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
1203                         }
1204                 }
1205         }
1206
1207         /* Initialize sort tables */
1208         for (i = 0; i < MAXBXCR; i++) {
1209                 sorted_bank_num[i] = i;
1210                 sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
1211         }
1212
1213         for (i = 0; i < MAXBXCR-1; i++) {
1214                 largest_size = sorted_bank_size[i];
1215                 largest_size_index = 255;
1216
1217                 /* Find the largest remaining value */
1218                 for (j = i + 1; j < MAXBXCR; j++) {
1219                         if (sorted_bank_size[j] > largest_size) {
1220                                 /* Save largest remaining value and its index */
1221                                 largest_size = sorted_bank_size[j];
1222                                 largest_size_index = j;
1223                         }
1224                 }
1225
1226                 if (largest_size_index != 255) {
1227                         /* Swap the current and largest values */
1228                         current_size_index = sorted_bank_num[largest_size_index];
1229                         sorted_bank_size[largest_size_index] = sorted_bank_size[i];
1230                         sorted_bank_size[i] = largest_size;
1231                         sorted_bank_num[largest_size_index] = sorted_bank_num[i];
1232                         sorted_bank_num[i] = current_size_index;
1233                 }
1234         }
1235
1236         /* Set the SDRAM0_BxCR regs thanks to sort tables */
1237         for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1238                 if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
1239                         mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
1240                         temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
1241                                                   SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
1242                         temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
1243                                 bank_parms[sorted_bank_num[bx_cr_num]].cr;
1244                         mtdcr(memcfgd, temp);
1245                         bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
1246                         debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp);
1247                 }
1248         }
1249
1250         return(bank_base_addr);
1251 }
1252 #endif /* CONFIG_SPD_EEPROM */