cpu/ppc4xx/44x_spd_ddr.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr.c
   3  * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
   4  * DDR controller. Those are 440GP/GX/EP/GR.
   5  *
   6  * (C) Copyright 2001
   7  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
   8  *
   9  * Based on code by:
  10  *
  11  * Kenneth Johansson ,Ericsson AB.
  12  * kenneth.johansson@etx.ericsson.se
  13  *
  14  * hacked up by bill hunter. fixed so we could run before
  15  * serial_init and console_init. previous version avoided this by
  16  * running out of cache memory during serial/console init, then running
  17  * this code later.
  18  *
  19  * (C) Copyright 2002
  20  * Jun Gu, Artesyn Technology, jung@artesyncp.com
  21  * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
  22  *
  23  * (C) Copyright 2005-2007
  24  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  25  *
  26  * See file CREDITS for list of people who contributed to this
  27  * project.
  28  *
  29  * This program is free software; you can redistribute it and/or
  30  * modify it under the terms of the GNU General Public License as
  31  * published by the Free Software Foundation; either version 2 of
  32  * the License, or (at your option) any later version.
  33  *
  34  * This program is distributed in the hope that it will be useful,
  35  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  36  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  37  * GNU General Public License for more details.
  38  *
  39  * You should have received a copy of the GNU General Public License
  40  * along with this program; if not, write to the Free Software
  41  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  42  * MA 02111-1307 USA
  43  */
  44
  45 /* define DEBUG for debugging output (obviously ;-)) */
  46 #if 0
  47 #define DEBUG
  48 #endif
  49
  50 #include <common.h>
  51 #include <asm/processor.h>
  52 #include <i2c.h>
  53 #include <ppc4xx.h>
  54 #include <asm/mmu.h>
  55
  56 #if defined(CONFIG_SPD_EEPROM) &&                                       \
  57         (defined(CONFIG_440GP) || defined(CONFIG_440GX) ||              \
  58          defined(CONFIG_440EP) || defined(CONFIG_440GR))
  59
  60 /*
  61  * Set default values
  62  */
  63 #ifndef CFG_I2C_SPEED
  64 #define CFG_I2C_SPEED   50000
  65 #endif
  66
  67 #ifndef CFG_I2C_SLAVE
  68 #define CFG_I2C_SLAVE   0xFE
  69 #endif
  70
  71 #define ONE_BILLION     1000000000
  72
  73 /*
  74  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
  75  */
  76 void __spd_ddr_init_hang (void)
  77 {
  78         hang ();
  79 }
  80 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
  81
  82 /*-----------------------------------------------------------------------------
  83   |  Memory Controller Options 0
  84   +-----------------------------------------------------------------------------*/
  85 #define SDRAM_CFG0_DCEN         0x80000000      /* SDRAM Controller Enable      */
  86 #define SDRAM_CFG0_MCHK_MASK    0x30000000      /* Memory data errchecking mask */
  87 #define SDRAM_CFG0_MCHK_NON     0x00000000      /* No ECC generation            */
  88 #define SDRAM_CFG0_MCHK_GEN     0x20000000      /* ECC generation               */
  89 #define SDRAM_CFG0_MCHK_CHK     0x30000000      /* ECC generation and checking  */
  90 #define SDRAM_CFG0_RDEN         0x08000000      /* Registered DIMM enable       */
  91 #define SDRAM_CFG0_PMUD         0x04000000      /* Page management unit         */
  92 #define SDRAM_CFG0_DMWD_MASK    0x02000000      /* DRAM width mask              */
  93 #define SDRAM_CFG0_DMWD_32      0x00000000      /* 32 bits                      */
  94 #define SDRAM_CFG0_DMWD_64      0x02000000      /* 64 bits                      */
  95 #define SDRAM_CFG0_UIOS_MASK    0x00C00000      /* Unused IO State              */
  96 #define SDRAM_CFG0_PDP          0x00200000      /* Page deallocation policy     */
  97
  98 /*-----------------------------------------------------------------------------
  99   |  Memory Controller Options 1
 100   +-----------------------------------------------------------------------------*/
 101 #define SDRAM_CFG1_SRE          0x80000000      /* Self-Refresh Entry           */
 102 #define SDRAM_CFG1_PMEN         0x40000000      /* Power Management Enable      */
 103
 104 /*-----------------------------------------------------------------------------+
 105   |  SDRAM DEVPOT Options
 106   +-----------------------------------------------------------------------------*/
 107 #define SDRAM_DEVOPT_DLL        0x80000000
 108 #define SDRAM_DEVOPT_DS         0x40000000
 109
 110 /*-----------------------------------------------------------------------------+
 111   |  SDRAM MCSTS Options
 112   +-----------------------------------------------------------------------------*/
 113 #define SDRAM_MCSTS_MRSC        0x80000000
 114 #define SDRAM_MCSTS_SRMS        0x40000000
 115 #define SDRAM_MCSTS_CIS         0x20000000
 116
 117 /*-----------------------------------------------------------------------------
 118   |  SDRAM Refresh Timer Register
 119   +-----------------------------------------------------------------------------*/
 120 #define SDRAM_RTR_RINT_MASK       0xFFFF0000
 121 #define SDRAM_RTR_RINT_ENCODE(n)  (((n) << 16) & SDRAM_RTR_RINT_MASK)
 122 #define sdram_HZ_to_ns(hertz)     (1000000000/(hertz))
 123
 124 /*-----------------------------------------------------------------------------+
 125   |  SDRAM UABus Base Address Reg
 126   +-----------------------------------------------------------------------------*/
 127 #define SDRAM_UABBA_UBBA_MASK   0x0000000F
 128
 129 /*-----------------------------------------------------------------------------+
 130   |  Memory Bank 0-7 configuration
 131   +-----------------------------------------------------------------------------*/
 132 #define SDRAM_BXCR_SDBA_MASK    0xff800000        /* Base address             */
 133 #define SDRAM_BXCR_SDSZ_MASK    0x000e0000        /* Size                     */
 134 #define SDRAM_BXCR_SDSZ_8       0x00020000        /*   8M                     */
 135 #define SDRAM_BXCR_SDSZ_16      0x00040000        /*  16M                     */
 136 #define SDRAM_BXCR_SDSZ_32      0x00060000        /*  32M                     */
 137 #define SDRAM_BXCR_SDSZ_64      0x00080000        /*  64M                     */
 138 #define SDRAM_BXCR_SDSZ_128     0x000a0000        /* 128M                     */
 139 #define SDRAM_BXCR_SDSZ_256     0x000c0000        /* 256M                     */
 140 #define SDRAM_BXCR_SDSZ_512     0x000e0000        /* 512M                     */
 141 #define SDRAM_BXCR_SDAM_MASK    0x0000e000        /* Addressing mode          */
 142 #define SDRAM_BXCR_SDAM_1       0x00000000        /*   Mode 1                 */
 143 #define SDRAM_BXCR_SDAM_2       0x00002000        /*   Mode 2                 */
 144 #define SDRAM_BXCR_SDAM_3       0x00004000        /*   Mode 3                 */
 145 #define SDRAM_BXCR_SDAM_4       0x00006000        /*   Mode 4                 */
 146 #define SDRAM_BXCR_SDBE         0x00000001        /* Memory Bank Enable       */
 147
 148 /*-----------------------------------------------------------------------------+
 149   |  SDRAM TR0 Options
 150   +-----------------------------------------------------------------------------*/
 151 #define SDRAM_TR0_SDWR_MASK     0x80000000
 152 #define  SDRAM_TR0_SDWR_2_CLK   0x00000000
 153 #define  SDRAM_TR0_SDWR_3_CLK   0x80000000
 154 #define SDRAM_TR0_SDWD_MASK     0x40000000
 155 #define  SDRAM_TR0_SDWD_0_CLK   0x00000000
 156 #define  SDRAM_TR0_SDWD_1_CLK   0x40000000
 157 #define SDRAM_TR0_SDCL_MASK     0x01800000
 158 #define  SDRAM_TR0_SDCL_2_0_CLK 0x00800000
 159 #define  SDRAM_TR0_SDCL_2_5_CLK 0x01000000
 160 #define  SDRAM_TR0_SDCL_3_0_CLK 0x01800000
 161 #define SDRAM_TR0_SDPA_MASK     0x000C0000
 162 #define  SDRAM_TR0_SDPA_2_CLK   0x00040000
 163 #define  SDRAM_TR0_SDPA_3_CLK   0x00080000
 164 #define  SDRAM_TR0_SDPA_4_CLK   0x000C0000
 165 #define SDRAM_TR0_SDCP_MASK     0x00030000
 166 #define  SDRAM_TR0_SDCP_2_CLK   0x00000000
 167 #define  SDRAM_TR0_SDCP_3_CLK   0x00010000
 168 #define  SDRAM_TR0_SDCP_4_CLK   0x00020000
 169 #define  SDRAM_TR0_SDCP_5_CLK   0x00030000
 170 #define SDRAM_TR0_SDLD_MASK     0x0000C000
 171 #define  SDRAM_TR0_SDLD_1_CLK   0x00000000
 172 #define  SDRAM_TR0_SDLD_2_CLK   0x00004000
 173 #define SDRAM_TR0_SDRA_MASK     0x0000001C
 174 #define  SDRAM_TR0_SDRA_6_CLK   0x00000000
 175 #define  SDRAM_TR0_SDRA_7_CLK   0x00000004
 176 #define  SDRAM_TR0_SDRA_8_CLK   0x00000008
 177 #define  SDRAM_TR0_SDRA_9_CLK   0x0000000C
 178 #define  SDRAM_TR0_SDRA_10_CLK  0x00000010
 179 #define  SDRAM_TR0_SDRA_11_CLK  0x00000014
 180 #define  SDRAM_TR0_SDRA_12_CLK  0x00000018
 181 #define  SDRAM_TR0_SDRA_13_CLK  0x0000001C
 182 #define SDRAM_TR0_SDRD_MASK     0x00000003
 183 #define  SDRAM_TR0_SDRD_2_CLK   0x00000001
 184 #define  SDRAM_TR0_SDRD_3_CLK   0x00000002
 185 #define  SDRAM_TR0_SDRD_4_CLK   0x00000003
 186
 187 /*-----------------------------------------------------------------------------+
 188   |  SDRAM TR1 Options
 189   +-----------------------------------------------------------------------------*/
 190 #define SDRAM_TR1_RDSS_MASK     0xC0000000
 191 #define  SDRAM_TR1_RDSS_TR0     0x00000000
 192 #define  SDRAM_TR1_RDSS_TR1     0x40000000
 193 #define  SDRAM_TR1_RDSS_TR2     0x80000000
 194 #define  SDRAM_TR1_RDSS_TR3     0xC0000000
 195 #define SDRAM_TR1_RDSL_MASK     0x00C00000
 196 #define  SDRAM_TR1_RDSL_STAGE1  0x00000000
 197 #define  SDRAM_TR1_RDSL_STAGE2  0x00400000
 198 #define  SDRAM_TR1_RDSL_STAGE3  0x00800000
 199 #define SDRAM_TR1_RDCD_MASK     0x00000800
 200 #define  SDRAM_TR1_RDCD_RCD_0_0 0x00000000
 201 #define  SDRAM_TR1_RDCD_RCD_1_2 0x00000800
 202 #define SDRAM_TR1_RDCT_MASK     0x000001FF
 203 #define  SDRAM_TR1_RDCT_ENCODE(x)  (((x) << 0) & SDRAM_TR1_RDCT_MASK)
 204 #define  SDRAM_TR1_RDCT_DECODE(x)  (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
 205 #define  SDRAM_TR1_RDCT_MIN     0x00000000
 206 #define  SDRAM_TR1_RDCT_MAX     0x000001FF
 207
 208 /*-----------------------------------------------------------------------------+
 209   |  SDRAM WDDCTR Options
 210   +-----------------------------------------------------------------------------*/
 211 #define SDRAM_WDDCTR_WRCP_MASK  0xC0000000
 212 #define  SDRAM_WDDCTR_WRCP_0DEG   0x00000000
 213 #define  SDRAM_WDDCTR_WRCP_90DEG  0x40000000
 214 #define  SDRAM_WDDCTR_WRCP_180DEG 0x80000000
 215 #define SDRAM_WDDCTR_DCD_MASK   0x000001FF
 216
 217 /*-----------------------------------------------------------------------------+
 218   |  SDRAM CLKTR Options
 219   +-----------------------------------------------------------------------------*/
 220 #define SDRAM_CLKTR_CLKP_MASK   0xC0000000
 221 #define  SDRAM_CLKTR_CLKP_0DEG    0x00000000
 222 #define  SDRAM_CLKTR_CLKP_90DEG   0x40000000
 223 #define  SDRAM_CLKTR_CLKP_180DEG  0x80000000
 224 #define SDRAM_CLKTR_DCDT_MASK   0x000001FF
 225
 226 /*-----------------------------------------------------------------------------+
 227   |  SDRAM DLYCAL Options
 228   +-----------------------------------------------------------------------------*/
 229 #define SDRAM_DLYCAL_DLCV_MASK  0x000003FC
 230 #define  SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
 231 #define  SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
 232
 233 /*-----------------------------------------------------------------------------+
 234   |  General Definition
 235   +-----------------------------------------------------------------------------*/
 236 #define DEFAULT_SPD_ADDR1       0x53
 237 #define DEFAULT_SPD_ADDR2       0x52
 238 #define MAXBANKS                4               /* at most 4 dimm banks */
 239 #define MAX_SPD_BYTES           256
 240 #define NUMHALFCYCLES           4
 241 #define NUMMEMTESTS             8
 242 #define NUMMEMWORDS             8
 243 #define MAXBXCR                 4
 244 #define TRUE                    1
 245 #define FALSE                   0
 246
 247 /*
 248  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
 249  * region. Right now the cache should still be disabled in U-Boot because of the
 250  * EMAC driver, that need it's buffer descriptor to be located in non cached
 251  * memory.
 252  *
 253  * If at some time this restriction doesn't apply anymore, just define
 254  * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
 255  * everything correctly.
 256  */
 257 #ifdef CFG_ENABLE_SDRAM_CACHE
 258 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
 259 #else
 260 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 261 #endif
 262
 263 /* bank_parms is used to sort the bank sizes by descending order */
 264 struct bank_param {
 265         unsigned long cr;
 266         unsigned long bank_size_bytes;
 267 };
 268
 269 typedef struct bank_param BANKPARMS;
 270
 271 #ifdef CFG_SIMULATE_SPD_EEPROM
 272 extern unsigned char cfg_simulate_spd_eeprom[128];
 273 #endif
 274 void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
 275
 276 static unsigned char spd_read(uchar chip, uint addr);
 277 static void get_spd_info(unsigned long *dimm_populated,
 278                          unsigned char *iic0_dimm_addr,
 279                          unsigned long num_dimm_banks);
 280 static void check_mem_type(unsigned long *dimm_populated,
 281                            unsigned char *iic0_dimm_addr,
 282                            unsigned long num_dimm_banks);
 283 static void check_volt_type(unsigned long *dimm_populated,
 284                             unsigned char *iic0_dimm_addr,
 285                             unsigned long num_dimm_banks);
 286 static void program_cfg0(unsigned long *dimm_populated,
 287                          unsigned char *iic0_dimm_addr,
 288                          unsigned long  num_dimm_banks);
 289 static void program_cfg1(unsigned long *dimm_populated,
 290                          unsigned char *iic0_dimm_addr,
 291                          unsigned long num_dimm_banks);
 292 static void program_rtr(unsigned long *dimm_populated,
 293                         unsigned char *iic0_dimm_addr,
 294                         unsigned long num_dimm_banks);
 295 static void program_tr0(unsigned long *dimm_populated,
 296                         unsigned char *iic0_dimm_addr,
 297                         unsigned long num_dimm_banks);
 298 static void program_tr1(void);
 299
 300 #ifdef CONFIG_DDR_ECC
 301 static void program_ecc(unsigned long num_bytes);
 302 #endif
 303
 304 static unsigned long program_bxcr(unsigned long *dimm_populated,
 305                                   unsigned char *iic0_dimm_addr,
 306                                   unsigned long num_dimm_banks);
 307
 308 /*
 309  * This function is reading data from the DIMM module EEPROM over the SPD bus
 310  * and uses that to program the sdram controller.
 311  *
 312  * This works on boards that has the same schematics that the AMCC walnut has.
 313  *
 314  * BUG: Don't handle ECC memory
 315  * BUG: A few values in the TR register is currently hardcoded
 316  */
 317 long int spd_sdram(void) {
 318         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 319         unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
 320         unsigned long total_size;
 321         unsigned long cfg0;
 322         unsigned long mcsts;
 323         unsigned long num_dimm_banks;               /* on board dimm banks */
 324
 325         num_dimm_banks = sizeof(iic0_dimm_addr);
 326
 327         /*
 328          * Make sure I2C controller is initialized
 329          * before continuing.
 330          */
 331         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 332
 333         /*
 334          * Read the SPD information using I2C interface. Check to see if the
 335          * DIMM slots are populated.
 336          */
 337         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 338
 339         /*
 340          * Check the memory type for the dimms plugged.
 341          */
 342         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 343
 344         /*
 345          * Check the voltage type for the dimms plugged.
 346          */
 347         check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 348
 349 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
 350         /*
 351          * Soft-reset SDRAM controller.
 352          */
 353         mtsdr(sdr_srst, SDR0_SRST_DMC);
 354         mtsdr(sdr_srst, 0x00000000);
 355 #endif
 356
 357         /*
 358          * program 440GP SDRAM controller options (SDRAM0_CFG0)
 359          */
 360         program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 361
 362         /*
 363          * program 440GP SDRAM controller options (SDRAM0_CFG1)
 364          */
 365         program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 366
 367         /*
 368          * program SDRAM refresh register (SDRAM0_RTR)
 369          */
 370         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 371
 372         /*
 373          * program SDRAM Timing Register 0 (SDRAM0_TR0)
 374          */
 375         program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 376
 377         /*
 378          * program the BxCR registers to find out total sdram installed
 379          */
 380         total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
 381                                   num_dimm_banks);
 382
 383 #ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
 384         /* and program tlb entries for this size (dynamic) */
 385         program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE);
 386 #endif
 387
 388         /*
 389          * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
 390          */
 391         mtsdram(mem_clktr, 0x40000000);
 392
 393         /*
 394          * delay to ensure 200 usec has elapsed
 395          */
 396         udelay(400);
 397
 398         /*
 399          * enable the memory controller
 400          */
 401         mfsdram(mem_cfg0, cfg0);
 402         mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
 403
 404         /*
 405          * wait for SDRAM_CFG0_DC_EN to complete
 406          */
 407         while (1) {
 408                 mfsdram(mem_mcsts, mcsts);
 409                 if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
 410                         break;
 411         }
 412
 413         /*
 414          * program SDRAM Timing Register 1, adding some delays
 415          */
 416         program_tr1();
 417
 418 #ifdef CONFIG_DDR_ECC
 419         /*
 420          * If ecc is enabled, initialize the parity bits.
 421          */
 422         program_ecc(total_size);
 423 #endif
 424
 425         return total_size;
 426 }
 427
 428 static unsigned char spd_read(uchar chip, uint addr)
 429 {
 430         unsigned char data[2];
 431
 432 #ifdef CFG_SIMULATE_SPD_EEPROM
 433         if (chip == CFG_SIMULATE_SPD_EEPROM) {
 434                 /*
 435                  * Onboard spd eeprom requested -> simulate values
 436                  */
 437                 return cfg_simulate_spd_eeprom[addr];
 438         }
 439 #endif /* CFG_SIMULATE_SPD_EEPROM */
 440
 441         if (i2c_probe(chip) == 0) {
 442                 if (i2c_read(chip, addr, 1, data, 1) == 0) {
 443                         return data[0];
 444                 }
 445         }
 446
 447         return 0;
 448 }
 449
 450 static void get_spd_info(unsigned long *dimm_populated,
 451                          unsigned char *iic0_dimm_addr,
 452                          unsigned long num_dimm_banks)
 453 {
 454         unsigned long dimm_num;
 455         unsigned long dimm_found;
 456         unsigned char num_of_bytes;
 457         unsigned char total_size;
 458
 459         dimm_found = FALSE;
 460         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 461                 num_of_bytes = 0;
 462                 total_size = 0;
 463
 464                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 465                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 466
 467                 if ((num_of_bytes != 0) && (total_size != 0)) {
 468                         dimm_populated[dimm_num] = TRUE;
 469                         dimm_found = TRUE;
 470                         debug("DIMM slot %lu: populated\n", dimm_num);
 471                 } else {
 472                         dimm_populated[dimm_num] = FALSE;
 473                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 474                 }
 475         }
 476
 477         if (dimm_found == FALSE) {
 478                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 479                 spd_ddr_init_hang ();
 480         }
 481 }
 482
 483 static void check_mem_type(unsigned long *dimm_populated,
 484                            unsigned char *iic0_dimm_addr,
 485                            unsigned long num_dimm_banks)
 486 {
 487         unsigned long dimm_num;
 488         unsigned char dimm_type;
 489
 490         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 491                 if (dimm_populated[dimm_num] == TRUE) {
 492                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 493                         switch (dimm_type) {
 494                         case 7:
 495                                 debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
 496                                 break;
 497                         default:
 498                                 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
 499                                        dimm_num);
 500                                 printf("Only DDR SDRAM DIMMs are supported.\n");
 501                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 502                                 spd_ddr_init_hang ();
 503                                 break;
 504                         }
 505                 }
 506         }
 507 }
 508
 509 static void check_volt_type(unsigned long *dimm_populated,
 510                             unsigned char *iic0_dimm_addr,
 511                             unsigned long num_dimm_banks)
 512 {
 513         unsigned long dimm_num;
 514         unsigned long voltage_type;
 515
 516         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 517                 if (dimm_populated[dimm_num] == TRUE) {
 518                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 519                         if (voltage_type != 0x04) {
 520                                 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
 521                                        dimm_num);
 522                                 spd_ddr_init_hang ();
 523                         } else {
 524                                 debug("DIMM %lu voltage level supported.\n", dimm_num);
 525                         }
 526                         break;
 527                 }
 528         }
 529 }
 530
 531 static void program_cfg0(unsigned long *dimm_populated,
 532                          unsigned char *iic0_dimm_addr,
 533                          unsigned long num_dimm_banks)
 534 {
 535         unsigned long dimm_num;
 536         unsigned long cfg0;
 537         unsigned long ecc_enabled;
 538         unsigned char ecc;
 539         unsigned char attributes;
 540         unsigned long data_width;
 541         unsigned long dimm_32bit;
 542         unsigned long dimm_64bit;
 543
 544         /*
 545          * get Memory Controller Options 0 data
 546          */
 547         mfsdram(mem_cfg0, cfg0);
 548
 549         /*
 550          * clear bits
 551          */
 552         cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
 553                   SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
 554                   SDRAM_CFG0_DMWD_MASK |
 555                   SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
 556
 557
 558         /*
 559          * FIXME: assume the DDR SDRAMs in both banks are the same
 560          */
 561         ecc_enabled = TRUE;
 562         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 563                 if (dimm_populated[dimm_num] == TRUE) {
 564                         ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
 565                         if (ecc != 0x02) {
 566                                 ecc_enabled = FALSE;
 567                         }
 568
 569                         /*
 570                          * program Registered DIMM Enable
 571                          */
 572                         attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
 573                         if ((attributes & 0x02) != 0x00) {
 574                                 cfg0 |= SDRAM_CFG0_RDEN;
 575                         }
 576
 577                         /*
 578                          * program DDR SDRAM Data Width
 579                          */
 580                         data_width =
 581                                 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
 582                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
 583                         if (data_width == 64 || data_width == 72) {
 584                                 dimm_64bit = TRUE;
 585                                 cfg0 |= SDRAM_CFG0_DMWD_64;
 586                         } else if (data_width == 32 || data_width == 40) {
 587                                 dimm_32bit = TRUE;
 588                                 cfg0 |= SDRAM_CFG0_DMWD_32;
 589                         } else {
 590                                 printf("WARNING: DIMM with datawidth of %lu bits.\n",
 591                                        data_width);
 592                                 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
 593                                 spd_ddr_init_hang ();
 594                         }
 595                         break;
 596                 }
 597         }
 598
 599         /*
 600          * program Memory Data Error Checking
 601          */
 602         if (ecc_enabled == TRUE) {
 603                 cfg0 |= SDRAM_CFG0_MCHK_GEN;
 604         } else {
 605                 cfg0 |= SDRAM_CFG0_MCHK_NON;
 606         }
 607
 608         /*
 609          * program Page Management Unit (0 == enabled)
 610          */
 611         cfg0 &= ~SDRAM_CFG0_PMUD;
 612
 613         /*
 614          * program Memory Controller Options 0
 615          * Note: DCEN must be enabled after all DDR SDRAM controller
 616          * configuration registers get initialized.
 617          */
 618         mtsdram(mem_cfg0, cfg0);
 619 }
 620
 621 static void program_cfg1(unsigned long *dimm_populated,
 622                          unsigned char *iic0_dimm_addr,
 623                          unsigned long num_dimm_banks)
 624 {
 625         unsigned long cfg1;
 626         mfsdram(mem_cfg1, cfg1);
 627
 628         /*
 629          * Self-refresh exit, disable PM
 630          */
 631         cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
 632
 633         /*
 634          * program Memory Controller Options 1
 635          */
 636         mtsdram(mem_cfg1, cfg1);
 637 }
 638
 639 static void program_rtr(unsigned long *dimm_populated,
 640                         unsigned char *iic0_dimm_addr,
 641                         unsigned long num_dimm_banks)
 642 {
 643         unsigned long dimm_num;
 644         unsigned long bus_period_x_10;
 645         unsigned long refresh_rate = 0;
 646         unsigned char refresh_rate_type;
 647         unsigned long refresh_interval;
 648         unsigned long sdram_rtr;
 649         PPC440_SYS_INFO sys_info;
 650
 651         /*
 652          * get the board info
 653          */
 654         get_sys_info(&sys_info);
 655         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 656
 657         for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
 658                 if (dimm_populated[dimm_num] == TRUE) {
 659                         refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
 660                         switch (refresh_rate_type) {
 661                         case 0x00:
 662                                 refresh_rate = 15625;
 663                                 break;
 664                         case 0x01:
 665                                 refresh_rate = 15625/4;
 666                                 break;
 667                         case 0x02:
 668                                 refresh_rate = 15625/2;
 669                                 break;
 670                         case 0x03:
 671                                 refresh_rate = 15626*2;
 672                                 break;
 673                         case 0x04:
 674                                 refresh_rate = 15625*4;
 675                                 break;
 676                         case 0x05:
 677                                 refresh_rate = 15625*8;
 678                                 break;
 679                         default:
 680                                 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
 681                                        dimm_num);
 682                                 printf("Replace the DIMM module with a supported DIMM.\n");
 683                                 break;
 684                         }
 685
 686                         break;
 687                 }
 688         }
 689
 690         refresh_interval = refresh_rate * 10 / bus_period_x_10;
 691         sdram_rtr = (refresh_interval & 0x3ff8) <<  16;
 692
 693         /*
 694          * program Refresh Timer Register (SDRAM0_RTR)
 695          */
 696         mtsdram(mem_rtr, sdram_rtr);
 697 }
 698
 699 static void program_tr0(unsigned long *dimm_populated,
 700                          unsigned char *iic0_dimm_addr,
 701                          unsigned long num_dimm_banks)
 702 {
 703         unsigned long dimm_num;
 704         unsigned long tr0;
 705         unsigned char wcsbc;
 706         unsigned char t_rp_ns;
 707         unsigned char t_rcd_ns;
 708         unsigned char t_ras_ns;
 709         unsigned long t_rp_clk;
 710         unsigned long t_ras_rcd_clk;
 711         unsigned long t_rcd_clk;
 712         unsigned long t_rfc_clk;
 713         unsigned long plb_check;
 714         unsigned char cas_bit;
 715         unsigned long cas_index;
 716         unsigned char cas_2_0_available;
 717         unsigned char cas_2_5_available;
 718         unsigned char cas_3_0_available;
 719         unsigned long cycle_time_ns_x_10[3];
 720         unsigned long tcyc_3_0_ns_x_10;
 721         unsigned long tcyc_2_5_ns_x_10;
 722         unsigned long tcyc_2_0_ns_x_10;
 723         unsigned long tcyc_reg;
 724         unsigned long bus_period_x_10;
 725         PPC440_SYS_INFO sys_info;
 726         unsigned long residue;
 727
 728         /*
 729          * get the board info
 730          */
 731         get_sys_info(&sys_info);
 732         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 733
 734         /*
 735          * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
 736          */
 737         mfsdram(mem_tr0, tr0);
 738         tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
 739                  SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
 740                  SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
 741                  SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
 742
 743         /*
 744          * initialization
 745          */
 746         wcsbc = 0;
 747         t_rp_ns = 0;
 748         t_rcd_ns = 0;
 749         t_ras_ns = 0;
 750         cas_2_0_available = TRUE;
 751         cas_2_5_available = TRUE;
 752         cas_3_0_available = TRUE;
 753         tcyc_2_0_ns_x_10 = 0;
 754         tcyc_2_5_ns_x_10 = 0;
 755         tcyc_3_0_ns_x_10 = 0;
 756
 757         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 758                 if (dimm_populated[dimm_num] == TRUE) {
 759                         wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
 760                         t_rp_ns  = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
 761                         t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
 762                         t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
 763                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
 764
 765                         for (cas_index = 0; cas_index < 3; cas_index++) {
 766                                 switch (cas_index) {
 767                                 case 0:
 768                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 769                                         break;
 770                                 case 1:
 771                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
 772                                         break;
 773                                 default:
 774                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
 775                                         break;
 776                                 }
 777
 778                                 if ((tcyc_reg & 0x0F) >= 10) {
 779                                         printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
 780                                                dimm_num);
 781                                         spd_ddr_init_hang ();
 782                                 }
 783
 784                                 cycle_time_ns_x_10[cas_index] =
 785                                         (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
 786                         }
 787
 788                         cas_index = 0;
 789
 790                         if ((cas_bit & 0x80) != 0) {
 791                                 cas_index += 3;
 792                         } else if ((cas_bit & 0x40) != 0) {
 793                                 cas_index += 2;
 794                         } else if ((cas_bit & 0x20) != 0) {
 795                                 cas_index += 1;
 796                         }
 797
 798                         if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
 799                                 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
 800                                 cas_index++;
 801                         } else {
 802                                 if (cas_index != 0) {
 803                                         cas_index++;
 804                                 }
 805                                 cas_3_0_available = FALSE;
 806                         }
 807
 808                         if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
 809                                 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
 810                                 cas_index++;
 811                         } else {
 812                                 if (cas_index != 0) {
 813                                         cas_index++;
 814                                 }
 815                                 cas_2_5_available = FALSE;
 816                         }
 817
 818                         if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
 819                                 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
 820                                 cas_index++;
 821                         } else {
 822                                 if (cas_index != 0) {
 823                                         cas_index++;
 824                                 }
 825                                 cas_2_0_available = FALSE;
 826                         }
 827
 828                         break;
 829                 }
 830         }
 831
 832         /*
 833          * Program SD_WR and SD_WCSBC fields
 834          */
 835         tr0 |= SDRAM_TR0_SDWR_2_CLK;                /* Write Recovery: 2 CLK */
 836         switch (wcsbc) {
 837         case 0:
 838                 tr0 |= SDRAM_TR0_SDWD_0_CLK;
 839                 break;
 840         default:
 841                 tr0 |= SDRAM_TR0_SDWD_1_CLK;
 842                 break;
 843         }
 844
 845         /*
 846          * Program SD_CASL field
 847          */
 848         if ((cas_2_0_available == TRUE) &&
 849             (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
 850                 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
 851         } else if ((cas_2_5_available == TRUE) &&
 852                  (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
 853                 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
 854         } else if ((cas_3_0_available == TRUE) &&
 855                  (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
 856                 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
 857         } else {
 858                 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
 859                 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
 860                 printf("Make sure the PLB speed is within the supported range.\n");
 861                 spd_ddr_init_hang ();
 862         }
 863
 864         /*
 865          * Calculate Trp in clock cycles and round up if necessary
 866          * Program SD_PTA field
 867          */
 868         t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
 869         plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
 870         if (sys_info.freqPLB != plb_check) {
 871                 t_rp_clk++;
 872         }
 873         switch ((unsigned long)t_rp_clk) {
 874         case 0:
 875         case 1:
 876         case 2:
 877                 tr0 |= SDRAM_TR0_SDPA_2_CLK;
 878                 break;
 879         case 3:
 880                 tr0 |= SDRAM_TR0_SDPA_3_CLK;
 881                 break;
 882         default:
 883                 tr0 |= SDRAM_TR0_SDPA_4_CLK;
 884                 break;
 885         }
 886
 887         /*
 888          * Program SD_CTP field
 889          */
 890         t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
 891         plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
 892         if (sys_info.freqPLB != plb_check) {
 893                 t_ras_rcd_clk++;
 894         }
 895         switch (t_ras_rcd_clk) {
 896         case 0:
 897         case 1:
 898         case 2:
 899                 tr0 |= SDRAM_TR0_SDCP_2_CLK;
 900                 break;
 901         case 3:
 902                 tr0 |= SDRAM_TR0_SDCP_3_CLK;
 903                 break;
 904         case 4:
 905                 tr0 |= SDRAM_TR0_SDCP_4_CLK;
 906                 break;
 907         default:
 908                 tr0 |= SDRAM_TR0_SDCP_5_CLK;
 909                 break;
 910         }
 911
 912         /*
 913          * Program SD_LDF field
 914          */
 915         tr0 |= SDRAM_TR0_SDLD_2_CLK;
 916
 917         /*
 918          * Program SD_RFTA field
 919          * FIXME tRFC hardcoded as 75 nanoseconds
 920          */
 921         t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
 922         residue = sys_info.freqPLB % (ONE_BILLION / 75);
 923         if (residue >= (ONE_BILLION / 150)) {
 924                 t_rfc_clk++;
 925         }
 926         switch (t_rfc_clk) {
 927         case 0:
 928         case 1:
 929         case 2:
 930         case 3:
 931         case 4:
 932         case 5:
 933         case 6:
 934                 tr0 |= SDRAM_TR0_SDRA_6_CLK;
 935                 break;
 936         case 7:
 937                 tr0 |= SDRAM_TR0_SDRA_7_CLK;
 938                 break;
 939         case 8:
 940                 tr0 |= SDRAM_TR0_SDRA_8_CLK;
 941                 break;
 942         case 9:
 943                 tr0 |= SDRAM_TR0_SDRA_9_CLK;
 944                 break;
 945         case 10:
 946                 tr0 |= SDRAM_TR0_SDRA_10_CLK;
 947                 break;
 948         case 11:
 949                 tr0 |= SDRAM_TR0_SDRA_11_CLK;
 950                 break;
 951         case 12:
 952                 tr0 |= SDRAM_TR0_SDRA_12_CLK;
 953                 break;
 954         default:
 955                 tr0 |= SDRAM_TR0_SDRA_13_CLK;
 956                 break;
 957         }
 958
 959         /*
 960          * Program SD_RCD field
 961          */
 962         t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
 963         plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
 964         if (sys_info.freqPLB != plb_check) {
 965                 t_rcd_clk++;
 966         }
 967         switch (t_rcd_clk) {
 968         case 0:
 969         case 1:
 970         case 2:
 971                 tr0 |= SDRAM_TR0_SDRD_2_CLK;
 972                 break;
 973         case 3:
 974                 tr0 |= SDRAM_TR0_SDRD_3_CLK;
 975                 break;
 976         default:
 977                 tr0 |= SDRAM_TR0_SDRD_4_CLK;
 978                 break;
 979         }
 980
 981         debug("tr0: %x\n", tr0);
 982         mtsdram(mem_tr0, tr0);
 983 }
 984
 985 static int short_mem_test(void)
 986 {
 987         unsigned long i, j;
 988         unsigned long bxcr_num;
 989         unsigned long *membase;
 990         const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
 991                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 992                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
 993                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 994                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
 995                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 996                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
 997                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 998                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
 999                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
1000                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
1001                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
1002                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
1003                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
1004                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
1005                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
1006                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
1007
1008         for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1009                 mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
1010                 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
1011                         /* Bank is enabled */
1012                         membase = (unsigned long*)
1013                                 (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
1014
1015                         /*
1016                          * Run the short memory test
1017                          */
1018                         for (i = 0; i < NUMMEMTESTS; i++) {
1019                                 for (j = 0; j < NUMMEMWORDS; j++) {
1020 //printf("bank enabled base:%x\n", &membase[j]);
1021                                         membase[j] = test[i][j];
1022                                         ppcDcbf((unsigned long)&(membase[j]));
1023                                 }
1024
1025                                 for (j = 0; j < NUMMEMWORDS; j++) {
1026                                         if (membase[j] != test[i][j]) {
1027                                                 ppcDcbf((unsigned long)&(membase[j]));
1028                                                 return 0;
1029                                         }
1030                                         ppcDcbf((unsigned long)&(membase[j]));
1031                                 }
1032
1033                                 if (j < NUMMEMWORDS)
1034                                         return 0;
1035                         }
1036
1037                         /*
1038                          * see if the rdclt value passed
1039                          */
1040                         if (i < NUMMEMTESTS)
1041                                 return 0;
1042                 }
1043         }
1044
1045         return 1;
1046 }
1047
1048 static void program_tr1(void)
1049 {
1050         unsigned long tr0;
1051         unsigned long tr1;
1052         unsigned long cfg0;
1053         unsigned long ecc_temp;
1054         unsigned long dlycal;
1055         unsigned long dly_val;
1056         unsigned long k;
1057         unsigned long max_pass_length;
1058         unsigned long current_pass_length;
1059         unsigned long current_fail_length;
1060         unsigned long current_start;
1061         unsigned long rdclt;
1062         unsigned long rdclt_offset;
1063         long max_start;
1064         long max_end;
1065         long rdclt_average;
1066         unsigned char window_found;
1067         unsigned char fail_found;
1068         unsigned char pass_found;
1069         PPC440_SYS_INFO sys_info;
1070
1071         /*
1072          * get the board info
1073          */
1074         get_sys_info(&sys_info);
1075
1076         /*
1077          * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1078          */
1079         mfsdram(mem_tr1, tr1);
1080         tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
1081                  SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
1082
1083         mfsdram(mem_tr0, tr0);
1084         if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
1085             (sys_info.freqPLB > 100000000)) {
1086                 tr1 |= SDRAM_TR1_RDSS_TR2;
1087                 tr1 |= SDRAM_TR1_RDSL_STAGE3;
1088                 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1089         } else {
1090                 tr1 |= SDRAM_TR1_RDSS_TR1;
1091                 tr1 |= SDRAM_TR1_RDSL_STAGE2;
1092                 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1093         }
1094
1095         /*
1096          * save CFG0 ECC setting to a temporary variable and turn ECC off
1097          */
1098         mfsdram(mem_cfg0, cfg0);
1099         ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
1100         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
1101
1102         /*
1103          * get the delay line calibration register value
1104          */
1105         mfsdram(mem_dlycal, dlycal);
1106         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
1107
1108         max_pass_length = 0;
1109         max_start = 0;
1110         max_end = 0;
1111         current_pass_length = 0;
1112         current_fail_length = 0;
1113         current_start = 0;
1114         rdclt_offset = 0;
1115         window_found = FALSE;
1116         fail_found = FALSE;
1117         pass_found = FALSE;
1118         debug("Starting memory test ");
1119
1120         for (k = 0; k < NUMHALFCYCLES; k++) {
1121                 for (rdclt = 0; rdclt < dly_val; rdclt++) {
1122                         /*
1123                          * Set the timing reg for the test.
1124                          */
1125                         mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
1126
1127                         if (short_mem_test()) {
1128                                 if (fail_found == TRUE) {
1129                                         pass_found = TRUE;
1130                                         if (current_pass_length == 0) {
1131                                                 current_start = rdclt_offset + rdclt;
1132                                         }
1133
1134                                         current_fail_length = 0;
1135                                         current_pass_length++;
1136
1137                                         if (current_pass_length > max_pass_length) {
1138                                                 max_pass_length = current_pass_length;
1139                                                 max_start = current_start;
1140                                                 max_end = rdclt_offset + rdclt;
1141                                         }
1142                                 }
1143                         } else {
1144                                 current_pass_length = 0;
1145                                 current_fail_length++;
1146
1147                                 if (current_fail_length >= (dly_val>>2)) {
1148                                         if (fail_found == FALSE) {
1149                                                 fail_found = TRUE;
1150                                         } else if (pass_found == TRUE) {
1151                                                 window_found = TRUE;
1152                                                 break;
1153                                         }
1154                                 }
1155                         }
1156                 }
1157                 debug(".");
1158
1159                 if (window_found == TRUE) {
1160                         break;
1161                 }
1162
1163                 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1164                 rdclt_offset += dly_val;
1165         }
1166         debug("\n");
1167
1168         /*
1169          * make sure we find the window
1170          */
1171         if (window_found == FALSE) {
1172                 printf("ERROR: Cannot determine a common read delay.\n");
1173                 spd_ddr_init_hang ();
1174         }
1175
1176         /*
1177          * restore the orignal ECC setting
1178          */
1179         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1180
1181         /*
1182          * set the SDRAM TR1 RDCD value
1183          */
1184         tr1 &= ~SDRAM_TR1_RDCD_MASK;
1185         if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1186                 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1187         } else {
1188                 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1189         }
1190
1191         /*
1192          * set the SDRAM TR1 RDCLT value
1193          */
1194         tr1 &= ~SDRAM_TR1_RDCT_MASK;
1195         while (max_end >= (dly_val << 1)) {
1196                 max_end -= (dly_val << 1);
1197                 max_start -= (dly_val << 1);
1198         }
1199
1200         rdclt_average = ((max_start + max_end) >> 1);
1201         if (rdclt_average >= 0x60)
1202                 while (1)
1203                         ;
1204
1205         if (rdclt_average < 0) {
1206                 rdclt_average = 0;
1207         }
1208
1209         if (rdclt_average >= dly_val) {
1210                 rdclt_average -= dly_val;
1211                 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1212         }
1213         tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1214
1215         debug("tr1: %x\n", tr1);
1216
1217         /*
1218          * program SDRAM Timing Register 1 TR1
1219          */
1220         mtsdram(mem_tr1, tr1);
1221 }
1222
1223 static unsigned long program_bxcr(unsigned long *dimm_populated,
1224                                   unsigned char *iic0_dimm_addr,
1225                                   unsigned long num_dimm_banks)
1226 {
1227         unsigned long dimm_num;
1228         unsigned long bank_base_addr;
1229         unsigned long cr;
1230         unsigned long i;
1231         unsigned long j;
1232         unsigned long temp;
1233         unsigned char num_row_addr;
1234         unsigned char num_col_addr;
1235         unsigned char num_banks;
1236         unsigned char bank_size_id;
1237         unsigned long ctrl_bank_num[MAXBANKS];
1238         unsigned long bx_cr_num;
1239         unsigned long largest_size_index;
1240         unsigned long largest_size;
1241         unsigned long current_size_index;
1242         BANKPARMS bank_parms[MAXBXCR];
1243         unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
1244         unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
1245
1246         /*
1247          * Set the BxCR regs.  First, wipe out the bank config registers.
1248          */
1249         for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1250                 mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2));
1251                 mtdcr(memcfgd, 0x00000000);
1252                 bank_parms[bx_cr_num].bank_size_bytes = 0;
1253         }
1254
1255 #ifdef CONFIG_BAMBOO
1256         /*
1257          * This next section is hardware dependent and must be programmed
1258          * to match the hardware.  For bamboo, the following holds...
1259          * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard)
1260          * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
1261          * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
1262          * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
1263          * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
1264          */
1265         ctrl_bank_num[0] = 0;
1266         ctrl_bank_num[1] = 1;
1267         ctrl_bank_num[2] = 3;
1268 #else
1269         /*
1270          * Ocotea, Ebony and the other IBM/AMCC eval boards have
1271          * 2 DIMM slots with each max 2 banks
1272          */
1273         ctrl_bank_num[0] = 0;
1274         ctrl_bank_num[1] = 2;
1275 #endif
1276
1277         /*
1278          * reset the bank_base address
1279          */
1280         bank_base_addr = CFG_SDRAM_BASE;
1281
1282         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1283                 if (dimm_populated[dimm_num] == TRUE) {
1284                         num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1285                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1286                         num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
1287                         bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1288                         debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num,
1289                               num_row_addr, num_col_addr, num_banks);
1290
1291                         /*
1292                          * Set the SDRAM0_BxCR regs
1293                          */
1294                         cr = 0;
1295                         switch (bank_size_id) {
1296                         case 0x02:
1297                                 cr |= SDRAM_BXCR_SDSZ_8;
1298                                 break;
1299                         case 0x04:
1300                                 cr |= SDRAM_BXCR_SDSZ_16;
1301                                 break;
1302                         case 0x08:
1303                                 cr |= SDRAM_BXCR_SDSZ_32;
1304                                 break;
1305                         case 0x10:
1306                                 cr |= SDRAM_BXCR_SDSZ_64;
1307                                 break;
1308                         case 0x20:
1309                                 cr |= SDRAM_BXCR_SDSZ_128;
1310                                 break;
1311                         case 0x40:
1312                                 cr |= SDRAM_BXCR_SDSZ_256;
1313                                 break;
1314                         case 0x80:
1315                                 cr |= SDRAM_BXCR_SDSZ_512;
1316                                 break;
1317                         default:
1318                                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1319                                        dimm_num);
1320                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
1321                                        bank_size_id);
1322                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1323                                 spd_ddr_init_hang ();
1324                         }
1325
1326                         switch (num_col_addr) {
1327                         case 0x08:
1328                                 cr |= SDRAM_BXCR_SDAM_1;
1329                                 break;
1330                         case 0x09:
1331                                 cr |= SDRAM_BXCR_SDAM_2;
1332                                 break;
1333                         case 0x0A:
1334                                 cr |= SDRAM_BXCR_SDAM_3;
1335                                 break;
1336                         case 0x0B:
1337                                 cr |= SDRAM_BXCR_SDAM_4;
1338                                 break;
1339                         default:
1340                                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1341                                        dimm_num);
1342                                 printf("ERROR: Unsupported value for number of "
1343                                        "column addresses: %d.\n", num_col_addr);
1344                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1345                                 spd_ddr_init_hang ();
1346                         }
1347
1348                         /*
1349                          * enable the bank
1350                          */
1351                         cr |= SDRAM_BXCR_SDBE;
1352
1353                         for (i = 0; i < num_banks; i++) {
1354                                 bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
1355                                         (4 << 20) * bank_size_id;
1356                                 bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
1357                                 debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
1358                                       dimm_num, i, ctrl_bank_num[dimm_num]+i,
1359                                       bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
1360                         }
1361                 }
1362         }
1363
1364         /* Initialize sort tables */
1365         for (i = 0; i < MAXBXCR; i++) {
1366                 sorted_bank_num[i] = i;
1367                 sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
1368         }
1369
1370         for (i = 0; i < MAXBXCR-1; i++) {
1371                 largest_size = sorted_bank_size[i];
1372                 largest_size_index = 255;
1373
1374                 /* Find the largest remaining value */
1375                 for (j = i + 1; j < MAXBXCR; j++) {
1376                         if (sorted_bank_size[j] > largest_size) {
1377                                 /* Save largest remaining value and its index */
1378                                 largest_size = sorted_bank_size[j];
1379                                 largest_size_index = j;
1380                         }
1381                 }
1382
1383                 if (largest_size_index != 255) {
1384                         /* Swap the current and largest values */
1385                         current_size_index = sorted_bank_num[largest_size_index];
1386                         sorted_bank_size[largest_size_index] = sorted_bank_size[i];
1387                         sorted_bank_size[i] = largest_size;
1388                         sorted_bank_num[largest_size_index] = sorted_bank_num[i];
1389                         sorted_bank_num[i] = current_size_index;
1390                 }
1391         }
1392
1393         /* Set the SDRAM0_BxCR regs thanks to sort tables */
1394         for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1395                 if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
1396                         mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
1397                         temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
1398                                                   SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
1399                         temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
1400                                 bank_parms[sorted_bank_num[bx_cr_num]].cr;
1401                         mtdcr(memcfgd, temp);
1402                         bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
1403                         debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp);
1404                 }
1405         }
1406
1407         return(bank_base_addr);
1408 }
1409
1410 #ifdef CONFIG_DDR_ECC
1411 static void program_ecc(unsigned long num_bytes)
1412 {
1413         unsigned long bank_base_addr;
1414         unsigned long current_address;
1415         unsigned long end_address;
1416         unsigned long address_increment;
1417         unsigned long cfg0;
1418
1419         /*
1420          * get Memory Controller Options 0 data
1421          */
1422         mfsdram(mem_cfg0, cfg0);
1423
1424         /*
1425          * reset the bank_base address
1426          */
1427         bank_base_addr = CFG_SDRAM_BASE;
1428
1429         if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
1430                 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN);
1431
1432                 if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32)
1433                         address_increment = 4;
1434                 else
1435                         address_increment = 8;
1436
1437                 current_address = (unsigned long)(bank_base_addr);
1438                 end_address = (unsigned long)(bank_base_addr) + num_bytes;
1439
1440                 while (current_address < end_address) {
1441                         *((unsigned long*)current_address) = 0x00000000;
1442                         current_address += address_increment;
1443                 }
1444
1445                 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1446                         SDRAM_CFG0_MCHK_CHK);
1447         }
1448 }
1449 #endif /* CONFIG_DDR_ECC */
1450 #endif /* CONFIG_SPD_EEPROM */