cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX(r)
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * Copyright (c) 2008 Nuovation System Designs, LLC
  10  *   Grant Erickson <gerickson@nuovations.com>
  11
  12  * (C) Copyright 2007-2008
  13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14  *
  15  * COPYRIGHT   AMCC   CORPORATION 2004
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  *
  35  */
  36
  37 /* define DEBUG for debugging output (obviously ;-)) */
  38 #if 0
  39 #define DEBUG
  40 #endif
  41
  42 #include <common.h>
  43 #include <command.h>
  44 #include <ppc4xx.h>
  45 #include <i2c.h>
  46 #include <asm/io.h>
  47 #include <asm/processor.h>
  48 #include <asm/mmu.h>
  49 #include <asm/cache.h>
  50
  51 #include "ecc.h"
  52
  53 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
  54
  55 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                         \
  56         do {                                                            \
  57                 u32 data;                                               \
  58                 mfsdram(SDRAM_##mnemonic, data);                        \
  59                 printf("%20s[%02x] = 0x%08X\n",                         \
  60                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  61         } while (0)
  62
  63 #define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic)                      \
  64         do {                                                            \
  65                 u32 data;                                               \
  66                 data = mfdcr(SDRAM_##mnemonic);                         \
  67                 printf("%20s[%02x] = 0x%08X\n",                         \
  68                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  69         } while (0)
  70
  71 #if defined(CONFIG_440)
  72 /*
  73  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
  74  * memory region. Right now the cache should still be disabled in U-Boot
  75  * because of the EMAC driver, that need its buffer descriptor to be located
  76  * in non cached memory.
  77  *
  78  * If at some time this restriction doesn't apply anymore, just define
  79  * CONFIG_4xx_DCACHE in the board config file and this code should setup
  80  * everything correctly.
  81  */
  82 #ifdef CONFIG_4xx_DCACHE
  83 /* enable caching on SDRAM */
  84 #define MY_TLB_WORD2_I_ENABLE           0
  85 #else
  86 /* disable caching on SDRAM */
  87 #define MY_TLB_WORD2_I_ENABLE           TLB_WORD2_I_ENABLE
  88 #endif /* CONFIG_4xx_DCACHE */
  89 #endif /* CONFIG_440 */
  90
  91 #if defined(CONFIG_SPD_EEPROM)
  92
  93 /*-----------------------------------------------------------------------------+
  94  * Defines
  95  *-----------------------------------------------------------------------------*/
  96 #ifndef TRUE
  97 #define TRUE            1
  98 #endif
  99 #ifndef FALSE
 100 #define FALSE           0
 101 #endif
 102
 103 #define SDRAM_DDR1      1
 104 #define SDRAM_DDR2      2
 105 #define SDRAM_NONE      0
 106
 107 #define MAXDIMMS        2
 108 #define MAXRANKS        4
 109 #define MAXBXCF         4
 110 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
 111
 112 #define ONE_BILLION     1000000000
 113
 114 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
 115
 116 #define CMD_NOP         (7 << 19)
 117 #define CMD_PRECHARGE   (2 << 19)
 118 #define CMD_REFRESH     (1 << 19)
 119 #define CMD_EMR         (0 << 19)
 120 #define CMD_READ        (5 << 19)
 121 #define CMD_WRITE       (4 << 19)
 122
 123 #define SELECT_MR       (0 << 16)
 124 #define SELECT_EMR      (1 << 16)
 125 #define SELECT_EMR2     (2 << 16)
 126 #define SELECT_EMR3     (3 << 16)
 127
 128 /* MR */
 129 #define DLL_RESET       0x00000100
 130
 131 #define WRITE_RECOV_2   (1 << 9)
 132 #define WRITE_RECOV_3   (2 << 9)
 133 #define WRITE_RECOV_4   (3 << 9)
 134 #define WRITE_RECOV_5   (4 << 9)
 135 #define WRITE_RECOV_6   (5 << 9)
 136
 137 #define BURST_LEN_4     0x00000002
 138
 139 /* EMR */
 140 #define ODT_0_OHM       0x00000000
 141 #define ODT_50_OHM      0x00000044
 142 #define ODT_75_OHM      0x00000004
 143 #define ODT_150_OHM     0x00000040
 144
 145 #define ODS_FULL        0x00000000
 146 #define ODS_REDUCED     0x00000002
 147 #define OCD_CALIB_DEF   0x00000380
 148
 149 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 150 #define ODT_EB0R        (0x80000000 >> 8)
 151 #define ODT_EB0W        (0x80000000 >> 7)
 152 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 153 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 154 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 155
 156 /* Defines for the Read Cycle Delay test */
 157 #define NUMMEMTESTS     8
 158 #define NUMMEMWORDS     8
 159 #define NUMLOOPS        64              /* memory test loops */
 160
 161 /*
 162  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
 163  * To support such configurations, we "only" map the first 2GB via the TLB's. We
 164  * need some free virtual address space for the remaining peripherals like, SoC
 165  * devices, FLASH etc.
 166  *
 167  * Note that ECC is currently not supported on configurations with more than 2GB
 168  * SDRAM. This is because we only map the first 2GB on such systems, and therefore
 169  * the ECC parity byte of the remaining area can't be written.
 170  */
 171
 172 /*
 173  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 174  */
 175 void __spd_ddr_init_hang (void)
 176 {
 177         hang ();
 178 }
 179 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 180
 181 /*
 182  * To provide an interface for board specific config values in this common
 183  * DDR setup code, we implement he "weak" default functions here. They return
 184  * the default value back to the caller.
 185  *
 186  * Please see include/configs/yucca.h for an example fora board specific
 187  * implementation.
 188  */
 189 u32 __ddr_wrdtr(u32 default_val)
 190 {
 191         return default_val;
 192 }
 193 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 194
 195 u32 __ddr_clktr(u32 default_val)
 196 {
 197         return default_val;
 198 }
 199 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 200
 201
 202 /* Private Structure Definitions */
 203
 204 /* enum only to ease code for cas latency setting */
 205 typedef enum ddr_cas_id {
 206         DDR_CAS_2      = 20,
 207         DDR_CAS_2_5    = 25,
 208         DDR_CAS_3      = 30,
 209         DDR_CAS_4      = 40,
 210         DDR_CAS_5      = 50
 211 } ddr_cas_id_t;
 212
 213 /*-----------------------------------------------------------------------------+
 214  * Prototypes
 215  *-----------------------------------------------------------------------------*/
 216 static phys_size_t sdram_memsize(void);
 217 static void get_spd_info(unsigned long *dimm_populated,
 218                          unsigned char *iic0_dimm_addr,
 219                          unsigned long num_dimm_banks);
 220 static void check_mem_type(unsigned long *dimm_populated,
 221                            unsigned char *iic0_dimm_addr,
 222                            unsigned long num_dimm_banks);
 223 static void check_frequency(unsigned long *dimm_populated,
 224                             unsigned char *iic0_dimm_addr,
 225                             unsigned long num_dimm_banks);
 226 static void check_rank_number(unsigned long *dimm_populated,
 227                               unsigned char *iic0_dimm_addr,
 228                               unsigned long num_dimm_banks);
 229 static void check_voltage_type(unsigned long *dimm_populated,
 230                                unsigned char *iic0_dimm_addr,
 231                                unsigned long num_dimm_banks);
 232 static void program_memory_queue(unsigned long *dimm_populated,
 233                                  unsigned char *iic0_dimm_addr,
 234                                  unsigned long num_dimm_banks);
 235 static void program_codt(unsigned long *dimm_populated,
 236                          unsigned char *iic0_dimm_addr,
 237                          unsigned long num_dimm_banks);
 238 static void program_mode(unsigned long *dimm_populated,
 239                          unsigned char *iic0_dimm_addr,
 240                          unsigned long num_dimm_banks,
 241                          ddr_cas_id_t *selected_cas,
 242                          int *write_recovery);
 243 static void program_tr(unsigned long *dimm_populated,
 244                        unsigned char *iic0_dimm_addr,
 245                        unsigned long num_dimm_banks);
 246 static void program_rtr(unsigned long *dimm_populated,
 247                         unsigned char *iic0_dimm_addr,
 248                         unsigned long num_dimm_banks);
 249 static void program_bxcf(unsigned long *dimm_populated,
 250                          unsigned char *iic0_dimm_addr,
 251                          unsigned long num_dimm_banks);
 252 static void program_copt1(unsigned long *dimm_populated,
 253                           unsigned char *iic0_dimm_addr,
 254                           unsigned long num_dimm_banks);
 255 static void program_initplr(unsigned long *dimm_populated,
 256                             unsigned char *iic0_dimm_addr,
 257                             unsigned long num_dimm_banks,
 258                             ddr_cas_id_t selected_cas,
 259                             int write_recovery);
 260 static unsigned long is_ecc_enabled(void);
 261 #ifdef CONFIG_DDR_ECC
 262 static void program_ecc(unsigned long *dimm_populated,
 263                         unsigned char *iic0_dimm_addr,
 264                         unsigned long num_dimm_banks,
 265                         unsigned long tlb_word2_i_value);
 266 static void program_ecc_addr(unsigned long start_address,
 267                              unsigned long num_bytes,
 268                              unsigned long tlb_word2_i_value);
 269 #endif
 270 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 271 static void program_DQS_calibration(unsigned long *dimm_populated,
 272                                 unsigned char *iic0_dimm_addr,
 273                                 unsigned long num_dimm_banks);
 274 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 275 static void     test(void);
 276 #else
 277 static void     DQS_calibration_process(void);
 278 #endif
 279 #endif
 280 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 281 void dcbz_area(u32 start_address, u32 num_bytes);
 282
 283 static unsigned char spd_read(uchar chip, uint addr)
 284 {
 285         unsigned char data[2];
 286
 287         if (i2c_probe(chip) == 0)
 288                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 289                         return data[0];
 290
 291         return 0;
 292 }
 293
 294 /*-----------------------------------------------------------------------------+
 295  * sdram_memsize
 296  *-----------------------------------------------------------------------------*/
 297 static phys_size_t sdram_memsize(void)
 298 {
 299         phys_size_t mem_size;
 300         unsigned long mcopt2;
 301         unsigned long mcstat;
 302         unsigned long mb0cf;
 303         unsigned long sdsz;
 304         unsigned long i;
 305
 306         mem_size = 0;
 307
 308         mfsdram(SDRAM_MCOPT2, mcopt2);
 309         mfsdram(SDRAM_MCSTAT, mcstat);
 310
 311         /* DDR controller must be enabled and not in self-refresh. */
 312         /* Otherwise memsize is zero. */
 313         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 314             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 315             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 316                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 317                 for (i = 0; i < MAXBXCF; i++) {
 318                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 319                         /* Banks enabled */
 320                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 321                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 322
 323                                 switch(sdsz) {
 324                                 case SDRAM_RXBAS_SDSZ_8:
 325                                         mem_size+=8;
 326                                         break;
 327                                 case SDRAM_RXBAS_SDSZ_16:
 328                                         mem_size+=16;
 329                                         break;
 330                                 case SDRAM_RXBAS_SDSZ_32:
 331                                         mem_size+=32;
 332                                         break;
 333                                 case SDRAM_RXBAS_SDSZ_64:
 334                                         mem_size+=64;
 335                                         break;
 336                                 case SDRAM_RXBAS_SDSZ_128:
 337                                         mem_size+=128;
 338                                         break;
 339                                 case SDRAM_RXBAS_SDSZ_256:
 340                                         mem_size+=256;
 341                                         break;
 342                                 case SDRAM_RXBAS_SDSZ_512:
 343                                         mem_size+=512;
 344                                         break;
 345                                 case SDRAM_RXBAS_SDSZ_1024:
 346                                         mem_size+=1024;
 347                                         break;
 348                                 case SDRAM_RXBAS_SDSZ_2048:
 349                                         mem_size+=2048;
 350                                         break;
 351                                 case SDRAM_RXBAS_SDSZ_4096:
 352                                         mem_size+=4096;
 353                                         break;
 354                                 default:
 355                                         printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
 356                                                , sdsz);
 357                                         mem_size=0;
 358                                         break;
 359                                 }
 360                         }
 361                 }
 362         }
 363
 364         return mem_size << 20;
 365 }
 366
 367 /*-----------------------------------------------------------------------------+
 368  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 369  * Note: This routine runs from flash with a stack set up in the chip's
 370  * sram space.  It is important that the routine does not require .sbss, .bss or
 371  * .data sections.  It also cannot call routines that require these sections.
 372  *-----------------------------------------------------------------------------*/
 373 /*-----------------------------------------------------------------------------
 374  * Function:     initdram
 375  * Description:  Configures SDRAM memory banks for DDR operation.
 376  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 377  *               via the IIC bus and then configures the DDR SDRAM memory
 378  *               banks appropriately. If Auto Memory Configuration is
 379  *               not used, it is assumed that no DIMM is plugged
 380  *-----------------------------------------------------------------------------*/
 381 phys_size_t initdram(int board_type)
 382 {
 383         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 384         unsigned char spd0[MAX_SPD_BYTES];
 385         unsigned char spd1[MAX_SPD_BYTES];
 386         unsigned char *dimm_spd[MAXDIMMS];
 387         unsigned long dimm_populated[MAXDIMMS];
 388         unsigned long num_dimm_banks;           /* on board dimm banks */
 389         unsigned long val;
 390         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 391         int write_recovery;
 392         phys_size_t dram_size = 0;
 393
 394         num_dimm_banks = sizeof(iic0_dimm_addr);
 395
 396         /*------------------------------------------------------------------
 397          * Set up an array of SPD matrixes.
 398          *-----------------------------------------------------------------*/
 399         dimm_spd[0] = spd0;
 400         dimm_spd[1] = spd1;
 401
 402         /*------------------------------------------------------------------
 403          * Reset the DDR-SDRAM controller.
 404          *-----------------------------------------------------------------*/
 405         mtsdr(SDR0_SRST, (0x80000000 >> 10));
 406         mtsdr(SDR0_SRST, 0x00000000);
 407
 408         /*
 409          * Make sure I2C controller is initialized
 410          * before continuing.
 411          */
 412
 413         /* switch to correct I2C bus */
 414         I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
 415         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 416
 417         /*------------------------------------------------------------------
 418          * Clear out the serial presence detect buffers.
 419          * Perform IIC reads from the dimm.  Fill in the spds.
 420          * Check to see if the dimm slots are populated
 421          *-----------------------------------------------------------------*/
 422         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 423
 424         /*------------------------------------------------------------------
 425          * Check the memory type for the dimms plugged.
 426          *-----------------------------------------------------------------*/
 427         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 428
 429         /*------------------------------------------------------------------
 430          * Check the frequency supported for the dimms plugged.
 431          *-----------------------------------------------------------------*/
 432         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 433
 434         /*------------------------------------------------------------------
 435          * Check the total rank number.
 436          *-----------------------------------------------------------------*/
 437         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 438
 439         /*------------------------------------------------------------------
 440          * Check the voltage type for the dimms plugged.
 441          *-----------------------------------------------------------------*/
 442         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 443
 444         /*------------------------------------------------------------------
 445          * Program SDRAM controller options 2 register
 446          * Except Enabling of the memory controller.
 447          *-----------------------------------------------------------------*/
 448         mfsdram(SDRAM_MCOPT2, val);
 449         mtsdram(SDRAM_MCOPT2,
 450                 (val &
 451                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 452                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 453                    SDRAM_MCOPT2_ISIE_MASK))
 454                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 455                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 456                    SDRAM_MCOPT2_ISIE_ENABLE));
 457
 458         /*------------------------------------------------------------------
 459          * Program SDRAM controller options 1 register
 460          * Note: Does not enable the memory controller.
 461          *-----------------------------------------------------------------*/
 462         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 463
 464         /*------------------------------------------------------------------
 465          * Set the SDRAM Controller On Die Termination Register
 466          *-----------------------------------------------------------------*/
 467         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 468
 469         /*------------------------------------------------------------------
 470          * Program SDRAM refresh register.
 471          *-----------------------------------------------------------------*/
 472         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 473
 474         /*------------------------------------------------------------------
 475          * Program SDRAM mode register.
 476          *-----------------------------------------------------------------*/
 477         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 478                      &selected_cas, &write_recovery);
 479
 480         /*------------------------------------------------------------------
 481          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 482          *-----------------------------------------------------------------*/
 483         mfsdram(SDRAM_WRDTR, val);
 484         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 485                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 486
 487         /*------------------------------------------------------------------
 488          * Set the SDRAM Clock Timing Register
 489          *-----------------------------------------------------------------*/
 490         mfsdram(SDRAM_CLKTR, val);
 491         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 492                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 493
 494         /*------------------------------------------------------------------
 495          * Program the BxCF registers.
 496          *-----------------------------------------------------------------*/
 497         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 498
 499         /*------------------------------------------------------------------
 500          * Program SDRAM timing registers.
 501          *-----------------------------------------------------------------*/
 502         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 503
 504         /*------------------------------------------------------------------
 505          * Set the Extended Mode register
 506          *-----------------------------------------------------------------*/
 507         mfsdram(SDRAM_MEMODE, val);
 508         mtsdram(SDRAM_MEMODE,
 509                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 510                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 511                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 512                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 513
 514         /*------------------------------------------------------------------
 515          * Program Initialization preload registers.
 516          *-----------------------------------------------------------------*/
 517         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 518                         selected_cas, write_recovery);
 519
 520         /*------------------------------------------------------------------
 521          * Delay to ensure 200usec have elapsed since reset.
 522          *-----------------------------------------------------------------*/
 523         udelay(400);
 524
 525         /*------------------------------------------------------------------
 526          * Set the memory queue core base addr.
 527          *-----------------------------------------------------------------*/
 528         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 529
 530         /*------------------------------------------------------------------
 531          * Program SDRAM controller options 2 register
 532          * Enable the memory controller.
 533          *-----------------------------------------------------------------*/
 534         mfsdram(SDRAM_MCOPT2, val);
 535         mtsdram(SDRAM_MCOPT2,
 536                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 537                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 538                          SDRAM_MCOPT2_IPTR_EXECUTE);
 539
 540         /*------------------------------------------------------------------
 541          * Wait for IPTR_EXECUTE init sequence to complete.
 542          *-----------------------------------------------------------------*/
 543         do {
 544                 mfsdram(SDRAM_MCSTAT, val);
 545         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 546
 547         /* enable the controller only after init sequence completes */
 548         mfsdram(SDRAM_MCOPT2, val);
 549         mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
 550
 551         /* Make sure delay-line calibration is done before proceeding */
 552         do {
 553                 mfsdram(SDRAM_DLCR, val);
 554         } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
 555
 556         /* get installed memory size */
 557         dram_size = sdram_memsize();
 558
 559         /*
 560          * Limit size to 2GB
 561          */
 562         if (dram_size > CONFIG_MAX_MEM_MAPPED)
 563                 dram_size = CONFIG_MAX_MEM_MAPPED;
 564
 565         /* and program tlb entries for this size (dynamic) */
 566
 567         /*
 568          * Program TLB entries with caches enabled, for best performace
 569          * while auto-calibrating and ECC generation
 570          */
 571         program_tlb(0, 0, dram_size, 0);
 572
 573         /*------------------------------------------------------------------
 574          * DQS calibration.
 575          *-----------------------------------------------------------------*/
 576 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 577         DQS_autocalibration();
 578 #else
 579         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 580 #endif
 581
 582 #ifdef CONFIG_DDR_ECC
 583         /*------------------------------------------------------------------
 584          * If ecc is enabled, initialize the parity bits.
 585          *-----------------------------------------------------------------*/
 586         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 587 #endif
 588
 589         /*
 590          * Now after initialization (auto-calibration and ECC generation)
 591          * remove the TLB entries with caches enabled and program again with
 592          * desired cache functionality
 593          */
 594         remove_tlb(0, dram_size);
 595         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 596
 597         ppc4xx_ibm_ddr2_register_dump();
 598
 599         /*
 600          * Clear potential errors resulting from auto-calibration.
 601          * If not done, then we could get an interrupt later on when
 602          * exceptions are enabled.
 603          */
 604         set_mcsr(get_mcsr());
 605
 606         return sdram_memsize();
 607 }
 608
 609 static void get_spd_info(unsigned long *dimm_populated,
 610                          unsigned char *iic0_dimm_addr,
 611                          unsigned long num_dimm_banks)
 612 {
 613         unsigned long dimm_num;
 614         unsigned long dimm_found;
 615         unsigned char num_of_bytes;
 616         unsigned char total_size;
 617
 618         dimm_found = FALSE;
 619         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 620                 num_of_bytes = 0;
 621                 total_size = 0;
 622
 623                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 624                 debug("\nspd_read(0x%x) returned %d\n",
 625                       iic0_dimm_addr[dimm_num], num_of_bytes);
 626                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 627                 debug("spd_read(0x%x) returned %d\n",
 628                       iic0_dimm_addr[dimm_num], total_size);
 629
 630                 if ((num_of_bytes != 0) && (total_size != 0)) {
 631                         dimm_populated[dimm_num] = TRUE;
 632                         dimm_found = TRUE;
 633                         debug("DIMM slot %lu: populated\n", dimm_num);
 634                 } else {
 635                         dimm_populated[dimm_num] = FALSE;
 636                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 637                 }
 638         }
 639
 640         if (dimm_found == FALSE) {
 641                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 642                 spd_ddr_init_hang ();
 643         }
 644 }
 645
 646 void board_add_ram_info(int use_default)
 647 {
 648         PPC4xx_SYS_INFO board_cfg;
 649         u32 val;
 650
 651         if (is_ecc_enabled())
 652                 puts(" (ECC");
 653         else
 654                 puts(" (ECC not");
 655
 656         get_sys_info(&board_cfg);
 657
 658         mfsdr(SDR0_DDR0, val);
 659         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 660         printf(" enabled, %d MHz", (val * 2) / 1000000);
 661
 662         mfsdram(SDRAM_MMODE, val);
 663         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 664         printf(", CL%d)", val);
 665 }
 666
 667 /*------------------------------------------------------------------
 668  * For the memory DIMMs installed, this routine verifies that they
 669  * really are DDR specific DIMMs.
 670  *-----------------------------------------------------------------*/
 671 static void check_mem_type(unsigned long *dimm_populated,
 672                            unsigned char *iic0_dimm_addr,
 673                            unsigned long num_dimm_banks)
 674 {
 675         unsigned long dimm_num;
 676         unsigned long dimm_type;
 677
 678         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 679                 if (dimm_populated[dimm_num] == TRUE) {
 680                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 681                         switch (dimm_type) {
 682                         case 1:
 683                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 684                                        "slot %d.\n", (unsigned int)dimm_num);
 685                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 686                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 687                                 spd_ddr_init_hang ();
 688                                 break;
 689                         case 2:
 690                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 691                                        (unsigned int)dimm_num);
 692                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 693                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 694                                 spd_ddr_init_hang ();
 695                                 break;
 696                         case 3:
 697                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 698                                        (unsigned int)dimm_num);
 699                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 700                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 701                                 spd_ddr_init_hang ();
 702                                 break;
 703                         case 4:
 704                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 705                                        (unsigned int)dimm_num);
 706                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 707                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 708                                 spd_ddr_init_hang ();
 709                                 break;
 710                         case 5:
 711                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 712                                        (unsigned int)dimm_num);
 713                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 714                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 715                                 spd_ddr_init_hang ();
 716                                 break;
 717                         case 6:
 718                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 719                                        (unsigned int)dimm_num);
 720                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 721                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 722                                 spd_ddr_init_hang ();
 723                                 break;
 724                         case 7:
 725                                 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
 726                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 727                                 break;
 728                         case 8:
 729                                 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
 730                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 731                                 break;
 732                         default:
 733                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 734                                        (unsigned int)dimm_num);
 735                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 736                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 737                                 spd_ddr_init_hang ();
 738                                 break;
 739                         }
 740                 }
 741         }
 742         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 743                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 744                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 745                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 746                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 747                         spd_ddr_init_hang ();
 748                 }
 749         }
 750 }
 751
 752 /*------------------------------------------------------------------
 753  * For the memory DIMMs installed, this routine verifies that
 754  * frequency previously calculated is supported.
 755  *-----------------------------------------------------------------*/
 756 static void check_frequency(unsigned long *dimm_populated,
 757                             unsigned char *iic0_dimm_addr,
 758                             unsigned long num_dimm_banks)
 759 {
 760         unsigned long dimm_num;
 761         unsigned long tcyc_reg;
 762         unsigned long cycle_time;
 763         unsigned long calc_cycle_time;
 764         unsigned long sdram_freq;
 765         unsigned long sdr_ddrpll;
 766         PPC4xx_SYS_INFO board_cfg;
 767
 768         /*------------------------------------------------------------------
 769          * Get the board configuration info.
 770          *-----------------------------------------------------------------*/
 771         get_sys_info(&board_cfg);
 772
 773         mfsdr(SDR0_DDR0, sdr_ddrpll);
 774         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 775
 776         /*
 777          * calc_cycle_time is calculated from DDR frequency set by board/chip
 778          * and is expressed in multiple of 10 picoseconds
 779          * to match the way DIMM cycle time is calculated below.
 780          */
 781         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 782
 783         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 784                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 785                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 786                         /*
 787                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 788                          * the higher order nibble (bits 4-7) designates the cycle time
 789                          * to a granularity of 1ns;
 790                          * the value presented by the lower order nibble (bits 0-3)
 791                          * has a granularity of .1ns and is added to the value designated
 792                          * by the higher nibble. In addition, four lines of the lower order
 793                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 794                          */
 795                          /* Convert from hex to decimal */
 796                         if ((tcyc_reg & 0x0F) == 0x0D)
 797                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 798                         else if ((tcyc_reg & 0x0F) == 0x0C)
 799                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 800                         else if ((tcyc_reg & 0x0F) == 0x0B)
 801                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 802                         else if ((tcyc_reg & 0x0F) == 0x0A)
 803                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 804                         else
 805                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 806                                         ((tcyc_reg & 0x0F)*10);
 807                         debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
 808
 809                         if  (cycle_time > (calc_cycle_time + 10)) {
 810                                 /*
 811                                  * the provided sdram cycle_time is too small
 812                                  * for the available DIMM cycle_time.
 813                                  * The additionnal 100ps is here to accept a small incertainty.
 814                                  */
 815                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 816                                        "slot %d \n while calculated cycle time is %d ps.\n",
 817                                        (unsigned int)(cycle_time*10),
 818                                        (unsigned int)dimm_num,
 819                                        (unsigned int)(calc_cycle_time*10));
 820                                 printf("Replace the DIMM, or change DDR frequency via "
 821                                        "strapping bits.\n\n");
 822                                 spd_ddr_init_hang ();
 823                         }
 824                 }
 825         }
 826 }
 827
 828 /*------------------------------------------------------------------
 829  * For the memory DIMMs installed, this routine verifies two
 830  * ranks/banks maximum are availables.
 831  *-----------------------------------------------------------------*/
 832 static void check_rank_number(unsigned long *dimm_populated,
 833                               unsigned char *iic0_dimm_addr,
 834                               unsigned long num_dimm_banks)
 835 {
 836         unsigned long dimm_num;
 837         unsigned long dimm_rank;
 838         unsigned long total_rank = 0;
 839
 840         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 841                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 842                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 843                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 844                                 dimm_rank = (dimm_rank & 0x0F) +1;
 845                         else
 846                                 dimm_rank = dimm_rank & 0x0F;
 847
 848
 849                         if (dimm_rank > MAXRANKS) {
 850                                 printf("ERROR: DRAM DIMM detected with %lu ranks in "
 851                                        "slot %lu is not supported.\n", dimm_rank, dimm_num);
 852                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 853                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 854                                 spd_ddr_init_hang ();
 855                         } else
 856                                 total_rank += dimm_rank;
 857                 }
 858                 if (total_rank > MAXRANKS) {
 859                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 860                                "for all slots.\n", (unsigned int)total_rank);
 861                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 862                         printf("Remove one of the DIMM modules.\n\n");
 863                         spd_ddr_init_hang ();
 864                 }
 865         }
 866 }
 867
 868 /*------------------------------------------------------------------
 869  * only support 2.5V modules.
 870  * This routine verifies this.
 871  *-----------------------------------------------------------------*/
 872 static void check_voltage_type(unsigned long *dimm_populated,
 873                                unsigned char *iic0_dimm_addr,
 874                                unsigned long num_dimm_banks)
 875 {
 876         unsigned long dimm_num;
 877         unsigned long voltage_type;
 878
 879         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 880                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 881                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 882                         switch (voltage_type) {
 883                         case 0x00:
 884                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 885                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 886                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 887                                        (unsigned int)dimm_num);
 888                                 spd_ddr_init_hang ();
 889                                 break;
 890                         case 0x01:
 891                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 892                                 printf("This DIMM is LVTTL.\n");
 893                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 894                                        (unsigned int)dimm_num);
 895                                 spd_ddr_init_hang ();
 896                                 break;
 897                         case 0x02:
 898                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 899                                 printf("This DIMM is 1.5 Volt.\n");
 900                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 901                                        (unsigned int)dimm_num);
 902                                 spd_ddr_init_hang ();
 903                                 break;
 904                         case 0x03:
 905                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 906                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 907                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 908                                        (unsigned int)dimm_num);
 909                                 spd_ddr_init_hang ();
 910                                 break;
 911                         case 0x04:
 912                                 /* 2.5 Voltage only for DDR1 */
 913                                 break;
 914                         case 0x05:
 915                                 /* 1.8 Voltage only for DDR2 */
 916                                 break;
 917                         default:
 918                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 919                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 920                                        (unsigned int)dimm_num);
 921                                 spd_ddr_init_hang ();
 922                                 break;
 923                         }
 924                 }
 925         }
 926 }
 927
 928 /*-----------------------------------------------------------------------------+
 929  * program_copt1.
 930  *-----------------------------------------------------------------------------*/
 931 static void program_copt1(unsigned long *dimm_populated,
 932                           unsigned char *iic0_dimm_addr,
 933                           unsigned long num_dimm_banks)
 934 {
 935         unsigned long dimm_num;
 936         unsigned long mcopt1;
 937         unsigned long ecc_enabled;
 938         unsigned long ecc = 0;
 939         unsigned long data_width = 0;
 940         unsigned long dimm_32bit;
 941         unsigned long dimm_64bit;
 942         unsigned long registered = 0;
 943         unsigned long attribute = 0;
 944         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 945         unsigned long bankcount;
 946         unsigned long ddrtype;
 947         unsigned long val;
 948
 949 #ifdef CONFIG_DDR_ECC
 950         ecc_enabled = TRUE;
 951 #else
 952         ecc_enabled = FALSE;
 953 #endif
 954         dimm_32bit = FALSE;
 955         dimm_64bit = FALSE;
 956         buf0 = FALSE;
 957         buf1 = FALSE;
 958
 959         /*------------------------------------------------------------------
 960          * Set memory controller options reg 1, SDRAM_MCOPT1.
 961          *-----------------------------------------------------------------*/
 962         mfsdram(SDRAM_MCOPT1, val);
 963         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 964                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 965                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 966                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 967                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
 968                          SDRAM_MCOPT1_DREF_MASK);
 969
 970         mcopt1 |= SDRAM_MCOPT1_QDEP;
 971         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
 972         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
 973         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
 974         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
 975         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
 976
 977         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 978                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 979                         /* test ecc support */
 980                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 981                         if (ecc != 0x02) /* ecc not supported */
 982                                 ecc_enabled = FALSE;
 983
 984                         /* test bank count */
 985                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
 986                         if (bankcount == 0x04) /* bank count = 4 */
 987                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
 988                         else /* bank count = 8 */
 989                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
 990
 991                         /* test DDR type */
 992                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
 993                         /* test for buffered/unbuffered, registered, differential clocks */
 994                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
 995                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
 996
 997                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 998                         if (dimm_num == 0) {
 999                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1000                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1001                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1002                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1003                                 if (registered == 1) { /* DDR2 always buffered */
1004                                         /* TODO: what about above  comments ? */
1005                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1006                                         buf0 = TRUE;
1007                                 } else {
1008                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1009                                         if ((attribute & 0x02) == 0x00) {
1010                                                 /* buffered not supported */
1011                                                 buf0 = FALSE;
1012                                         } else {
1013                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1014                                                 buf0 = TRUE;
1015                                         }
1016                                 }
1017                         }
1018                         else if (dimm_num == 1) {
1019                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1020                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1021                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1022                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1023                                 if (registered == 1) {
1024                                         /* DDR2 always buffered */
1025                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1026                                         buf1 = TRUE;
1027                                 } else {
1028                                         if ((attribute & 0x02) == 0x00) {
1029                                                 /* buffered not supported */
1030                                                 buf1 = FALSE;
1031                                         } else {
1032                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1033                                                 buf1 = TRUE;
1034                                         }
1035                                 }
1036                         }
1037
1038                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1039                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1040                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1041
1042                         switch (data_width) {
1043                         case 72:
1044                         case 64:
1045                                 dimm_64bit = TRUE;
1046                                 break;
1047                         case 40:
1048                         case 32:
1049                                 dimm_32bit = TRUE;
1050                                 break;
1051                         default:
1052                                 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1053                                        data_width);
1054                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1055                                 break;
1056                         }
1057                 }
1058         }
1059
1060         /* verify matching properties */
1061         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1062                 if (buf0 != buf1) {
1063                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1064                         spd_ddr_init_hang ();
1065                 }
1066         }
1067
1068         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1069                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1070                 spd_ddr_init_hang ();
1071         }
1072         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1073                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1074         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1075                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1076         } else {
1077                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1078                 spd_ddr_init_hang ();
1079         }
1080
1081         if (ecc_enabled == TRUE)
1082                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1083         else
1084                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1085
1086         mtsdram(SDRAM_MCOPT1, mcopt1);
1087 }
1088
1089 /*-----------------------------------------------------------------------------+
1090  * program_codt.
1091  *-----------------------------------------------------------------------------*/
1092 static void program_codt(unsigned long *dimm_populated,
1093                          unsigned char *iic0_dimm_addr,
1094                          unsigned long num_dimm_banks)
1095 {
1096         unsigned long codt;
1097         unsigned long modt0 = 0;
1098         unsigned long modt1 = 0;
1099         unsigned long modt2 = 0;
1100         unsigned long modt3 = 0;
1101         unsigned char dimm_num;
1102         unsigned char dimm_rank;
1103         unsigned char total_rank = 0;
1104         unsigned char total_dimm = 0;
1105         unsigned char dimm_type = 0;
1106         unsigned char firstSlot = 0;
1107
1108         /*------------------------------------------------------------------
1109          * Set the SDRAM Controller On Die Termination Register
1110          *-----------------------------------------------------------------*/
1111         mfsdram(SDRAM_CODT, codt);
1112         codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1113         codt |= SDRAM_CODT_IO_NMODE;
1114
1115         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1116                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1117                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1118                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1119                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1120                                 dimm_type = SDRAM_DDR2;
1121                         } else {
1122                                 dimm_rank = dimm_rank & 0x0F;
1123                                 dimm_type = SDRAM_DDR1;
1124                         }
1125
1126                         total_rank += dimm_rank;
1127                         total_dimm++;
1128                         if ((dimm_num == 0) && (total_dimm == 1))
1129                                 firstSlot = TRUE;
1130                         else
1131                                 firstSlot = FALSE;
1132                 }
1133         }
1134         if (dimm_type == SDRAM_DDR2) {
1135                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1136                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1137                         if (total_rank == 1) {  /* PUUU */
1138                                 codt |= CALC_ODT_R(0);
1139                                 modt0 = CALC_ODT_W(0);
1140                                 modt1 = 0x00000000;
1141                                 modt2 = 0x00000000;
1142                                 modt3 = 0x00000000;
1143                         }
1144                         if (total_rank == 2) {  /* PPUU */
1145                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1146                                 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1147                                 modt1 = 0x00000000;
1148                                 modt2 = 0x00000000;
1149                                 modt3 = 0x00000000;
1150                         }
1151                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1152                         if (total_rank == 1) {  /* UUPU */
1153                                 codt |= CALC_ODT_R(2);
1154                                 modt0 = 0x00000000;
1155                                 modt1 = 0x00000000;
1156                                 modt2 = CALC_ODT_W(2);
1157                                 modt3 = 0x00000000;
1158                         }
1159                         if (total_rank == 2) {  /* UUPP */
1160                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1161                                 modt0 = 0x00000000;
1162                                 modt1 = 0x00000000;
1163                                 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1164                                 modt3 = 0x00000000;
1165                         }
1166                 }
1167                 if (total_dimm == 2) {
1168                         if (total_rank == 2) {  /* PUPU */
1169                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1170                                 modt0 = CALC_ODT_RW(2);
1171                                 modt1 = 0x00000000;
1172                                 modt2 = CALC_ODT_RW(0);
1173                                 modt3 = 0x00000000;
1174                         }
1175                         if (total_rank == 4) {  /* PPPP */
1176                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1177                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1178                                 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1179                                 modt1 = 0x00000000;
1180                                 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1181                                 modt3 = 0x00000000;
1182                         }
1183                 }
1184         } else {
1185                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1186                 modt0 = 0x00000000;
1187                 modt1 = 0x00000000;
1188                 modt2 = 0x00000000;
1189                 modt3 = 0x00000000;
1190
1191                 if (total_dimm == 1) {
1192                         if (total_rank == 1)
1193                                 codt |= 0x00800000;
1194                         if (total_rank == 2)
1195                                 codt |= 0x02800000;
1196                 }
1197                 if (total_dimm == 2) {
1198                         if (total_rank == 2)
1199                                 codt |= 0x08800000;
1200                         if (total_rank == 4)
1201                                 codt |= 0x2a800000;
1202                 }
1203         }
1204
1205         debug("nb of dimm %d\n", total_dimm);
1206         debug("nb of rank %d\n", total_rank);
1207         if (total_dimm == 1)
1208                 debug("dimm in slot %d\n", firstSlot);
1209
1210         mtsdram(SDRAM_CODT, codt);
1211         mtsdram(SDRAM_MODT0, modt0);
1212         mtsdram(SDRAM_MODT1, modt1);
1213         mtsdram(SDRAM_MODT2, modt2);
1214         mtsdram(SDRAM_MODT3, modt3);
1215 }
1216
1217 /*-----------------------------------------------------------------------------+
1218  * program_initplr.
1219  *-----------------------------------------------------------------------------*/
1220 static void program_initplr(unsigned long *dimm_populated,
1221                             unsigned char *iic0_dimm_addr,
1222                             unsigned long num_dimm_banks,
1223                             ddr_cas_id_t selected_cas,
1224                             int write_recovery)
1225 {
1226         u32 cas = 0;
1227         u32 odt = 0;
1228         u32 ods = 0;
1229         u32 mr;
1230         u32 wr;
1231         u32 emr;
1232         u32 emr2;
1233         u32 emr3;
1234         int dimm_num;
1235         int total_dimm = 0;
1236
1237         /******************************************************
1238          ** Assumption: if more than one DIMM, all DIMMs are the same
1239          **             as already checked in check_memory_type
1240          ******************************************************/
1241
1242         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1243                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1244                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1245                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1246                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1247                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1248                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1249                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1250                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1251         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1252                 switch (selected_cas) {
1253                 case DDR_CAS_3:
1254                         cas = 3 << 4;
1255                         break;
1256                 case DDR_CAS_4:
1257                         cas = 4 << 4;
1258                         break;
1259                 case DDR_CAS_5:
1260                         cas = 5 << 4;
1261                         break;
1262                 default:
1263                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1264                         spd_ddr_init_hang ();
1265                         break;
1266                 }
1267
1268 #if 0
1269                 /*
1270                  * ToDo - Still a problem with the write recovery:
1271                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1272                  * in the INITPLR reg to the value calculated in program_mode()
1273                  * results in not correctly working DDR2 memory (crash after
1274                  * relocation).
1275                  *
1276                  * So for now, set the write recovery to 3. This seems to work
1277                  * on the Corair module too.
1278                  *
1279                  * 2007-03-01, sr
1280                  */
1281                 switch (write_recovery) {
1282                 case 3:
1283                         wr = WRITE_RECOV_3;
1284                         break;
1285                 case 4:
1286                         wr = WRITE_RECOV_4;
1287                         break;
1288                 case 5:
1289                         wr = WRITE_RECOV_5;
1290                         break;
1291                 case 6:
1292                         wr = WRITE_RECOV_6;
1293                         break;
1294                 default:
1295                         printf("ERROR: write recovery not support (%d)", write_recovery);
1296                         spd_ddr_init_hang ();
1297                         break;
1298                 }
1299 #else
1300                 wr = WRITE_RECOV_3; /* test-only, see description above */
1301 #endif
1302
1303                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1304                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1305                                 total_dimm++;
1306                 if (total_dimm == 1) {
1307                         odt = ODT_150_OHM;
1308                         ods = ODS_FULL;
1309                 } else if (total_dimm == 2) {
1310                         odt = ODT_75_OHM;
1311                         ods = ODS_REDUCED;
1312                 } else {
1313                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1314                         spd_ddr_init_hang ();
1315                 }
1316
1317                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1318                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1319                 emr2 = CMD_EMR | SELECT_EMR2;
1320                 emr3 = CMD_EMR | SELECT_EMR3;
1321                 /* NOP - Wait 106 MemClk cycles */
1322                 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1323                                         SDRAM_INITPLR_IMWT_ENCODE(106));
1324                 udelay(1000);
1325                 /* precharge 4 MemClk cycles */
1326                 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1327                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1328                 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1329                 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1330                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1331                 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1332                 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1333                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1334                 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1335                 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1336                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1337                 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1338                 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1339                                         SDRAM_INITPLR_IMWT_ENCODE(200));
1340                 udelay(1000);
1341                 /* precharge 4 MemClk cycles */
1342                 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1343                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1344                 /* Refresh 25 MemClk cycles */
1345                 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1346                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1347                 /* Refresh 25 MemClk cycles */
1348                 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1349                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1350                 /* Refresh 25 MemClk cycles */
1351                 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1352                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1353                 /* Refresh 25 MemClk cycles */
1354                 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1355                                          SDRAM_INITPLR_IMWT_ENCODE(25));
1356                 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1357                 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1358                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1359                 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1360                 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1361                                          SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1362                 /* EMR OCD Exit */
1363                 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1364                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1365         } else {
1366                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1367                 spd_ddr_init_hang ();
1368         }
1369 }
1370
1371 /*------------------------------------------------------------------
1372  * This routine programs the SDRAM_MMODE register.
1373  * the selected_cas is an output parameter, that will be passed
1374  * by caller to call the above program_initplr( )
1375  *-----------------------------------------------------------------*/
1376 static void program_mode(unsigned long *dimm_populated,
1377                          unsigned char *iic0_dimm_addr,
1378                          unsigned long num_dimm_banks,
1379                          ddr_cas_id_t *selected_cas,
1380                          int *write_recovery)
1381 {
1382         unsigned long dimm_num;
1383         unsigned long sdram_ddr1;
1384         unsigned long t_wr_ns;
1385         unsigned long t_wr_clk;
1386         unsigned long cas_bit;
1387         unsigned long cas_index;
1388         unsigned long sdram_freq;
1389         unsigned long ddr_check;
1390         unsigned long mmode;
1391         unsigned long tcyc_reg;
1392         unsigned long cycle_2_0_clk;
1393         unsigned long cycle_2_5_clk;
1394         unsigned long cycle_3_0_clk;
1395         unsigned long cycle_4_0_clk;
1396         unsigned long cycle_5_0_clk;
1397         unsigned long max_2_0_tcyc_ns_x_100;
1398         unsigned long max_2_5_tcyc_ns_x_100;
1399         unsigned long max_3_0_tcyc_ns_x_100;
1400         unsigned long max_4_0_tcyc_ns_x_100;
1401         unsigned long max_5_0_tcyc_ns_x_100;
1402         unsigned long cycle_time_ns_x_100[3];
1403         PPC4xx_SYS_INFO board_cfg;
1404         unsigned char cas_2_0_available;
1405         unsigned char cas_2_5_available;
1406         unsigned char cas_3_0_available;
1407         unsigned char cas_4_0_available;
1408         unsigned char cas_5_0_available;
1409         unsigned long sdr_ddrpll;
1410
1411         /*------------------------------------------------------------------
1412          * Get the board configuration info.
1413          *-----------------------------------------------------------------*/
1414         get_sys_info(&board_cfg);
1415
1416         mfsdr(SDR0_DDR0, sdr_ddrpll);
1417         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1418         debug("sdram_freq=%lu\n", sdram_freq);
1419
1420         /*------------------------------------------------------------------
1421          * Handle the timing.  We need to find the worst case timing of all
1422          * the dimm modules installed.
1423          *-----------------------------------------------------------------*/
1424         t_wr_ns = 0;
1425         cas_2_0_available = TRUE;
1426         cas_2_5_available = TRUE;
1427         cas_3_0_available = TRUE;
1428         cas_4_0_available = TRUE;
1429         cas_5_0_available = TRUE;
1430         max_2_0_tcyc_ns_x_100 = 10;
1431         max_2_5_tcyc_ns_x_100 = 10;
1432         max_3_0_tcyc_ns_x_100 = 10;
1433         max_4_0_tcyc_ns_x_100 = 10;
1434         max_5_0_tcyc_ns_x_100 = 10;
1435         sdram_ddr1 = TRUE;
1436
1437         /* loop through all the DIMM slots on the board */
1438         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1439                 /* If a dimm is installed in a particular slot ... */
1440                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1441                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1442                                 sdram_ddr1 = TRUE;
1443                         else
1444                                 sdram_ddr1 = FALSE;
1445
1446                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1447                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1448                         debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
1449
1450                         /* For a particular DIMM, grab the three CAS values it supports */
1451                         for (cas_index = 0; cas_index < 3; cas_index++) {
1452                                 switch (cas_index) {
1453                                 case 0:
1454                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1455                                         break;
1456                                 case 1:
1457                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1458                                         break;
1459                                 default:
1460                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1461                                         break;
1462                                 }
1463
1464                                 if ((tcyc_reg & 0x0F) >= 10) {
1465                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1466                                                 /* Convert from hex to decimal */
1467                                                 cycle_time_ns_x_100[cas_index] =
1468                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1469                                         } else {
1470                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1471                                                        "in slot %d\n", (unsigned int)dimm_num);
1472                                                 spd_ddr_init_hang ();
1473                                         }
1474                                 } else {
1475                                         /* Convert from hex to decimal */
1476                                         cycle_time_ns_x_100[cas_index] =
1477                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1478                                                 ((tcyc_reg & 0x0F)*10);
1479                                 }
1480                                 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
1481                                       cycle_time_ns_x_100[cas_index]);
1482                         }
1483
1484                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1485                         /* supported for a particular DIMM. */
1486                         cas_index = 0;
1487
1488                         if (sdram_ddr1) {
1489                                 /*
1490                                  * DDR devices use the following bitmask for CAS latency:
1491                                  *  Bit   7    6    5    4    3    2    1    0
1492                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1493                                  */
1494                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1495                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1496                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1497                                                                     cycle_time_ns_x_100[cas_index]);
1498                                         cas_index++;
1499                                 } else {
1500                                         if (cas_index != 0)
1501                                                 cas_index++;
1502                                         cas_4_0_available = FALSE;
1503                                 }
1504
1505                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1506                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1507                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1508                                                                     cycle_time_ns_x_100[cas_index]);
1509                                         cas_index++;
1510                                 } else {
1511                                         if (cas_index != 0)
1512                                                 cas_index++;
1513                                         cas_3_0_available = FALSE;
1514                                 }
1515
1516                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1517                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1518                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1519                                                                     cycle_time_ns_x_100[cas_index]);
1520                                         cas_index++;
1521                                 } else {
1522                                         if (cas_index != 0)
1523                                                 cas_index++;
1524                                         cas_2_5_available = FALSE;
1525                                 }
1526
1527                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1528                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1529                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1530                                                                     cycle_time_ns_x_100[cas_index]);
1531                                         cas_index++;
1532                                 } else {
1533                                         if (cas_index != 0)
1534                                                 cas_index++;
1535                                         cas_2_0_available = FALSE;
1536                                 }
1537                         } else {
1538                                 /*
1539                                  * DDR2 devices use the following bitmask for CAS latency:
1540                                  *  Bit   7    6    5    4    3    2    1    0
1541                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1542                                  */
1543                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1544                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1545                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1546                                                                     cycle_time_ns_x_100[cas_index]);
1547                                         cas_index++;
1548                                 } else {
1549                                         if (cas_index != 0)
1550                                                 cas_index++;
1551                                         cas_5_0_available = FALSE;
1552                                 }
1553
1554                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1555                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1556                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1557                                                                     cycle_time_ns_x_100[cas_index]);
1558                                         cas_index++;
1559                                 } else {
1560                                         if (cas_index != 0)
1561                                                 cas_index++;
1562                                         cas_4_0_available = FALSE;
1563                                 }
1564
1565                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1566                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1567                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1568                                                                     cycle_time_ns_x_100[cas_index]);
1569                                         cas_index++;
1570                                 } else {
1571                                         if (cas_index != 0)
1572                                                 cas_index++;
1573                                         cas_3_0_available = FALSE;
1574                                 }
1575                         }
1576                 }
1577         }
1578
1579         /*------------------------------------------------------------------
1580          * Set the SDRAM mode, SDRAM_MMODE
1581          *-----------------------------------------------------------------*/
1582         mfsdram(SDRAM_MMODE, mmode);
1583         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1584
1585         /* add 10 here because of rounding problems */
1586         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1587         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1588         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1589         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1590         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1591         debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1592         debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1593         debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
1594
1595         if (sdram_ddr1 == TRUE) { /* DDR1 */
1596                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1597                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1598                         *selected_cas = DDR_CAS_2;
1599                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1600                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1601                         *selected_cas = DDR_CAS_2_5;
1602                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1603                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1604                         *selected_cas = DDR_CAS_3;
1605                 } else {
1606                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1607                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1608                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1609                         spd_ddr_init_hang ();
1610                 }
1611         } else { /* DDR2 */
1612                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1613                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1614                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1615                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1616                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1617                         *selected_cas = DDR_CAS_3;
1618                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1619                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1620                         *selected_cas = DDR_CAS_4;
1621                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1622                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1623                         *selected_cas = DDR_CAS_5;
1624                 } else {
1625                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1626                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1627                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1628                         printf("cas3=%d cas4=%d cas5=%d\n",
1629                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1630                         printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1631                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1632                         spd_ddr_init_hang ();
1633                 }
1634         }
1635
1636         if (sdram_ddr1 == TRUE)
1637                 mmode |= SDRAM_MMODE_WR_DDR1;
1638         else {
1639
1640                 /* loop through all the DIMM slots on the board */
1641                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1642                         /* If a dimm is installed in a particular slot ... */
1643                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1644                                 t_wr_ns = max(t_wr_ns,
1645                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1646                 }
1647
1648                 /*
1649                  * convert from nanoseconds to ddr clocks
1650                  * round up if necessary
1651                  */
1652                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1653                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1654                 if (sdram_freq != ddr_check)
1655                         t_wr_clk++;
1656
1657                 switch (t_wr_clk) {
1658                 case 0:
1659                 case 1:
1660                 case 2:
1661                 case 3:
1662                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1663                         break;
1664                 case 4:
1665                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1666                         break;
1667                 case 5:
1668                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1669                         break;
1670                 default:
1671                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1672                         break;
1673                 }
1674                 *write_recovery = t_wr_clk;
1675         }
1676
1677         debug("CAS latency = %d\n", *selected_cas);
1678         debug("Write recovery = %d\n", *write_recovery);
1679
1680         mtsdram(SDRAM_MMODE, mmode);
1681 }
1682
1683 /*-----------------------------------------------------------------------------+
1684  * program_rtr.
1685  *-----------------------------------------------------------------------------*/
1686 static void program_rtr(unsigned long *dimm_populated,
1687                         unsigned char *iic0_dimm_addr,
1688                         unsigned long num_dimm_banks)
1689 {
1690         PPC4xx_SYS_INFO board_cfg;
1691         unsigned long max_refresh_rate;
1692         unsigned long dimm_num;
1693         unsigned long refresh_rate_type;
1694         unsigned long refresh_rate;
1695         unsigned long rint;
1696         unsigned long sdram_freq;
1697         unsigned long sdr_ddrpll;
1698         unsigned long val;
1699
1700         /*------------------------------------------------------------------
1701          * Get the board configuration info.
1702          *-----------------------------------------------------------------*/
1703         get_sys_info(&board_cfg);
1704
1705         /*------------------------------------------------------------------
1706          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1707          *-----------------------------------------------------------------*/
1708         mfsdr(SDR0_DDR0, sdr_ddrpll);
1709         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1710
1711         max_refresh_rate = 0;
1712         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1713                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1714
1715                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1716                         refresh_rate_type &= 0x7F;
1717                         switch (refresh_rate_type) {
1718                         case 0:
1719                                 refresh_rate =  15625;
1720                                 break;
1721                         case 1:
1722                                 refresh_rate =   3906;
1723                                 break;
1724                         case 2:
1725                                 refresh_rate =   7812;
1726                                 break;
1727                         case 3:
1728                                 refresh_rate =  31250;
1729                                 break;
1730                         case 4:
1731                                 refresh_rate =  62500;
1732                                 break;
1733                         case 5:
1734                                 refresh_rate = 125000;
1735                                 break;
1736                         default:
1737                                 refresh_rate = 0;
1738                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1739                                        (unsigned int)dimm_num);
1740                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1741                                 spd_ddr_init_hang ();
1742                                 break;
1743                         }
1744
1745                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1746                 }
1747         }
1748
1749         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1750         mfsdram(SDRAM_RTR, val);
1751         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1752                 (SDRAM_RTR_RINT_ENCODE(rint)));
1753 }
1754
1755 /*------------------------------------------------------------------
1756  * This routine programs the SDRAM_TRx registers.
1757  *-----------------------------------------------------------------*/
1758 static void program_tr(unsigned long *dimm_populated,
1759                        unsigned char *iic0_dimm_addr,
1760                        unsigned long num_dimm_banks)
1761 {
1762         unsigned long dimm_num;
1763         unsigned long sdram_ddr1;
1764         unsigned long t_rp_ns;
1765         unsigned long t_rcd_ns;
1766         unsigned long t_rrd_ns;
1767         unsigned long t_ras_ns;
1768         unsigned long t_rc_ns;
1769         unsigned long t_rfc_ns;
1770         unsigned long t_wpc_ns;
1771         unsigned long t_wtr_ns;
1772         unsigned long t_rpc_ns;
1773         unsigned long t_rp_clk;
1774         unsigned long t_rcd_clk;
1775         unsigned long t_rrd_clk;
1776         unsigned long t_ras_clk;
1777         unsigned long t_rc_clk;
1778         unsigned long t_rfc_clk;
1779         unsigned long t_wpc_clk;
1780         unsigned long t_wtr_clk;
1781         unsigned long t_rpc_clk;
1782         unsigned long sdtr1, sdtr2, sdtr3;
1783         unsigned long ddr_check;
1784         unsigned long sdram_freq;
1785         unsigned long sdr_ddrpll;
1786
1787         PPC4xx_SYS_INFO board_cfg;
1788
1789         /*------------------------------------------------------------------
1790          * Get the board configuration info.
1791          *-----------------------------------------------------------------*/
1792         get_sys_info(&board_cfg);
1793
1794         mfsdr(SDR0_DDR0, sdr_ddrpll);
1795         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1796
1797         /*------------------------------------------------------------------
1798          * Handle the timing.  We need to find the worst case timing of all
1799          * the dimm modules installed.
1800          *-----------------------------------------------------------------*/
1801         t_rp_ns = 0;
1802         t_rrd_ns = 0;
1803         t_rcd_ns = 0;
1804         t_ras_ns = 0;
1805         t_rc_ns = 0;
1806         t_rfc_ns = 0;
1807         t_wpc_ns = 0;
1808         t_wtr_ns = 0;
1809         t_rpc_ns = 0;
1810         sdram_ddr1 = TRUE;
1811
1812         /* loop through all the DIMM slots on the board */
1813         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1814                 /* If a dimm is installed in a particular slot ... */
1815                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1816                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1817                                 sdram_ddr1 = TRUE;
1818                         else
1819                                 sdram_ddr1 = FALSE;
1820
1821                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1822                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1823                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1824                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1825                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1826                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1827                 }
1828         }
1829
1830         /*------------------------------------------------------------------
1831          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1832          *-----------------------------------------------------------------*/
1833         mfsdram(SDRAM_SDTR1, sdtr1);
1834         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1835                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1836
1837         /* default values */
1838         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1839         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1840
1841         /* normal operations */
1842         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1843         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1844
1845         mtsdram(SDRAM_SDTR1, sdtr1);
1846
1847         /*------------------------------------------------------------------
1848          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1849          *-----------------------------------------------------------------*/
1850         mfsdram(SDRAM_SDTR2, sdtr2);
1851         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1852                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1853                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1854                    SDRAM_SDTR2_RRD_MASK);
1855
1856         /*
1857          * convert t_rcd from nanoseconds to ddr clocks
1858          * round up if necessary
1859          */
1860         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1861         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1862         if (sdram_freq != ddr_check)
1863                 t_rcd_clk++;
1864
1865         switch (t_rcd_clk) {
1866         case 0:
1867         case 1:
1868                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1869                 break;
1870         case 2:
1871                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1872                 break;
1873         case 3:
1874                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1875                 break;
1876         case 4:
1877                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1878                 break;
1879         default:
1880                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1881                 break;
1882         }
1883
1884         if (sdram_ddr1 == TRUE) { /* DDR1 */
1885                 if (sdram_freq < 200000000) {
1886                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1887                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1888                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1889                 } else {
1890                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1891                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1892                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1893                 }
1894         } else { /* DDR2 */
1895                 /* loop through all the DIMM slots on the board */
1896                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1897                         /* If a dimm is installed in a particular slot ... */
1898                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1899                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1900                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1901                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1902                         }
1903                 }
1904
1905                 /*
1906                  * convert from nanoseconds to ddr clocks
1907                  * round up if necessary
1908                  */
1909                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1910                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1911                 if (sdram_freq != ddr_check)
1912                         t_wpc_clk++;
1913
1914                 switch (t_wpc_clk) {
1915                 case 0:
1916                 case 1:
1917                 case 2:
1918                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1919                         break;
1920                 case 3:
1921                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1922                         break;
1923                 case 4:
1924                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1925                         break;
1926                 case 5:
1927                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1928                         break;
1929                 default:
1930                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1931                         break;
1932                 }
1933
1934                 /*
1935                  * convert from nanoseconds to ddr clocks
1936                  * round up if necessary
1937                  */
1938                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1939                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1940                 if (sdram_freq != ddr_check)
1941                         t_wtr_clk++;
1942
1943                 switch (t_wtr_clk) {
1944                 case 0:
1945                 case 1:
1946                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1947                         break;
1948                 case 2:
1949                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1950                         break;
1951                 case 3:
1952                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1953                         break;
1954                 default:
1955                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1956                         break;
1957                 }
1958
1959                 /*
1960                  * convert from nanoseconds to ddr clocks
1961                  * round up if necessary
1962                  */
1963                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1964                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1965                 if (sdram_freq != ddr_check)
1966                         t_rpc_clk++;
1967
1968                 switch (t_rpc_clk) {
1969                 case 0:
1970                 case 1:
1971                 case 2:
1972                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1973                         break;
1974                 case 3:
1975                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1976                         break;
1977                 default:
1978                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1979                         break;
1980                 }
1981         }
1982
1983         /* default value */
1984         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1985
1986         /*
1987          * convert t_rrd from nanoseconds to ddr clocks
1988          * round up if necessary
1989          */
1990         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1991         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1992         if (sdram_freq != ddr_check)
1993                 t_rrd_clk++;
1994
1995         if (t_rrd_clk == 3)
1996                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1997         else
1998                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1999
2000         /*
2001          * convert t_rp from nanoseconds to ddr clocks
2002          * round up if necessary
2003          */
2004         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2005         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2006         if (sdram_freq != ddr_check)
2007                 t_rp_clk++;
2008
2009         switch (t_rp_clk) {
2010         case 0:
2011         case 1:
2012         case 2:
2013         case 3:
2014                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2015                 break;
2016         case 4:
2017                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2018                 break;
2019         case 5:
2020                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2021                 break;
2022         case 6:
2023                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2024                 break;
2025         default:
2026                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2027                 break;
2028         }
2029
2030         mtsdram(SDRAM_SDTR2, sdtr2);
2031
2032         /*------------------------------------------------------------------
2033          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2034          *-----------------------------------------------------------------*/
2035         mfsdram(SDRAM_SDTR3, sdtr3);
2036         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2037                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2038
2039         /*
2040          * convert t_ras from nanoseconds to ddr clocks
2041          * round up if necessary
2042          */
2043         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2044         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2045         if (sdram_freq != ddr_check)
2046                 t_ras_clk++;
2047
2048         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2049
2050         /*
2051          * convert t_rc from nanoseconds to ddr clocks
2052          * round up if necessary
2053          */
2054         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2055         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2056         if (sdram_freq != ddr_check)
2057                 t_rc_clk++;
2058
2059         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2060
2061         /* default xcs value */
2062         sdtr3 |= SDRAM_SDTR3_XCS;
2063
2064         /*
2065          * convert t_rfc from nanoseconds to ddr clocks
2066          * round up if necessary
2067          */
2068         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2069         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2070         if (sdram_freq != ddr_check)
2071                 t_rfc_clk++;
2072
2073         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2074
2075         mtsdram(SDRAM_SDTR3, sdtr3);
2076 }
2077
2078 /*-----------------------------------------------------------------------------+
2079  * program_bxcf.
2080  *-----------------------------------------------------------------------------*/
2081 static void program_bxcf(unsigned long *dimm_populated,
2082                          unsigned char *iic0_dimm_addr,
2083                          unsigned long num_dimm_banks)
2084 {
2085         unsigned long dimm_num;
2086         unsigned long num_col_addr;
2087         unsigned long num_ranks;
2088         unsigned long num_banks;
2089         unsigned long mode;
2090         unsigned long ind_rank;
2091         unsigned long ind;
2092         unsigned long ind_bank;
2093         unsigned long bank_0_populated;
2094
2095         /*------------------------------------------------------------------
2096          * Set the BxCF regs.  First, wipe out the bank config registers.
2097          *-----------------------------------------------------------------*/
2098         mtsdram(SDRAM_MB0CF, 0x00000000);
2099         mtsdram(SDRAM_MB1CF, 0x00000000);
2100         mtsdram(SDRAM_MB2CF, 0x00000000);
2101         mtsdram(SDRAM_MB3CF, 0x00000000);
2102
2103         mode = SDRAM_BXCF_M_BE_ENABLE;
2104
2105         bank_0_populated = 0;
2106
2107         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2108                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2109                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2110                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2111                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2112                                 num_ranks = (num_ranks & 0x0F) +1;
2113                         else
2114                                 num_ranks = num_ranks & 0x0F;
2115
2116                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2117
2118                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2119                                 if (num_banks == 4)
2120                                         ind = 0;
2121                                 else
2122                                         ind = 5 << 8;
2123                                 switch (num_col_addr) {
2124                                 case 0x08:
2125                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2126                                         break;
2127                                 case 0x09:
2128                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2129                                         break;
2130                                 case 0x0A:
2131                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2132                                         break;
2133                                 case 0x0B:
2134                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2135                                         break;
2136                                 case 0x0C:
2137                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2138                                         break;
2139                                 default:
2140                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2141                                                (unsigned int)dimm_num);
2142                                         printf("ERROR: Unsupported value for number of "
2143                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2144                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2145                                         spd_ddr_init_hang ();
2146                                 }
2147                         }
2148
2149                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2150                                 bank_0_populated = 1;
2151
2152                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2153                                 mtsdram(SDRAM_MB0CF +
2154                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2155                                         mode);
2156                         }
2157                 }
2158         }
2159 }
2160
2161 /*------------------------------------------------------------------
2162  * program memory queue.
2163  *-----------------------------------------------------------------*/
2164 static void program_memory_queue(unsigned long *dimm_populated,
2165                                  unsigned char *iic0_dimm_addr,
2166                                  unsigned long num_dimm_banks)
2167 {
2168         unsigned long dimm_num;
2169         phys_size_t rank_base_addr;
2170         unsigned long rank_reg;
2171         phys_size_t rank_size_bytes;
2172         unsigned long rank_size_id;
2173         unsigned long num_ranks;
2174         unsigned long baseadd_size;
2175         unsigned long i;
2176         unsigned long bank_0_populated = 0;
2177         phys_size_t total_size = 0;
2178
2179         /*------------------------------------------------------------------
2180          * Reset the rank_base_address.
2181          *-----------------------------------------------------------------*/
2182         rank_reg   = SDRAM_R0BAS;
2183
2184         rank_base_addr = 0x00000000;
2185
2186         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2187                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2188                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2189                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2190                                 num_ranks = (num_ranks & 0x0F) + 1;
2191                         else
2192                                 num_ranks = num_ranks & 0x0F;
2193
2194                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2195
2196                         /*------------------------------------------------------------------
2197                          * Set the sizes
2198                          *-----------------------------------------------------------------*/
2199                         baseadd_size = 0;
2200                         switch (rank_size_id) {
2201                         case 0x01:
2202                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2203                                 total_size = 1024;
2204                                 break;
2205                         case 0x02:
2206                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2207                                 total_size = 2048;
2208                                 break;
2209                         case 0x04:
2210                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2211                                 total_size = 4096;
2212                                 break;
2213                         case 0x08:
2214                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2215                                 total_size = 32;
2216                                 break;
2217                         case 0x10:
2218                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2219                                 total_size = 64;
2220                                 break;
2221                         case 0x20:
2222                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2223                                 total_size = 128;
2224                                 break;
2225                         case 0x40:
2226                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2227                                 total_size = 256;
2228                                 break;
2229                         case 0x80:
2230                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2231                                 total_size = 512;
2232                                 break;
2233                         default:
2234                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2235                                        (unsigned int)dimm_num);
2236                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2237                                        (unsigned int)rank_size_id);
2238                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2239                                 spd_ddr_init_hang ();
2240                         }
2241                         rank_size_bytes = total_size << 20;
2242
2243                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2244                                 bank_0_populated = 1;
2245
2246                         for (i = 0; i < num_ranks; i++) {
2247                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2248                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2249                                            baseadd_size));
2250                                 rank_base_addr += rank_size_bytes;
2251                         }
2252                 }
2253         }
2254
2255 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2256     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2257     defined(CONFIG_460SX)
2258         /*
2259          * Enable high bandwidth access
2260          * This is currently not used, but with this setup
2261          * it is possible to use it later on in e.g. the Linux
2262          * EMAC driver for performance gain.
2263          */
2264         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2265         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2266
2267         /*
2268          * Set optimal value for Memory Queue HB/LL Configuration registers
2269          */
2270         mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2271               SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2272               SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2273         mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2274               SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2275               SDRAM_CONF1LL_RPLM);
2276         mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2277 #endif
2278 }
2279
2280 /*-----------------------------------------------------------------------------+
2281  * is_ecc_enabled.
2282  *-----------------------------------------------------------------------------*/
2283 static unsigned long is_ecc_enabled(void)
2284 {
2285         unsigned long dimm_num;
2286         unsigned long ecc;
2287         unsigned long val;
2288
2289         ecc = 0;
2290         /* loop through all the DIMM slots on the board */
2291         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2292                 mfsdram(SDRAM_MCOPT1, val);
2293                 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2294         }
2295
2296         return ecc;
2297 }
2298
2299 #ifdef CONFIG_DDR_ECC
2300 /*-----------------------------------------------------------------------------+
2301  * program_ecc.
2302  *-----------------------------------------------------------------------------*/
2303 static void program_ecc(unsigned long *dimm_populated,
2304                         unsigned char *iic0_dimm_addr,
2305                         unsigned long num_dimm_banks,
2306                         unsigned long tlb_word2_i_value)
2307 {
2308         unsigned long mcopt1;
2309         unsigned long mcopt2;
2310         unsigned long mcstat;
2311         unsigned long dimm_num;
2312         unsigned long ecc;
2313
2314         ecc = 0;
2315         /* loop through all the DIMM slots on the board */
2316         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2317                 /* If a dimm is installed in a particular slot ... */
2318                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2319                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2320         }
2321         if (ecc == 0)
2322                 return;
2323
2324         if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
2325                 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
2326                 return;
2327         }
2328
2329         mfsdram(SDRAM_MCOPT1, mcopt1);
2330         mfsdram(SDRAM_MCOPT2, mcopt2);
2331
2332         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2333                 /* DDR controller must be enabled and not in self-refresh. */
2334                 mfsdram(SDRAM_MCSTAT, mcstat);
2335                 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2336                     && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2337                     && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2338                         == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2339
2340                         program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2341                 }
2342         }
2343
2344         return;
2345 }
2346
2347 static void wait_ddr_idle(void)
2348 {
2349         u32 val;
2350
2351         do {
2352                 mfsdram(SDRAM_MCSTAT, val);
2353         } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2354 }
2355
2356 /*-----------------------------------------------------------------------------+
2357  * program_ecc_addr.
2358  *-----------------------------------------------------------------------------*/
2359 static void program_ecc_addr(unsigned long start_address,
2360                              unsigned long num_bytes,
2361                              unsigned long tlb_word2_i_value)
2362 {
2363         unsigned long current_address;
2364         unsigned long end_address;
2365         unsigned long address_increment;
2366         unsigned long mcopt1;
2367         char str[] = "ECC generation -";
2368         char slash[] = "\\|/-\\|/-";
2369         int loop = 0;
2370         int loopi = 0;
2371
2372         current_address = start_address;
2373         mfsdram(SDRAM_MCOPT1, mcopt1);
2374         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2375                 mtsdram(SDRAM_MCOPT1,
2376                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2377                 sync();
2378                 eieio();
2379                 wait_ddr_idle();
2380
2381                 puts(str);
2382                 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2383                         /* ECC bit set method for non-cached memory */
2384                         if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2385                                 address_increment = 4;
2386                         else
2387                                 address_increment = 8;
2388                         end_address = current_address + num_bytes;
2389
2390                         while (current_address < end_address) {
2391                                 *((unsigned long *)current_address) = 0x00000000;
2392                                 current_address += address_increment;
2393
2394                                 if ((loop++ % (2 << 20)) == 0) {
2395                                         putc('\b');
2396                                         putc(slash[loopi++ % 8]);
2397                                 }
2398                         }
2399
2400                 } else {
2401                         /* ECC bit set method for cached memory */
2402                         dcbz_area(start_address, num_bytes);
2403                         /* Write modified dcache lines back to memory */
2404                         clean_dcache_range(start_address, start_address + num_bytes);
2405                 }
2406
2407                 blank_string(strlen(str));
2408
2409                 sync();
2410                 eieio();
2411                 wait_ddr_idle();
2412
2413                 /* clear ECC error repoting registers */
2414                 mtsdram(SDRAM_ECCCR, 0xffffffff);
2415                 mtdcr(0x4c, 0xffffffff);
2416
2417                 mtsdram(SDRAM_MCOPT1,
2418                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2419                 sync();
2420                 eieio();
2421                 wait_ddr_idle();
2422         }
2423 }
2424 #endif
2425
2426 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2427 /*-----------------------------------------------------------------------------+
2428  * program_DQS_calibration.
2429  *-----------------------------------------------------------------------------*/
2430 static void program_DQS_calibration(unsigned long *dimm_populated,
2431                                     unsigned char *iic0_dimm_addr,
2432                                     unsigned long num_dimm_banks)
2433 {
2434         unsigned long val;
2435
2436 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2437         mtsdram(SDRAM_RQDC, 0x80000037);
2438         mtsdram(SDRAM_RDCC, 0x40000000);
2439         mtsdram(SDRAM_RFDC, 0x000001DF);
2440
2441         test();
2442 #else
2443         /*------------------------------------------------------------------
2444          * Program RDCC register
2445          * Read sample cycle auto-update enable
2446          *-----------------------------------------------------------------*/
2447
2448         mfsdram(SDRAM_RDCC, val);
2449         mtsdram(SDRAM_RDCC,
2450                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2451                 | SDRAM_RDCC_RSAE_ENABLE);
2452
2453         /*------------------------------------------------------------------
2454          * Program RQDC register
2455          * Internal DQS delay mechanism enable
2456          *-----------------------------------------------------------------*/
2457         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2458
2459         /*------------------------------------------------------------------
2460          * Program RFDC register
2461          * Set Feedback Fractional Oversample
2462          * Auto-detect read sample cycle enable
2463          * Set RFOS to 1/4 of memclk cycle (0x3f)
2464          *-----------------------------------------------------------------*/
2465         mfsdram(SDRAM_RFDC, val);
2466         mtsdram(SDRAM_RFDC,
2467                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2468                          SDRAM_RFDC_RFFD_MASK))
2469                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2470                    SDRAM_RFDC_RFFD_ENCODE(0)));
2471
2472         DQS_calibration_process();
2473 #endif
2474 }
2475
2476 static int short_mem_test(void)
2477 {
2478         u32 *membase;
2479         u32 bxcr_num;
2480         u32 bxcf;
2481         int i;
2482         int j;
2483         phys_size_t base_addr;
2484         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2485                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2486                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2487                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2488                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2489                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2490                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2491                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2492                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2493                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2494                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2495                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2496                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2497                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2498                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2499                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2500                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2501         int l;
2502
2503         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2504                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2505
2506                 /* Banks enabled */
2507                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2508                         /* Bank is enabled */
2509
2510                         /*
2511                          * Only run test on accessable memory (below 2GB)
2512                          */
2513                         base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2514                         if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2515                                 continue;
2516
2517                         /*------------------------------------------------------------------
2518                          * Run the short memory test.
2519                          *-----------------------------------------------------------------*/
2520                         membase = (u32 *)(u32)base_addr;
2521
2522                         for (i = 0; i < NUMMEMTESTS; i++) {
2523                                 for (j = 0; j < NUMMEMWORDS; j++) {
2524                                         membase[j] = test[i][j];
2525                                         ppcDcbf((u32)&(membase[j]));
2526                                 }
2527                                 sync();
2528                                 for (l=0; l<NUMLOOPS; l++) {
2529                                         for (j = 0; j < NUMMEMWORDS; j++) {
2530                                                 if (membase[j] != test[i][j]) {
2531                                                         ppcDcbf((u32)&(membase[j]));
2532                                                         return 0;
2533                                                 }
2534                                                 ppcDcbf((u32)&(membase[j]));
2535                                         }
2536                                         sync();
2537                                 }
2538                         }
2539                 }       /* if bank enabled */
2540         }               /* for bxcf_num */
2541
2542         return 1;
2543 }
2544
2545 #ifndef HARD_CODED_DQS
2546 /*-----------------------------------------------------------------------------+
2547  * DQS_calibration_process.
2548  *-----------------------------------------------------------------------------*/
2549 static void DQS_calibration_process(void)
2550 {
2551         unsigned long rfdc_reg;
2552         unsigned long rffd;
2553         unsigned long val;
2554         long rffd_average;
2555         long max_start;
2556         long min_end;
2557         unsigned long begin_rqfd[MAXRANKS];
2558         unsigned long begin_rffd[MAXRANKS];
2559         unsigned long end_rqfd[MAXRANKS];
2560         unsigned long end_rffd[MAXRANKS];
2561         char window_found;
2562         unsigned long dlycal;
2563         unsigned long dly_val;
2564         unsigned long max_pass_length;
2565         unsigned long current_pass_length;
2566         unsigned long current_fail_length;
2567         unsigned long current_start;
2568         long max_end;
2569         unsigned char fail_found;
2570         unsigned char pass_found;
2571 #if !defined(CONFIG_DDR_RQDC_FIXED)
2572         u32 rqdc_reg;
2573         u32 rqfd;
2574         u32 rqfd_start;
2575         u32 rqfd_average;
2576         int loopi = 0;
2577         char str[] = "Auto calibration -";
2578         char slash[] = "\\|/-\\|/-";
2579
2580         /*------------------------------------------------------------------
2581          * Test to determine the best read clock delay tuning bits.
2582          *
2583          * Before the DDR controller can be used, the read clock delay needs to be
2584          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2585          * This value cannot be hardcoded into the program because it changes
2586          * depending on the board's setup and environment.
2587          * To do this, all delay values are tested to see if they
2588          * work or not.  By doing this, you get groups of fails with groups of
2589          * passing values.  The idea is to find the start and end of a passing
2590          * window and take the center of it to use as the read clock delay.
2591          *
2592          * A failure has to be seen first so that when we hit a pass, we know
2593          * that it is truely the start of the window.  If we get passing values
2594          * to start off with, we don't know if we are at the start of the window.
2595          *
2596          * The code assumes that a failure will always be found.
2597          * If a failure is not found, there is no easy way to get the middle
2598          * of the passing window.  I guess we can pretty much pick any value
2599          * but some values will be better than others.  Since the lowest speed
2600          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2601          * from experimentation it is safe to say you will always have a failure.
2602          *-----------------------------------------------------------------*/
2603
2604         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2605         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2606
2607         puts(str);
2608
2609 calibration_loop:
2610         mfsdram(SDRAM_RQDC, rqdc_reg);
2611         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2612                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2613 #else /* CONFIG_DDR_RQDC_FIXED */
2614         /*
2615          * On Katmai the complete auto-calibration somehow doesn't seem to
2616          * produce the best results, meaning optimal values for RQFD/RFFD.
2617          * This was discovered by GDA using a high bandwidth scope,
2618          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2619          * so now on Katmai "only" RFFD is auto-calibrated.
2620          */
2621         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2622 #endif /* CONFIG_DDR_RQDC_FIXED */
2623
2624         max_start = 0;
2625         min_end = 0;
2626         begin_rqfd[0] = 0;
2627         begin_rffd[0] = 0;
2628         begin_rqfd[1] = 0;
2629         begin_rffd[1] = 0;
2630         end_rqfd[0] = 0;
2631         end_rffd[0] = 0;
2632         end_rqfd[1] = 0;
2633         end_rffd[1] = 0;
2634         window_found = FALSE;
2635
2636         max_pass_length = 0;
2637         max_start = 0;
2638         max_end = 0;
2639         current_pass_length = 0;
2640         current_fail_length = 0;
2641         current_start = 0;
2642         window_found = FALSE;
2643         fail_found = FALSE;
2644         pass_found = FALSE;
2645
2646         /*
2647          * get the delay line calibration register value
2648          */
2649         mfsdram(SDRAM_DLCR, dlycal);
2650         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2651
2652         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2653                 mfsdram(SDRAM_RFDC, rfdc_reg);
2654                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2655
2656                 /*------------------------------------------------------------------
2657                  * Set the timing reg for the test.
2658                  *-----------------------------------------------------------------*/
2659                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2660
2661                 /*------------------------------------------------------------------
2662                  * See if the rffd value passed.
2663                  *-----------------------------------------------------------------*/
2664                 if (short_mem_test()) {
2665                         if (fail_found == TRUE) {
2666                                 pass_found = TRUE;
2667                                 if (current_pass_length == 0)
2668                                         current_start = rffd;
2669
2670                                 current_fail_length = 0;
2671                                 current_pass_length++;
2672
2673                                 if (current_pass_length > max_pass_length) {
2674                                         max_pass_length = current_pass_length;
2675                                         max_start = current_start;
2676                                         max_end = rffd;
2677                                 }
2678                         }
2679                 } else {
2680                         current_pass_length = 0;
2681                         current_fail_length++;
2682
2683                         if (current_fail_length >= (dly_val >> 2)) {
2684                                 if (fail_found == FALSE) {
2685                                         fail_found = TRUE;
2686                                 } else if (pass_found == TRUE) {
2687                                         window_found = TRUE;
2688                                         break;
2689                                 }
2690                         }
2691                 }
2692         }               /* for rffd */
2693
2694         /*------------------------------------------------------------------
2695          * Set the average RFFD value
2696          *-----------------------------------------------------------------*/
2697         rffd_average = ((max_start + max_end) >> 1);
2698
2699         if (rffd_average < 0)
2700                 rffd_average = 0;
2701
2702         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2703                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2704         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2705         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2706
2707 #if !defined(CONFIG_DDR_RQDC_FIXED)
2708         max_pass_length = 0;
2709         max_start = 0;
2710         max_end = 0;
2711         current_pass_length = 0;
2712         current_fail_length = 0;
2713         current_start = 0;
2714         window_found = FALSE;
2715         fail_found = FALSE;
2716         pass_found = FALSE;
2717
2718         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2719                 mfsdram(SDRAM_RQDC, rqdc_reg);
2720                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2721
2722                 /*------------------------------------------------------------------
2723                  * Set the timing reg for the test.
2724                  *-----------------------------------------------------------------*/
2725                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2726
2727                 /*------------------------------------------------------------------
2728                  * See if the rffd value passed.
2729                  *-----------------------------------------------------------------*/
2730                 if (short_mem_test()) {
2731                         if (fail_found == TRUE) {
2732                                 pass_found = TRUE;
2733                                 if (current_pass_length == 0)
2734                                         current_start = rqfd;
2735
2736                                 current_fail_length = 0;
2737                                 current_pass_length++;
2738
2739                                 if (current_pass_length > max_pass_length) {
2740                                         max_pass_length = current_pass_length;
2741                                         max_start = current_start;
2742                                         max_end = rqfd;
2743                                 }
2744                         }
2745                 } else {
2746                         current_pass_length = 0;
2747                         current_fail_length++;
2748
2749                         if (fail_found == FALSE) {
2750                                 fail_found = TRUE;
2751                         } else if (pass_found == TRUE) {
2752                                 window_found = TRUE;
2753                                 break;
2754                         }
2755                 }
2756         }
2757
2758         rqfd_average = ((max_start + max_end) >> 1);
2759
2760         /*------------------------------------------------------------------
2761          * Make sure we found the valid read passing window.  Halt if not
2762          *-----------------------------------------------------------------*/
2763         if (window_found == FALSE) {
2764                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2765                         putc('\b');
2766                         putc(slash[loopi++ % 8]);
2767
2768                         /* try again from with a different RQFD start value */
2769                         rqfd_start++;
2770                         goto calibration_loop;
2771                 }
2772
2773                 printf("\nERROR: Cannot determine a common read delay for the "
2774                        "DIMM(s) installed.\n");
2775                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2776                 ppc4xx_ibm_ddr2_register_dump();
2777                 spd_ddr_init_hang ();
2778         }
2779
2780         if (rqfd_average < 0)
2781                 rqfd_average = 0;
2782
2783         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2784                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2785
2786         mtsdram(SDRAM_RQDC,
2787                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2788                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2789
2790         blank_string(strlen(str));
2791 #endif /* CONFIG_DDR_RQDC_FIXED */
2792
2793         /*
2794          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2795          * PowerPC440SP/SPe DDR2 application note:
2796          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2797          */
2798         mfsdram(SDRAM_RTSR, val);
2799         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2800                 mfsdram(SDRAM_RDCC, val);
2801                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2802                         val += 0x40000000;
2803                         mtsdram(SDRAM_RDCC, val);
2804                 }
2805         }
2806
2807         mfsdram(SDRAM_DLCR, val);
2808         debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2809         mfsdram(SDRAM_RQDC, val);
2810         debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2811         mfsdram(SDRAM_RFDC, val);
2812         debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2813         mfsdram(SDRAM_RDCC, val);
2814         debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2815 }
2816 #else /* calibration test with hardvalues */
2817 /*-----------------------------------------------------------------------------+
2818  * DQS_calibration_process.
2819  *-----------------------------------------------------------------------------*/
2820 static void test(void)
2821 {
2822         unsigned long dimm_num;
2823         unsigned long ecc_temp;
2824         unsigned long i, j;
2825         unsigned long *membase;
2826         unsigned long bxcf[MAXRANKS];
2827         unsigned long val;
2828         char window_found;
2829         char begin_found[MAXDIMMS];
2830         char end_found[MAXDIMMS];
2831         char search_end[MAXDIMMS];
2832         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2833                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2834                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2835                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2836                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2837                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2838                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2839                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2840                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2841                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2842                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2843                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2844                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2845                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2846                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2847                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2848                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2849
2850         /*------------------------------------------------------------------
2851          * Test to determine the best read clock delay tuning bits.
2852          *
2853          * Before the DDR controller can be used, the read clock delay needs to be
2854          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2855          * This value cannot be hardcoded into the program because it changes
2856          * depending on the board's setup and environment.
2857          * To do this, all delay values are tested to see if they
2858          * work or not.  By doing this, you get groups of fails with groups of
2859          * passing values.  The idea is to find the start and end of a passing
2860          * window and take the center of it to use as the read clock delay.
2861          *
2862          * A failure has to be seen first so that when we hit a pass, we know
2863          * that it is truely the start of the window.  If we get passing values
2864          * to start off with, we don't know if we are at the start of the window.
2865          *
2866          * The code assumes that a failure will always be found.
2867          * If a failure is not found, there is no easy way to get the middle
2868          * of the passing window.  I guess we can pretty much pick any value
2869          * but some values will be better than others.  Since the lowest speed
2870          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2871          * from experimentation it is safe to say you will always have a failure.
2872          *-----------------------------------------------------------------*/
2873         mfsdram(SDRAM_MCOPT1, ecc_temp);
2874         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2875         mfsdram(SDRAM_MCOPT1, val);
2876         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2877                 SDRAM_MCOPT1_MCHK_NON);
2878
2879         window_found = FALSE;
2880         begin_found[0] = FALSE;
2881         end_found[0] = FALSE;
2882         search_end[0] = FALSE;
2883         begin_found[1] = FALSE;
2884         end_found[1] = FALSE;
2885         search_end[1] = FALSE;
2886
2887         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2888                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2889
2890                 /* Banks enabled */
2891                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2892
2893                         /* Bank is enabled */
2894                         membase =
2895                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2896
2897                         /*------------------------------------------------------------------
2898                          * Run the short memory test.
2899                          *-----------------------------------------------------------------*/
2900                         for (i = 0; i < NUMMEMTESTS; i++) {
2901                                 for (j = 0; j < NUMMEMWORDS; j++) {
2902                                         membase[j] = test[i][j];
2903                                         ppcDcbf((u32)&(membase[j]));
2904                                 }
2905                                 sync();
2906                                 for (j = 0; j < NUMMEMWORDS; j++) {
2907                                         if (membase[j] != test[i][j]) {
2908                                                 ppcDcbf((u32)&(membase[j]));
2909                                                 break;
2910                                         }
2911                                         ppcDcbf((u32)&(membase[j]));
2912                                 }
2913                                 sync();
2914                                 if (j < NUMMEMWORDS)
2915                                         break;
2916                         }
2917
2918                         /*------------------------------------------------------------------
2919                          * See if the rffd value passed.
2920                          *-----------------------------------------------------------------*/
2921                         if (i < NUMMEMTESTS) {
2922                                 if ((end_found[dimm_num] == FALSE) &&
2923                                     (search_end[dimm_num] == TRUE)) {
2924                                         end_found[dimm_num] = TRUE;
2925                                 }
2926                                 if ((end_found[0] == TRUE) &&
2927                                     (end_found[1] == TRUE))
2928                                         break;
2929                         } else {
2930                                 if (begin_found[dimm_num] == FALSE) {
2931                                         begin_found[dimm_num] = TRUE;
2932                                         search_end[dimm_num] = TRUE;
2933                                 }
2934                         }
2935                 } else {
2936                         begin_found[dimm_num] = TRUE;
2937                         end_found[dimm_num] = TRUE;
2938                 }
2939         }
2940
2941         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2942                 window_found = TRUE;
2943
2944         /*------------------------------------------------------------------
2945          * Make sure we found the valid read passing window.  Halt if not
2946          *-----------------------------------------------------------------*/
2947         if (window_found == FALSE) {
2948                 printf("ERROR: Cannot determine a common read delay for the "
2949                        "DIMM(s) installed.\n");
2950                 spd_ddr_init_hang ();
2951         }
2952
2953         /*------------------------------------------------------------------
2954          * Restore the ECC variable to what it originally was
2955          *-----------------------------------------------------------------*/
2956         mtsdram(SDRAM_MCOPT1,
2957                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2958                 | ecc_temp);
2959 }
2960 #endif /* !HARD_CODED_DQS */
2961 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2962
2963 #else /* CONFIG_SPD_EEPROM */
2964
2965 /*-----------------------------------------------------------------------------
2966  * Function:    initdram
2967  * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2968  *              The configuration is performed using static, compile-
2969  *              time parameters.
2970  *              Configures the PPC405EX(r) and PPC460EX/GT
2971  *---------------------------------------------------------------------------*/
2972 phys_size_t initdram(int board_type)
2973 {
2974         /*
2975          * Only run this SDRAM init code once. For NAND booting
2976          * targets like Kilauea, we call initdram() early from the
2977          * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2978          * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2979          * which calls initdram() again. This time the controller
2980          * mustn't be reconfigured again since we're already running
2981          * from SDRAM.
2982          */
2983 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2984         unsigned long val;
2985
2986 #if defined(CONFIG_440)
2987         mtdcr(SDRAM_R0BAS,      CONFIG_SYS_SDRAM_R0BAS);
2988         mtdcr(SDRAM_R1BAS,      CONFIG_SYS_SDRAM_R1BAS);
2989         mtdcr(SDRAM_R2BAS,      CONFIG_SYS_SDRAM_R2BAS);
2990         mtdcr(SDRAM_R3BAS,      CONFIG_SYS_SDRAM_R3BAS);
2991         mtdcr(SDRAM_PLBADDULL,  CONFIG_SYS_SDRAM_PLBADDULL);    /* MQ0_BAUL */
2992         mtdcr(SDRAM_PLBADDUHB,  CONFIG_SYS_SDRAM_PLBADDUHB);    /* MQ0_BAUH */
2993         mtdcr(SDRAM_CONF1LL,    CONFIG_SYS_SDRAM_CONF1LL);
2994         mtdcr(SDRAM_CONF1HB,    CONFIG_SYS_SDRAM_CONF1HB);
2995         mtdcr(SDRAM_CONFPATHB,  CONFIG_SYS_SDRAM_CONFPATHB);
2996 #endif
2997
2998         /* Set Memory Bank Configuration Registers */
2999
3000         mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
3001         mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
3002         mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
3003         mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
3004
3005         /* Set Memory Clock Timing Register */
3006
3007         mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
3008
3009         /* Set Refresh Time Register */
3010
3011         mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
3012
3013         /* Set SDRAM Timing Registers */
3014
3015         mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
3016         mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
3017         mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
3018
3019         /* Set Mode and Extended Mode Registers */
3020
3021         mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
3022         mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
3023
3024         /* Set Memory Controller Options 1 Register */
3025
3026         mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
3027
3028         /* Set Manual Initialization Control Registers */
3029
3030         mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
3031         mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
3032         mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
3033         mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
3034         mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
3035         mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
3036         mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
3037         mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
3038         mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
3039         mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
3040         mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
3041         mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
3042         mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
3043         mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
3044         mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
3045         mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
3046
3047         /* Set On-Die Termination Registers */
3048
3049         mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
3050         mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
3051         mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
3052
3053         /* Set Write Timing Register */
3054
3055         mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
3056
3057         /*
3058          * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3059          * SDRAM0_MCOPT2[IPTR] = 1
3060          */
3061
3062         mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3063                                SDRAM_MCOPT2_IPTR_EXECUTE));
3064
3065         /*
3066          * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3067          * completion of initialization.
3068          */
3069
3070         do {
3071                 mfsdram(SDRAM_MCSTAT, val);
3072         } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3073
3074         /* Set Delay Control Registers */
3075
3076         mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
3077
3078 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3079         mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
3080         mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
3081         mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
3082 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3083
3084         /*
3085          * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3086          */
3087
3088         mfsdram(SDRAM_MCOPT2, val);
3089         mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3090
3091 #if defined(CONFIG_440)
3092         /*
3093          * Program TLB entries with caches enabled, for best performace
3094          * while auto-calibrating and ECC generation
3095          */
3096         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
3097 #endif
3098
3099 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3100 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3101         /*------------------------------------------------------------------
3102          | DQS calibration.
3103          +-----------------------------------------------------------------*/
3104         DQS_autocalibration();
3105 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3106 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3107
3108 #if defined(CONFIG_DDR_ECC)
3109         ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
3110 #endif /* defined(CONFIG_DDR_ECC) */
3111
3112 #if defined(CONFIG_440)
3113         /*
3114          * Now after initialization (auto-calibration and ECC generation)
3115          * remove the TLB entries with caches enabled and program again with
3116          * desired cache functionality
3117          */
3118         remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
3119         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3120 #endif
3121
3122         ppc4xx_ibm_ddr2_register_dump();
3123
3124 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3125         /*
3126          * Clear potential errors resulting from auto-calibration.
3127          * If not done, then we could get an interrupt later on when
3128          * exceptions are enabled.
3129          */
3130         set_mcsr(get_mcsr());
3131 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3132
3133 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3134
3135         return (CONFIG_SYS_MBYTES_SDRAM << 20);
3136 }
3137 #endif /* CONFIG_SPD_EEPROM */
3138
3139 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3140 #if defined(CONFIG_440)
3141 u32 mfdcr_any(u32 dcr)
3142 {
3143         u32 val;
3144
3145         switch (dcr) {
3146         case SDRAM_R0BAS + 0:
3147                 val = mfdcr(SDRAM_R0BAS + 0);
3148                 break;
3149         case SDRAM_R0BAS + 1:
3150                 val = mfdcr(SDRAM_R0BAS + 1);
3151                 break;
3152         case SDRAM_R0BAS + 2:
3153                 val = mfdcr(SDRAM_R0BAS + 2);
3154                 break;
3155         case SDRAM_R0BAS + 3:
3156                 val = mfdcr(SDRAM_R0BAS + 3);
3157                 break;
3158         default:
3159                 printf("DCR %d not defined in case statement!!!\n", dcr);
3160                 val = 0; /* just to satisfy the compiler */
3161         }
3162
3163         return val;
3164 }
3165
3166 void mtdcr_any(u32 dcr, u32 val)
3167 {
3168         switch (dcr) {
3169         case SDRAM_R0BAS + 0:
3170                 mtdcr(SDRAM_R0BAS + 0, val);
3171                 break;
3172         case SDRAM_R0BAS + 1:
3173                 mtdcr(SDRAM_R0BAS + 1, val);
3174                 break;
3175         case SDRAM_R0BAS + 2:
3176                 mtdcr(SDRAM_R0BAS + 2, val);
3177                 break;
3178         case SDRAM_R0BAS + 3:
3179                 mtdcr(SDRAM_R0BAS + 3, val);
3180                 break;
3181         default:
3182                 printf("DCR %d not defined in case statement!!!\n", dcr);
3183         }
3184 }
3185 #endif /* defined(CONFIG_440) */
3186
3187 void blank_string(int size)
3188 {
3189         int i;
3190
3191         for (i = 0; i < size; i++)
3192                 putc('\b');
3193         for (i = 0; i < size; i++)
3194                 putc(' ');
3195         for (i = 0; i < size; i++)
3196                 putc('\b');
3197 }
3198 #endif /* !defined(CONFIG_NAND_U_BOOT) &&  !defined(CONFIG_NAND_SPL) */
3199
3200 inline void ppc4xx_ibm_ddr2_register_dump(void)
3201 {
3202 #if defined(DEBUG)
3203         printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3204
3205 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3206      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3207         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
3208         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
3209         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
3210         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
3211 #endif /* (defined(CONFIG_440SP) || ... */
3212 #if defined(CONFIG_405EX)
3213         PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3214         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3215         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3216         PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3217         PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3218         PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3219 #endif /* defined(CONFIG_405EX) */
3220         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3221         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3222         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3223         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3224         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3225         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3226         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3227         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3228         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3229         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3230         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3231         PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3232 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3233      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3234         PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3235         PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3236         /*
3237          * OPART is only used as a trigger register.
3238          *
3239          * No data is contained in this register, and reading or writing
3240          * to is can cause bad things to happen (hangs). Just skip it and
3241          * report "N/A".
3242          */
3243         printf("%20s = N/A\n", "SDRAM_OPART");
3244 #endif /* defined(CONFIG_440SP) || ... */
3245         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3246         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3247         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3248         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3249         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3250         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3251         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3252         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3253         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3254         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3255         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3256         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3257         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3258         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3259         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3260         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3261         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3262         PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3263         PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3264         PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3265         PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3266         PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3267         PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3268         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3269         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3270         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3271         PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3272         PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3273         PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
3274 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3275      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3276         PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3277 #endif /* defined(CONFIG_440SP) || ... */
3278         PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3279         PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3280         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3281 #endif /* defined(DEBUG) */
3282 }
3283
3284 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */