cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX(r)
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * Copyright (c) 2008 Nuovation System Designs, LLC
  10  *   Grant Erickson <gerickson@nuovations.com>
  11
  12  * (C) Copyright 2007-2008
  13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14  *
  15  * COPYRIGHT   AMCC   CORPORATION 2004
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  *
  35  */
  36
  37 /* define DEBUG for debugging output (obviously ;-)) */
  38 #if 0
  39 #define DEBUG
  40 #endif
  41
  42 #include <common.h>
  43 #include <command.h>
  44 #include <ppc4xx.h>
  45 #include <i2c.h>
  46 #include <asm/io.h>
  47 #include <asm/processor.h>
  48 #include <asm/mmu.h>
  49 #include <asm/cache.h>
  50
  51 #include "ecc.h"
  52
  53 #if defined(CONFIG_SPD_EEPROM) &&                               \
  54         (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  55          defined(CONFIG_460EX) || defined(CONFIG_460GT))
  56
  57 /*-----------------------------------------------------------------------------+
  58  * Defines
  59  *-----------------------------------------------------------------------------*/
  60 #ifndef TRUE
  61 #define TRUE            1
  62 #endif
  63 #ifndef FALSE
  64 #define FALSE           0
  65 #endif
  66
  67 #define SDRAM_DDR1      1
  68 #define SDRAM_DDR2      2
  69 #define SDRAM_NONE      0
  70
  71 #define MAXDIMMS        2
  72 #define MAXRANKS        4
  73 #define MAXBXCF         4
  74 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
  75
  76 #define ONE_BILLION     1000000000
  77
  78 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  79
  80 #define CMD_NOP         (7 << 19)
  81 #define CMD_PRECHARGE   (2 << 19)
  82 #define CMD_REFRESH     (1 << 19)
  83 #define CMD_EMR         (0 << 19)
  84 #define CMD_READ        (5 << 19)
  85 #define CMD_WRITE       (4 << 19)
  86
  87 #define SELECT_MR       (0 << 16)
  88 #define SELECT_EMR      (1 << 16)
  89 #define SELECT_EMR2     (2 << 16)
  90 #define SELECT_EMR3     (3 << 16)
  91
  92 /* MR */
  93 #define DLL_RESET       0x00000100
  94
  95 #define WRITE_RECOV_2   (1 << 9)
  96 #define WRITE_RECOV_3   (2 << 9)
  97 #define WRITE_RECOV_4   (3 << 9)
  98 #define WRITE_RECOV_5   (4 << 9)
  99 #define WRITE_RECOV_6   (5 << 9)
 100
 101 #define BURST_LEN_4     0x00000002
 102
 103 /* EMR */
 104 #define ODT_0_OHM       0x00000000
 105 #define ODT_50_OHM      0x00000044
 106 #define ODT_75_OHM      0x00000004
 107 #define ODT_150_OHM     0x00000040
 108
 109 #define ODS_FULL        0x00000000
 110 #define ODS_REDUCED     0x00000002
 111
 112 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 113 #define ODT_EB0R        (0x80000000 >> 8)
 114 #define ODT_EB0W        (0x80000000 >> 7)
 115 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 116 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 117 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 118
 119 /* Defines for the Read Cycle Delay test */
 120 #define NUMMEMTESTS     8
 121 #define NUMMEMWORDS     8
 122 #define NUMLOOPS        64              /* memory test loops */
 123
 124 /*
 125  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
 126  * region. Right now the cache should still be disabled in U-Boot because of the
 127  * EMAC driver, that need it's buffer descriptor to be located in non cached
 128  * memory.
 129  *
 130  * If at some time this restriction doesn't apply anymore, just define
 131  * CONFIG_4xx_DCACHE in the board config file and this code should setup
 132  * everything correctly.
 133  */
 134 #ifdef CONFIG_4xx_DCACHE
 135 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
 136 #else
 137 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 138 #endif
 139
 140 /*
 141  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 142  */
 143 void __spd_ddr_init_hang (void)
 144 {
 145         hang ();
 146 }
 147 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 148
 149 /*
 150  * To provide an interface for board specific config values in this common
 151  * DDR setup code, we implement he "weak" default functions here. They return
 152  * the default value back to the caller.
 153  *
 154  * Please see include/configs/yucca.h for an example fora board specific
 155  * implementation.
 156  */
 157 u32 __ddr_wrdtr(u32 default_val)
 158 {
 159         return default_val;
 160 }
 161 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 162
 163 u32 __ddr_clktr(u32 default_val)
 164 {
 165         return default_val;
 166 }
 167 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 168
 169
 170 /* Private Structure Definitions */
 171
 172 /* enum only to ease code for cas latency setting */
 173 typedef enum ddr_cas_id {
 174         DDR_CAS_2      = 20,
 175         DDR_CAS_2_5    = 25,
 176         DDR_CAS_3      = 30,
 177         DDR_CAS_4      = 40,
 178         DDR_CAS_5      = 50
 179 } ddr_cas_id_t;
 180
 181 /*-----------------------------------------------------------------------------+
 182  * Prototypes
 183  *-----------------------------------------------------------------------------*/
 184 static unsigned long sdram_memsize(void);
 185 static void get_spd_info(unsigned long *dimm_populated,
 186                          unsigned char *iic0_dimm_addr,
 187                          unsigned long num_dimm_banks);
 188 static void check_mem_type(unsigned long *dimm_populated,
 189                            unsigned char *iic0_dimm_addr,
 190                            unsigned long num_dimm_banks);
 191 static void check_frequency(unsigned long *dimm_populated,
 192                             unsigned char *iic0_dimm_addr,
 193                             unsigned long num_dimm_banks);
 194 static void check_rank_number(unsigned long *dimm_populated,
 195                               unsigned char *iic0_dimm_addr,
 196                               unsigned long num_dimm_banks);
 197 static void check_voltage_type(unsigned long *dimm_populated,
 198                                unsigned char *iic0_dimm_addr,
 199                                unsigned long num_dimm_banks);
 200 static void program_memory_queue(unsigned long *dimm_populated,
 201                                  unsigned char *iic0_dimm_addr,
 202                                  unsigned long num_dimm_banks);
 203 static void program_codt(unsigned long *dimm_populated,
 204                          unsigned char *iic0_dimm_addr,
 205                          unsigned long num_dimm_banks);
 206 static void program_mode(unsigned long *dimm_populated,
 207                          unsigned char *iic0_dimm_addr,
 208                          unsigned long num_dimm_banks,
 209                          ddr_cas_id_t *selected_cas,
 210                          int *write_recovery);
 211 static void program_tr(unsigned long *dimm_populated,
 212                        unsigned char *iic0_dimm_addr,
 213                        unsigned long num_dimm_banks);
 214 static void program_rtr(unsigned long *dimm_populated,
 215                         unsigned char *iic0_dimm_addr,
 216                         unsigned long num_dimm_banks);
 217 static void program_bxcf(unsigned long *dimm_populated,
 218                          unsigned char *iic0_dimm_addr,
 219                          unsigned long num_dimm_banks);
 220 static void program_copt1(unsigned long *dimm_populated,
 221                           unsigned char *iic0_dimm_addr,
 222                           unsigned long num_dimm_banks);
 223 static void program_initplr(unsigned long *dimm_populated,
 224                             unsigned char *iic0_dimm_addr,
 225                             unsigned long num_dimm_banks,
 226                             ddr_cas_id_t selected_cas,
 227                             int write_recovery);
 228 static unsigned long is_ecc_enabled(void);
 229 #ifdef CONFIG_DDR_ECC
 230 static void program_ecc(unsigned long *dimm_populated,
 231                         unsigned char *iic0_dimm_addr,
 232                         unsigned long num_dimm_banks,
 233                         unsigned long tlb_word2_i_value);
 234 static void program_ecc_addr(unsigned long start_address,
 235                              unsigned long num_bytes,
 236                              unsigned long tlb_word2_i_value);
 237 #endif
 238 static void program_DQS_calibration(unsigned long *dimm_populated,
 239                                     unsigned char *iic0_dimm_addr,
 240                                     unsigned long num_dimm_banks);
 241 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 242 static void     test(void);
 243 #else
 244 static void     DQS_calibration_process(void);
 245 #endif
 246 static void ppc440sp_sdram_register_dump(void);
 247 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 248 void dcbz_area(u32 start_address, u32 num_bytes);
 249
 250 static u32 mfdcr_any(u32 dcr)
 251 {
 252         u32 val;
 253
 254         switch (dcr) {
 255         case SDRAM_R0BAS + 0:
 256                 val = mfdcr(SDRAM_R0BAS + 0);
 257                 break;
 258         case SDRAM_R0BAS + 1:
 259                 val = mfdcr(SDRAM_R0BAS + 1);
 260                 break;
 261         case SDRAM_R0BAS + 2:
 262                 val = mfdcr(SDRAM_R0BAS + 2);
 263                 break;
 264         case SDRAM_R0BAS + 3:
 265                 val = mfdcr(SDRAM_R0BAS + 3);
 266                 break;
 267         default:
 268                 printf("DCR %d not defined in case statement!!!\n", dcr);
 269                 val = 0; /* just to satisfy the compiler */
 270         }
 271
 272         return val;
 273 }
 274
 275 static void mtdcr_any(u32 dcr, u32 val)
 276 {
 277         switch (dcr) {
 278         case SDRAM_R0BAS + 0:
 279                 mtdcr(SDRAM_R0BAS + 0, val);
 280                 break;
 281         case SDRAM_R0BAS + 1:
 282                 mtdcr(SDRAM_R0BAS + 1, val);
 283                 break;
 284         case SDRAM_R0BAS + 2:
 285                 mtdcr(SDRAM_R0BAS + 2, val);
 286                 break;
 287         case SDRAM_R0BAS + 3:
 288                 mtdcr(SDRAM_R0BAS + 3, val);
 289                 break;
 290         default:
 291                 printf("DCR %d not defined in case statement!!!\n", dcr);
 292         }
 293 }
 294
 295 static unsigned char spd_read(uchar chip, uint addr)
 296 {
 297         unsigned char data[2];
 298
 299         if (i2c_probe(chip) == 0)
 300                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 301                         return data[0];
 302
 303         return 0;
 304 }
 305
 306 /*-----------------------------------------------------------------------------+
 307  * sdram_memsize
 308  *-----------------------------------------------------------------------------*/
 309 static unsigned long sdram_memsize(void)
 310 {
 311         unsigned long mem_size;
 312         unsigned long mcopt2;
 313         unsigned long mcstat;
 314         unsigned long mb0cf;
 315         unsigned long sdsz;
 316         unsigned long i;
 317
 318         mem_size = 0;
 319
 320         mfsdram(SDRAM_MCOPT2, mcopt2);
 321         mfsdram(SDRAM_MCSTAT, mcstat);
 322
 323         /* DDR controller must be enabled and not in self-refresh. */
 324         /* Otherwise memsize is zero. */
 325         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 326             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 327             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 328                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 329                 for (i = 0; i < MAXBXCF; i++) {
 330                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 331                         /* Banks enabled */
 332                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 333                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 334
 335                                 switch(sdsz) {
 336                                 case SDRAM_RXBAS_SDSZ_8:
 337                                         mem_size+=8;
 338                                         break;
 339                                 case SDRAM_RXBAS_SDSZ_16:
 340                                         mem_size+=16;
 341                                         break;
 342                                 case SDRAM_RXBAS_SDSZ_32:
 343                                         mem_size+=32;
 344                                         break;
 345                                 case SDRAM_RXBAS_SDSZ_64:
 346                                         mem_size+=64;
 347                                         break;
 348                                 case SDRAM_RXBAS_SDSZ_128:
 349                                         mem_size+=128;
 350                                         break;
 351                                 case SDRAM_RXBAS_SDSZ_256:
 352                                         mem_size+=256;
 353                                         break;
 354                                 case SDRAM_RXBAS_SDSZ_512:
 355                                         mem_size+=512;
 356                                         break;
 357                                 case SDRAM_RXBAS_SDSZ_1024:
 358                                         mem_size+=1024;
 359                                         break;
 360                                 case SDRAM_RXBAS_SDSZ_2048:
 361                                         mem_size+=2048;
 362                                         break;
 363                                 case SDRAM_RXBAS_SDSZ_4096:
 364                                         mem_size+=4096;
 365                                         break;
 366                                 default:
 367                                         mem_size=0;
 368                                         break;
 369                                 }
 370                         }
 371                 }
 372         }
 373
 374         mem_size *= 1024 * 1024;
 375         return(mem_size);
 376 }
 377
 378 /*-----------------------------------------------------------------------------+
 379  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 380  * Note: This routine runs from flash with a stack set up in the chip's
 381  * sram space.  It is important that the routine does not require .sbss, .bss or
 382  * .data sections.  It also cannot call routines that require these sections.
 383  *-----------------------------------------------------------------------------*/
 384 /*-----------------------------------------------------------------------------
 385  * Function:     initdram
 386  * Description:  Configures SDRAM memory banks for DDR operation.
 387  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 388  *               via the IIC bus and then configures the DDR SDRAM memory
 389  *               banks appropriately. If Auto Memory Configuration is
 390  *               not used, it is assumed that no DIMM is plugged
 391  *-----------------------------------------------------------------------------*/
 392 long int initdram(int board_type)
 393 {
 394         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 395         unsigned char spd0[MAX_SPD_BYTES];
 396         unsigned char spd1[MAX_SPD_BYTES];
 397         unsigned char *dimm_spd[MAXDIMMS];
 398         unsigned long dimm_populated[MAXDIMMS];
 399         unsigned long num_dimm_banks;           /* on board dimm banks */
 400         unsigned long val;
 401         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 402         int write_recovery;
 403         unsigned long dram_size = 0;
 404
 405         num_dimm_banks = sizeof(iic0_dimm_addr);
 406
 407         /*------------------------------------------------------------------
 408          * Set up an array of SPD matrixes.
 409          *-----------------------------------------------------------------*/
 410         dimm_spd[0] = spd0;
 411         dimm_spd[1] = spd1;
 412
 413         /*------------------------------------------------------------------
 414          * Reset the DDR-SDRAM controller.
 415          *-----------------------------------------------------------------*/
 416         mtsdr(SDR0_SRST, (0x80000000 >> 10));
 417         mtsdr(SDR0_SRST, 0x00000000);
 418
 419         /*
 420          * Make sure I2C controller is initialized
 421          * before continuing.
 422          */
 423
 424         /* switch to correct I2C bus */
 425         I2C_SET_BUS(CFG_SPD_BUS_NUM);
 426         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 427
 428         /*------------------------------------------------------------------
 429          * Clear out the serial presence detect buffers.
 430          * Perform IIC reads from the dimm.  Fill in the spds.
 431          * Check to see if the dimm slots are populated
 432          *-----------------------------------------------------------------*/
 433         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 434
 435         /*------------------------------------------------------------------
 436          * Check the memory type for the dimms plugged.
 437          *-----------------------------------------------------------------*/
 438         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 439
 440         /*------------------------------------------------------------------
 441          * Check the frequency supported for the dimms plugged.
 442          *-----------------------------------------------------------------*/
 443         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 444
 445         /*------------------------------------------------------------------
 446          * Check the total rank number.
 447          *-----------------------------------------------------------------*/
 448         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 449
 450         /*------------------------------------------------------------------
 451          * Check the voltage type for the dimms plugged.
 452          *-----------------------------------------------------------------*/
 453         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 454
 455         /*------------------------------------------------------------------
 456          * Program SDRAM controller options 2 register
 457          * Except Enabling of the memory controller.
 458          *-----------------------------------------------------------------*/
 459         mfsdram(SDRAM_MCOPT2, val);
 460         mtsdram(SDRAM_MCOPT2,
 461                 (val &
 462                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 463                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 464                    SDRAM_MCOPT2_ISIE_MASK))
 465                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 466                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 467                    SDRAM_MCOPT2_ISIE_ENABLE));
 468
 469         /*------------------------------------------------------------------
 470          * Program SDRAM controller options 1 register
 471          * Note: Does not enable the memory controller.
 472          *-----------------------------------------------------------------*/
 473         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 474
 475         /*------------------------------------------------------------------
 476          * Set the SDRAM Controller On Die Termination Register
 477          *-----------------------------------------------------------------*/
 478         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 479
 480         /*------------------------------------------------------------------
 481          * Program SDRAM refresh register.
 482          *-----------------------------------------------------------------*/
 483         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 484
 485         /*------------------------------------------------------------------
 486          * Program SDRAM mode register.
 487          *-----------------------------------------------------------------*/
 488         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 489                      &selected_cas, &write_recovery);
 490
 491         /*------------------------------------------------------------------
 492          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 493          *-----------------------------------------------------------------*/
 494         mfsdram(SDRAM_WRDTR, val);
 495         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 496                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 497
 498         /*------------------------------------------------------------------
 499          * Set the SDRAM Clock Timing Register
 500          *-----------------------------------------------------------------*/
 501         mfsdram(SDRAM_CLKTR, val);
 502         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 503                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 504
 505         /*------------------------------------------------------------------
 506          * Program the BxCF registers.
 507          *-----------------------------------------------------------------*/
 508         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 509
 510         /*------------------------------------------------------------------
 511          * Program SDRAM timing registers.
 512          *-----------------------------------------------------------------*/
 513         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 514
 515         /*------------------------------------------------------------------
 516          * Set the Extended Mode register
 517          *-----------------------------------------------------------------*/
 518         mfsdram(SDRAM_MEMODE, val);
 519         mtsdram(SDRAM_MEMODE,
 520                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 521                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 522                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 523                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 524
 525         /*------------------------------------------------------------------
 526          * Program Initialization preload registers.
 527          *-----------------------------------------------------------------*/
 528         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 529                         selected_cas, write_recovery);
 530
 531         /*------------------------------------------------------------------
 532          * Delay to ensure 200usec have elapsed since reset.
 533          *-----------------------------------------------------------------*/
 534         udelay(400);
 535
 536         /*------------------------------------------------------------------
 537          * Set the memory queue core base addr.
 538          *-----------------------------------------------------------------*/
 539         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 540
 541         /*------------------------------------------------------------------
 542          * Program SDRAM controller options 2 register
 543          * Enable the memory controller.
 544          *-----------------------------------------------------------------*/
 545         mfsdram(SDRAM_MCOPT2, val);
 546         mtsdram(SDRAM_MCOPT2,
 547                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 548                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 549                 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
 550
 551         /*------------------------------------------------------------------
 552          * Wait for SDRAM_CFG0_DC_EN to complete.
 553          *-----------------------------------------------------------------*/
 554         do {
 555                 mfsdram(SDRAM_MCSTAT, val);
 556         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 557
 558         /* get installed memory size */
 559         dram_size = sdram_memsize();
 560
 561         /* and program tlb entries for this size (dynamic) */
 562
 563         /*
 564          * Program TLB entries with caches enabled, for best performace
 565          * while auto-calibrating and ECC generation
 566          */
 567         program_tlb(0, 0, dram_size, 0);
 568
 569         /*------------------------------------------------------------------
 570          * DQS calibration.
 571          *-----------------------------------------------------------------*/
 572         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 573
 574 #ifdef CONFIG_DDR_ECC
 575         /*------------------------------------------------------------------
 576          * If ecc is enabled, initialize the parity bits.
 577          *-----------------------------------------------------------------*/
 578         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 579 #endif
 580
 581         /*
 582          * Now after initialization (auto-calibration and ECC generation)
 583          * remove the TLB entries with caches enabled and program again with
 584          * desired cache functionality
 585          */
 586         remove_tlb(0, dram_size);
 587         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 588
 589         ppc440sp_sdram_register_dump();
 590
 591         /*
 592          * Clear potential errors resulting from auto-calibration.
 593          * If not done, then we could get an interrupt later on when
 594          * exceptions are enabled.
 595          */
 596         set_mcsr(get_mcsr());
 597
 598         return dram_size;
 599 }
 600
 601 static void get_spd_info(unsigned long *dimm_populated,
 602                          unsigned char *iic0_dimm_addr,
 603                          unsigned long num_dimm_banks)
 604 {
 605         unsigned long dimm_num;
 606         unsigned long dimm_found;
 607         unsigned char num_of_bytes;
 608         unsigned char total_size;
 609
 610         dimm_found = FALSE;
 611         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 612                 num_of_bytes = 0;
 613                 total_size = 0;
 614
 615                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 616                 debug("\nspd_read(0x%x) returned %d\n",
 617                       iic0_dimm_addr[dimm_num], num_of_bytes);
 618                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 619                 debug("spd_read(0x%x) returned %d\n",
 620                       iic0_dimm_addr[dimm_num], total_size);
 621
 622                 if ((num_of_bytes != 0) && (total_size != 0)) {
 623                         dimm_populated[dimm_num] = TRUE;
 624                         dimm_found = TRUE;
 625                         debug("DIMM slot %lu: populated\n", dimm_num);
 626                 } else {
 627                         dimm_populated[dimm_num] = FALSE;
 628                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 629                 }
 630         }
 631
 632         if (dimm_found == FALSE) {
 633                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 634                 spd_ddr_init_hang ();
 635         }
 636 }
 637
 638 void board_add_ram_info(int use_default)
 639 {
 640         PPC4xx_SYS_INFO board_cfg;
 641         u32 val;
 642
 643         if (is_ecc_enabled())
 644                 puts(" (ECC");
 645         else
 646                 puts(" (ECC not");
 647
 648         get_sys_info(&board_cfg);
 649
 650         mfsdr(SDR0_DDR0, val);
 651         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 652         printf(" enabled, %d MHz", (val * 2) / 1000000);
 653
 654         mfsdram(SDRAM_MMODE, val);
 655         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 656         printf(", CL%d)", val);
 657 }
 658
 659 /*------------------------------------------------------------------
 660  * For the memory DIMMs installed, this routine verifies that they
 661  * really are DDR specific DIMMs.
 662  *-----------------------------------------------------------------*/
 663 static void check_mem_type(unsigned long *dimm_populated,
 664                            unsigned char *iic0_dimm_addr,
 665                            unsigned long num_dimm_banks)
 666 {
 667         unsigned long dimm_num;
 668         unsigned long dimm_type;
 669
 670         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 671                 if (dimm_populated[dimm_num] == TRUE) {
 672                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 673                         switch (dimm_type) {
 674                         case 1:
 675                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 676                                        "slot %d.\n", (unsigned int)dimm_num);
 677                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 678                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 679                                 spd_ddr_init_hang ();
 680                                 break;
 681                         case 2:
 682                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 683                                        (unsigned int)dimm_num);
 684                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 685                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 686                                 spd_ddr_init_hang ();
 687                                 break;
 688                         case 3:
 689                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 690                                        (unsigned int)dimm_num);
 691                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 692                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 693                                 spd_ddr_init_hang ();
 694                                 break;
 695                         case 4:
 696                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 697                                        (unsigned int)dimm_num);
 698                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 699                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 700                                 spd_ddr_init_hang ();
 701                                 break;
 702                         case 5:
 703                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 704                                        (unsigned int)dimm_num);
 705                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 706                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 707                                 spd_ddr_init_hang ();
 708                                 break;
 709                         case 6:
 710                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 711                                        (unsigned int)dimm_num);
 712                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 713                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 714                                 spd_ddr_init_hang ();
 715                                 break;
 716                         case 7:
 717                                 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
 718                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 719                                 break;
 720                         case 8:
 721                                 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
 722                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 723                                 break;
 724                         default:
 725                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 726                                        (unsigned int)dimm_num);
 727                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 728                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 729                                 spd_ddr_init_hang ();
 730                                 break;
 731                         }
 732                 }
 733         }
 734         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 735                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 736                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 737                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 738                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 739                         spd_ddr_init_hang ();
 740                 }
 741         }
 742 }
 743
 744 /*------------------------------------------------------------------
 745  * For the memory DIMMs installed, this routine verifies that
 746  * frequency previously calculated is supported.
 747  *-----------------------------------------------------------------*/
 748 static void check_frequency(unsigned long *dimm_populated,
 749                             unsigned char *iic0_dimm_addr,
 750                             unsigned long num_dimm_banks)
 751 {
 752         unsigned long dimm_num;
 753         unsigned long tcyc_reg;
 754         unsigned long cycle_time;
 755         unsigned long calc_cycle_time;
 756         unsigned long sdram_freq;
 757         unsigned long sdr_ddrpll;
 758         PPC4xx_SYS_INFO board_cfg;
 759
 760         /*------------------------------------------------------------------
 761          * Get the board configuration info.
 762          *-----------------------------------------------------------------*/
 763         get_sys_info(&board_cfg);
 764
 765         mfsdr(SDR0_DDR0, sdr_ddrpll);
 766         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 767
 768         /*
 769          * calc_cycle_time is calculated from DDR frequency set by board/chip
 770          * and is expressed in multiple of 10 picoseconds
 771          * to match the way DIMM cycle time is calculated below.
 772          */
 773         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 774
 775         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 776                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 777                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 778                         /*
 779                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 780                          * the higher order nibble (bits 4-7) designates the cycle time
 781                          * to a granularity of 1ns;
 782                          * the value presented by the lower order nibble (bits 0-3)
 783                          * has a granularity of .1ns and is added to the value designated
 784                          * by the higher nibble. In addition, four lines of the lower order
 785                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 786                          */
 787                          /* Convert from hex to decimal */
 788                         if ((tcyc_reg & 0x0F) == 0x0D)
 789                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 790                         else if ((tcyc_reg & 0x0F) == 0x0C)
 791                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 792                         else if ((tcyc_reg & 0x0F) == 0x0B)
 793                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 794                         else if ((tcyc_reg & 0x0F) == 0x0A)
 795                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 796                         else
 797                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 798                                         ((tcyc_reg & 0x0F)*10);
 799                         debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
 800
 801                         if  (cycle_time > (calc_cycle_time + 10)) {
 802                                 /*
 803                                  * the provided sdram cycle_time is too small
 804                                  * for the available DIMM cycle_time.
 805                                  * The additionnal 100ps is here to accept a small incertainty.
 806                                  */
 807                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 808                                        "slot %d \n while calculated cycle time is %d ps.\n",
 809                                        (unsigned int)(cycle_time*10),
 810                                        (unsigned int)dimm_num,
 811                                        (unsigned int)(calc_cycle_time*10));
 812                                 printf("Replace the DIMM, or change DDR frequency via "
 813                                        "strapping bits.\n\n");
 814                                 spd_ddr_init_hang ();
 815                         }
 816                 }
 817         }
 818 }
 819
 820 /*------------------------------------------------------------------
 821  * For the memory DIMMs installed, this routine verifies two
 822  * ranks/banks maximum are availables.
 823  *-----------------------------------------------------------------*/
 824 static void check_rank_number(unsigned long *dimm_populated,
 825                               unsigned char *iic0_dimm_addr,
 826                               unsigned long num_dimm_banks)
 827 {
 828         unsigned long dimm_num;
 829         unsigned long dimm_rank;
 830         unsigned long total_rank = 0;
 831
 832         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 833                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 834                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 835                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 836                                 dimm_rank = (dimm_rank & 0x0F) +1;
 837                         else
 838                                 dimm_rank = dimm_rank & 0x0F;
 839
 840
 841                         if (dimm_rank > MAXRANKS) {
 842                                 printf("ERROR: DRAM DIMM detected with %d ranks in "
 843                                        "slot %d is not supported.\n", dimm_rank, dimm_num);
 844                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 845                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 846                                 spd_ddr_init_hang ();
 847                         } else
 848                                 total_rank += dimm_rank;
 849                 }
 850                 if (total_rank > MAXRANKS) {
 851                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 852                                "for all slots.\n", (unsigned int)total_rank);
 853                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 854                         printf("Remove one of the DIMM modules.\n\n");
 855                         spd_ddr_init_hang ();
 856                 }
 857         }
 858 }
 859
 860 /*------------------------------------------------------------------
 861  * only support 2.5V modules.
 862  * This routine verifies this.
 863  *-----------------------------------------------------------------*/
 864 static void check_voltage_type(unsigned long *dimm_populated,
 865                                unsigned char *iic0_dimm_addr,
 866                                unsigned long num_dimm_banks)
 867 {
 868         unsigned long dimm_num;
 869         unsigned long voltage_type;
 870
 871         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 872                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 873                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 874                         switch (voltage_type) {
 875                         case 0x00:
 876                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 877                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 878                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 879                                        (unsigned int)dimm_num);
 880                                 spd_ddr_init_hang ();
 881                                 break;
 882                         case 0x01:
 883                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 884                                 printf("This DIMM is LVTTL.\n");
 885                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 886                                        (unsigned int)dimm_num);
 887                                 spd_ddr_init_hang ();
 888                                 break;
 889                         case 0x02:
 890                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 891                                 printf("This DIMM is 1.5 Volt.\n");
 892                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 893                                        (unsigned int)dimm_num);
 894                                 spd_ddr_init_hang ();
 895                                 break;
 896                         case 0x03:
 897                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 898                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 899                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 900                                        (unsigned int)dimm_num);
 901                                 spd_ddr_init_hang ();
 902                                 break;
 903                         case 0x04:
 904                                 /* 2.5 Voltage only for DDR1 */
 905                                 break;
 906                         case 0x05:
 907                                 /* 1.8 Voltage only for DDR2 */
 908                                 break;
 909                         default:
 910                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 911                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 912                                        (unsigned int)dimm_num);
 913                                 spd_ddr_init_hang ();
 914                                 break;
 915                         }
 916                 }
 917         }
 918 }
 919
 920 /*-----------------------------------------------------------------------------+
 921  * program_copt1.
 922  *-----------------------------------------------------------------------------*/
 923 static void program_copt1(unsigned long *dimm_populated,
 924                           unsigned char *iic0_dimm_addr,
 925                           unsigned long num_dimm_banks)
 926 {
 927         unsigned long dimm_num;
 928         unsigned long mcopt1;
 929         unsigned long ecc_enabled;
 930         unsigned long ecc = 0;
 931         unsigned long data_width = 0;
 932         unsigned long dimm_32bit;
 933         unsigned long dimm_64bit;
 934         unsigned long registered = 0;
 935         unsigned long attribute = 0;
 936         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 937         unsigned long bankcount;
 938         unsigned long ddrtype;
 939         unsigned long val;
 940
 941 #ifdef CONFIG_DDR_ECC
 942         ecc_enabled = TRUE;
 943 #else
 944         ecc_enabled = FALSE;
 945 #endif
 946         dimm_32bit = FALSE;
 947         dimm_64bit = FALSE;
 948         buf0 = FALSE;
 949         buf1 = FALSE;
 950
 951         /*------------------------------------------------------------------
 952          * Set memory controller options reg 1, SDRAM_MCOPT1.
 953          *-----------------------------------------------------------------*/
 954         mfsdram(SDRAM_MCOPT1, val);
 955         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 956                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 957                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 958                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 959                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
 960                          SDRAM_MCOPT1_DREF_MASK);
 961
 962         mcopt1 |= SDRAM_MCOPT1_QDEP;
 963         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
 964         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
 965         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
 966         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
 967         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
 968
 969         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 970                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 971                         /* test ecc support */
 972                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 973                         if (ecc != 0x02) /* ecc not supported */
 974                                 ecc_enabled = FALSE;
 975
 976                         /* test bank count */
 977                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
 978                         if (bankcount == 0x04) /* bank count = 4 */
 979                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
 980                         else /* bank count = 8 */
 981                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
 982
 983                         /* test DDR type */
 984                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
 985                         /* test for buffered/unbuffered, registered, differential clocks */
 986                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
 987                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
 988
 989                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 990                         if (dimm_num == 0) {
 991                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
 992                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
 993                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
 994                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
 995                                 if (registered == 1) { /* DDR2 always buffered */
 996                                         /* TODO: what about above  comments ? */
 997                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
 998                                         buf0 = TRUE;
 999                                 } else {
1000                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1001                                         if ((attribute & 0x02) == 0x00) {
1002                                                 /* buffered not supported */
1003                                                 buf0 = FALSE;
1004                                         } else {
1005                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1006                                                 buf0 = TRUE;
1007                                         }
1008                                 }
1009                         }
1010                         else if (dimm_num == 1) {
1011                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1012                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1013                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1014                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1015                                 if (registered == 1) {
1016                                         /* DDR2 always buffered */
1017                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1018                                         buf1 = TRUE;
1019                                 } else {
1020                                         if ((attribute & 0x02) == 0x00) {
1021                                                 /* buffered not supported */
1022                                                 buf1 = FALSE;
1023                                         } else {
1024                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1025                                                 buf1 = TRUE;
1026                                         }
1027                                 }
1028                         }
1029
1030                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1031                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1032                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1033
1034                         switch (data_width) {
1035                         case 72:
1036                         case 64:
1037                                 dimm_64bit = TRUE;
1038                                 break;
1039                         case 40:
1040                         case 32:
1041                                 dimm_32bit = TRUE;
1042                                 break;
1043                         default:
1044                                 printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
1045                                        data_width);
1046                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1047                                 break;
1048                         }
1049                 }
1050         }
1051
1052         /* verify matching properties */
1053         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1054                 if (buf0 != buf1) {
1055                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1056                         spd_ddr_init_hang ();
1057                 }
1058         }
1059
1060         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1061                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1062                 spd_ddr_init_hang ();
1063         }
1064         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1065                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1066         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1067                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1068         } else {
1069                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1070                 spd_ddr_init_hang ();
1071         }
1072
1073         if (ecc_enabled == TRUE)
1074                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1075         else
1076                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1077
1078         mtsdram(SDRAM_MCOPT1, mcopt1);
1079 }
1080
1081 /*-----------------------------------------------------------------------------+
1082  * program_codt.
1083  *-----------------------------------------------------------------------------*/
1084 static void program_codt(unsigned long *dimm_populated,
1085                          unsigned char *iic0_dimm_addr,
1086                          unsigned long num_dimm_banks)
1087 {
1088         unsigned long codt;
1089         unsigned long modt0 = 0;
1090         unsigned long modt1 = 0;
1091         unsigned long modt2 = 0;
1092         unsigned long modt3 = 0;
1093         unsigned char dimm_num;
1094         unsigned char dimm_rank;
1095         unsigned char total_rank = 0;
1096         unsigned char total_dimm = 0;
1097         unsigned char dimm_type = 0;
1098         unsigned char firstSlot = 0;
1099
1100         /*------------------------------------------------------------------
1101          * Set the SDRAM Controller On Die Termination Register
1102          *-----------------------------------------------------------------*/
1103         mfsdram(SDRAM_CODT, codt);
1104         codt |= (SDRAM_CODT_IO_NMODE
1105                  & (~SDRAM_CODT_DQS_SINGLE_END
1106                     & ~SDRAM_CODT_CKSE_SINGLE_END
1107                     & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1108                     & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1109
1110         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1111                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1112                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1113                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1114                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1115                                 dimm_type = SDRAM_DDR2;
1116                         } else {
1117                                 dimm_rank = dimm_rank & 0x0F;
1118                                 dimm_type = SDRAM_DDR1;
1119                         }
1120
1121                         total_rank += dimm_rank;
1122                         total_dimm++;
1123                         if ((dimm_num == 0) && (total_dimm == 1))
1124                                 firstSlot = TRUE;
1125                         else
1126                                 firstSlot = FALSE;
1127                 }
1128         }
1129         if (dimm_type == SDRAM_DDR2) {
1130                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1131                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1132                         if (total_rank == 1) {
1133                                 codt |= CALC_ODT_R(0);
1134                                 modt0 = CALC_ODT_W(0);
1135                                 modt1 = 0x00000000;
1136                                 modt2 = 0x00000000;
1137                                 modt3 = 0x00000000;
1138                         }
1139                         if (total_rank == 2) {
1140                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1141                                 modt0 = CALC_ODT_W(0);
1142                                 modt1 = CALC_ODT_W(0);
1143                                 modt2 = 0x00000000;
1144                                 modt3 = 0x00000000;
1145                         }
1146                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1147                         if (total_rank == 1) {
1148                                 codt |= CALC_ODT_R(2);
1149                                 modt0 = 0x00000000;
1150                                 modt1 = 0x00000000;
1151                                 modt2 = CALC_ODT_W(2);
1152                                 modt3 = 0x00000000;
1153                         }
1154                         if (total_rank == 2) {
1155                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1156                                 modt0 = 0x00000000;
1157                                 modt1 = 0x00000000;
1158                                 modt2 = CALC_ODT_W(2);
1159                                 modt3 = CALC_ODT_W(2);
1160                         }
1161                 }
1162                 if (total_dimm == 2) {
1163                         if (total_rank == 2) {
1164                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1165                                 modt0 = CALC_ODT_RW(2);
1166                                 modt1 = 0x00000000;
1167                                 modt2 = CALC_ODT_RW(0);
1168                                 modt3 = 0x00000000;
1169                         }
1170                         if (total_rank == 4) {
1171                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1172                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1173                                 modt0 = CALC_ODT_RW(2);
1174                                 modt1 = 0x00000000;
1175                                 modt2 = CALC_ODT_RW(0);
1176                                 modt3 = 0x00000000;
1177                         }
1178                 }
1179         } else {
1180                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1181                 modt0 = 0x00000000;
1182                 modt1 = 0x00000000;
1183                 modt2 = 0x00000000;
1184                 modt3 = 0x00000000;
1185
1186                 if (total_dimm == 1) {
1187                         if (total_rank == 1)
1188                                 codt |= 0x00800000;
1189                         if (total_rank == 2)
1190                                 codt |= 0x02800000;
1191                 }
1192                 if (total_dimm == 2) {
1193                         if (total_rank == 2)
1194                                 codt |= 0x08800000;
1195                         if (total_rank == 4)
1196                                 codt |= 0x2a800000;
1197                 }
1198         }
1199
1200         debug("nb of dimm %d\n", total_dimm);
1201         debug("nb of rank %d\n", total_rank);
1202         if (total_dimm == 1)
1203                 debug("dimm in slot %d\n", firstSlot);
1204
1205         mtsdram(SDRAM_CODT, codt);
1206         mtsdram(SDRAM_MODT0, modt0);
1207         mtsdram(SDRAM_MODT1, modt1);
1208         mtsdram(SDRAM_MODT2, modt2);
1209         mtsdram(SDRAM_MODT3, modt3);
1210 }
1211
1212 /*-----------------------------------------------------------------------------+
1213  * program_initplr.
1214  *-----------------------------------------------------------------------------*/
1215 static void program_initplr(unsigned long *dimm_populated,
1216                             unsigned char *iic0_dimm_addr,
1217                             unsigned long num_dimm_banks,
1218                             ddr_cas_id_t selected_cas,
1219                             int write_recovery)
1220 {
1221         u32 cas = 0;
1222         u32 odt = 0;
1223         u32 ods = 0;
1224         u32 mr;
1225         u32 wr;
1226         u32 emr;
1227         u32 emr2;
1228         u32 emr3;
1229         int dimm_num;
1230         int total_dimm = 0;
1231
1232         /******************************************************
1233          ** Assumption: if more than one DIMM, all DIMMs are the same
1234          **             as already checked in check_memory_type
1235          ******************************************************/
1236
1237         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1238                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1239                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1240                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1241                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1242                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1243                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1244                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1245                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1246         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1247                 switch (selected_cas) {
1248                 case DDR_CAS_3:
1249                         cas = 3 << 4;
1250                         break;
1251                 case DDR_CAS_4:
1252                         cas = 4 << 4;
1253                         break;
1254                 case DDR_CAS_5:
1255                         cas = 5 << 4;
1256                         break;
1257                 default:
1258                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1259                         spd_ddr_init_hang ();
1260                         break;
1261                 }
1262
1263 #if 0
1264                 /*
1265                  * ToDo - Still a problem with the write recovery:
1266                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1267                  * in the INITPLR reg to the value calculated in program_mode()
1268                  * results in not correctly working DDR2 memory (crash after
1269                  * relocation).
1270                  *
1271                  * So for now, set the write recovery to 3. This seems to work
1272                  * on the Corair module too.
1273                  *
1274                  * 2007-03-01, sr
1275                  */
1276                 switch (write_recovery) {
1277                 case 3:
1278                         wr = WRITE_RECOV_3;
1279                         break;
1280                 case 4:
1281                         wr = WRITE_RECOV_4;
1282                         break;
1283                 case 5:
1284                         wr = WRITE_RECOV_5;
1285                         break;
1286                 case 6:
1287                         wr = WRITE_RECOV_6;
1288                         break;
1289                 default:
1290                         printf("ERROR: write recovery not support (%d)", write_recovery);
1291                         spd_ddr_init_hang ();
1292                         break;
1293                 }
1294 #else
1295                 wr = WRITE_RECOV_3; /* test-only, see description above */
1296 #endif
1297
1298                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1299                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1300                                 total_dimm++;
1301                 if (total_dimm == 1) {
1302                         odt = ODT_150_OHM;
1303                         ods = ODS_FULL;
1304                 } else if (total_dimm == 2) {
1305                         odt = ODT_75_OHM;
1306                         ods = ODS_REDUCED;
1307                 } else {
1308                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1309                         spd_ddr_init_hang ();
1310                 }
1311
1312                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1313                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1314                 emr2 = CMD_EMR | SELECT_EMR2;
1315                 emr3 = CMD_EMR | SELECT_EMR3;
1316                 mtsdram(SDRAM_INITPLR0,  0xB5000000 | CMD_NOP);         /* NOP */
1317                 udelay(1000);
1318                 mtsdram(SDRAM_INITPLR1,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1319                 mtsdram(SDRAM_INITPLR2,  0x80800000 | emr2);            /* EMR2 */
1320                 mtsdram(SDRAM_INITPLR3,  0x80800000 | emr3);            /* EMR3 */
1321                 mtsdram(SDRAM_INITPLR4,  0x80800000 | emr);             /* EMR DLL ENABLE */
1322                 mtsdram(SDRAM_INITPLR5,  0x80800000 | mr | DLL_RESET);  /* MR w/ DLL reset */
1323                 udelay(1000);
1324                 mtsdram(SDRAM_INITPLR6,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1325                 mtsdram(SDRAM_INITPLR7,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1326                 mtsdram(SDRAM_INITPLR8,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1327                 mtsdram(SDRAM_INITPLR9,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1328                 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1329                 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr);              /* MR w/o DLL reset */
1330                 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr);             /* EMR OCD Default */
1331                 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr);             /* EMR OCD Exit */
1332         } else {
1333                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1334                 spd_ddr_init_hang ();
1335         }
1336 }
1337
1338 /*------------------------------------------------------------------
1339  * This routine programs the SDRAM_MMODE register.
1340  * the selected_cas is an output parameter, that will be passed
1341  * by caller to call the above program_initplr( )
1342  *-----------------------------------------------------------------*/
1343 static void program_mode(unsigned long *dimm_populated,
1344                          unsigned char *iic0_dimm_addr,
1345                          unsigned long num_dimm_banks,
1346                          ddr_cas_id_t *selected_cas,
1347                          int *write_recovery)
1348 {
1349         unsigned long dimm_num;
1350         unsigned long sdram_ddr1;
1351         unsigned long t_wr_ns;
1352         unsigned long t_wr_clk;
1353         unsigned long cas_bit;
1354         unsigned long cas_index;
1355         unsigned long sdram_freq;
1356         unsigned long ddr_check;
1357         unsigned long mmode;
1358         unsigned long tcyc_reg;
1359         unsigned long cycle_2_0_clk;
1360         unsigned long cycle_2_5_clk;
1361         unsigned long cycle_3_0_clk;
1362         unsigned long cycle_4_0_clk;
1363         unsigned long cycle_5_0_clk;
1364         unsigned long max_2_0_tcyc_ns_x_100;
1365         unsigned long max_2_5_tcyc_ns_x_100;
1366         unsigned long max_3_0_tcyc_ns_x_100;
1367         unsigned long max_4_0_tcyc_ns_x_100;
1368         unsigned long max_5_0_tcyc_ns_x_100;
1369         unsigned long cycle_time_ns_x_100[3];
1370         PPC4xx_SYS_INFO board_cfg;
1371         unsigned char cas_2_0_available;
1372         unsigned char cas_2_5_available;
1373         unsigned char cas_3_0_available;
1374         unsigned char cas_4_0_available;
1375         unsigned char cas_5_0_available;
1376         unsigned long sdr_ddrpll;
1377
1378         /*------------------------------------------------------------------
1379          * Get the board configuration info.
1380          *-----------------------------------------------------------------*/
1381         get_sys_info(&board_cfg);
1382
1383         mfsdr(SDR0_DDR0, sdr_ddrpll);
1384         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1385         debug("sdram_freq=%d\n", sdram_freq);
1386
1387         /*------------------------------------------------------------------
1388          * Handle the timing.  We need to find the worst case timing of all
1389          * the dimm modules installed.
1390          *-----------------------------------------------------------------*/
1391         t_wr_ns = 0;
1392         cas_2_0_available = TRUE;
1393         cas_2_5_available = TRUE;
1394         cas_3_0_available = TRUE;
1395         cas_4_0_available = TRUE;
1396         cas_5_0_available = TRUE;
1397         max_2_0_tcyc_ns_x_100 = 10;
1398         max_2_5_tcyc_ns_x_100 = 10;
1399         max_3_0_tcyc_ns_x_100 = 10;
1400         max_4_0_tcyc_ns_x_100 = 10;
1401         max_5_0_tcyc_ns_x_100 = 10;
1402         sdram_ddr1 = TRUE;
1403
1404         /* loop through all the DIMM slots on the board */
1405         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1406                 /* If a dimm is installed in a particular slot ... */
1407                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1408                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1409                                 sdram_ddr1 = TRUE;
1410                         else
1411                                 sdram_ddr1 = FALSE;
1412
1413                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1414                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1415                         debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1416
1417                         /* For a particular DIMM, grab the three CAS values it supports */
1418                         for (cas_index = 0; cas_index < 3; cas_index++) {
1419                                 switch (cas_index) {
1420                                 case 0:
1421                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1422                                         break;
1423                                 case 1:
1424                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1425                                         break;
1426                                 default:
1427                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1428                                         break;
1429                                 }
1430
1431                                 if ((tcyc_reg & 0x0F) >= 10) {
1432                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1433                                                 /* Convert from hex to decimal */
1434                                                 cycle_time_ns_x_100[cas_index] =
1435                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1436                                         } else {
1437                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1438                                                        "in slot %d\n", (unsigned int)dimm_num);
1439                                                 spd_ddr_init_hang ();
1440                                         }
1441                                 } else {
1442                                         /* Convert from hex to decimal */
1443                                         cycle_time_ns_x_100[cas_index] =
1444                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1445                                                 ((tcyc_reg & 0x0F)*10);
1446                                 }
1447                                 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1448                                       cycle_time_ns_x_100[cas_index]);
1449                         }
1450
1451                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1452                         /* supported for a particular DIMM. */
1453                         cas_index = 0;
1454
1455                         if (sdram_ddr1) {
1456                                 /*
1457                                  * DDR devices use the following bitmask for CAS latency:
1458                                  *  Bit   7    6    5    4    3    2    1    0
1459                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1460                                  */
1461                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1462                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1463                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1464                                                                     cycle_time_ns_x_100[cas_index]);
1465                                         cas_index++;
1466                                 } else {
1467                                         if (cas_index != 0)
1468                                                 cas_index++;
1469                                         cas_4_0_available = FALSE;
1470                                 }
1471
1472                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1473                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1474                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1475                                                                     cycle_time_ns_x_100[cas_index]);
1476                                         cas_index++;
1477                                 } else {
1478                                         if (cas_index != 0)
1479                                                 cas_index++;
1480                                         cas_3_0_available = FALSE;
1481                                 }
1482
1483                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1484                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1485                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1486                                                                     cycle_time_ns_x_100[cas_index]);
1487                                         cas_index++;
1488                                 } else {
1489                                         if (cas_index != 0)
1490                                                 cas_index++;
1491                                         cas_2_5_available = FALSE;
1492                                 }
1493
1494                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1495                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1496                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1497                                                                     cycle_time_ns_x_100[cas_index]);
1498                                         cas_index++;
1499                                 } else {
1500                                         if (cas_index != 0)
1501                                                 cas_index++;
1502                                         cas_2_0_available = FALSE;
1503                                 }
1504                         } else {
1505                                 /*
1506                                  * DDR2 devices use the following bitmask for CAS latency:
1507                                  *  Bit   7    6    5    4    3    2    1    0
1508                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1509                                  */
1510                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1511                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1512                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1513                                                                     cycle_time_ns_x_100[cas_index]);
1514                                         cas_index++;
1515                                 } else {
1516                                         if (cas_index != 0)
1517                                                 cas_index++;
1518                                         cas_5_0_available = FALSE;
1519                                 }
1520
1521                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1522                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1523                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1524                                                                     cycle_time_ns_x_100[cas_index]);
1525                                         cas_index++;
1526                                 } else {
1527                                         if (cas_index != 0)
1528                                                 cas_index++;
1529                                         cas_4_0_available = FALSE;
1530                                 }
1531
1532                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1533                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1534                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1535                                                                     cycle_time_ns_x_100[cas_index]);
1536                                         cas_index++;
1537                                 } else {
1538                                         if (cas_index != 0)
1539                                                 cas_index++;
1540                                         cas_3_0_available = FALSE;
1541                                 }
1542                         }
1543                 }
1544         }
1545
1546         /*------------------------------------------------------------------
1547          * Set the SDRAM mode, SDRAM_MMODE
1548          *-----------------------------------------------------------------*/
1549         mfsdram(SDRAM_MMODE, mmode);
1550         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1551
1552         /* add 10 here because of rounding problems */
1553         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1554         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1555         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1556         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1557         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1558         debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1559         debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1560         debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1561
1562         if (sdram_ddr1 == TRUE) { /* DDR1 */
1563                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1564                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1565                         *selected_cas = DDR_CAS_2;
1566                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1567                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1568                         *selected_cas = DDR_CAS_2_5;
1569                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1570                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1571                         *selected_cas = DDR_CAS_3;
1572                 } else {
1573                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1574                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1575                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1576                         spd_ddr_init_hang ();
1577                 }
1578         } else { /* DDR2 */
1579                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1580                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1581                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1582                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1583                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1584                         *selected_cas = DDR_CAS_3;
1585                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1586                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1587                         *selected_cas = DDR_CAS_4;
1588                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1589                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1590                         *selected_cas = DDR_CAS_5;
1591                 } else {
1592                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1593                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1594                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1595                         printf("cas3=%d cas4=%d cas5=%d\n",
1596                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1597                         printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
1598                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1599                         spd_ddr_init_hang ();
1600                 }
1601         }
1602
1603         if (sdram_ddr1 == TRUE)
1604                 mmode |= SDRAM_MMODE_WR_DDR1;
1605         else {
1606
1607                 /* loop through all the DIMM slots on the board */
1608                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1609                         /* If a dimm is installed in a particular slot ... */
1610                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1611                                 t_wr_ns = max(t_wr_ns,
1612                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1613                 }
1614
1615                 /*
1616                  * convert from nanoseconds to ddr clocks
1617                  * round up if necessary
1618                  */
1619                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1620                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1621                 if (sdram_freq != ddr_check)
1622                         t_wr_clk++;
1623
1624                 switch (t_wr_clk) {
1625                 case 0:
1626                 case 1:
1627                 case 2:
1628                 case 3:
1629                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1630                         break;
1631                 case 4:
1632                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1633                         break;
1634                 case 5:
1635                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1636                         break;
1637                 default:
1638                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1639                         break;
1640                 }
1641                 *write_recovery = t_wr_clk;
1642         }
1643
1644         debug("CAS latency = %d\n", *selected_cas);
1645         debug("Write recovery = %d\n", *write_recovery);
1646
1647         mtsdram(SDRAM_MMODE, mmode);
1648 }
1649
1650 /*-----------------------------------------------------------------------------+
1651  * program_rtr.
1652  *-----------------------------------------------------------------------------*/
1653 static void program_rtr(unsigned long *dimm_populated,
1654                         unsigned char *iic0_dimm_addr,
1655                         unsigned long num_dimm_banks)
1656 {
1657         PPC4xx_SYS_INFO board_cfg;
1658         unsigned long max_refresh_rate;
1659         unsigned long dimm_num;
1660         unsigned long refresh_rate_type;
1661         unsigned long refresh_rate;
1662         unsigned long rint;
1663         unsigned long sdram_freq;
1664         unsigned long sdr_ddrpll;
1665         unsigned long val;
1666
1667         /*------------------------------------------------------------------
1668          * Get the board configuration info.
1669          *-----------------------------------------------------------------*/
1670         get_sys_info(&board_cfg);
1671
1672         /*------------------------------------------------------------------
1673          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1674          *-----------------------------------------------------------------*/
1675         mfsdr(SDR0_DDR0, sdr_ddrpll);
1676         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1677
1678         max_refresh_rate = 0;
1679         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1680                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1681
1682                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1683                         refresh_rate_type &= 0x7F;
1684                         switch (refresh_rate_type) {
1685                         case 0:
1686                                 refresh_rate =  15625;
1687                                 break;
1688                         case 1:
1689                                 refresh_rate =   3906;
1690                                 break;
1691                         case 2:
1692                                 refresh_rate =   7812;
1693                                 break;
1694                         case 3:
1695                                 refresh_rate =  31250;
1696                                 break;
1697                         case 4:
1698                                 refresh_rate =  62500;
1699                                 break;
1700                         case 5:
1701                                 refresh_rate = 125000;
1702                                 break;
1703                         default:
1704                                 refresh_rate = 0;
1705                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1706                                        (unsigned int)dimm_num);
1707                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1708                                 spd_ddr_init_hang ();
1709                                 break;
1710                         }
1711
1712                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1713                 }
1714         }
1715
1716         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1717         mfsdram(SDRAM_RTR, val);
1718         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1719                 (SDRAM_RTR_RINT_ENCODE(rint)));
1720 }
1721
1722 /*------------------------------------------------------------------
1723  * This routine programs the SDRAM_TRx registers.
1724  *-----------------------------------------------------------------*/
1725 static void program_tr(unsigned long *dimm_populated,
1726                        unsigned char *iic0_dimm_addr,
1727                        unsigned long num_dimm_banks)
1728 {
1729         unsigned long dimm_num;
1730         unsigned long sdram_ddr1;
1731         unsigned long t_rp_ns;
1732         unsigned long t_rcd_ns;
1733         unsigned long t_rrd_ns;
1734         unsigned long t_ras_ns;
1735         unsigned long t_rc_ns;
1736         unsigned long t_rfc_ns;
1737         unsigned long t_wpc_ns;
1738         unsigned long t_wtr_ns;
1739         unsigned long t_rpc_ns;
1740         unsigned long t_rp_clk;
1741         unsigned long t_rcd_clk;
1742         unsigned long t_rrd_clk;
1743         unsigned long t_ras_clk;
1744         unsigned long t_rc_clk;
1745         unsigned long t_rfc_clk;
1746         unsigned long t_wpc_clk;
1747         unsigned long t_wtr_clk;
1748         unsigned long t_rpc_clk;
1749         unsigned long sdtr1, sdtr2, sdtr3;
1750         unsigned long ddr_check;
1751         unsigned long sdram_freq;
1752         unsigned long sdr_ddrpll;
1753
1754         PPC4xx_SYS_INFO board_cfg;
1755
1756         /*------------------------------------------------------------------
1757          * Get the board configuration info.
1758          *-----------------------------------------------------------------*/
1759         get_sys_info(&board_cfg);
1760
1761         mfsdr(SDR0_DDR0, sdr_ddrpll);
1762         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1763
1764         /*------------------------------------------------------------------
1765          * Handle the timing.  We need to find the worst case timing of all
1766          * the dimm modules installed.
1767          *-----------------------------------------------------------------*/
1768         t_rp_ns = 0;
1769         t_rrd_ns = 0;
1770         t_rcd_ns = 0;
1771         t_ras_ns = 0;
1772         t_rc_ns = 0;
1773         t_rfc_ns = 0;
1774         t_wpc_ns = 0;
1775         t_wtr_ns = 0;
1776         t_rpc_ns = 0;
1777         sdram_ddr1 = TRUE;
1778
1779         /* loop through all the DIMM slots on the board */
1780         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1781                 /* If a dimm is installed in a particular slot ... */
1782                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1783                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1784                                 sdram_ddr1 = TRUE;
1785                         else
1786                                 sdram_ddr1 = FALSE;
1787
1788                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1789                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1790                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1791                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1792                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1793                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1794                 }
1795         }
1796
1797         /*------------------------------------------------------------------
1798          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1799          *-----------------------------------------------------------------*/
1800         mfsdram(SDRAM_SDTR1, sdtr1);
1801         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1802                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1803
1804         /* default values */
1805         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1806         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1807
1808         /* normal operations */
1809         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1810         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1811
1812         mtsdram(SDRAM_SDTR1, sdtr1);
1813
1814         /*------------------------------------------------------------------
1815          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1816          *-----------------------------------------------------------------*/
1817         mfsdram(SDRAM_SDTR2, sdtr2);
1818         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1819                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1820                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1821                    SDRAM_SDTR2_RRD_MASK);
1822
1823         /*
1824          * convert t_rcd from nanoseconds to ddr clocks
1825          * round up if necessary
1826          */
1827         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1828         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1829         if (sdram_freq != ddr_check)
1830                 t_rcd_clk++;
1831
1832         switch (t_rcd_clk) {
1833         case 0:
1834         case 1:
1835                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1836                 break;
1837         case 2:
1838                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1839                 break;
1840         case 3:
1841                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1842                 break;
1843         case 4:
1844                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1845                 break;
1846         default:
1847                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1848                 break;
1849         }
1850
1851         if (sdram_ddr1 == TRUE) { /* DDR1 */
1852                 if (sdram_freq < 200000000) {
1853                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1854                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1855                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1856                 } else {
1857                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1858                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1859                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1860                 }
1861         } else { /* DDR2 */
1862                 /* loop through all the DIMM slots on the board */
1863                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1864                         /* If a dimm is installed in a particular slot ... */
1865                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1866                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1867                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1868                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1869                         }
1870                 }
1871
1872                 /*
1873                  * convert from nanoseconds to ddr clocks
1874                  * round up if necessary
1875                  */
1876                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1877                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1878                 if (sdram_freq != ddr_check)
1879                         t_wpc_clk++;
1880
1881                 switch (t_wpc_clk) {
1882                 case 0:
1883                 case 1:
1884                 case 2:
1885                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1886                         break;
1887                 case 3:
1888                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1889                         break;
1890                 case 4:
1891                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1892                         break;
1893                 case 5:
1894                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1895                         break;
1896                 default:
1897                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1898                         break;
1899                 }
1900
1901                 /*
1902                  * convert from nanoseconds to ddr clocks
1903                  * round up if necessary
1904                  */
1905                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1906                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1907                 if (sdram_freq != ddr_check)
1908                         t_wtr_clk++;
1909
1910                 switch (t_wtr_clk) {
1911                 case 0:
1912                 case 1:
1913                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1914                         break;
1915                 case 2:
1916                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1917                         break;
1918                 case 3:
1919                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1920                         break;
1921                 default:
1922                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1923                         break;
1924                 }
1925
1926                 /*
1927                  * convert from nanoseconds to ddr clocks
1928                  * round up if necessary
1929                  */
1930                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1931                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1932                 if (sdram_freq != ddr_check)
1933                         t_rpc_clk++;
1934
1935                 switch (t_rpc_clk) {
1936                 case 0:
1937                 case 1:
1938                 case 2:
1939                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1940                         break;
1941                 case 3:
1942                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1943                         break;
1944                 default:
1945                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1946                         break;
1947                 }
1948         }
1949
1950         /* default value */
1951         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1952
1953         /*
1954          * convert t_rrd from nanoseconds to ddr clocks
1955          * round up if necessary
1956          */
1957         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1958         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1959         if (sdram_freq != ddr_check)
1960                 t_rrd_clk++;
1961
1962         if (t_rrd_clk == 3)
1963                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1964         else
1965                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1966
1967         /*
1968          * convert t_rp from nanoseconds to ddr clocks
1969          * round up if necessary
1970          */
1971         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1972         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1973         if (sdram_freq != ddr_check)
1974                 t_rp_clk++;
1975
1976         switch (t_rp_clk) {
1977         case 0:
1978         case 1:
1979         case 2:
1980         case 3:
1981                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
1982                 break;
1983         case 4:
1984                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
1985                 break;
1986         case 5:
1987                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
1988                 break;
1989         case 6:
1990                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
1991                 break;
1992         default:
1993                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
1994                 break;
1995         }
1996
1997         mtsdram(SDRAM_SDTR2, sdtr2);
1998
1999         /*------------------------------------------------------------------
2000          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2001          *-----------------------------------------------------------------*/
2002         mfsdram(SDRAM_SDTR3, sdtr3);
2003         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2004                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2005
2006         /*
2007          * convert t_ras from nanoseconds to ddr clocks
2008          * round up if necessary
2009          */
2010         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2011         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2012         if (sdram_freq != ddr_check)
2013                 t_ras_clk++;
2014
2015         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2016
2017         /*
2018          * convert t_rc from nanoseconds to ddr clocks
2019          * round up if necessary
2020          */
2021         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2022         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2023         if (sdram_freq != ddr_check)
2024                 t_rc_clk++;
2025
2026         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2027
2028         /* default xcs value */
2029         sdtr3 |= SDRAM_SDTR3_XCS;
2030
2031         /*
2032          * convert t_rfc from nanoseconds to ddr clocks
2033          * round up if necessary
2034          */
2035         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2036         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2037         if (sdram_freq != ddr_check)
2038                 t_rfc_clk++;
2039
2040         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2041
2042         mtsdram(SDRAM_SDTR3, sdtr3);
2043 }
2044
2045 /*-----------------------------------------------------------------------------+
2046  * program_bxcf.
2047  *-----------------------------------------------------------------------------*/
2048 static void program_bxcf(unsigned long *dimm_populated,
2049                          unsigned char *iic0_dimm_addr,
2050                          unsigned long num_dimm_banks)
2051 {
2052         unsigned long dimm_num;
2053         unsigned long num_col_addr;
2054         unsigned long num_ranks;
2055         unsigned long num_banks;
2056         unsigned long mode;
2057         unsigned long ind_rank;
2058         unsigned long ind;
2059         unsigned long ind_bank;
2060         unsigned long bank_0_populated;
2061
2062         /*------------------------------------------------------------------
2063          * Set the BxCF regs.  First, wipe out the bank config registers.
2064          *-----------------------------------------------------------------*/
2065         mtsdram(SDRAM_MB0CF, 0x00000000);
2066         mtsdram(SDRAM_MB1CF, 0x00000000);
2067         mtsdram(SDRAM_MB2CF, 0x00000000);
2068         mtsdram(SDRAM_MB3CF, 0x00000000);
2069
2070         mode = SDRAM_BXCF_M_BE_ENABLE;
2071
2072         bank_0_populated = 0;
2073
2074         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2075                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2076                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2077                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2078                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2079                                 num_ranks = (num_ranks & 0x0F) +1;
2080                         else
2081                                 num_ranks = num_ranks & 0x0F;
2082
2083                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2084
2085                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2086                                 if (num_banks == 4)
2087                                         ind = 0;
2088                                 else
2089                                         ind = 5 << 8;
2090                                 switch (num_col_addr) {
2091                                 case 0x08:
2092                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2093                                         break;
2094                                 case 0x09:
2095                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2096                                         break;
2097                                 case 0x0A:
2098                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2099                                         break;
2100                                 case 0x0B:
2101                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2102                                         break;
2103                                 case 0x0C:
2104                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2105                                         break;
2106                                 default:
2107                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2108                                                (unsigned int)dimm_num);
2109                                         printf("ERROR: Unsupported value for number of "
2110                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2111                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2112                                         spd_ddr_init_hang ();
2113                                 }
2114                         }
2115
2116                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2117                                 bank_0_populated = 1;
2118
2119                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2120                                 mtsdram(SDRAM_MB0CF +
2121                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2122                                         mode);
2123                         }
2124                 }
2125         }
2126 }
2127
2128 /*------------------------------------------------------------------
2129  * program memory queue.
2130  *-----------------------------------------------------------------*/
2131 static void program_memory_queue(unsigned long *dimm_populated,
2132                                  unsigned char *iic0_dimm_addr,
2133                                  unsigned long num_dimm_banks)
2134 {
2135         unsigned long dimm_num;
2136         unsigned long rank_base_addr;
2137         unsigned long rank_reg;
2138         unsigned long rank_size_bytes;
2139         unsigned long rank_size_id;
2140         unsigned long num_ranks;
2141         unsigned long baseadd_size;
2142         unsigned long i;
2143         unsigned long bank_0_populated = 0;
2144         unsigned long total_size = 0;
2145
2146         /*------------------------------------------------------------------
2147          * Reset the rank_base_address.
2148          *-----------------------------------------------------------------*/
2149         rank_reg   = SDRAM_R0BAS;
2150
2151         rank_base_addr = 0x00000000;
2152
2153         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2154                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2155                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2156                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2157                                 num_ranks = (num_ranks & 0x0F) + 1;
2158                         else
2159                                 num_ranks = num_ranks & 0x0F;
2160
2161                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2162
2163                         /*------------------------------------------------------------------
2164                          * Set the sizes
2165                          *-----------------------------------------------------------------*/
2166                         baseadd_size = 0;
2167                         switch (rank_size_id) {
2168                         case 0x01:
2169                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2170                                 total_size = 1024;
2171                                 break;
2172                         case 0x02:
2173                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2174                                 total_size = 2048;
2175                                 break;
2176                         case 0x04:
2177                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2178                                 total_size = 4096;
2179                                 break;
2180                         case 0x08:
2181                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2182                                 total_size = 32;
2183                                 break;
2184                         case 0x10:
2185                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2186                                 total_size = 64;
2187                                 break;
2188                         case 0x20:
2189                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2190                                 total_size = 128;
2191                                 break;
2192                         case 0x40:
2193                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2194                                 total_size = 256;
2195                                 break;
2196                         case 0x80:
2197                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2198                                 total_size = 512;
2199                                 break;
2200                         default:
2201                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2202                                        (unsigned int)dimm_num);
2203                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2204                                        (unsigned int)rank_size_id);
2205                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2206                                 spd_ddr_init_hang ();
2207                         }
2208                         rank_size_bytes = total_size << 20;
2209
2210                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2211                                 bank_0_populated = 1;
2212
2213                         for (i = 0; i < num_ranks; i++) {
2214                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2215                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2216                                            baseadd_size));
2217                                 rank_base_addr += rank_size_bytes;
2218                         }
2219                 }
2220         }
2221
2222 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
2223         /*
2224          * Enable high bandwidth access on 460EX/GT.
2225          * This should/could probably be done on other
2226          * PPC's too, like 440SPe.
2227          * This is currently not used, but with this setup
2228          * it is possible to use it later on in e.g. the Linux
2229          * EMAC driver for performance gain.
2230          */
2231         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2232         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2233 #endif
2234 }
2235
2236 /*-----------------------------------------------------------------------------+
2237  * is_ecc_enabled.
2238  *-----------------------------------------------------------------------------*/
2239 static unsigned long is_ecc_enabled(void)
2240 {
2241         unsigned long dimm_num;
2242         unsigned long ecc;
2243         unsigned long val;
2244
2245         ecc = 0;
2246         /* loop through all the DIMM slots on the board */
2247         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2248                 mfsdram(SDRAM_MCOPT1, val);
2249                 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2250         }
2251
2252         return ecc;
2253 }
2254
2255 static void blank_string(int size)
2256 {
2257         int i;
2258
2259         for (i=0; i<size; i++)
2260                 putc('\b');
2261         for (i=0; i<size; i++)
2262                 putc(' ');
2263         for (i=0; i<size; i++)
2264                 putc('\b');
2265 }
2266
2267 #ifdef CONFIG_DDR_ECC
2268 /*-----------------------------------------------------------------------------+
2269  * program_ecc.
2270  *-----------------------------------------------------------------------------*/
2271 static void program_ecc(unsigned long *dimm_populated,
2272                         unsigned char *iic0_dimm_addr,
2273                         unsigned long num_dimm_banks,
2274                         unsigned long tlb_word2_i_value)
2275 {
2276         unsigned long mcopt1;
2277         unsigned long mcopt2;
2278         unsigned long mcstat;
2279         unsigned long dimm_num;
2280         unsigned long ecc;
2281
2282         ecc = 0;
2283         /* loop through all the DIMM slots on the board */
2284         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2285                 /* If a dimm is installed in a particular slot ... */
2286                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2287                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2288         }
2289         if (ecc == 0)
2290                 return;
2291
2292         mfsdram(SDRAM_MCOPT1, mcopt1);
2293         mfsdram(SDRAM_MCOPT2, mcopt2);
2294
2295         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2296                 /* DDR controller must be enabled and not in self-refresh. */
2297                 mfsdram(SDRAM_MCSTAT, mcstat);
2298                 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2299                     && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2300                     && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2301                         == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2302
2303                         program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2304                 }
2305         }
2306
2307         return;
2308 }
2309
2310 static void wait_ddr_idle(void)
2311 {
2312         u32 val;
2313
2314         do {
2315                 mfsdram(SDRAM_MCSTAT, val);
2316         } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2317 }
2318
2319 /*-----------------------------------------------------------------------------+
2320  * program_ecc_addr.
2321  *-----------------------------------------------------------------------------*/
2322 static void program_ecc_addr(unsigned long start_address,
2323                              unsigned long num_bytes,
2324                              unsigned long tlb_word2_i_value)
2325 {
2326         unsigned long current_address;
2327         unsigned long end_address;
2328         unsigned long address_increment;
2329         unsigned long mcopt1;
2330         char str[] = "ECC generation -";
2331         char slash[] = "\\|/-\\|/-";
2332         int loop = 0;
2333         int loopi = 0;
2334
2335         current_address = start_address;
2336         mfsdram(SDRAM_MCOPT1, mcopt1);
2337         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2338                 mtsdram(SDRAM_MCOPT1,
2339                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2340                 sync();
2341                 eieio();
2342                 wait_ddr_idle();
2343
2344                 puts(str);
2345                 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2346                         /* ECC bit set method for non-cached memory */
2347                         if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2348                                 address_increment = 4;
2349                         else
2350                                 address_increment = 8;
2351                         end_address = current_address + num_bytes;
2352
2353                         while (current_address < end_address) {
2354                                 *((unsigned long *)current_address) = 0x00000000;
2355                                 current_address += address_increment;
2356
2357                                 if ((loop++ % (2 << 20)) == 0) {
2358                                         putc('\b');
2359                                         putc(slash[loopi++ % 8]);
2360                                 }
2361                         }
2362
2363                 } else {
2364                         /* ECC bit set method for cached memory */
2365                         dcbz_area(start_address, num_bytes);
2366                         /* Write modified dcache lines back to memory */
2367                         clean_dcache_range(start_address, start_address + num_bytes);
2368                 }
2369
2370                 blank_string(strlen(str));
2371
2372                 sync();
2373                 eieio();
2374                 wait_ddr_idle();
2375
2376                 /* clear ECC error repoting registers */
2377                 mtsdram(SDRAM_ECCCR, 0xffffffff);
2378                 mtdcr(0x4c, 0xffffffff);
2379
2380                 mtsdram(SDRAM_MCOPT1,
2381                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2382                 sync();
2383                 eieio();
2384                 wait_ddr_idle();
2385         }
2386 }
2387 #endif
2388
2389 /*-----------------------------------------------------------------------------+
2390  * program_DQS_calibration.
2391  *-----------------------------------------------------------------------------*/
2392 static void program_DQS_calibration(unsigned long *dimm_populated,
2393                                     unsigned char *iic0_dimm_addr,
2394                                     unsigned long num_dimm_banks)
2395 {
2396         unsigned long val;
2397
2398 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2399         mtsdram(SDRAM_RQDC, 0x80000037);
2400         mtsdram(SDRAM_RDCC, 0x40000000);
2401         mtsdram(SDRAM_RFDC, 0x000001DF);
2402
2403         test();
2404 #else
2405         /*------------------------------------------------------------------
2406          * Program RDCC register
2407          * Read sample cycle auto-update enable
2408          *-----------------------------------------------------------------*/
2409
2410         mfsdram(SDRAM_RDCC, val);
2411         mtsdram(SDRAM_RDCC,
2412                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2413                 | SDRAM_RDCC_RSAE_ENABLE);
2414
2415         /*------------------------------------------------------------------
2416          * Program RQDC register
2417          * Internal DQS delay mechanism enable
2418          *-----------------------------------------------------------------*/
2419         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2420
2421         /*------------------------------------------------------------------
2422          * Program RFDC register
2423          * Set Feedback Fractional Oversample
2424          * Auto-detect read sample cycle enable
2425          *-----------------------------------------------------------------*/
2426         mfsdram(SDRAM_RFDC, val);
2427         mtsdram(SDRAM_RFDC,
2428                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2429                          SDRAM_RFDC_RFFD_MASK))
2430                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2431                    SDRAM_RFDC_RFFD_ENCODE(0)));
2432
2433         DQS_calibration_process();
2434 #endif
2435 }
2436
2437 static int short_mem_test(void)
2438 {
2439         u32 *membase;
2440         u32 bxcr_num;
2441         u32 bxcf;
2442         int i;
2443         int j;
2444         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2445                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2446                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2447                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2448                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2449                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2450                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2451                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2452                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2453                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2454                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2455                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2456                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2457                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2458                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2459                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2460                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2461         int l;
2462
2463         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2464                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2465
2466                 /* Banks enabled */
2467                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2468                         /* Bank is enabled */
2469
2470                         /*------------------------------------------------------------------
2471                          * Run the short memory test.
2472                          *-----------------------------------------------------------------*/
2473                         membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
2474
2475                         for (i = 0; i < NUMMEMTESTS; i++) {
2476                                 for (j = 0; j < NUMMEMWORDS; j++) {
2477                                         membase[j] = test[i][j];
2478                                         ppcDcbf((u32)&(membase[j]));
2479                                 }
2480                                 sync();
2481                                 for (l=0; l<NUMLOOPS; l++) {
2482                                         for (j = 0; j < NUMMEMWORDS; j++) {
2483                                                 if (membase[j] != test[i][j]) {
2484                                                         ppcDcbf((u32)&(membase[j]));
2485                                                         return 0;
2486                                                 }
2487                                                 ppcDcbf((u32)&(membase[j]));
2488                                         }
2489                                         sync();
2490                                 }
2491                         }
2492                 }       /* if bank enabled */
2493         }               /* for bxcf_num */
2494
2495         return 1;
2496 }
2497
2498 #ifndef HARD_CODED_DQS
2499 /*-----------------------------------------------------------------------------+
2500  * DQS_calibration_process.
2501  *-----------------------------------------------------------------------------*/
2502 static void DQS_calibration_process(void)
2503 {
2504         unsigned long rfdc_reg;
2505         unsigned long rffd;
2506         unsigned long val;
2507         long rffd_average;
2508         long max_start;
2509         long min_end;
2510         unsigned long begin_rqfd[MAXRANKS];
2511         unsigned long begin_rffd[MAXRANKS];
2512         unsigned long end_rqfd[MAXRANKS];
2513         unsigned long end_rffd[MAXRANKS];
2514         char window_found;
2515         unsigned long dlycal;
2516         unsigned long dly_val;
2517         unsigned long max_pass_length;
2518         unsigned long current_pass_length;
2519         unsigned long current_fail_length;
2520         unsigned long current_start;
2521         long max_end;
2522         unsigned char fail_found;
2523         unsigned char pass_found;
2524 #if !defined(CONFIG_DDR_RQDC_FIXED)
2525         u32 rqdc_reg;
2526         u32 rqfd;
2527         u32 rqfd_start;
2528         u32 rqfd_average;
2529         int loopi = 0;
2530         char str[] = "Auto calibration -";
2531         char slash[] = "\\|/-\\|/-";
2532
2533         /*------------------------------------------------------------------
2534          * Test to determine the best read clock delay tuning bits.
2535          *
2536          * Before the DDR controller can be used, the read clock delay needs to be
2537          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2538          * This value cannot be hardcoded into the program because it changes
2539          * depending on the board's setup and environment.
2540          * To do this, all delay values are tested to see if they
2541          * work or not.  By doing this, you get groups of fails with groups of
2542          * passing values.  The idea is to find the start and end of a passing
2543          * window and take the center of it to use as the read clock delay.
2544          *
2545          * A failure has to be seen first so that when we hit a pass, we know
2546          * that it is truely the start of the window.  If we get passing values
2547          * to start off with, we don't know if we are at the start of the window.
2548          *
2549          * The code assumes that a failure will always be found.
2550          * If a failure is not found, there is no easy way to get the middle
2551          * of the passing window.  I guess we can pretty much pick any value
2552          * but some values will be better than others.  Since the lowest speed
2553          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2554          * from experimentation it is safe to say you will always have a failure.
2555          *-----------------------------------------------------------------*/
2556
2557         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2558         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2559
2560         puts(str);
2561
2562 calibration_loop:
2563         mfsdram(SDRAM_RQDC, rqdc_reg);
2564         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2565                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2566 #else /* CONFIG_DDR_RQDC_FIXED */
2567         /*
2568          * On Katmai the complete auto-calibration somehow doesn't seem to
2569          * produce the best results, meaning optimal values for RQFD/RFFD.
2570          * This was discovered by GDA using a high bandwidth scope,
2571          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2572          * so now on Katmai "only" RFFD is auto-calibrated.
2573          */
2574         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2575 #endif /* CONFIG_DDR_RQDC_FIXED */
2576
2577         max_start = 0;
2578         min_end = 0;
2579         begin_rqfd[0] = 0;
2580         begin_rffd[0] = 0;
2581         begin_rqfd[1] = 0;
2582         begin_rffd[1] = 0;
2583         end_rqfd[0] = 0;
2584         end_rffd[0] = 0;
2585         end_rqfd[1] = 0;
2586         end_rffd[1] = 0;
2587         window_found = FALSE;
2588
2589         max_pass_length = 0;
2590         max_start = 0;
2591         max_end = 0;
2592         current_pass_length = 0;
2593         current_fail_length = 0;
2594         current_start = 0;
2595         window_found = FALSE;
2596         fail_found = FALSE;
2597         pass_found = FALSE;
2598
2599         /*
2600          * get the delay line calibration register value
2601          */
2602         mfsdram(SDRAM_DLCR, dlycal);
2603         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2604
2605         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2606                 mfsdram(SDRAM_RFDC, rfdc_reg);
2607                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2608
2609                 /*------------------------------------------------------------------
2610                  * Set the timing reg for the test.
2611                  *-----------------------------------------------------------------*/
2612                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2613
2614                 /*------------------------------------------------------------------
2615                  * See if the rffd value passed.
2616                  *-----------------------------------------------------------------*/
2617                 if (short_mem_test()) {
2618                         if (fail_found == TRUE) {
2619                                 pass_found = TRUE;
2620                                 if (current_pass_length == 0)
2621                                         current_start = rffd;
2622
2623                                 current_fail_length = 0;
2624                                 current_pass_length++;
2625
2626                                 if (current_pass_length > max_pass_length) {
2627                                         max_pass_length = current_pass_length;
2628                                         max_start = current_start;
2629                                         max_end = rffd;
2630                                 }
2631                         }
2632                 } else {
2633                         current_pass_length = 0;
2634                         current_fail_length++;
2635
2636                         if (current_fail_length >= (dly_val >> 2)) {
2637                                 if (fail_found == FALSE) {
2638                                         fail_found = TRUE;
2639                                 } else if (pass_found == TRUE) {
2640                                         window_found = TRUE;
2641                                         break;
2642                                 }
2643                         }
2644                 }
2645         }               /* for rffd */
2646
2647         /*------------------------------------------------------------------
2648          * Set the average RFFD value
2649          *-----------------------------------------------------------------*/
2650         rffd_average = ((max_start + max_end) >> 1);
2651
2652         if (rffd_average < 0)
2653                 rffd_average = 0;
2654
2655         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2656                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2657         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2658         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2659
2660 #if !defined(CONFIG_DDR_RQDC_FIXED)
2661         max_pass_length = 0;
2662         max_start = 0;
2663         max_end = 0;
2664         current_pass_length = 0;
2665         current_fail_length = 0;
2666         current_start = 0;
2667         window_found = FALSE;
2668         fail_found = FALSE;
2669         pass_found = FALSE;
2670
2671         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2672                 mfsdram(SDRAM_RQDC, rqdc_reg);
2673                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2674
2675                 /*------------------------------------------------------------------
2676                  * Set the timing reg for the test.
2677                  *-----------------------------------------------------------------*/
2678                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2679
2680                 /*------------------------------------------------------------------
2681                  * See if the rffd value passed.
2682                  *-----------------------------------------------------------------*/
2683                 if (short_mem_test()) {
2684                         if (fail_found == TRUE) {
2685                                 pass_found = TRUE;
2686                                 if (current_pass_length == 0)
2687                                         current_start = rqfd;
2688
2689                                 current_fail_length = 0;
2690                                 current_pass_length++;
2691
2692                                 if (current_pass_length > max_pass_length) {
2693                                         max_pass_length = current_pass_length;
2694                                         max_start = current_start;
2695                                         max_end = rqfd;
2696                                 }
2697                         }
2698                 } else {
2699                         current_pass_length = 0;
2700                         current_fail_length++;
2701
2702                         if (fail_found == FALSE) {
2703                                 fail_found = TRUE;
2704                         } else if (pass_found == TRUE) {
2705                                 window_found = TRUE;
2706                                 break;
2707                         }
2708                 }
2709         }
2710
2711         rqfd_average = ((max_start + max_end) >> 1);
2712
2713         /*------------------------------------------------------------------
2714          * Make sure we found the valid read passing window.  Halt if not
2715          *-----------------------------------------------------------------*/
2716         if (window_found == FALSE) {
2717                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2718                         putc('\b');
2719                         putc(slash[loopi++ % 8]);
2720
2721                         /* try again from with a different RQFD start value */
2722                         rqfd_start++;
2723                         goto calibration_loop;
2724                 }
2725
2726                 printf("\nERROR: Cannot determine a common read delay for the "
2727                        "DIMM(s) installed.\n");
2728                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2729                 ppc440sp_sdram_register_dump();
2730                 spd_ddr_init_hang ();
2731         }
2732
2733         if (rqfd_average < 0)
2734                 rqfd_average = 0;
2735
2736         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2737                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2738
2739         mtsdram(SDRAM_RQDC,
2740                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2741                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2742
2743         blank_string(strlen(str));
2744 #endif /* CONFIG_DDR_RQDC_FIXED */
2745
2746         /*
2747          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2748          * PowerPC440SP/SPe DDR2 application note:
2749          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2750          */
2751         mfsdram(SDRAM_RTSR, val);
2752         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2753                 mfsdram(SDRAM_RDCC, val);
2754                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2755                         val += 0x40000000;
2756                         mtsdram(SDRAM_RDCC, val);
2757                 }
2758         }
2759
2760         mfsdram(SDRAM_DLCR, val);
2761         debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2762         mfsdram(SDRAM_RQDC, val);
2763         debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2764         mfsdram(SDRAM_RFDC, val);
2765         debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2766         mfsdram(SDRAM_RDCC, val);
2767         debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2768 }
2769 #else /* calibration test with hardvalues */
2770 /*-----------------------------------------------------------------------------+
2771  * DQS_calibration_process.
2772  *-----------------------------------------------------------------------------*/
2773 static void test(void)
2774 {
2775         unsigned long dimm_num;
2776         unsigned long ecc_temp;
2777         unsigned long i, j;
2778         unsigned long *membase;
2779         unsigned long bxcf[MAXRANKS];
2780         unsigned long val;
2781         char window_found;
2782         char begin_found[MAXDIMMS];
2783         char end_found[MAXDIMMS];
2784         char search_end[MAXDIMMS];
2785         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2786                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2787                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2788                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2789                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2790                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2791                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2792                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2793                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2794                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2795                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2796                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2797                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2798                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2799                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2800                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2801                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2802
2803         /*------------------------------------------------------------------
2804          * Test to determine the best read clock delay tuning bits.
2805          *
2806          * Before the DDR controller can be used, the read clock delay needs to be
2807          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2808          * This value cannot be hardcoded into the program because it changes
2809          * depending on the board's setup and environment.
2810          * To do this, all delay values are tested to see if they
2811          * work or not.  By doing this, you get groups of fails with groups of
2812          * passing values.  The idea is to find the start and end of a passing
2813          * window and take the center of it to use as the read clock delay.
2814          *
2815          * A failure has to be seen first so that when we hit a pass, we know
2816          * that it is truely the start of the window.  If we get passing values
2817          * to start off with, we don't know if we are at the start of the window.
2818          *
2819          * The code assumes that a failure will always be found.
2820          * If a failure is not found, there is no easy way to get the middle
2821          * of the passing window.  I guess we can pretty much pick any value
2822          * but some values will be better than others.  Since the lowest speed
2823          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2824          * from experimentation it is safe to say you will always have a failure.
2825          *-----------------------------------------------------------------*/
2826         mfsdram(SDRAM_MCOPT1, ecc_temp);
2827         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2828         mfsdram(SDRAM_MCOPT1, val);
2829         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2830                 SDRAM_MCOPT1_MCHK_NON);
2831
2832         window_found = FALSE;
2833         begin_found[0] = FALSE;
2834         end_found[0] = FALSE;
2835         search_end[0] = FALSE;
2836         begin_found[1] = FALSE;
2837         end_found[1] = FALSE;
2838         search_end[1] = FALSE;
2839
2840         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2841                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2842
2843                 /* Banks enabled */
2844                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2845
2846                         /* Bank is enabled */
2847                         membase =
2848                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2849
2850                         /*------------------------------------------------------------------
2851                          * Run the short memory test.
2852                          *-----------------------------------------------------------------*/
2853                         for (i = 0; i < NUMMEMTESTS; i++) {
2854                                 for (j = 0; j < NUMMEMWORDS; j++) {
2855                                         membase[j] = test[i][j];
2856                                         ppcDcbf((u32)&(membase[j]));
2857                                 }
2858                                 sync();
2859                                 for (j = 0; j < NUMMEMWORDS; j++) {
2860                                         if (membase[j] != test[i][j]) {
2861                                                 ppcDcbf((u32)&(membase[j]));
2862                                                 break;
2863                                         }
2864                                         ppcDcbf((u32)&(membase[j]));
2865                                 }
2866                                 sync();
2867                                 if (j < NUMMEMWORDS)
2868                                         break;
2869                         }
2870
2871                         /*------------------------------------------------------------------
2872                          * See if the rffd value passed.
2873                          *-----------------------------------------------------------------*/
2874                         if (i < NUMMEMTESTS) {
2875                                 if ((end_found[dimm_num] == FALSE) &&
2876                                     (search_end[dimm_num] == TRUE)) {
2877                                         end_found[dimm_num] = TRUE;
2878                                 }
2879                                 if ((end_found[0] == TRUE) &&
2880                                     (end_found[1] == TRUE))
2881                                         break;
2882                         } else {
2883                                 if (begin_found[dimm_num] == FALSE) {
2884                                         begin_found[dimm_num] = TRUE;
2885                                         search_end[dimm_num] = TRUE;
2886                                 }
2887                         }
2888                 } else {
2889                         begin_found[dimm_num] = TRUE;
2890                         end_found[dimm_num] = TRUE;
2891                 }
2892         }
2893
2894         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2895                 window_found = TRUE;
2896
2897         /*------------------------------------------------------------------
2898          * Make sure we found the valid read passing window.  Halt if not
2899          *-----------------------------------------------------------------*/
2900         if (window_found == FALSE) {
2901                 printf("ERROR: Cannot determine a common read delay for the "
2902                        "DIMM(s) installed.\n");
2903                 spd_ddr_init_hang ();
2904         }
2905
2906         /*------------------------------------------------------------------
2907          * Restore the ECC variable to what it originally was
2908          *-----------------------------------------------------------------*/
2909         mtsdram(SDRAM_MCOPT1,
2910                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2911                 | ecc_temp);
2912 }
2913 #endif
2914
2915 #if defined(DEBUG)
2916 static void ppc440sp_sdram_register_dump(void)
2917 {
2918         unsigned int sdram_reg;
2919         unsigned int sdram_data;
2920         unsigned int dcr_data;
2921
2922         printf("\n  Register Dump:\n");
2923         sdram_reg = SDRAM_MCSTAT;
2924         mfsdram(sdram_reg, sdram_data);
2925         printf("        SDRAM_MCSTAT    = 0x%08X", sdram_data);
2926         sdram_reg = SDRAM_MCOPT1;
2927         mfsdram(sdram_reg, sdram_data);
2928         printf("        SDRAM_MCOPT1    = 0x%08X\n", sdram_data);
2929         sdram_reg = SDRAM_MCOPT2;
2930         mfsdram(sdram_reg, sdram_data);
2931         printf("        SDRAM_MCOPT2    = 0x%08X", sdram_data);
2932         sdram_reg = SDRAM_MODT0;
2933         mfsdram(sdram_reg, sdram_data);
2934         printf("        SDRAM_MODT0     = 0x%08X\n", sdram_data);
2935         sdram_reg = SDRAM_MODT1;
2936         mfsdram(sdram_reg, sdram_data);
2937         printf("        SDRAM_MODT1     = 0x%08X", sdram_data);
2938         sdram_reg = SDRAM_MODT2;
2939         mfsdram(sdram_reg, sdram_data);
2940         printf("        SDRAM_MODT2     = 0x%08X\n", sdram_data);
2941         sdram_reg = SDRAM_MODT3;
2942         mfsdram(sdram_reg, sdram_data);
2943         printf("        SDRAM_MODT3     = 0x%08X", sdram_data);
2944         sdram_reg = SDRAM_CODT;
2945         mfsdram(sdram_reg, sdram_data);
2946         printf("        SDRAM_CODT      = 0x%08X\n", sdram_data);
2947         sdram_reg = SDRAM_VVPR;
2948         mfsdram(sdram_reg, sdram_data);
2949         printf("        SDRAM_VVPR      = 0x%08X", sdram_data);
2950         sdram_reg = SDRAM_OPARS;
2951         mfsdram(sdram_reg, sdram_data);
2952         printf("        SDRAM_OPARS     = 0x%08X\n", sdram_data);
2953         /*
2954          * OPAR2 is only used as a trigger register.
2955          * No data is contained in this register, and reading or writing
2956          * to is can cause bad things to happen (hangs).  Just skip it
2957          * and report NA
2958          * sdram_reg = SDRAM_OPAR2;
2959          * mfsdram(sdram_reg, sdram_data);
2960          * printf("        SDRAM_OPAR2     = 0x%08X\n", sdram_data);
2961          */
2962         printf("        SDRAM_OPART     = N/A       ");
2963         sdram_reg = SDRAM_RTR;
2964         mfsdram(sdram_reg, sdram_data);
2965         printf("        SDRAM_RTR       = 0x%08X\n", sdram_data);
2966         sdram_reg = SDRAM_MB0CF;
2967         mfsdram(sdram_reg, sdram_data);
2968         printf("        SDRAM_MB0CF     = 0x%08X", sdram_data);
2969         sdram_reg = SDRAM_MB1CF;
2970         mfsdram(sdram_reg, sdram_data);
2971         printf("        SDRAM_MB1CF     = 0x%08X\n", sdram_data);
2972         sdram_reg = SDRAM_MB2CF;
2973         mfsdram(sdram_reg, sdram_data);
2974         printf("        SDRAM_MB2CF     = 0x%08X", sdram_data);
2975         sdram_reg = SDRAM_MB3CF;
2976         mfsdram(sdram_reg, sdram_data);
2977         printf("        SDRAM_MB3CF     = 0x%08X\n", sdram_data);
2978         sdram_reg = SDRAM_INITPLR0;
2979         mfsdram(sdram_reg, sdram_data);
2980         printf("        SDRAM_INITPLR0  = 0x%08X", sdram_data);
2981         sdram_reg = SDRAM_INITPLR1;
2982         mfsdram(sdram_reg, sdram_data);
2983         printf("        SDRAM_INITPLR1  = 0x%08X\n", sdram_data);
2984         sdram_reg = SDRAM_INITPLR2;
2985         mfsdram(sdram_reg, sdram_data);
2986         printf("        SDRAM_INITPLR2  = 0x%08X", sdram_data);
2987         sdram_reg = SDRAM_INITPLR3;
2988         mfsdram(sdram_reg, sdram_data);
2989         printf("        SDRAM_INITPLR3  = 0x%08X\n", sdram_data);
2990         sdram_reg = SDRAM_INITPLR4;
2991         mfsdram(sdram_reg, sdram_data);
2992         printf("        SDRAM_INITPLR4  = 0x%08X", sdram_data);
2993         sdram_reg = SDRAM_INITPLR5;
2994         mfsdram(sdram_reg, sdram_data);
2995         printf("        SDRAM_INITPLR5  = 0x%08X\n", sdram_data);
2996         sdram_reg = SDRAM_INITPLR6;
2997         mfsdram(sdram_reg, sdram_data);
2998         printf("        SDRAM_INITPLR6  = 0x%08X", sdram_data);
2999         sdram_reg = SDRAM_INITPLR7;
3000         mfsdram(sdram_reg, sdram_data);
3001         printf("        SDRAM_INITPLR7  = 0x%08X\n", sdram_data);
3002         sdram_reg = SDRAM_INITPLR8;
3003         mfsdram(sdram_reg, sdram_data);
3004         printf("        SDRAM_INITPLR8  = 0x%08X", sdram_data);
3005         sdram_reg = SDRAM_INITPLR9;
3006         mfsdram(sdram_reg, sdram_data);
3007         printf("        SDRAM_INITPLR9  = 0x%08X\n", sdram_data);
3008         sdram_reg = SDRAM_INITPLR10;
3009         mfsdram(sdram_reg, sdram_data);
3010         printf("        SDRAM_INITPLR10 = 0x%08X", sdram_data);
3011         sdram_reg = SDRAM_INITPLR11;
3012         mfsdram(sdram_reg, sdram_data);
3013         printf("        SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
3014         sdram_reg = SDRAM_INITPLR12;
3015         mfsdram(sdram_reg, sdram_data);
3016         printf("        SDRAM_INITPLR12 = 0x%08X", sdram_data);
3017         sdram_reg = SDRAM_INITPLR13;
3018         mfsdram(sdram_reg, sdram_data);
3019         printf("        SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
3020         sdram_reg = SDRAM_INITPLR14;
3021         mfsdram(sdram_reg, sdram_data);
3022         printf("        SDRAM_INITPLR14 = 0x%08X", sdram_data);
3023         sdram_reg = SDRAM_INITPLR15;
3024         mfsdram(sdram_reg, sdram_data);
3025         printf("        SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
3026         sdram_reg = SDRAM_RQDC;
3027         mfsdram(sdram_reg, sdram_data);
3028         printf("        SDRAM_RQDC      = 0x%08X", sdram_data);
3029         sdram_reg = SDRAM_RFDC;
3030         mfsdram(sdram_reg, sdram_data);
3031         printf("        SDRAM_RFDC      = 0x%08X\n", sdram_data);
3032         sdram_reg = SDRAM_RDCC;
3033         mfsdram(sdram_reg, sdram_data);
3034         printf("        SDRAM_RDCC      = 0x%08X", sdram_data);
3035         sdram_reg = SDRAM_DLCR;
3036         mfsdram(sdram_reg, sdram_data);
3037         printf("        SDRAM_DLCR      = 0x%08X\n", sdram_data);
3038         sdram_reg = SDRAM_CLKTR;
3039         mfsdram(sdram_reg, sdram_data);
3040         printf("        SDRAM_CLKTR     = 0x%08X", sdram_data);
3041         sdram_reg = SDRAM_WRDTR;
3042         mfsdram(sdram_reg, sdram_data);
3043         printf("        SDRAM_WRDTR     = 0x%08X\n", sdram_data);
3044         sdram_reg = SDRAM_SDTR1;
3045         mfsdram(sdram_reg, sdram_data);
3046         printf("        SDRAM_SDTR1     = 0x%08X", sdram_data);
3047         sdram_reg = SDRAM_SDTR2;
3048         mfsdram(sdram_reg, sdram_data);
3049         printf("        SDRAM_SDTR2     = 0x%08X\n", sdram_data);
3050         sdram_reg = SDRAM_SDTR3;
3051         mfsdram(sdram_reg, sdram_data);
3052         printf("        SDRAM_SDTR3     = 0x%08X", sdram_data);
3053         sdram_reg = SDRAM_MMODE;
3054         mfsdram(sdram_reg, sdram_data);
3055         printf("        SDRAM_MMODE     = 0x%08X\n", sdram_data);
3056         sdram_reg = SDRAM_MEMODE;
3057         mfsdram(sdram_reg, sdram_data);
3058         printf("        SDRAM_MEMODE    = 0x%08X", sdram_data);
3059         sdram_reg = SDRAM_ECCCR;
3060         mfsdram(sdram_reg, sdram_data);
3061         printf("        SDRAM_ECCCR     = 0x%08X\n\n", sdram_data);
3062
3063         dcr_data = mfdcr(SDRAM_R0BAS);
3064         printf("        MQ0_B0BAS       = 0x%08X", dcr_data);
3065         dcr_data = mfdcr(SDRAM_R1BAS);
3066         printf("        MQ1_B0BAS       = 0x%08X\n", dcr_data);
3067         dcr_data = mfdcr(SDRAM_R2BAS);
3068         printf("        MQ2_B0BAS       = 0x%08X", dcr_data);
3069         dcr_data = mfdcr(SDRAM_R3BAS);
3070         printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
3071 }
3072 #else /* !defined(DEBUG) */
3073 static void ppc440sp_sdram_register_dump(void)
3074 {
3075 }
3076 #endif /* defined(DEBUG) */
3077 #elif defined(CONFIG_405EX)
3078 /*-----------------------------------------------------------------------------
3079  * Function:    initdram
3080  * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
3081  *              banks. The configuration is performed using static, compile-
3082  *              time parameters.
3083  *---------------------------------------------------------------------------*/
3084 long initdram(int board_type)
3085 {
3086         /*
3087          * Only run this SDRAM init code once. For NAND booting
3088          * targets like Kilauea, we call initdram() early from the
3089          * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
3090          * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
3091          * which calls initdram() again. This time the controller
3092          * mustn't be reconfigured again since we're already running
3093          * from SDRAM.
3094          */
3095 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
3096         unsigned long val;
3097
3098         /* Set Memory Bank Configuration Registers */
3099
3100         mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
3101         mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
3102         mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
3103         mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
3104
3105         /* Set Memory Clock Timing Register */
3106
3107         mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
3108
3109         /* Set Refresh Time Register */
3110
3111         mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
3112
3113         /* Set SDRAM Timing Registers */
3114
3115         mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
3116         mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
3117         mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
3118
3119         /* Set Mode and Extended Mode Registers */
3120
3121         mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
3122         mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
3123
3124         /* Set Memory Controller Options 1 Register */
3125
3126         mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
3127
3128         /* Set Manual Initialization Control Registers */
3129
3130         mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
3131         mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
3132         mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
3133         mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
3134         mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
3135         mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
3136         mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
3137         mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
3138         mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
3139         mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
3140         mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
3141         mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
3142         mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
3143         mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
3144         mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
3145         mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
3146
3147         /* Set On-Die Termination Registers */
3148
3149         mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
3150         mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
3151         mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
3152
3153         /* Set Write Timing Register */
3154
3155         mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
3156
3157         /*
3158          * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3159          * SDRAM0_MCOPT2[IPTR] = 1
3160          */
3161
3162         mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3163                                SDRAM_MCOPT2_IPTR_EXECUTE));
3164
3165         /*
3166          * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3167          * completion of initialization.
3168          */
3169
3170         do {
3171                 mfsdram(SDRAM_MCSTAT, val);
3172         } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3173
3174         /* Set Delay Control Registers */
3175
3176         mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
3177         mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
3178         mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
3179         mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
3180
3181         /*
3182          * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3183          */
3184
3185         mfsdram(SDRAM_MCOPT2, val);
3186         mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3187
3188 #if defined(CONFIG_DDR_ECC)
3189         ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
3190 #endif /* defined(CONFIG_DDR_ECC) */
3191 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3192
3193         return (CFG_MBYTES_SDRAM << 20);
3194 }
3195 #endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */