cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX(r)
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * Copyright (c) 2008 Nuovation System Designs, LLC
  10  *   Grant Erickson <gerickson@nuovations.com>
  11
  12  * (C) Copyright 2007-2008
  13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14  *
  15  * COPYRIGHT   AMCC   CORPORATION 2004
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  *
  35  */
  36
  37 /* define DEBUG for debugging output (obviously ;-)) */
  38 #if 0
  39 #define DEBUG
  40 #endif
  41
  42 #include <common.h>
  43 #include <command.h>
  44 #include <ppc4xx.h>
  45 #include <i2c.h>
  46 #include <asm/io.h>
  47 #include <asm/processor.h>
  48 #include <asm/mmu.h>
  49 #include <asm/cache.h>
  50
  51 #include "ecc.h"
  52
  53 static void ppc4xx_ibm_ddr2_register_dump(void);
  54
  55 #if defined(CONFIG_SPD_EEPROM) &&                               \
  56         (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  57          defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
  58          defined(CONFIG_460SX))
  59
  60 /*-----------------------------------------------------------------------------+
  61  * Defines
  62  *-----------------------------------------------------------------------------*/
  63 #ifndef TRUE
  64 #define TRUE            1
  65 #endif
  66 #ifndef FALSE
  67 #define FALSE           0
  68 #endif
  69
  70 #define SDRAM_DDR1      1
  71 #define SDRAM_DDR2      2
  72 #define SDRAM_NONE      0
  73
  74 #define MAXDIMMS        2
  75 #define MAXRANKS        4
  76 #define MAXBXCF         4
  77 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
  78
  79 #define ONE_BILLION     1000000000
  80
  81 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  82
  83 #define CMD_NOP         (7 << 19)
  84 #define CMD_PRECHARGE   (2 << 19)
  85 #define CMD_REFRESH     (1 << 19)
  86 #define CMD_EMR         (0 << 19)
  87 #define CMD_READ        (5 << 19)
  88 #define CMD_WRITE       (4 << 19)
  89
  90 #define SELECT_MR       (0 << 16)
  91 #define SELECT_EMR      (1 << 16)
  92 #define SELECT_EMR2     (2 << 16)
  93 #define SELECT_EMR3     (3 << 16)
  94
  95 /* MR */
  96 #define DLL_RESET       0x00000100
  97
  98 #define WRITE_RECOV_2   (1 << 9)
  99 #define WRITE_RECOV_3   (2 << 9)
 100 #define WRITE_RECOV_4   (3 << 9)
 101 #define WRITE_RECOV_5   (4 << 9)
 102 #define WRITE_RECOV_6   (5 << 9)
 103
 104 #define BURST_LEN_4     0x00000002
 105
 106 /* EMR */
 107 #define ODT_0_OHM       0x00000000
 108 #define ODT_50_OHM      0x00000044
 109 #define ODT_75_OHM      0x00000004
 110 #define ODT_150_OHM     0x00000040
 111
 112 #define ODS_FULL        0x00000000
 113 #define ODS_REDUCED     0x00000002
 114
 115 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 116 #define ODT_EB0R        (0x80000000 >> 8)
 117 #define ODT_EB0W        (0x80000000 >> 7)
 118 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 119 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 120 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 121
 122 /* Defines for the Read Cycle Delay test */
 123 #define NUMMEMTESTS     8
 124 #define NUMMEMWORDS     8
 125 #define NUMLOOPS        64              /* memory test loops */
 126
 127 /*
 128  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
 129  * region. Right now the cache should still be disabled in U-Boot because of the
 130  * EMAC driver, that need it's buffer descriptor to be located in non cached
 131  * memory.
 132  *
 133  * If at some time this restriction doesn't apply anymore, just define
 134  * CONFIG_4xx_DCACHE in the board config file and this code should setup
 135  * everything correctly.
 136  */
 137 #ifdef CONFIG_4xx_DCACHE
 138 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
 139 #else
 140 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 141 #endif
 142
 143 /*
 144  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
 145  * To support such configurations, we "only" map the first 2GB via the TLB's. We
 146  * need some free virtual address space for the remaining peripherals like, SoC
 147  * devices, FLASH etc.
 148  *
 149  * Note that ECC is currently not supported on configurations with more than 2GB
 150  * SDRAM. This is because we only map the first 2GB on such systems, and therefore
 151  * the ECC parity byte of the remaining area can't be written.
 152  */
 153 #ifndef CONFIG_MAX_MEM_MAPPED
 154 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)2 << 30)
 155 #endif
 156
 157 /*
 158  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 159  */
 160 void __spd_ddr_init_hang (void)
 161 {
 162         hang ();
 163 }
 164 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 165
 166 /*
 167  * To provide an interface for board specific config values in this common
 168  * DDR setup code, we implement he "weak" default functions here. They return
 169  * the default value back to the caller.
 170  *
 171  * Please see include/configs/yucca.h for an example fora board specific
 172  * implementation.
 173  */
 174 u32 __ddr_wrdtr(u32 default_val)
 175 {
 176         return default_val;
 177 }
 178 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 179
 180 u32 __ddr_clktr(u32 default_val)
 181 {
 182         return default_val;
 183 }
 184 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 185
 186
 187 /* Private Structure Definitions */
 188
 189 /* enum only to ease code for cas latency setting */
 190 typedef enum ddr_cas_id {
 191         DDR_CAS_2      = 20,
 192         DDR_CAS_2_5    = 25,
 193         DDR_CAS_3      = 30,
 194         DDR_CAS_4      = 40,
 195         DDR_CAS_5      = 50
 196 } ddr_cas_id_t;
 197
 198 /*-----------------------------------------------------------------------------+
 199  * Prototypes
 200  *-----------------------------------------------------------------------------*/
 201 static phys_size_t sdram_memsize(void);
 202 static void get_spd_info(unsigned long *dimm_populated,
 203                          unsigned char *iic0_dimm_addr,
 204                          unsigned long num_dimm_banks);
 205 static void check_mem_type(unsigned long *dimm_populated,
 206                            unsigned char *iic0_dimm_addr,
 207                            unsigned long num_dimm_banks);
 208 static void check_frequency(unsigned long *dimm_populated,
 209                             unsigned char *iic0_dimm_addr,
 210                             unsigned long num_dimm_banks);
 211 static void check_rank_number(unsigned long *dimm_populated,
 212                               unsigned char *iic0_dimm_addr,
 213                               unsigned long num_dimm_banks);
 214 static void check_voltage_type(unsigned long *dimm_populated,
 215                                unsigned char *iic0_dimm_addr,
 216                                unsigned long num_dimm_banks);
 217 static void program_memory_queue(unsigned long *dimm_populated,
 218                                  unsigned char *iic0_dimm_addr,
 219                                  unsigned long num_dimm_banks);
 220 static void program_codt(unsigned long *dimm_populated,
 221                          unsigned char *iic0_dimm_addr,
 222                          unsigned long num_dimm_banks);
 223 static void program_mode(unsigned long *dimm_populated,
 224                          unsigned char *iic0_dimm_addr,
 225                          unsigned long num_dimm_banks,
 226                          ddr_cas_id_t *selected_cas,
 227                          int *write_recovery);
 228 static void program_tr(unsigned long *dimm_populated,
 229                        unsigned char *iic0_dimm_addr,
 230                        unsigned long num_dimm_banks);
 231 static void program_rtr(unsigned long *dimm_populated,
 232                         unsigned char *iic0_dimm_addr,
 233                         unsigned long num_dimm_banks);
 234 static void program_bxcf(unsigned long *dimm_populated,
 235                          unsigned char *iic0_dimm_addr,
 236                          unsigned long num_dimm_banks);
 237 static void program_copt1(unsigned long *dimm_populated,
 238                           unsigned char *iic0_dimm_addr,
 239                           unsigned long num_dimm_banks);
 240 static void program_initplr(unsigned long *dimm_populated,
 241                             unsigned char *iic0_dimm_addr,
 242                             unsigned long num_dimm_banks,
 243                             ddr_cas_id_t selected_cas,
 244                             int write_recovery);
 245 static unsigned long is_ecc_enabled(void);
 246 #ifdef CONFIG_DDR_ECC
 247 static void program_ecc(unsigned long *dimm_populated,
 248                         unsigned char *iic0_dimm_addr,
 249                         unsigned long num_dimm_banks,
 250                         unsigned long tlb_word2_i_value);
 251 static void program_ecc_addr(unsigned long start_address,
 252                              unsigned long num_bytes,
 253                              unsigned long tlb_word2_i_value);
 254 #endif
 255 static void program_DQS_calibration(unsigned long *dimm_populated,
 256                                     unsigned char *iic0_dimm_addr,
 257                                     unsigned long num_dimm_banks);
 258 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 259 static void     test(void);
 260 #else
 261 static void     DQS_calibration_process(void);
 262 #endif
 263 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 264 void dcbz_area(u32 start_address, u32 num_bytes);
 265
 266 static u32 mfdcr_any(u32 dcr)
 267 {
 268         u32 val;
 269
 270         switch (dcr) {
 271         case SDRAM_R0BAS + 0:
 272                 val = mfdcr(SDRAM_R0BAS + 0);
 273                 break;
 274         case SDRAM_R0BAS + 1:
 275                 val = mfdcr(SDRAM_R0BAS + 1);
 276                 break;
 277         case SDRAM_R0BAS + 2:
 278                 val = mfdcr(SDRAM_R0BAS + 2);
 279                 break;
 280         case SDRAM_R0BAS + 3:
 281                 val = mfdcr(SDRAM_R0BAS + 3);
 282                 break;
 283         default:
 284                 printf("DCR %d not defined in case statement!!!\n", dcr);
 285                 val = 0; /* just to satisfy the compiler */
 286         }
 287
 288         return val;
 289 }
 290
 291 static void mtdcr_any(u32 dcr, u32 val)
 292 {
 293         switch (dcr) {
 294         case SDRAM_R0BAS + 0:
 295                 mtdcr(SDRAM_R0BAS + 0, val);
 296                 break;
 297         case SDRAM_R0BAS + 1:
 298                 mtdcr(SDRAM_R0BAS + 1, val);
 299                 break;
 300         case SDRAM_R0BAS + 2:
 301                 mtdcr(SDRAM_R0BAS + 2, val);
 302                 break;
 303         case SDRAM_R0BAS + 3:
 304                 mtdcr(SDRAM_R0BAS + 3, val);
 305                 break;
 306         default:
 307                 printf("DCR %d not defined in case statement!!!\n", dcr);
 308         }
 309 }
 310
 311 static unsigned char spd_read(uchar chip, uint addr)
 312 {
 313         unsigned char data[2];
 314
 315         if (i2c_probe(chip) == 0)
 316                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 317                         return data[0];
 318
 319         return 0;
 320 }
 321
 322 /*-----------------------------------------------------------------------------+
 323  * sdram_memsize
 324  *-----------------------------------------------------------------------------*/
 325 static phys_size_t sdram_memsize(void)
 326 {
 327         phys_size_t mem_size;
 328         unsigned long mcopt2;
 329         unsigned long mcstat;
 330         unsigned long mb0cf;
 331         unsigned long sdsz;
 332         unsigned long i;
 333
 334         mem_size = 0;
 335
 336         mfsdram(SDRAM_MCOPT2, mcopt2);
 337         mfsdram(SDRAM_MCSTAT, mcstat);
 338
 339         /* DDR controller must be enabled and not in self-refresh. */
 340         /* Otherwise memsize is zero. */
 341         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 342             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 343             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 344                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 345                 for (i = 0; i < MAXBXCF; i++) {
 346                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 347                         /* Banks enabled */
 348                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 349                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 350
 351                                 switch(sdsz) {
 352                                 case SDRAM_RXBAS_SDSZ_8:
 353                                         mem_size+=8;
 354                                         break;
 355                                 case SDRAM_RXBAS_SDSZ_16:
 356                                         mem_size+=16;
 357                                         break;
 358                                 case SDRAM_RXBAS_SDSZ_32:
 359                                         mem_size+=32;
 360                                         break;
 361                                 case SDRAM_RXBAS_SDSZ_64:
 362                                         mem_size+=64;
 363                                         break;
 364                                 case SDRAM_RXBAS_SDSZ_128:
 365                                         mem_size+=128;
 366                                         break;
 367                                 case SDRAM_RXBAS_SDSZ_256:
 368                                         mem_size+=256;
 369                                         break;
 370                                 case SDRAM_RXBAS_SDSZ_512:
 371                                         mem_size+=512;
 372                                         break;
 373                                 case SDRAM_RXBAS_SDSZ_1024:
 374                                         mem_size+=1024;
 375                                         break;
 376                                 case SDRAM_RXBAS_SDSZ_2048:
 377                                         mem_size+=2048;
 378                                         break;
 379                                 case SDRAM_RXBAS_SDSZ_4096:
 380                                         mem_size+=4096;
 381                                         break;
 382                                 default:
 383                                         printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
 384                                                , sdsz);
 385                                         mem_size=0;
 386                                         break;
 387                                 }
 388                         }
 389                 }
 390         }
 391
 392         return mem_size << 20;
 393 }
 394
 395 /*-----------------------------------------------------------------------------+
 396  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 397  * Note: This routine runs from flash with a stack set up in the chip's
 398  * sram space.  It is important that the routine does not require .sbss, .bss or
 399  * .data sections.  It also cannot call routines that require these sections.
 400  *-----------------------------------------------------------------------------*/
 401 /*-----------------------------------------------------------------------------
 402  * Function:     initdram
 403  * Description:  Configures SDRAM memory banks for DDR operation.
 404  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 405  *               via the IIC bus and then configures the DDR SDRAM memory
 406  *               banks appropriately. If Auto Memory Configuration is
 407  *               not used, it is assumed that no DIMM is plugged
 408  *-----------------------------------------------------------------------------*/
 409 phys_size_t initdram(int board_type)
 410 {
 411         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 412         unsigned char spd0[MAX_SPD_BYTES];
 413         unsigned char spd1[MAX_SPD_BYTES];
 414         unsigned char *dimm_spd[MAXDIMMS];
 415         unsigned long dimm_populated[MAXDIMMS];
 416         unsigned long num_dimm_banks;           /* on board dimm banks */
 417         unsigned long val;
 418         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 419         int write_recovery;
 420         phys_size_t dram_size = 0;
 421
 422         num_dimm_banks = sizeof(iic0_dimm_addr);
 423
 424         /*------------------------------------------------------------------
 425          * Set up an array of SPD matrixes.
 426          *-----------------------------------------------------------------*/
 427         dimm_spd[0] = spd0;
 428         dimm_spd[1] = spd1;
 429
 430         /*------------------------------------------------------------------
 431          * Reset the DDR-SDRAM controller.
 432          *-----------------------------------------------------------------*/
 433         mtsdr(SDR0_SRST, (0x80000000 >> 10));
 434         mtsdr(SDR0_SRST, 0x00000000);
 435
 436         /*
 437          * Make sure I2C controller is initialized
 438          * before continuing.
 439          */
 440
 441         /* switch to correct I2C bus */
 442         I2C_SET_BUS(CFG_SPD_BUS_NUM);
 443         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 444
 445         /*------------------------------------------------------------------
 446          * Clear out the serial presence detect buffers.
 447          * Perform IIC reads from the dimm.  Fill in the spds.
 448          * Check to see if the dimm slots are populated
 449          *-----------------------------------------------------------------*/
 450         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 451
 452         /*------------------------------------------------------------------
 453          * Check the memory type for the dimms plugged.
 454          *-----------------------------------------------------------------*/
 455         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 456
 457         /*------------------------------------------------------------------
 458          * Check the frequency supported for the dimms plugged.
 459          *-----------------------------------------------------------------*/
 460         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 461
 462         /*------------------------------------------------------------------
 463          * Check the total rank number.
 464          *-----------------------------------------------------------------*/
 465         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 466
 467         /*------------------------------------------------------------------
 468          * Check the voltage type for the dimms plugged.
 469          *-----------------------------------------------------------------*/
 470         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 471
 472         /*------------------------------------------------------------------
 473          * Program SDRAM controller options 2 register
 474          * Except Enabling of the memory controller.
 475          *-----------------------------------------------------------------*/
 476         mfsdram(SDRAM_MCOPT2, val);
 477         mtsdram(SDRAM_MCOPT2,
 478                 (val &
 479                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 480                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 481                    SDRAM_MCOPT2_ISIE_MASK))
 482                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 483                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 484                    SDRAM_MCOPT2_ISIE_ENABLE));
 485
 486         /*------------------------------------------------------------------
 487          * Program SDRAM controller options 1 register
 488          * Note: Does not enable the memory controller.
 489          *-----------------------------------------------------------------*/
 490         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 491
 492         /*------------------------------------------------------------------
 493          * Set the SDRAM Controller On Die Termination Register
 494          *-----------------------------------------------------------------*/
 495         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 496
 497         /*------------------------------------------------------------------
 498          * Program SDRAM refresh register.
 499          *-----------------------------------------------------------------*/
 500         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 501
 502         /*------------------------------------------------------------------
 503          * Program SDRAM mode register.
 504          *-----------------------------------------------------------------*/
 505         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 506                      &selected_cas, &write_recovery);
 507
 508         /*------------------------------------------------------------------
 509          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 510          *-----------------------------------------------------------------*/
 511         mfsdram(SDRAM_WRDTR, val);
 512         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 513                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 514
 515         /*------------------------------------------------------------------
 516          * Set the SDRAM Clock Timing Register
 517          *-----------------------------------------------------------------*/
 518         mfsdram(SDRAM_CLKTR, val);
 519         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 520                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 521
 522         /*------------------------------------------------------------------
 523          * Program the BxCF registers.
 524          *-----------------------------------------------------------------*/
 525         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 526
 527         /*------------------------------------------------------------------
 528          * Program SDRAM timing registers.
 529          *-----------------------------------------------------------------*/
 530         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 531
 532         /*------------------------------------------------------------------
 533          * Set the Extended Mode register
 534          *-----------------------------------------------------------------*/
 535         mfsdram(SDRAM_MEMODE, val);
 536         mtsdram(SDRAM_MEMODE,
 537                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 538                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 539                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 540                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 541
 542         /*------------------------------------------------------------------
 543          * Program Initialization preload registers.
 544          *-----------------------------------------------------------------*/
 545         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 546                         selected_cas, write_recovery);
 547
 548         /*------------------------------------------------------------------
 549          * Delay to ensure 200usec have elapsed since reset.
 550          *-----------------------------------------------------------------*/
 551         udelay(400);
 552
 553         /*------------------------------------------------------------------
 554          * Set the memory queue core base addr.
 555          *-----------------------------------------------------------------*/
 556         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 557
 558         /*------------------------------------------------------------------
 559          * Program SDRAM controller options 2 register
 560          * Enable the memory controller.
 561          *-----------------------------------------------------------------*/
 562         mfsdram(SDRAM_MCOPT2, val);
 563         mtsdram(SDRAM_MCOPT2,
 564                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 565                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 566                 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
 567
 568         /*------------------------------------------------------------------
 569          * Wait for SDRAM_CFG0_DC_EN to complete.
 570          *-----------------------------------------------------------------*/
 571         do {
 572                 mfsdram(SDRAM_MCSTAT, val);
 573         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 574
 575         /* get installed memory size */
 576         dram_size = sdram_memsize();
 577
 578         /*
 579          * Limit size to 2GB
 580          */
 581         if (dram_size > CONFIG_MAX_MEM_MAPPED)
 582                 dram_size = CONFIG_MAX_MEM_MAPPED;
 583
 584         /* and program tlb entries for this size (dynamic) */
 585
 586         /*
 587          * Program TLB entries with caches enabled, for best performace
 588          * while auto-calibrating and ECC generation
 589          */
 590         program_tlb(0, 0, dram_size, 0);
 591
 592         /*------------------------------------------------------------------
 593          * DQS calibration.
 594          *-----------------------------------------------------------------*/
 595         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 596
 597 #ifdef CONFIG_DDR_ECC
 598         /*------------------------------------------------------------------
 599          * If ecc is enabled, initialize the parity bits.
 600          *-----------------------------------------------------------------*/
 601         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 602 #endif
 603
 604         /*
 605          * Now after initialization (auto-calibration and ECC generation)
 606          * remove the TLB entries with caches enabled and program again with
 607          * desired cache functionality
 608          */
 609         remove_tlb(0, dram_size);
 610         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 611
 612         ppc4xx_ibm_ddr2_register_dump();
 613
 614         /*
 615          * Clear potential errors resulting from auto-calibration.
 616          * If not done, then we could get an interrupt later on when
 617          * exceptions are enabled.
 618          */
 619         set_mcsr(get_mcsr());
 620
 621         return sdram_memsize();
 622 }
 623
 624 static void get_spd_info(unsigned long *dimm_populated,
 625                          unsigned char *iic0_dimm_addr,
 626                          unsigned long num_dimm_banks)
 627 {
 628         unsigned long dimm_num;
 629         unsigned long dimm_found;
 630         unsigned char num_of_bytes;
 631         unsigned char total_size;
 632
 633         dimm_found = FALSE;
 634         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 635                 num_of_bytes = 0;
 636                 total_size = 0;
 637
 638                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 639                 debug("\nspd_read(0x%x) returned %d\n",
 640                       iic0_dimm_addr[dimm_num], num_of_bytes);
 641                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 642                 debug("spd_read(0x%x) returned %d\n",
 643                       iic0_dimm_addr[dimm_num], total_size);
 644
 645                 if ((num_of_bytes != 0) && (total_size != 0)) {
 646                         dimm_populated[dimm_num] = TRUE;
 647                         dimm_found = TRUE;
 648                         debug("DIMM slot %lu: populated\n", dimm_num);
 649                 } else {
 650                         dimm_populated[dimm_num] = FALSE;
 651                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 652                 }
 653         }
 654
 655         if (dimm_found == FALSE) {
 656                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 657                 spd_ddr_init_hang ();
 658         }
 659 }
 660
 661 void board_add_ram_info(int use_default)
 662 {
 663         PPC4xx_SYS_INFO board_cfg;
 664         u32 val;
 665
 666         if (is_ecc_enabled())
 667                 puts(" (ECC");
 668         else
 669                 puts(" (ECC not");
 670
 671         get_sys_info(&board_cfg);
 672
 673         mfsdr(SDR0_DDR0, val);
 674         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 675         printf(" enabled, %d MHz", (val * 2) / 1000000);
 676
 677         mfsdram(SDRAM_MMODE, val);
 678         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 679         printf(", CL%d)", val);
 680 }
 681
 682 /*------------------------------------------------------------------
 683  * For the memory DIMMs installed, this routine verifies that they
 684  * really are DDR specific DIMMs.
 685  *-----------------------------------------------------------------*/
 686 static void check_mem_type(unsigned long *dimm_populated,
 687                            unsigned char *iic0_dimm_addr,
 688                            unsigned long num_dimm_banks)
 689 {
 690         unsigned long dimm_num;
 691         unsigned long dimm_type;
 692
 693         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 694                 if (dimm_populated[dimm_num] == TRUE) {
 695                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 696                         switch (dimm_type) {
 697                         case 1:
 698                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 699                                        "slot %d.\n", (unsigned int)dimm_num);
 700                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 701                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 702                                 spd_ddr_init_hang ();
 703                                 break;
 704                         case 2:
 705                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 706                                        (unsigned int)dimm_num);
 707                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 708                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 709                                 spd_ddr_init_hang ();
 710                                 break;
 711                         case 3:
 712                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 713                                        (unsigned int)dimm_num);
 714                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 715                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 716                                 spd_ddr_init_hang ();
 717                                 break;
 718                         case 4:
 719                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 720                                        (unsigned int)dimm_num);
 721                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 722                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 723                                 spd_ddr_init_hang ();
 724                                 break;
 725                         case 5:
 726                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 727                                        (unsigned int)dimm_num);
 728                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 729                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 730                                 spd_ddr_init_hang ();
 731                                 break;
 732                         case 6:
 733                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 734                                        (unsigned int)dimm_num);
 735                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 736                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 737                                 spd_ddr_init_hang ();
 738                                 break;
 739                         case 7:
 740                                 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
 741                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 742                                 break;
 743                         case 8:
 744                                 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
 745                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 746                                 break;
 747                         default:
 748                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 749                                        (unsigned int)dimm_num);
 750                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 751                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 752                                 spd_ddr_init_hang ();
 753                                 break;
 754                         }
 755                 }
 756         }
 757         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 758                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 759                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 760                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 761                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 762                         spd_ddr_init_hang ();
 763                 }
 764         }
 765 }
 766
 767 /*------------------------------------------------------------------
 768  * For the memory DIMMs installed, this routine verifies that
 769  * frequency previously calculated is supported.
 770  *-----------------------------------------------------------------*/
 771 static void check_frequency(unsigned long *dimm_populated,
 772                             unsigned char *iic0_dimm_addr,
 773                             unsigned long num_dimm_banks)
 774 {
 775         unsigned long dimm_num;
 776         unsigned long tcyc_reg;
 777         unsigned long cycle_time;
 778         unsigned long calc_cycle_time;
 779         unsigned long sdram_freq;
 780         unsigned long sdr_ddrpll;
 781         PPC4xx_SYS_INFO board_cfg;
 782
 783         /*------------------------------------------------------------------
 784          * Get the board configuration info.
 785          *-----------------------------------------------------------------*/
 786         get_sys_info(&board_cfg);
 787
 788         mfsdr(SDR0_DDR0, sdr_ddrpll);
 789         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 790
 791         /*
 792          * calc_cycle_time is calculated from DDR frequency set by board/chip
 793          * and is expressed in multiple of 10 picoseconds
 794          * to match the way DIMM cycle time is calculated below.
 795          */
 796         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 797
 798         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 799                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 800                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 801                         /*
 802                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 803                          * the higher order nibble (bits 4-7) designates the cycle time
 804                          * to a granularity of 1ns;
 805                          * the value presented by the lower order nibble (bits 0-3)
 806                          * has a granularity of .1ns and is added to the value designated
 807                          * by the higher nibble. In addition, four lines of the lower order
 808                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 809                          */
 810                          /* Convert from hex to decimal */
 811                         if ((tcyc_reg & 0x0F) == 0x0D)
 812                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 813                         else if ((tcyc_reg & 0x0F) == 0x0C)
 814                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 815                         else if ((tcyc_reg & 0x0F) == 0x0B)
 816                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 817                         else if ((tcyc_reg & 0x0F) == 0x0A)
 818                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 819                         else
 820                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 821                                         ((tcyc_reg & 0x0F)*10);
 822                         debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
 823
 824                         if  (cycle_time > (calc_cycle_time + 10)) {
 825                                 /*
 826                                  * the provided sdram cycle_time is too small
 827                                  * for the available DIMM cycle_time.
 828                                  * The additionnal 100ps is here to accept a small incertainty.
 829                                  */
 830                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 831                                        "slot %d \n while calculated cycle time is %d ps.\n",
 832                                        (unsigned int)(cycle_time*10),
 833                                        (unsigned int)dimm_num,
 834                                        (unsigned int)(calc_cycle_time*10));
 835                                 printf("Replace the DIMM, or change DDR frequency via "
 836                                        "strapping bits.\n\n");
 837                                 spd_ddr_init_hang ();
 838                         }
 839                 }
 840         }
 841 }
 842
 843 /*------------------------------------------------------------------
 844  * For the memory DIMMs installed, this routine verifies two
 845  * ranks/banks maximum are availables.
 846  *-----------------------------------------------------------------*/
 847 static void check_rank_number(unsigned long *dimm_populated,
 848                               unsigned char *iic0_dimm_addr,
 849                               unsigned long num_dimm_banks)
 850 {
 851         unsigned long dimm_num;
 852         unsigned long dimm_rank;
 853         unsigned long total_rank = 0;
 854
 855         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 856                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 857                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 858                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 859                                 dimm_rank = (dimm_rank & 0x0F) +1;
 860                         else
 861                                 dimm_rank = dimm_rank & 0x0F;
 862
 863
 864                         if (dimm_rank > MAXRANKS) {
 865                                 printf("ERROR: DRAM DIMM detected with %lu ranks in "
 866                                        "slot %lu is not supported.\n", dimm_rank, dimm_num);
 867                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 868                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 869                                 spd_ddr_init_hang ();
 870                         } else
 871                                 total_rank += dimm_rank;
 872                 }
 873                 if (total_rank > MAXRANKS) {
 874                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 875                                "for all slots.\n", (unsigned int)total_rank);
 876                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 877                         printf("Remove one of the DIMM modules.\n\n");
 878                         spd_ddr_init_hang ();
 879                 }
 880         }
 881 }
 882
 883 /*------------------------------------------------------------------
 884  * only support 2.5V modules.
 885  * This routine verifies this.
 886  *-----------------------------------------------------------------*/
 887 static void check_voltage_type(unsigned long *dimm_populated,
 888                                unsigned char *iic0_dimm_addr,
 889                                unsigned long num_dimm_banks)
 890 {
 891         unsigned long dimm_num;
 892         unsigned long voltage_type;
 893
 894         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 895                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 896                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 897                         switch (voltage_type) {
 898                         case 0x00:
 899                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 900                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 901                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 902                                        (unsigned int)dimm_num);
 903                                 spd_ddr_init_hang ();
 904                                 break;
 905                         case 0x01:
 906                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 907                                 printf("This DIMM is LVTTL.\n");
 908                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 909                                        (unsigned int)dimm_num);
 910                                 spd_ddr_init_hang ();
 911                                 break;
 912                         case 0x02:
 913                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 914                                 printf("This DIMM is 1.5 Volt.\n");
 915                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 916                                        (unsigned int)dimm_num);
 917                                 spd_ddr_init_hang ();
 918                                 break;
 919                         case 0x03:
 920                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 921                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 922                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 923                                        (unsigned int)dimm_num);
 924                                 spd_ddr_init_hang ();
 925                                 break;
 926                         case 0x04:
 927                                 /* 2.5 Voltage only for DDR1 */
 928                                 break;
 929                         case 0x05:
 930                                 /* 1.8 Voltage only for DDR2 */
 931                                 break;
 932                         default:
 933                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 934                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 935                                        (unsigned int)dimm_num);
 936                                 spd_ddr_init_hang ();
 937                                 break;
 938                         }
 939                 }
 940         }
 941 }
 942
 943 /*-----------------------------------------------------------------------------+
 944  * program_copt1.
 945  *-----------------------------------------------------------------------------*/
 946 static void program_copt1(unsigned long *dimm_populated,
 947                           unsigned char *iic0_dimm_addr,
 948                           unsigned long num_dimm_banks)
 949 {
 950         unsigned long dimm_num;
 951         unsigned long mcopt1;
 952         unsigned long ecc_enabled;
 953         unsigned long ecc = 0;
 954         unsigned long data_width = 0;
 955         unsigned long dimm_32bit;
 956         unsigned long dimm_64bit;
 957         unsigned long registered = 0;
 958         unsigned long attribute = 0;
 959         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 960         unsigned long bankcount;
 961         unsigned long ddrtype;
 962         unsigned long val;
 963
 964 #ifdef CONFIG_DDR_ECC
 965         ecc_enabled = TRUE;
 966 #else
 967         ecc_enabled = FALSE;
 968 #endif
 969         dimm_32bit = FALSE;
 970         dimm_64bit = FALSE;
 971         buf0 = FALSE;
 972         buf1 = FALSE;
 973
 974         /*------------------------------------------------------------------
 975          * Set memory controller options reg 1, SDRAM_MCOPT1.
 976          *-----------------------------------------------------------------*/
 977         mfsdram(SDRAM_MCOPT1, val);
 978         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 979                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 980                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 981                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 982                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
 983                          SDRAM_MCOPT1_DREF_MASK);
 984
 985         mcopt1 |= SDRAM_MCOPT1_QDEP;
 986         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
 987         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
 988         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
 989         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
 990         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
 991
 992         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 993                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 994                         /* test ecc support */
 995                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 996                         if (ecc != 0x02) /* ecc not supported */
 997                                 ecc_enabled = FALSE;
 998
 999                         /* test bank count */
1000                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1001                         if (bankcount == 0x04) /* bank count = 4 */
1002                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1003                         else /* bank count = 8 */
1004                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1005
1006                         /* test DDR type */
1007                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
1008                         /* test for buffered/unbuffered, registered, differential clocks */
1009                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1010                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1011
1012                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1013                         if (dimm_num == 0) {
1014                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1015                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1016                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1017                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1018                                 if (registered == 1) { /* DDR2 always buffered */
1019                                         /* TODO: what about above  comments ? */
1020                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1021                                         buf0 = TRUE;
1022                                 } else {
1023                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1024                                         if ((attribute & 0x02) == 0x00) {
1025                                                 /* buffered not supported */
1026                                                 buf0 = FALSE;
1027                                         } else {
1028                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1029                                                 buf0 = TRUE;
1030                                         }
1031                                 }
1032                         }
1033                         else if (dimm_num == 1) {
1034                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1035                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1036                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1037                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1038                                 if (registered == 1) {
1039                                         /* DDR2 always buffered */
1040                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1041                                         buf1 = TRUE;
1042                                 } else {
1043                                         if ((attribute & 0x02) == 0x00) {
1044                                                 /* buffered not supported */
1045                                                 buf1 = FALSE;
1046                                         } else {
1047                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1048                                                 buf1 = TRUE;
1049                                         }
1050                                 }
1051                         }
1052
1053                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1054                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1055                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1056
1057                         switch (data_width) {
1058                         case 72:
1059                         case 64:
1060                                 dimm_64bit = TRUE;
1061                                 break;
1062                         case 40:
1063                         case 32:
1064                                 dimm_32bit = TRUE;
1065                                 break;
1066                         default:
1067                                 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1068                                        data_width);
1069                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1070                                 break;
1071                         }
1072                 }
1073         }
1074
1075         /* verify matching properties */
1076         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1077                 if (buf0 != buf1) {
1078                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1079                         spd_ddr_init_hang ();
1080                 }
1081         }
1082
1083         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1084                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1085                 spd_ddr_init_hang ();
1086         }
1087         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1088                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1089         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1090                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1091         } else {
1092                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1093                 spd_ddr_init_hang ();
1094         }
1095
1096         if (ecc_enabled == TRUE)
1097                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1098         else
1099                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1100
1101         mtsdram(SDRAM_MCOPT1, mcopt1);
1102 }
1103
1104 /*-----------------------------------------------------------------------------+
1105  * program_codt.
1106  *-----------------------------------------------------------------------------*/
1107 static void program_codt(unsigned long *dimm_populated,
1108                          unsigned char *iic0_dimm_addr,
1109                          unsigned long num_dimm_banks)
1110 {
1111         unsigned long codt;
1112         unsigned long modt0 = 0;
1113         unsigned long modt1 = 0;
1114         unsigned long modt2 = 0;
1115         unsigned long modt3 = 0;
1116         unsigned char dimm_num;
1117         unsigned char dimm_rank;
1118         unsigned char total_rank = 0;
1119         unsigned char total_dimm = 0;
1120         unsigned char dimm_type = 0;
1121         unsigned char firstSlot = 0;
1122
1123         /*------------------------------------------------------------------
1124          * Set the SDRAM Controller On Die Termination Register
1125          *-----------------------------------------------------------------*/
1126         mfsdram(SDRAM_CODT, codt);
1127         codt |= (SDRAM_CODT_IO_NMODE
1128                  & (~SDRAM_CODT_DQS_SINGLE_END
1129                     & ~SDRAM_CODT_CKSE_SINGLE_END
1130                     & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1131                     & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1132
1133         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1134                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1135                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1136                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1137                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1138                                 dimm_type = SDRAM_DDR2;
1139                         } else {
1140                                 dimm_rank = dimm_rank & 0x0F;
1141                                 dimm_type = SDRAM_DDR1;
1142                         }
1143
1144                         total_rank += dimm_rank;
1145                         total_dimm++;
1146                         if ((dimm_num == 0) && (total_dimm == 1))
1147                                 firstSlot = TRUE;
1148                         else
1149                                 firstSlot = FALSE;
1150                 }
1151         }
1152         if (dimm_type == SDRAM_DDR2) {
1153                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1154                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1155                         if (total_rank == 1) {
1156                                 codt |= CALC_ODT_R(0);
1157                                 modt0 = CALC_ODT_W(0);
1158                                 modt1 = 0x00000000;
1159                                 modt2 = 0x00000000;
1160                                 modt3 = 0x00000000;
1161                         }
1162                         if (total_rank == 2) {
1163                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1164                                 modt0 = CALC_ODT_W(0);
1165                                 modt1 = CALC_ODT_W(0);
1166                                 modt2 = 0x00000000;
1167                                 modt3 = 0x00000000;
1168                         }
1169                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1170                         if (total_rank == 1) {
1171                                 codt |= CALC_ODT_R(2);
1172                                 modt0 = 0x00000000;
1173                                 modt1 = 0x00000000;
1174                                 modt2 = CALC_ODT_W(2);
1175                                 modt3 = 0x00000000;
1176                         }
1177                         if (total_rank == 2) {
1178                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1179                                 modt0 = 0x00000000;
1180                                 modt1 = 0x00000000;
1181                                 modt2 = CALC_ODT_W(2);
1182                                 modt3 = CALC_ODT_W(2);
1183                         }
1184                 }
1185                 if (total_dimm == 2) {
1186                         if (total_rank == 2) {
1187                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1188                                 modt0 = CALC_ODT_RW(2);
1189                                 modt1 = 0x00000000;
1190                                 modt2 = CALC_ODT_RW(0);
1191                                 modt3 = 0x00000000;
1192                         }
1193                         if (total_rank == 4) {
1194                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1195                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1196                                 modt0 = CALC_ODT_RW(2);
1197                                 modt1 = 0x00000000;
1198                                 modt2 = CALC_ODT_RW(0);
1199                                 modt3 = 0x00000000;
1200                         }
1201                 }
1202         } else {
1203                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1204                 modt0 = 0x00000000;
1205                 modt1 = 0x00000000;
1206                 modt2 = 0x00000000;
1207                 modt3 = 0x00000000;
1208
1209                 if (total_dimm == 1) {
1210                         if (total_rank == 1)
1211                                 codt |= 0x00800000;
1212                         if (total_rank == 2)
1213                                 codt |= 0x02800000;
1214                 }
1215                 if (total_dimm == 2) {
1216                         if (total_rank == 2)
1217                                 codt |= 0x08800000;
1218                         if (total_rank == 4)
1219                                 codt |= 0x2a800000;
1220                 }
1221         }
1222
1223         debug("nb of dimm %d\n", total_dimm);
1224         debug("nb of rank %d\n", total_rank);
1225         if (total_dimm == 1)
1226                 debug("dimm in slot %d\n", firstSlot);
1227
1228         mtsdram(SDRAM_CODT, codt);
1229         mtsdram(SDRAM_MODT0, modt0);
1230         mtsdram(SDRAM_MODT1, modt1);
1231         mtsdram(SDRAM_MODT2, modt2);
1232         mtsdram(SDRAM_MODT3, modt3);
1233 }
1234
1235 /*-----------------------------------------------------------------------------+
1236  * program_initplr.
1237  *-----------------------------------------------------------------------------*/
1238 static void program_initplr(unsigned long *dimm_populated,
1239                             unsigned char *iic0_dimm_addr,
1240                             unsigned long num_dimm_banks,
1241                             ddr_cas_id_t selected_cas,
1242                             int write_recovery)
1243 {
1244         u32 cas = 0;
1245         u32 odt = 0;
1246         u32 ods = 0;
1247         u32 mr;
1248         u32 wr;
1249         u32 emr;
1250         u32 emr2;
1251         u32 emr3;
1252         int dimm_num;
1253         int total_dimm = 0;
1254
1255         /******************************************************
1256          ** Assumption: if more than one DIMM, all DIMMs are the same
1257          **             as already checked in check_memory_type
1258          ******************************************************/
1259
1260         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1261                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1262                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1263                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1264                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1265                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1266                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1267                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1268                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1269         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1270                 switch (selected_cas) {
1271                 case DDR_CAS_3:
1272                         cas = 3 << 4;
1273                         break;
1274                 case DDR_CAS_4:
1275                         cas = 4 << 4;
1276                         break;
1277                 case DDR_CAS_5:
1278                         cas = 5 << 4;
1279                         break;
1280                 default:
1281                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1282                         spd_ddr_init_hang ();
1283                         break;
1284                 }
1285
1286 #if 0
1287                 /*
1288                  * ToDo - Still a problem with the write recovery:
1289                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1290                  * in the INITPLR reg to the value calculated in program_mode()
1291                  * results in not correctly working DDR2 memory (crash after
1292                  * relocation).
1293                  *
1294                  * So for now, set the write recovery to 3. This seems to work
1295                  * on the Corair module too.
1296                  *
1297                  * 2007-03-01, sr
1298                  */
1299                 switch (write_recovery) {
1300                 case 3:
1301                         wr = WRITE_RECOV_3;
1302                         break;
1303                 case 4:
1304                         wr = WRITE_RECOV_4;
1305                         break;
1306                 case 5:
1307                         wr = WRITE_RECOV_5;
1308                         break;
1309                 case 6:
1310                         wr = WRITE_RECOV_6;
1311                         break;
1312                 default:
1313                         printf("ERROR: write recovery not support (%d)", write_recovery);
1314                         spd_ddr_init_hang ();
1315                         break;
1316                 }
1317 #else
1318                 wr = WRITE_RECOV_3; /* test-only, see description above */
1319 #endif
1320
1321                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1322                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1323                                 total_dimm++;
1324                 if (total_dimm == 1) {
1325                         odt = ODT_150_OHM;
1326                         ods = ODS_FULL;
1327                 } else if (total_dimm == 2) {
1328                         odt = ODT_75_OHM;
1329                         ods = ODS_REDUCED;
1330                 } else {
1331                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1332                         spd_ddr_init_hang ();
1333                 }
1334
1335                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1336                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1337                 emr2 = CMD_EMR | SELECT_EMR2;
1338                 emr3 = CMD_EMR | SELECT_EMR3;
1339                 mtsdram(SDRAM_INITPLR0,  0xB5000000 | CMD_NOP);         /* NOP */
1340                 udelay(1000);
1341                 mtsdram(SDRAM_INITPLR1,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1342                 mtsdram(SDRAM_INITPLR2,  0x80800000 | emr2);            /* EMR2 */
1343                 mtsdram(SDRAM_INITPLR3,  0x80800000 | emr3);            /* EMR3 */
1344                 mtsdram(SDRAM_INITPLR4,  0x80800000 | emr);             /* EMR DLL ENABLE */
1345                 mtsdram(SDRAM_INITPLR5,  0x80800000 | mr | DLL_RESET);  /* MR w/ DLL reset */
1346                 udelay(1000);
1347                 mtsdram(SDRAM_INITPLR6,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1348                 mtsdram(SDRAM_INITPLR7,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1349                 mtsdram(SDRAM_INITPLR8,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1350                 mtsdram(SDRAM_INITPLR9,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1351                 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1352                 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr);              /* MR w/o DLL reset */
1353                 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr);             /* EMR OCD Default */
1354                 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr);             /* EMR OCD Exit */
1355         } else {
1356                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1357                 spd_ddr_init_hang ();
1358         }
1359 }
1360
1361 /*------------------------------------------------------------------
1362  * This routine programs the SDRAM_MMODE register.
1363  * the selected_cas is an output parameter, that will be passed
1364  * by caller to call the above program_initplr( )
1365  *-----------------------------------------------------------------*/
1366 static void program_mode(unsigned long *dimm_populated,
1367                          unsigned char *iic0_dimm_addr,
1368                          unsigned long num_dimm_banks,
1369                          ddr_cas_id_t *selected_cas,
1370                          int *write_recovery)
1371 {
1372         unsigned long dimm_num;
1373         unsigned long sdram_ddr1;
1374         unsigned long t_wr_ns;
1375         unsigned long t_wr_clk;
1376         unsigned long cas_bit;
1377         unsigned long cas_index;
1378         unsigned long sdram_freq;
1379         unsigned long ddr_check;
1380         unsigned long mmode;
1381         unsigned long tcyc_reg;
1382         unsigned long cycle_2_0_clk;
1383         unsigned long cycle_2_5_clk;
1384         unsigned long cycle_3_0_clk;
1385         unsigned long cycle_4_0_clk;
1386         unsigned long cycle_5_0_clk;
1387         unsigned long max_2_0_tcyc_ns_x_100;
1388         unsigned long max_2_5_tcyc_ns_x_100;
1389         unsigned long max_3_0_tcyc_ns_x_100;
1390         unsigned long max_4_0_tcyc_ns_x_100;
1391         unsigned long max_5_0_tcyc_ns_x_100;
1392         unsigned long cycle_time_ns_x_100[3];
1393         PPC4xx_SYS_INFO board_cfg;
1394         unsigned char cas_2_0_available;
1395         unsigned char cas_2_5_available;
1396         unsigned char cas_3_0_available;
1397         unsigned char cas_4_0_available;
1398         unsigned char cas_5_0_available;
1399         unsigned long sdr_ddrpll;
1400
1401         /*------------------------------------------------------------------
1402          * Get the board configuration info.
1403          *-----------------------------------------------------------------*/
1404         get_sys_info(&board_cfg);
1405
1406         mfsdr(SDR0_DDR0, sdr_ddrpll);
1407         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1408         debug("sdram_freq=%d\n", sdram_freq);
1409
1410         /*------------------------------------------------------------------
1411          * Handle the timing.  We need to find the worst case timing of all
1412          * the dimm modules installed.
1413          *-----------------------------------------------------------------*/
1414         t_wr_ns = 0;
1415         cas_2_0_available = TRUE;
1416         cas_2_5_available = TRUE;
1417         cas_3_0_available = TRUE;
1418         cas_4_0_available = TRUE;
1419         cas_5_0_available = TRUE;
1420         max_2_0_tcyc_ns_x_100 = 10;
1421         max_2_5_tcyc_ns_x_100 = 10;
1422         max_3_0_tcyc_ns_x_100 = 10;
1423         max_4_0_tcyc_ns_x_100 = 10;
1424         max_5_0_tcyc_ns_x_100 = 10;
1425         sdram_ddr1 = TRUE;
1426
1427         /* loop through all the DIMM slots on the board */
1428         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1429                 /* If a dimm is installed in a particular slot ... */
1430                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1431                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1432                                 sdram_ddr1 = TRUE;
1433                         else
1434                                 sdram_ddr1 = FALSE;
1435
1436                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1437                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1438                         debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1439
1440                         /* For a particular DIMM, grab the three CAS values it supports */
1441                         for (cas_index = 0; cas_index < 3; cas_index++) {
1442                                 switch (cas_index) {
1443                                 case 0:
1444                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1445                                         break;
1446                                 case 1:
1447                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1448                                         break;
1449                                 default:
1450                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1451                                         break;
1452                                 }
1453
1454                                 if ((tcyc_reg & 0x0F) >= 10) {
1455                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1456                                                 /* Convert from hex to decimal */
1457                                                 cycle_time_ns_x_100[cas_index] =
1458                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1459                                         } else {
1460                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1461                                                        "in slot %d\n", (unsigned int)dimm_num);
1462                                                 spd_ddr_init_hang ();
1463                                         }
1464                                 } else {
1465                                         /* Convert from hex to decimal */
1466                                         cycle_time_ns_x_100[cas_index] =
1467                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1468                                                 ((tcyc_reg & 0x0F)*10);
1469                                 }
1470                                 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1471                                       cycle_time_ns_x_100[cas_index]);
1472                         }
1473
1474                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1475                         /* supported for a particular DIMM. */
1476                         cas_index = 0;
1477
1478                         if (sdram_ddr1) {
1479                                 /*
1480                                  * DDR devices use the following bitmask for CAS latency:
1481                                  *  Bit   7    6    5    4    3    2    1    0
1482                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1483                                  */
1484                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1485                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1486                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1487                                                                     cycle_time_ns_x_100[cas_index]);
1488                                         cas_index++;
1489                                 } else {
1490                                         if (cas_index != 0)
1491                                                 cas_index++;
1492                                         cas_4_0_available = FALSE;
1493                                 }
1494
1495                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1496                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1497                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1498                                                                     cycle_time_ns_x_100[cas_index]);
1499                                         cas_index++;
1500                                 } else {
1501                                         if (cas_index != 0)
1502                                                 cas_index++;
1503                                         cas_3_0_available = FALSE;
1504                                 }
1505
1506                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1507                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1508                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1509                                                                     cycle_time_ns_x_100[cas_index]);
1510                                         cas_index++;
1511                                 } else {
1512                                         if (cas_index != 0)
1513                                                 cas_index++;
1514                                         cas_2_5_available = FALSE;
1515                                 }
1516
1517                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1518                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1519                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1520                                                                     cycle_time_ns_x_100[cas_index]);
1521                                         cas_index++;
1522                                 } else {
1523                                         if (cas_index != 0)
1524                                                 cas_index++;
1525                                         cas_2_0_available = FALSE;
1526                                 }
1527                         } else {
1528                                 /*
1529                                  * DDR2 devices use the following bitmask for CAS latency:
1530                                  *  Bit   7    6    5    4    3    2    1    0
1531                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1532                                  */
1533                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1534                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1535                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1536                                                                     cycle_time_ns_x_100[cas_index]);
1537                                         cas_index++;
1538                                 } else {
1539                                         if (cas_index != 0)
1540                                                 cas_index++;
1541                                         cas_5_0_available = FALSE;
1542                                 }
1543
1544                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1545                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1546                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1547                                                                     cycle_time_ns_x_100[cas_index]);
1548                                         cas_index++;
1549                                 } else {
1550                                         if (cas_index != 0)
1551                                                 cas_index++;
1552                                         cas_4_0_available = FALSE;
1553                                 }
1554
1555                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1556                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1557                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1558                                                                     cycle_time_ns_x_100[cas_index]);
1559                                         cas_index++;
1560                                 } else {
1561                                         if (cas_index != 0)
1562                                                 cas_index++;
1563                                         cas_3_0_available = FALSE;
1564                                 }
1565                         }
1566                 }
1567         }
1568
1569         /*------------------------------------------------------------------
1570          * Set the SDRAM mode, SDRAM_MMODE
1571          *-----------------------------------------------------------------*/
1572         mfsdram(SDRAM_MMODE, mmode);
1573         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1574
1575         /* add 10 here because of rounding problems */
1576         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1577         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1578         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1579         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1580         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1581         debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1582         debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1583         debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1584
1585         if (sdram_ddr1 == TRUE) { /* DDR1 */
1586                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1587                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1588                         *selected_cas = DDR_CAS_2;
1589                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1590                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1591                         *selected_cas = DDR_CAS_2_5;
1592                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1593                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1594                         *selected_cas = DDR_CAS_3;
1595                 } else {
1596                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1597                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1598                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1599                         spd_ddr_init_hang ();
1600                 }
1601         } else { /* DDR2 */
1602                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1603                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1604                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1605                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1606                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1607                         *selected_cas = DDR_CAS_3;
1608                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1609                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1610                         *selected_cas = DDR_CAS_4;
1611                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1612                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1613                         *selected_cas = DDR_CAS_5;
1614                 } else {
1615                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1616                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1617                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1618                         printf("cas3=%d cas4=%d cas5=%d\n",
1619                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1620                         printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1621                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1622                         spd_ddr_init_hang ();
1623                 }
1624         }
1625
1626         if (sdram_ddr1 == TRUE)
1627                 mmode |= SDRAM_MMODE_WR_DDR1;
1628         else {
1629
1630                 /* loop through all the DIMM slots on the board */
1631                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1632                         /* If a dimm is installed in a particular slot ... */
1633                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1634                                 t_wr_ns = max(t_wr_ns,
1635                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1636                 }
1637
1638                 /*
1639                  * convert from nanoseconds to ddr clocks
1640                  * round up if necessary
1641                  */
1642                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1643                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1644                 if (sdram_freq != ddr_check)
1645                         t_wr_clk++;
1646
1647                 switch (t_wr_clk) {
1648                 case 0:
1649                 case 1:
1650                 case 2:
1651                 case 3:
1652                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1653                         break;
1654                 case 4:
1655                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1656                         break;
1657                 case 5:
1658                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1659                         break;
1660                 default:
1661                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1662                         break;
1663                 }
1664                 *write_recovery = t_wr_clk;
1665         }
1666
1667         debug("CAS latency = %d\n", *selected_cas);
1668         debug("Write recovery = %d\n", *write_recovery);
1669
1670         mtsdram(SDRAM_MMODE, mmode);
1671 }
1672
1673 /*-----------------------------------------------------------------------------+
1674  * program_rtr.
1675  *-----------------------------------------------------------------------------*/
1676 static void program_rtr(unsigned long *dimm_populated,
1677                         unsigned char *iic0_dimm_addr,
1678                         unsigned long num_dimm_banks)
1679 {
1680         PPC4xx_SYS_INFO board_cfg;
1681         unsigned long max_refresh_rate;
1682         unsigned long dimm_num;
1683         unsigned long refresh_rate_type;
1684         unsigned long refresh_rate;
1685         unsigned long rint;
1686         unsigned long sdram_freq;
1687         unsigned long sdr_ddrpll;
1688         unsigned long val;
1689
1690         /*------------------------------------------------------------------
1691          * Get the board configuration info.
1692          *-----------------------------------------------------------------*/
1693         get_sys_info(&board_cfg);
1694
1695         /*------------------------------------------------------------------
1696          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1697          *-----------------------------------------------------------------*/
1698         mfsdr(SDR0_DDR0, sdr_ddrpll);
1699         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1700
1701         max_refresh_rate = 0;
1702         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1703                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1704
1705                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1706                         refresh_rate_type &= 0x7F;
1707                         switch (refresh_rate_type) {
1708                         case 0:
1709                                 refresh_rate =  15625;
1710                                 break;
1711                         case 1:
1712                                 refresh_rate =   3906;
1713                                 break;
1714                         case 2:
1715                                 refresh_rate =   7812;
1716                                 break;
1717                         case 3:
1718                                 refresh_rate =  31250;
1719                                 break;
1720                         case 4:
1721                                 refresh_rate =  62500;
1722                                 break;
1723                         case 5:
1724                                 refresh_rate = 125000;
1725                                 break;
1726                         default:
1727                                 refresh_rate = 0;
1728                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1729                                        (unsigned int)dimm_num);
1730                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1731                                 spd_ddr_init_hang ();
1732                                 break;
1733                         }
1734
1735                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1736                 }
1737         }
1738
1739         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1740         mfsdram(SDRAM_RTR, val);
1741         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1742                 (SDRAM_RTR_RINT_ENCODE(rint)));
1743 }
1744
1745 /*------------------------------------------------------------------
1746  * This routine programs the SDRAM_TRx registers.
1747  *-----------------------------------------------------------------*/
1748 static void program_tr(unsigned long *dimm_populated,
1749                        unsigned char *iic0_dimm_addr,
1750                        unsigned long num_dimm_banks)
1751 {
1752         unsigned long dimm_num;
1753         unsigned long sdram_ddr1;
1754         unsigned long t_rp_ns;
1755         unsigned long t_rcd_ns;
1756         unsigned long t_rrd_ns;
1757         unsigned long t_ras_ns;
1758         unsigned long t_rc_ns;
1759         unsigned long t_rfc_ns;
1760         unsigned long t_wpc_ns;
1761         unsigned long t_wtr_ns;
1762         unsigned long t_rpc_ns;
1763         unsigned long t_rp_clk;
1764         unsigned long t_rcd_clk;
1765         unsigned long t_rrd_clk;
1766         unsigned long t_ras_clk;
1767         unsigned long t_rc_clk;
1768         unsigned long t_rfc_clk;
1769         unsigned long t_wpc_clk;
1770         unsigned long t_wtr_clk;
1771         unsigned long t_rpc_clk;
1772         unsigned long sdtr1, sdtr2, sdtr3;
1773         unsigned long ddr_check;
1774         unsigned long sdram_freq;
1775         unsigned long sdr_ddrpll;
1776
1777         PPC4xx_SYS_INFO board_cfg;
1778
1779         /*------------------------------------------------------------------
1780          * Get the board configuration info.
1781          *-----------------------------------------------------------------*/
1782         get_sys_info(&board_cfg);
1783
1784         mfsdr(SDR0_DDR0, sdr_ddrpll);
1785         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1786
1787         /*------------------------------------------------------------------
1788          * Handle the timing.  We need to find the worst case timing of all
1789          * the dimm modules installed.
1790          *-----------------------------------------------------------------*/
1791         t_rp_ns = 0;
1792         t_rrd_ns = 0;
1793         t_rcd_ns = 0;
1794         t_ras_ns = 0;
1795         t_rc_ns = 0;
1796         t_rfc_ns = 0;
1797         t_wpc_ns = 0;
1798         t_wtr_ns = 0;
1799         t_rpc_ns = 0;
1800         sdram_ddr1 = TRUE;
1801
1802         /* loop through all the DIMM slots on the board */
1803         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1804                 /* If a dimm is installed in a particular slot ... */
1805                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1806                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1807                                 sdram_ddr1 = TRUE;
1808                         else
1809                                 sdram_ddr1 = FALSE;
1810
1811                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1812                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1813                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1814                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1815                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1816                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1817                 }
1818         }
1819
1820         /*------------------------------------------------------------------
1821          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1822          *-----------------------------------------------------------------*/
1823         mfsdram(SDRAM_SDTR1, sdtr1);
1824         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1825                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1826
1827         /* default values */
1828         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1829         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1830
1831         /* normal operations */
1832         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1833         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1834
1835         mtsdram(SDRAM_SDTR1, sdtr1);
1836
1837         /*------------------------------------------------------------------
1838          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1839          *-----------------------------------------------------------------*/
1840         mfsdram(SDRAM_SDTR2, sdtr2);
1841         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1842                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1843                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1844                    SDRAM_SDTR2_RRD_MASK);
1845
1846         /*
1847          * convert t_rcd from nanoseconds to ddr clocks
1848          * round up if necessary
1849          */
1850         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1851         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1852         if (sdram_freq != ddr_check)
1853                 t_rcd_clk++;
1854
1855         switch (t_rcd_clk) {
1856         case 0:
1857         case 1:
1858                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1859                 break;
1860         case 2:
1861                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1862                 break;
1863         case 3:
1864                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1865                 break;
1866         case 4:
1867                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1868                 break;
1869         default:
1870                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1871                 break;
1872         }
1873
1874         if (sdram_ddr1 == TRUE) { /* DDR1 */
1875                 if (sdram_freq < 200000000) {
1876                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1877                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1878                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1879                 } else {
1880                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1881                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1882                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1883                 }
1884         } else { /* DDR2 */
1885                 /* loop through all the DIMM slots on the board */
1886                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1887                         /* If a dimm is installed in a particular slot ... */
1888                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1889                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1890                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1891                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1892                         }
1893                 }
1894
1895                 /*
1896                  * convert from nanoseconds to ddr clocks
1897                  * round up if necessary
1898                  */
1899                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1900                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1901                 if (sdram_freq != ddr_check)
1902                         t_wpc_clk++;
1903
1904                 switch (t_wpc_clk) {
1905                 case 0:
1906                 case 1:
1907                 case 2:
1908                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1909                         break;
1910                 case 3:
1911                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1912                         break;
1913                 case 4:
1914                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1915                         break;
1916                 case 5:
1917                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1918                         break;
1919                 default:
1920                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1921                         break;
1922                 }
1923
1924                 /*
1925                  * convert from nanoseconds to ddr clocks
1926                  * round up if necessary
1927                  */
1928                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1929                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1930                 if (sdram_freq != ddr_check)
1931                         t_wtr_clk++;
1932
1933                 switch (t_wtr_clk) {
1934                 case 0:
1935                 case 1:
1936                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1937                         break;
1938                 case 2:
1939                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1940                         break;
1941                 case 3:
1942                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1943                         break;
1944                 default:
1945                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1946                         break;
1947                 }
1948
1949                 /*
1950                  * convert from nanoseconds to ddr clocks
1951                  * round up if necessary
1952                  */
1953                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1954                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1955                 if (sdram_freq != ddr_check)
1956                         t_rpc_clk++;
1957
1958                 switch (t_rpc_clk) {
1959                 case 0:
1960                 case 1:
1961                 case 2:
1962                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1963                         break;
1964                 case 3:
1965                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1966                         break;
1967                 default:
1968                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1969                         break;
1970                 }
1971         }
1972
1973         /* default value */
1974         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1975
1976         /*
1977          * convert t_rrd from nanoseconds to ddr clocks
1978          * round up if necessary
1979          */
1980         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1981         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1982         if (sdram_freq != ddr_check)
1983                 t_rrd_clk++;
1984
1985         if (t_rrd_clk == 3)
1986                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1987         else
1988                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1989
1990         /*
1991          * convert t_rp from nanoseconds to ddr clocks
1992          * round up if necessary
1993          */
1994         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1995         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1996         if (sdram_freq != ddr_check)
1997                 t_rp_clk++;
1998
1999         switch (t_rp_clk) {
2000         case 0:
2001         case 1:
2002         case 2:
2003         case 3:
2004                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2005                 break;
2006         case 4:
2007                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2008                 break;
2009         case 5:
2010                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2011                 break;
2012         case 6:
2013                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2014                 break;
2015         default:
2016                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2017                 break;
2018         }
2019
2020         mtsdram(SDRAM_SDTR2, sdtr2);
2021
2022         /*------------------------------------------------------------------
2023          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2024          *-----------------------------------------------------------------*/
2025         mfsdram(SDRAM_SDTR3, sdtr3);
2026         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2027                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2028
2029         /*
2030          * convert t_ras from nanoseconds to ddr clocks
2031          * round up if necessary
2032          */
2033         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2034         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2035         if (sdram_freq != ddr_check)
2036                 t_ras_clk++;
2037
2038         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2039
2040         /*
2041          * convert t_rc from nanoseconds to ddr clocks
2042          * round up if necessary
2043          */
2044         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2045         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2046         if (sdram_freq != ddr_check)
2047                 t_rc_clk++;
2048
2049         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2050
2051         /* default xcs value */
2052         sdtr3 |= SDRAM_SDTR3_XCS;
2053
2054         /*
2055          * convert t_rfc from nanoseconds to ddr clocks
2056          * round up if necessary
2057          */
2058         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2059         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2060         if (sdram_freq != ddr_check)
2061                 t_rfc_clk++;
2062
2063         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2064
2065         mtsdram(SDRAM_SDTR3, sdtr3);
2066 }
2067
2068 /*-----------------------------------------------------------------------------+
2069  * program_bxcf.
2070  *-----------------------------------------------------------------------------*/
2071 static void program_bxcf(unsigned long *dimm_populated,
2072                          unsigned char *iic0_dimm_addr,
2073                          unsigned long num_dimm_banks)
2074 {
2075         unsigned long dimm_num;
2076         unsigned long num_col_addr;
2077         unsigned long num_ranks;
2078         unsigned long num_banks;
2079         unsigned long mode;
2080         unsigned long ind_rank;
2081         unsigned long ind;
2082         unsigned long ind_bank;
2083         unsigned long bank_0_populated;
2084
2085         /*------------------------------------------------------------------
2086          * Set the BxCF regs.  First, wipe out the bank config registers.
2087          *-----------------------------------------------------------------*/
2088         mtsdram(SDRAM_MB0CF, 0x00000000);
2089         mtsdram(SDRAM_MB1CF, 0x00000000);
2090         mtsdram(SDRAM_MB2CF, 0x00000000);
2091         mtsdram(SDRAM_MB3CF, 0x00000000);
2092
2093         mode = SDRAM_BXCF_M_BE_ENABLE;
2094
2095         bank_0_populated = 0;
2096
2097         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2098                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2099                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2100                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2101                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2102                                 num_ranks = (num_ranks & 0x0F) +1;
2103                         else
2104                                 num_ranks = num_ranks & 0x0F;
2105
2106                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2107
2108                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2109                                 if (num_banks == 4)
2110                                         ind = 0;
2111                                 else
2112                                         ind = 5 << 8;
2113                                 switch (num_col_addr) {
2114                                 case 0x08:
2115                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2116                                         break;
2117                                 case 0x09:
2118                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2119                                         break;
2120                                 case 0x0A:
2121                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2122                                         break;
2123                                 case 0x0B:
2124                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2125                                         break;
2126                                 case 0x0C:
2127                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2128                                         break;
2129                                 default:
2130                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2131                                                (unsigned int)dimm_num);
2132                                         printf("ERROR: Unsupported value for number of "
2133                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2134                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2135                                         spd_ddr_init_hang ();
2136                                 }
2137                         }
2138
2139                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2140                                 bank_0_populated = 1;
2141
2142                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2143                                 mtsdram(SDRAM_MB0CF +
2144                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2145                                         mode);
2146                         }
2147                 }
2148         }
2149 }
2150
2151 /*------------------------------------------------------------------
2152  * program memory queue.
2153  *-----------------------------------------------------------------*/
2154 static void program_memory_queue(unsigned long *dimm_populated,
2155                                  unsigned char *iic0_dimm_addr,
2156                                  unsigned long num_dimm_banks)
2157 {
2158         unsigned long dimm_num;
2159         phys_size_t rank_base_addr;
2160         unsigned long rank_reg;
2161         phys_size_t rank_size_bytes;
2162         unsigned long rank_size_id;
2163         unsigned long num_ranks;
2164         unsigned long baseadd_size;
2165         unsigned long i;
2166         unsigned long bank_0_populated = 0;
2167         phys_size_t total_size = 0;
2168
2169         /*------------------------------------------------------------------
2170          * Reset the rank_base_address.
2171          *-----------------------------------------------------------------*/
2172         rank_reg   = SDRAM_R0BAS;
2173
2174         rank_base_addr = 0x00000000;
2175
2176         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2177                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2178                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2179                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2180                                 num_ranks = (num_ranks & 0x0F) + 1;
2181                         else
2182                                 num_ranks = num_ranks & 0x0F;
2183
2184                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2185
2186                         /*------------------------------------------------------------------
2187                          * Set the sizes
2188                          *-----------------------------------------------------------------*/
2189                         baseadd_size = 0;
2190                         switch (rank_size_id) {
2191                         case 0x01:
2192                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2193                                 total_size = 1024;
2194                                 break;
2195                         case 0x02:
2196                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2197                                 total_size = 2048;
2198                                 break;
2199                         case 0x04:
2200                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2201                                 total_size = 4096;
2202                                 break;
2203                         case 0x08:
2204                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2205                                 total_size = 32;
2206                                 break;
2207                         case 0x10:
2208                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2209                                 total_size = 64;
2210                                 break;
2211                         case 0x20:
2212                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2213                                 total_size = 128;
2214                                 break;
2215                         case 0x40:
2216                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2217                                 total_size = 256;
2218                                 break;
2219                         case 0x80:
2220                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2221                                 total_size = 512;
2222                                 break;
2223                         default:
2224                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2225                                        (unsigned int)dimm_num);
2226                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2227                                        (unsigned int)rank_size_id);
2228                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2229                                 spd_ddr_init_hang ();
2230                         }
2231                         rank_size_bytes = total_size << 20;
2232
2233                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2234                                 bank_0_populated = 1;
2235
2236                         for (i = 0; i < num_ranks; i++) {
2237                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2238                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2239                                            baseadd_size));
2240                                 rank_base_addr += rank_size_bytes;
2241                         }
2242                 }
2243         }
2244
2245 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
2246         /*
2247          * Enable high bandwidth access on 460EX/GT.
2248          * This should/could probably be done on other
2249          * PPC's too, like 440SPe.
2250          * This is currently not used, but with this setup
2251          * it is possible to use it later on in e.g. the Linux
2252          * EMAC driver for performance gain.
2253          */
2254         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2255         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2256 #endif
2257 }
2258
2259 /*-----------------------------------------------------------------------------+
2260  * is_ecc_enabled.
2261  *-----------------------------------------------------------------------------*/
2262 static unsigned long is_ecc_enabled(void)
2263 {
2264         unsigned long dimm_num;
2265         unsigned long ecc;
2266         unsigned long val;
2267
2268         ecc = 0;
2269         /* loop through all the DIMM slots on the board */
2270         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2271                 mfsdram(SDRAM_MCOPT1, val);
2272                 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2273         }
2274
2275         return ecc;
2276 }
2277
2278 static void blank_string(int size)
2279 {
2280         int i;
2281
2282         for (i=0; i<size; i++)
2283                 putc('\b');
2284         for (i=0; i<size; i++)
2285                 putc(' ');
2286         for (i=0; i<size; i++)
2287                 putc('\b');
2288 }
2289
2290 #ifdef CONFIG_DDR_ECC
2291 /*-----------------------------------------------------------------------------+
2292  * program_ecc.
2293  *-----------------------------------------------------------------------------*/
2294 static void program_ecc(unsigned long *dimm_populated,
2295                         unsigned char *iic0_dimm_addr,
2296                         unsigned long num_dimm_banks,
2297                         unsigned long tlb_word2_i_value)
2298 {
2299         unsigned long mcopt1;
2300         unsigned long mcopt2;
2301         unsigned long mcstat;
2302         unsigned long dimm_num;
2303         unsigned long ecc;
2304
2305         ecc = 0;
2306         /* loop through all the DIMM slots on the board */
2307         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2308                 /* If a dimm is installed in a particular slot ... */
2309                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2310                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2311         }
2312         if (ecc == 0)
2313                 return;
2314
2315         if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
2316                 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
2317                 return;
2318         }
2319
2320         mfsdram(SDRAM_MCOPT1, mcopt1);
2321         mfsdram(SDRAM_MCOPT2, mcopt2);
2322
2323         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2324                 /* DDR controller must be enabled and not in self-refresh. */
2325                 mfsdram(SDRAM_MCSTAT, mcstat);
2326                 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2327                     && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2328                     && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2329                         == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2330
2331                         program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2332                 }
2333         }
2334
2335         return;
2336 }
2337
2338 static void wait_ddr_idle(void)
2339 {
2340         u32 val;
2341
2342         do {
2343                 mfsdram(SDRAM_MCSTAT, val);
2344         } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2345 }
2346
2347 /*-----------------------------------------------------------------------------+
2348  * program_ecc_addr.
2349  *-----------------------------------------------------------------------------*/
2350 static void program_ecc_addr(unsigned long start_address,
2351                              unsigned long num_bytes,
2352                              unsigned long tlb_word2_i_value)
2353 {
2354         unsigned long current_address;
2355         unsigned long end_address;
2356         unsigned long address_increment;
2357         unsigned long mcopt1;
2358         char str[] = "ECC generation -";
2359         char slash[] = "\\|/-\\|/-";
2360         int loop = 0;
2361         int loopi = 0;
2362
2363         current_address = start_address;
2364         mfsdram(SDRAM_MCOPT1, mcopt1);
2365         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2366                 mtsdram(SDRAM_MCOPT1,
2367                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2368                 sync();
2369                 eieio();
2370                 wait_ddr_idle();
2371
2372                 puts(str);
2373                 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2374                         /* ECC bit set method for non-cached memory */
2375                         if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2376                                 address_increment = 4;
2377                         else
2378                                 address_increment = 8;
2379                         end_address = current_address + num_bytes;
2380
2381                         while (current_address < end_address) {
2382                                 *((unsigned long *)current_address) = 0x00000000;
2383                                 current_address += address_increment;
2384
2385                                 if ((loop++ % (2 << 20)) == 0) {
2386                                         putc('\b');
2387                                         putc(slash[loopi++ % 8]);
2388                                 }
2389                         }
2390
2391                 } else {
2392                         /* ECC bit set method for cached memory */
2393                         dcbz_area(start_address, num_bytes);
2394                         /* Write modified dcache lines back to memory */
2395                         clean_dcache_range(start_address, start_address + num_bytes);
2396                 }
2397
2398                 blank_string(strlen(str));
2399
2400                 sync();
2401                 eieio();
2402                 wait_ddr_idle();
2403
2404                 /* clear ECC error repoting registers */
2405                 mtsdram(SDRAM_ECCCR, 0xffffffff);
2406                 mtdcr(0x4c, 0xffffffff);
2407
2408                 mtsdram(SDRAM_MCOPT1,
2409                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2410                 sync();
2411                 eieio();
2412                 wait_ddr_idle();
2413         }
2414 }
2415 #endif
2416
2417 /*-----------------------------------------------------------------------------+
2418  * program_DQS_calibration.
2419  *-----------------------------------------------------------------------------*/
2420 static void program_DQS_calibration(unsigned long *dimm_populated,
2421                                     unsigned char *iic0_dimm_addr,
2422                                     unsigned long num_dimm_banks)
2423 {
2424         unsigned long val;
2425
2426 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2427         mtsdram(SDRAM_RQDC, 0x80000037);
2428         mtsdram(SDRAM_RDCC, 0x40000000);
2429         mtsdram(SDRAM_RFDC, 0x000001DF);
2430
2431         test();
2432 #else
2433         /*------------------------------------------------------------------
2434          * Program RDCC register
2435          * Read sample cycle auto-update enable
2436          *-----------------------------------------------------------------*/
2437
2438         mfsdram(SDRAM_RDCC, val);
2439         mtsdram(SDRAM_RDCC,
2440                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2441                 | SDRAM_RDCC_RSAE_ENABLE);
2442
2443         /*------------------------------------------------------------------
2444          * Program RQDC register
2445          * Internal DQS delay mechanism enable
2446          *-----------------------------------------------------------------*/
2447         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2448
2449         /*------------------------------------------------------------------
2450          * Program RFDC register
2451          * Set Feedback Fractional Oversample
2452          * Auto-detect read sample cycle enable
2453          *-----------------------------------------------------------------*/
2454         mfsdram(SDRAM_RFDC, val);
2455         mtsdram(SDRAM_RFDC,
2456                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2457                          SDRAM_RFDC_RFFD_MASK))
2458                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2459                    SDRAM_RFDC_RFFD_ENCODE(0)));
2460
2461         DQS_calibration_process();
2462 #endif
2463 }
2464
2465 static int short_mem_test(void)
2466 {
2467         u32 *membase;
2468         u32 bxcr_num;
2469         u32 bxcf;
2470         int i;
2471         int j;
2472         phys_size_t base_addr;
2473         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2474                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2475                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2476                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2477                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2478                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2479                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2480                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2481                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2482                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2483                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2484                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2485                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2486                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2487                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2488                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2489                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2490         int l;
2491
2492         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2493                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2494
2495                 /* Banks enabled */
2496                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2497                         /* Bank is enabled */
2498
2499                         /*
2500                          * Only run test on accessable memory (below 2GB)
2501                          */
2502                         base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2503                         if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2504                                 continue;
2505
2506                         /*------------------------------------------------------------------
2507                          * Run the short memory test.
2508                          *-----------------------------------------------------------------*/
2509                         membase = (u32 *)(u32)base_addr;
2510
2511                         for (i = 0; i < NUMMEMTESTS; i++) {
2512                                 for (j = 0; j < NUMMEMWORDS; j++) {
2513                                         membase[j] = test[i][j];
2514                                         ppcDcbf((u32)&(membase[j]));
2515                                 }
2516                                 sync();
2517                                 for (l=0; l<NUMLOOPS; l++) {
2518                                         for (j = 0; j < NUMMEMWORDS; j++) {
2519                                                 if (membase[j] != test[i][j]) {
2520                                                         ppcDcbf((u32)&(membase[j]));
2521                                                         return 0;
2522                                                 }
2523                                                 ppcDcbf((u32)&(membase[j]));
2524                                         }
2525                                         sync();
2526                                 }
2527                         }
2528                 }       /* if bank enabled */
2529         }               /* for bxcf_num */
2530
2531         return 1;
2532 }
2533
2534 #ifndef HARD_CODED_DQS
2535 /*-----------------------------------------------------------------------------+
2536  * DQS_calibration_process.
2537  *-----------------------------------------------------------------------------*/
2538 static void DQS_calibration_process(void)
2539 {
2540         unsigned long rfdc_reg;
2541         unsigned long rffd;
2542         unsigned long val;
2543         long rffd_average;
2544         long max_start;
2545         long min_end;
2546         unsigned long begin_rqfd[MAXRANKS];
2547         unsigned long begin_rffd[MAXRANKS];
2548         unsigned long end_rqfd[MAXRANKS];
2549         unsigned long end_rffd[MAXRANKS];
2550         char window_found;
2551         unsigned long dlycal;
2552         unsigned long dly_val;
2553         unsigned long max_pass_length;
2554         unsigned long current_pass_length;
2555         unsigned long current_fail_length;
2556         unsigned long current_start;
2557         long max_end;
2558         unsigned char fail_found;
2559         unsigned char pass_found;
2560 #if !defined(CONFIG_DDR_RQDC_FIXED)
2561         u32 rqdc_reg;
2562         u32 rqfd;
2563         u32 rqfd_start;
2564         u32 rqfd_average;
2565         int loopi = 0;
2566         char str[] = "Auto calibration -";
2567         char slash[] = "\\|/-\\|/-";
2568
2569         /*------------------------------------------------------------------
2570          * Test to determine the best read clock delay tuning bits.
2571          *
2572          * Before the DDR controller can be used, the read clock delay needs to be
2573          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2574          * This value cannot be hardcoded into the program because it changes
2575          * depending on the board's setup and environment.
2576          * To do this, all delay values are tested to see if they
2577          * work or not.  By doing this, you get groups of fails with groups of
2578          * passing values.  The idea is to find the start and end of a passing
2579          * window and take the center of it to use as the read clock delay.
2580          *
2581          * A failure has to be seen first so that when we hit a pass, we know
2582          * that it is truely the start of the window.  If we get passing values
2583          * to start off with, we don't know if we are at the start of the window.
2584          *
2585          * The code assumes that a failure will always be found.
2586          * If a failure is not found, there is no easy way to get the middle
2587          * of the passing window.  I guess we can pretty much pick any value
2588          * but some values will be better than others.  Since the lowest speed
2589          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2590          * from experimentation it is safe to say you will always have a failure.
2591          *-----------------------------------------------------------------*/
2592
2593         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2594         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2595
2596         puts(str);
2597
2598 calibration_loop:
2599         mfsdram(SDRAM_RQDC, rqdc_reg);
2600         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2601                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2602 #else /* CONFIG_DDR_RQDC_FIXED */
2603         /*
2604          * On Katmai the complete auto-calibration somehow doesn't seem to
2605          * produce the best results, meaning optimal values for RQFD/RFFD.
2606          * This was discovered by GDA using a high bandwidth scope,
2607          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2608          * so now on Katmai "only" RFFD is auto-calibrated.
2609          */
2610         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2611 #endif /* CONFIG_DDR_RQDC_FIXED */
2612
2613         max_start = 0;
2614         min_end = 0;
2615         begin_rqfd[0] = 0;
2616         begin_rffd[0] = 0;
2617         begin_rqfd[1] = 0;
2618         begin_rffd[1] = 0;
2619         end_rqfd[0] = 0;
2620         end_rffd[0] = 0;
2621         end_rqfd[1] = 0;
2622         end_rffd[1] = 0;
2623         window_found = FALSE;
2624
2625         max_pass_length = 0;
2626         max_start = 0;
2627         max_end = 0;
2628         current_pass_length = 0;
2629         current_fail_length = 0;
2630         current_start = 0;
2631         window_found = FALSE;
2632         fail_found = FALSE;
2633         pass_found = FALSE;
2634
2635         /*
2636          * get the delay line calibration register value
2637          */
2638         mfsdram(SDRAM_DLCR, dlycal);
2639         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2640
2641         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2642                 mfsdram(SDRAM_RFDC, rfdc_reg);
2643                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2644
2645                 /*------------------------------------------------------------------
2646                  * Set the timing reg for the test.
2647                  *-----------------------------------------------------------------*/
2648                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2649
2650                 /*------------------------------------------------------------------
2651                  * See if the rffd value passed.
2652                  *-----------------------------------------------------------------*/
2653                 if (short_mem_test()) {
2654                         if (fail_found == TRUE) {
2655                                 pass_found = TRUE;
2656                                 if (current_pass_length == 0)
2657                                         current_start = rffd;
2658
2659                                 current_fail_length = 0;
2660                                 current_pass_length++;
2661
2662                                 if (current_pass_length > max_pass_length) {
2663                                         max_pass_length = current_pass_length;
2664                                         max_start = current_start;
2665                                         max_end = rffd;
2666                                 }
2667                         }
2668                 } else {
2669                         current_pass_length = 0;
2670                         current_fail_length++;
2671
2672                         if (current_fail_length >= (dly_val >> 2)) {
2673                                 if (fail_found == FALSE) {
2674                                         fail_found = TRUE;
2675                                 } else if (pass_found == TRUE) {
2676                                         window_found = TRUE;
2677                                         break;
2678                                 }
2679                         }
2680                 }
2681         }               /* for rffd */
2682
2683         /*------------------------------------------------------------------
2684          * Set the average RFFD value
2685          *-----------------------------------------------------------------*/
2686         rffd_average = ((max_start + max_end) >> 1);
2687
2688         if (rffd_average < 0)
2689                 rffd_average = 0;
2690
2691         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2692                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2693         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2694         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2695
2696 #if !defined(CONFIG_DDR_RQDC_FIXED)
2697         max_pass_length = 0;
2698         max_start = 0;
2699         max_end = 0;
2700         current_pass_length = 0;
2701         current_fail_length = 0;
2702         current_start = 0;
2703         window_found = FALSE;
2704         fail_found = FALSE;
2705         pass_found = FALSE;
2706
2707         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2708                 mfsdram(SDRAM_RQDC, rqdc_reg);
2709                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2710
2711                 /*------------------------------------------------------------------
2712                  * Set the timing reg for the test.
2713                  *-----------------------------------------------------------------*/
2714                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2715
2716                 /*------------------------------------------------------------------
2717                  * See if the rffd value passed.
2718                  *-----------------------------------------------------------------*/
2719                 if (short_mem_test()) {
2720                         if (fail_found == TRUE) {
2721                                 pass_found = TRUE;
2722                                 if (current_pass_length == 0)
2723                                         current_start = rqfd;
2724
2725                                 current_fail_length = 0;
2726                                 current_pass_length++;
2727
2728                                 if (current_pass_length > max_pass_length) {
2729                                         max_pass_length = current_pass_length;
2730                                         max_start = current_start;
2731                                         max_end = rqfd;
2732                                 }
2733                         }
2734                 } else {
2735                         current_pass_length = 0;
2736                         current_fail_length++;
2737
2738                         if (fail_found == FALSE) {
2739                                 fail_found = TRUE;
2740                         } else if (pass_found == TRUE) {
2741                                 window_found = TRUE;
2742                                 break;
2743                         }
2744                 }
2745         }
2746
2747         rqfd_average = ((max_start + max_end) >> 1);
2748
2749         /*------------------------------------------------------------------
2750          * Make sure we found the valid read passing window.  Halt if not
2751          *-----------------------------------------------------------------*/
2752         if (window_found == FALSE) {
2753                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2754                         putc('\b');
2755                         putc(slash[loopi++ % 8]);
2756
2757                         /* try again from with a different RQFD start value */
2758                         rqfd_start++;
2759                         goto calibration_loop;
2760                 }
2761
2762                 printf("\nERROR: Cannot determine a common read delay for the "
2763                        "DIMM(s) installed.\n");
2764                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2765                 ppc4xx_ibm_ddr2_register_dump();
2766                 spd_ddr_init_hang ();
2767         }
2768
2769         if (rqfd_average < 0)
2770                 rqfd_average = 0;
2771
2772         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2773                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2774
2775         mtsdram(SDRAM_RQDC,
2776                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2777                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2778
2779         blank_string(strlen(str));
2780 #endif /* CONFIG_DDR_RQDC_FIXED */
2781
2782         /*
2783          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2784          * PowerPC440SP/SPe DDR2 application note:
2785          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2786          */
2787         mfsdram(SDRAM_RTSR, val);
2788         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2789                 mfsdram(SDRAM_RDCC, val);
2790                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2791                         val += 0x40000000;
2792                         mtsdram(SDRAM_RDCC, val);
2793                 }
2794         }
2795
2796         mfsdram(SDRAM_DLCR, val);
2797         debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2798         mfsdram(SDRAM_RQDC, val);
2799         debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2800         mfsdram(SDRAM_RFDC, val);
2801         debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2802         mfsdram(SDRAM_RDCC, val);
2803         debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2804 }
2805 #else /* calibration test with hardvalues */
2806 /*-----------------------------------------------------------------------------+
2807  * DQS_calibration_process.
2808  *-----------------------------------------------------------------------------*/
2809 static void test(void)
2810 {
2811         unsigned long dimm_num;
2812         unsigned long ecc_temp;
2813         unsigned long i, j;
2814         unsigned long *membase;
2815         unsigned long bxcf[MAXRANKS];
2816         unsigned long val;
2817         char window_found;
2818         char begin_found[MAXDIMMS];
2819         char end_found[MAXDIMMS];
2820         char search_end[MAXDIMMS];
2821         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2822                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2823                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2824                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2825                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2826                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2827                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2828                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2829                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2830                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2831                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2832                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2833                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2834                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2835                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2836                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2837                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2838
2839         /*------------------------------------------------------------------
2840          * Test to determine the best read clock delay tuning bits.
2841          *
2842          * Before the DDR controller can be used, the read clock delay needs to be
2843          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2844          * This value cannot be hardcoded into the program because it changes
2845          * depending on the board's setup and environment.
2846          * To do this, all delay values are tested to see if they
2847          * work or not.  By doing this, you get groups of fails with groups of
2848          * passing values.  The idea is to find the start and end of a passing
2849          * window and take the center of it to use as the read clock delay.
2850          *
2851          * A failure has to be seen first so that when we hit a pass, we know
2852          * that it is truely the start of the window.  If we get passing values
2853          * to start off with, we don't know if we are at the start of the window.
2854          *
2855          * The code assumes that a failure will always be found.
2856          * If a failure is not found, there is no easy way to get the middle
2857          * of the passing window.  I guess we can pretty much pick any value
2858          * but some values will be better than others.  Since the lowest speed
2859          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2860          * from experimentation it is safe to say you will always have a failure.
2861          *-----------------------------------------------------------------*/
2862         mfsdram(SDRAM_MCOPT1, ecc_temp);
2863         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2864         mfsdram(SDRAM_MCOPT1, val);
2865         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2866                 SDRAM_MCOPT1_MCHK_NON);
2867
2868         window_found = FALSE;
2869         begin_found[0] = FALSE;
2870         end_found[0] = FALSE;
2871         search_end[0] = FALSE;
2872         begin_found[1] = FALSE;
2873         end_found[1] = FALSE;
2874         search_end[1] = FALSE;
2875
2876         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2877                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2878
2879                 /* Banks enabled */
2880                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2881
2882                         /* Bank is enabled */
2883                         membase =
2884                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2885
2886                         /*------------------------------------------------------------------
2887                          * Run the short memory test.
2888                          *-----------------------------------------------------------------*/
2889                         for (i = 0; i < NUMMEMTESTS; i++) {
2890                                 for (j = 0; j < NUMMEMWORDS; j++) {
2891                                         membase[j] = test[i][j];
2892                                         ppcDcbf((u32)&(membase[j]));
2893                                 }
2894                                 sync();
2895                                 for (j = 0; j < NUMMEMWORDS; j++) {
2896                                         if (membase[j] != test[i][j]) {
2897                                                 ppcDcbf((u32)&(membase[j]));
2898                                                 break;
2899                                         }
2900                                         ppcDcbf((u32)&(membase[j]));
2901                                 }
2902                                 sync();
2903                                 if (j < NUMMEMWORDS)
2904                                         break;
2905                         }
2906
2907                         /*------------------------------------------------------------------
2908                          * See if the rffd value passed.
2909                          *-----------------------------------------------------------------*/
2910                         if (i < NUMMEMTESTS) {
2911                                 if ((end_found[dimm_num] == FALSE) &&
2912                                     (search_end[dimm_num] == TRUE)) {
2913                                         end_found[dimm_num] = TRUE;
2914                                 }
2915                                 if ((end_found[0] == TRUE) &&
2916                                     (end_found[1] == TRUE))
2917                                         break;
2918                         } else {
2919                                 if (begin_found[dimm_num] == FALSE) {
2920                                         begin_found[dimm_num] = TRUE;
2921                                         search_end[dimm_num] = TRUE;
2922                                 }
2923                         }
2924                 } else {
2925                         begin_found[dimm_num] = TRUE;
2926                         end_found[dimm_num] = TRUE;
2927                 }
2928         }
2929
2930         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2931                 window_found = TRUE;
2932
2933         /*------------------------------------------------------------------
2934          * Make sure we found the valid read passing window.  Halt if not
2935          *-----------------------------------------------------------------*/
2936         if (window_found == FALSE) {
2937                 printf("ERROR: Cannot determine a common read delay for the "
2938                        "DIMM(s) installed.\n");
2939                 spd_ddr_init_hang ();
2940         }
2941
2942         /*------------------------------------------------------------------
2943          * Restore the ECC variable to what it originally was
2944          *-----------------------------------------------------------------*/
2945         mtsdram(SDRAM_MCOPT1,
2946                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2947                 | ecc_temp);
2948 }
2949 #endif
2950
2951 #elif defined(CONFIG_405EX)
2952 /*-----------------------------------------------------------------------------
2953  * Function:    initdram
2954  * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
2955  *              banks. The configuration is performed using static, compile-
2956  *              time parameters.
2957  *---------------------------------------------------------------------------*/
2958 phys_size_t initdram(int board_type)
2959 {
2960         /*
2961          * Only run this SDRAM init code once. For NAND booting
2962          * targets like Kilauea, we call initdram() early from the
2963          * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2964          * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2965          * which calls initdram() again. This time the controller
2966          * mustn't be reconfigured again since we're already running
2967          * from SDRAM.
2968          */
2969 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2970         unsigned long val;
2971
2972         /* Set Memory Bank Configuration Registers */
2973
2974         mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
2975         mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
2976         mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
2977         mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
2978
2979         /* Set Memory Clock Timing Register */
2980
2981         mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
2982
2983         /* Set Refresh Time Register */
2984
2985         mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
2986
2987         /* Set SDRAM Timing Registers */
2988
2989         mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
2990         mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
2991         mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
2992
2993         /* Set Mode and Extended Mode Registers */
2994
2995         mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
2996         mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
2997
2998         /* Set Memory Controller Options 1 Register */
2999
3000         mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
3001
3002         /* Set Manual Initialization Control Registers */
3003
3004         mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
3005         mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
3006         mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
3007         mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
3008         mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
3009         mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
3010         mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
3011         mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
3012         mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
3013         mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
3014         mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
3015         mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
3016         mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
3017         mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
3018         mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
3019         mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
3020
3021         /* Set On-Die Termination Registers */
3022
3023         mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
3024         mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
3025         mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
3026
3027         /* Set Write Timing Register */
3028
3029         mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
3030
3031         /*
3032          * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3033          * SDRAM0_MCOPT2[IPTR] = 1
3034          */
3035
3036         mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3037                                SDRAM_MCOPT2_IPTR_EXECUTE));
3038
3039         /*
3040          * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3041          * completion of initialization.
3042          */
3043
3044         do {
3045                 mfsdram(SDRAM_MCSTAT, val);
3046         } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3047
3048         /* Set Delay Control Registers */
3049
3050         mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
3051         mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
3052         mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
3053         mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
3054
3055         /*
3056          * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3057          */
3058
3059         mfsdram(SDRAM_MCOPT2, val);
3060         mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3061
3062 #if defined(CONFIG_DDR_ECC)
3063         ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
3064 #endif /* defined(CONFIG_DDR_ECC) */
3065
3066         ppc4xx_ibm_ddr2_register_dump();
3067 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3068
3069         return (CFG_MBYTES_SDRAM << 20);
3070 }
3071 #endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */
3072
3073 static void ppc4xx_ibm_ddr2_register_dump(void)
3074 {
3075 #if defined(DEBUG) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
3076 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                         \
3077         do {                                                            \
3078                 u32 data;                                               \
3079                 mfsdram(SDRAM_##mnemonic, data);                        \
3080                 printf("%20s[%02x] = 0x%08X\n",                         \
3081                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
3082         } while (0)
3083
3084         printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3085
3086 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3087      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3088         PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS);
3089         PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS);
3090         PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS);
3091         PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS);
3092 #endif /* (defined(CONFIG_440SP) || ... */
3093 #if defined(CONFIG_405EX)
3094         PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3095         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3096         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3097         PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3098         PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3099         PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3100 #endif /* defined(CONFIG_405EX) */
3101         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3102         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3103         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3104         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3105         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3106         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3107         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3108         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3109         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3110         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3111         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3112         PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3113 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3114      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3115         PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3116         PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3117         /*
3118          * OPART is only used as a trigger register.
3119          *
3120          * No data is contained in this register, and reading or writing
3121          * to is can cause bad things to happen (hangs). Just skip it and
3122          * report "N/A".
3123          */
3124         printf("%20s = N/A\n", "SDRAM_OPART");
3125 #endif /* defined(CONFIG_440SP) || ... */
3126         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3127         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3128         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3129         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3130         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3131         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3132         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3133         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3134         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3135         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3136         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3137         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3138         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3139         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3140         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3141         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3142         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3143         PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3144         PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3145         PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3146         PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3147         PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3148         PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3149         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3150         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3151         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3152         PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3153         PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3154         PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
3155 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3156      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3157         PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3158 #endif /* defined(CONFIG_440SP) || ... */
3159         PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3160         PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3161         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3162 #endif /* defined(DEBUG)  && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) */