cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those are 440SP/SPe.
   5  *
   6  * (C) Copyright 2007
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * COPYRIGHT   AMCC   CORPORATION 2004
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  *
  29  */
  30
  31 /* define DEBUG for debugging output (obviously ;-)) */
  32 #if 0
  33 #define DEBUG
  34 #endif
  35
  36 #include <common.h>
  37 #include <command.h>
  38 #include <ppc4xx.h>
  39 #include <i2c.h>
  40 #include <asm/io.h>
  41 #include <asm/processor.h>
  42 #include <asm/mmu.h>
  43
  44 #if defined(CONFIG_SPD_EEPROM) &&                               \
  45         (defined(CONFIG_440SP) || defined(CONFIG_440SPE))
  46
  47 /*-----------------------------------------------------------------------------+
  48  * Defines
  49  *-----------------------------------------------------------------------------*/
  50 #ifndef TRUE
  51 #define TRUE            1
  52 #endif
  53 #ifndef FALSE
  54 #define FALSE           0
  55 #endif
  56
  57 #define SDRAM_DDR1      1
  58 #define SDRAM_DDR2      2
  59 #define SDRAM_NONE      0
  60
  61 #define MAXDIMMS        2
  62 #define MAXRANKS        4
  63 #define MAXBXCF         4
  64 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
  65
  66 #define ONE_BILLION     1000000000
  67
  68 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  69
  70 #define CMD_NOP         (7 << 19)
  71 #define CMD_PRECHARGE   (2 << 19)
  72 #define CMD_REFRESH     (1 << 19)
  73 #define CMD_EMR         (0 << 19)
  74 #define CMD_READ        (5 << 19)
  75 #define CMD_WRITE       (4 << 19)
  76
  77 #define SELECT_MR       (0 << 16)
  78 #define SELECT_EMR      (1 << 16)
  79 #define SELECT_EMR2     (2 << 16)
  80 #define SELECT_EMR3     (3 << 16)
  81
  82 /* MR */
  83 #define DLL_RESET       0x00000100
  84
  85 #define WRITE_RECOV_2   (1 << 9)
  86 #define WRITE_RECOV_3   (2 << 9)
  87 #define WRITE_RECOV_4   (3 << 9)
  88 #define WRITE_RECOV_5   (4 << 9)
  89 #define WRITE_RECOV_6   (5 << 9)
  90
  91 #define BURST_LEN_4     0x00000002
  92
  93 /* EMR */
  94 #define ODT_0_OHM       0x00000000
  95 #define ODT_50_OHM      0x00000044
  96 #define ODT_75_OHM      0x00000004
  97 #define ODT_150_OHM     0x00000040
  98
  99 #define ODS_FULL        0x00000000
 100 #define ODS_REDUCED     0x00000002
 101
 102 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 103 #define ODT_EB0R        (0x80000000 >> 8)
 104 #define ODT_EB0W        (0x80000000 >> 7)
 105 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 106 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 107 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 108
 109 /* Defines for the Read Cycle Delay test */
 110 #define NUMMEMTESTS     8
 111 #define NUMMEMWORDS     8
 112 #define NUMLOOPS        64              /* memory test loops */
 113
 114 #undef CONFIG_ECC_ERROR_RESET           /* test-only: see description below, at check_ecc() */
 115
 116 /*
 117  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
 118  * region. Right now the cache should still be disabled in U-Boot because of the
 119  * EMAC driver, that need it's buffer descriptor to be located in non cached
 120  * memory.
 121  *
 122  * If at some time this restriction doesn't apply anymore, just define
 123  * CONFIG_4xx_DCACHE in the board config file and this code should setup
 124  * everything correctly.
 125  */
 126 #ifdef CONFIG_4xx_DCACHE
 127 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
 128 #else
 129 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 130 #endif
 131
 132 /*
 133  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 134  */
 135 void __spd_ddr_init_hang (void)
 136 {
 137         hang ();
 138 }
 139 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 140
 141 /*
 142  * To provide an interface for board specific config values in this common
 143  * DDR setup code, we implement he "weak" default functions here. They return
 144  * the default value back to the caller.
 145  *
 146  * Please see include/configs/yucca.h for an example fora board specific
 147  * implementation.
 148  */
 149 u32 __ddr_wrdtr(u32 default_val)
 150 {
 151         return default_val;
 152 }
 153 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 154
 155 u32 __ddr_clktr(u32 default_val)
 156 {
 157         return default_val;
 158 }
 159 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 160
 161
 162 /* Private Structure Definitions */
 163
 164 /* enum only to ease code for cas latency setting */
 165 typedef enum ddr_cas_id {
 166         DDR_CAS_2      = 20,
 167         DDR_CAS_2_5    = 25,
 168         DDR_CAS_3      = 30,
 169         DDR_CAS_4      = 40,
 170         DDR_CAS_5      = 50
 171 } ddr_cas_id_t;
 172
 173 /*-----------------------------------------------------------------------------+
 174  * Prototypes
 175  *-----------------------------------------------------------------------------*/
 176 static unsigned long sdram_memsize(void);
 177 static void get_spd_info(unsigned long *dimm_populated,
 178                          unsigned char *iic0_dimm_addr,
 179                          unsigned long num_dimm_banks);
 180 static void check_mem_type(unsigned long *dimm_populated,
 181                            unsigned char *iic0_dimm_addr,
 182                            unsigned long num_dimm_banks);
 183 static void check_frequency(unsigned long *dimm_populated,
 184                             unsigned char *iic0_dimm_addr,
 185                             unsigned long num_dimm_banks);
 186 static void check_rank_number(unsigned long *dimm_populated,
 187                               unsigned char *iic0_dimm_addr,
 188                               unsigned long num_dimm_banks);
 189 static void check_voltage_type(unsigned long *dimm_populated,
 190                                unsigned char *iic0_dimm_addr,
 191                                unsigned long num_dimm_banks);
 192 static void program_memory_queue(unsigned long *dimm_populated,
 193                                  unsigned char *iic0_dimm_addr,
 194                                  unsigned long num_dimm_banks);
 195 static void program_codt(unsigned long *dimm_populated,
 196                          unsigned char *iic0_dimm_addr,
 197                          unsigned long num_dimm_banks);
 198 static void program_mode(unsigned long *dimm_populated,
 199                          unsigned char *iic0_dimm_addr,
 200                          unsigned long num_dimm_banks,
 201                          ddr_cas_id_t *selected_cas,
 202                          int *write_recovery);
 203 static void program_tr(unsigned long *dimm_populated,
 204                        unsigned char *iic0_dimm_addr,
 205                        unsigned long num_dimm_banks);
 206 static void program_rtr(unsigned long *dimm_populated,
 207                         unsigned char *iic0_dimm_addr,
 208                         unsigned long num_dimm_banks);
 209 static void program_bxcf(unsigned long *dimm_populated,
 210                          unsigned char *iic0_dimm_addr,
 211                          unsigned long num_dimm_banks);
 212 static void program_copt1(unsigned long *dimm_populated,
 213                           unsigned char *iic0_dimm_addr,
 214                           unsigned long num_dimm_banks);
 215 static void program_initplr(unsigned long *dimm_populated,
 216                             unsigned char *iic0_dimm_addr,
 217                             unsigned long num_dimm_banks,
 218                             ddr_cas_id_t selected_cas,
 219                             int write_recovery);
 220 static unsigned long is_ecc_enabled(void);
 221 #ifdef CONFIG_DDR_ECC
 222 static void program_ecc(unsigned long *dimm_populated,
 223                         unsigned char *iic0_dimm_addr,
 224                         unsigned long num_dimm_banks,
 225                         unsigned long tlb_word2_i_value);
 226 static void program_ecc_addr(unsigned long start_address,
 227                              unsigned long num_bytes,
 228                              unsigned long tlb_word2_i_value);
 229 #endif
 230 static void program_DQS_calibration(unsigned long *dimm_populated,
 231                                     unsigned char *iic0_dimm_addr,
 232                                     unsigned long num_dimm_banks);
 233 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 234 static void     test(void);
 235 #else
 236 static void     DQS_calibration_process(void);
 237 #endif
 238 static void ppc440sp_sdram_register_dump(void);
 239 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 240 void dcbz_area(u32 start_address, u32 num_bytes);
 241 void dflush(void);
 242
 243 static u32 mfdcr_any(u32 dcr)
 244 {
 245         u32 val;
 246
 247         switch (dcr) {
 248         case SDRAM_R0BAS + 0:
 249                 val = mfdcr(SDRAM_R0BAS + 0);
 250                 break;
 251         case SDRAM_R0BAS + 1:
 252                 val = mfdcr(SDRAM_R0BAS + 1);
 253                 break;
 254         case SDRAM_R0BAS + 2:
 255                 val = mfdcr(SDRAM_R0BAS + 2);
 256                 break;
 257         case SDRAM_R0BAS + 3:
 258                 val = mfdcr(SDRAM_R0BAS + 3);
 259                 break;
 260         default:
 261                 printf("DCR %d not defined in case statement!!!\n", dcr);
 262                 val = 0; /* just to satisfy the compiler */
 263         }
 264
 265         return val;
 266 }
 267
 268 static void mtdcr_any(u32 dcr, u32 val)
 269 {
 270         switch (dcr) {
 271         case SDRAM_R0BAS + 0:
 272                 mtdcr(SDRAM_R0BAS + 0, val);
 273                 break;
 274         case SDRAM_R0BAS + 1:
 275                 mtdcr(SDRAM_R0BAS + 1, val);
 276                 break;
 277         case SDRAM_R0BAS + 2:
 278                 mtdcr(SDRAM_R0BAS + 2, val);
 279                 break;
 280         case SDRAM_R0BAS + 3:
 281                 mtdcr(SDRAM_R0BAS + 3, val);
 282                 break;
 283         default:
 284                 printf("DCR %d not defined in case statement!!!\n", dcr);
 285         }
 286 }
 287
 288 static unsigned char spd_read(uchar chip, uint addr)
 289 {
 290         unsigned char data[2];
 291
 292         if (i2c_probe(chip) == 0)
 293                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 294                         return data[0];
 295
 296         return 0;
 297 }
 298
 299 /*-----------------------------------------------------------------------------+
 300  * sdram_memsize
 301  *-----------------------------------------------------------------------------*/
 302 static unsigned long sdram_memsize(void)
 303 {
 304         unsigned long mem_size;
 305         unsigned long mcopt2;
 306         unsigned long mcstat;
 307         unsigned long mb0cf;
 308         unsigned long sdsz;
 309         unsigned long i;
 310
 311         mem_size = 0;
 312
 313         mfsdram(SDRAM_MCOPT2, mcopt2);
 314         mfsdram(SDRAM_MCSTAT, mcstat);
 315
 316         /* DDR controller must be enabled and not in self-refresh. */
 317         /* Otherwise memsize is zero. */
 318         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 319             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 320             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 321                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 322                 for (i = 0; i < MAXBXCF; i++) {
 323                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 324                         /* Banks enabled */
 325                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 326                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 327
 328                                 switch(sdsz) {
 329                                 case SDRAM_RXBAS_SDSZ_8:
 330                                         mem_size+=8;
 331                                         break;
 332                                 case SDRAM_RXBAS_SDSZ_16:
 333                                         mem_size+=16;
 334                                         break;
 335                                 case SDRAM_RXBAS_SDSZ_32:
 336                                         mem_size+=32;
 337                                         break;
 338                                 case SDRAM_RXBAS_SDSZ_64:
 339                                         mem_size+=64;
 340                                         break;
 341                                 case SDRAM_RXBAS_SDSZ_128:
 342                                         mem_size+=128;
 343                                         break;
 344                                 case SDRAM_RXBAS_SDSZ_256:
 345                                         mem_size+=256;
 346                                         break;
 347                                 case SDRAM_RXBAS_SDSZ_512:
 348                                         mem_size+=512;
 349                                         break;
 350                                 case SDRAM_RXBAS_SDSZ_1024:
 351                                         mem_size+=1024;
 352                                         break;
 353                                 case SDRAM_RXBAS_SDSZ_2048:
 354                                         mem_size+=2048;
 355                                         break;
 356                                 case SDRAM_RXBAS_SDSZ_4096:
 357                                         mem_size+=4096;
 358                                         break;
 359                                 default:
 360                                         mem_size=0;
 361                                         break;
 362                                 }
 363                         }
 364                 }
 365         }
 366
 367         mem_size *= 1024 * 1024;
 368         return(mem_size);
 369 }
 370
 371 /*-----------------------------------------------------------------------------+
 372  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 373  * Note: This routine runs from flash with a stack set up in the chip's
 374  * sram space.  It is important that the routine does not require .sbss, .bss or
 375  * .data sections.  It also cannot call routines that require these sections.
 376  *-----------------------------------------------------------------------------*/
 377 /*-----------------------------------------------------------------------------
 378  * Function:     initdram
 379  * Description:  Configures SDRAM memory banks for DDR operation.
 380  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 381  *               via the IIC bus and then configures the DDR SDRAM memory
 382  *               banks appropriately. If Auto Memory Configuration is
 383  *               not used, it is assumed that no DIMM is plugged
 384  *-----------------------------------------------------------------------------*/
 385 long int initdram(int board_type)
 386 {
 387         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 388         unsigned char spd0[MAX_SPD_BYTES];
 389         unsigned char spd1[MAX_SPD_BYTES];
 390         unsigned char *dimm_spd[MAXDIMMS];
 391         unsigned long dimm_populated[MAXDIMMS];
 392         unsigned long num_dimm_banks;               /* on board dimm banks */
 393         unsigned long val;
 394         ddr_cas_id_t  selected_cas;
 395         int write_recovery;
 396         unsigned long dram_size = 0;
 397
 398         num_dimm_banks = sizeof(iic0_dimm_addr);
 399
 400         /*------------------------------------------------------------------
 401          * Set up an array of SPD matrixes.
 402          *-----------------------------------------------------------------*/
 403         dimm_spd[0] = spd0;
 404         dimm_spd[1] = spd1;
 405
 406         /*------------------------------------------------------------------
 407          * Reset the DDR-SDRAM controller.
 408          *-----------------------------------------------------------------*/
 409         mtsdr(SDR0_SRST, (0x80000000 >> 10));
 410         mtsdr(SDR0_SRST, 0x00000000);
 411
 412         /*
 413          * Make sure I2C controller is initialized
 414          * before continuing.
 415          */
 416
 417         /* switch to correct I2C bus */
 418         I2C_SET_BUS(CFG_SPD_BUS_NUM);
 419         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 420
 421         /*------------------------------------------------------------------
 422          * Clear out the serial presence detect buffers.
 423          * Perform IIC reads from the dimm.  Fill in the spds.
 424          * Check to see if the dimm slots are populated
 425          *-----------------------------------------------------------------*/
 426         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 427
 428         /*------------------------------------------------------------------
 429          * Check the memory type for the dimms plugged.
 430          *-----------------------------------------------------------------*/
 431         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 432
 433         /*------------------------------------------------------------------
 434          * Check the frequency supported for the dimms plugged.
 435          *-----------------------------------------------------------------*/
 436         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 437
 438         /*------------------------------------------------------------------
 439          * Check the total rank number.
 440          *-----------------------------------------------------------------*/
 441         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 442
 443         /*------------------------------------------------------------------
 444          * Check the voltage type for the dimms plugged.
 445          *-----------------------------------------------------------------*/
 446         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 447
 448         /*------------------------------------------------------------------
 449          * Program SDRAM controller options 2 register
 450          * Except Enabling of the memory controller.
 451          *-----------------------------------------------------------------*/
 452         mfsdram(SDRAM_MCOPT2, val);
 453         mtsdram(SDRAM_MCOPT2,
 454                 (val &
 455                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 456                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 457                    SDRAM_MCOPT2_ISIE_MASK))
 458                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 459                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 460                    SDRAM_MCOPT2_ISIE_ENABLE));
 461
 462         /*------------------------------------------------------------------
 463          * Program SDRAM controller options 1 register
 464          * Note: Does not enable the memory controller.
 465          *-----------------------------------------------------------------*/
 466         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 467
 468         /*------------------------------------------------------------------
 469          * Set the SDRAM Controller On Die Termination Register
 470          *-----------------------------------------------------------------*/
 471         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 472
 473         /*------------------------------------------------------------------
 474          * Program SDRAM refresh register.
 475          *-----------------------------------------------------------------*/
 476         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 477
 478         /*------------------------------------------------------------------
 479          * Program SDRAM mode register.
 480          *-----------------------------------------------------------------*/
 481         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 482                      &selected_cas, &write_recovery);
 483
 484         /*------------------------------------------------------------------
 485          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 486          *-----------------------------------------------------------------*/
 487         mfsdram(SDRAM_WRDTR, val);
 488         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 489                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 490
 491         /*------------------------------------------------------------------
 492          * Set the SDRAM Clock Timing Register
 493          *-----------------------------------------------------------------*/
 494         mfsdram(SDRAM_CLKTR, val);
 495         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 496                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 497
 498         /*------------------------------------------------------------------
 499          * Program the BxCF registers.
 500          *-----------------------------------------------------------------*/
 501         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 502
 503         /*------------------------------------------------------------------
 504          * Program SDRAM timing registers.
 505          *-----------------------------------------------------------------*/
 506         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 507
 508         /*------------------------------------------------------------------
 509          * Set the Extended Mode register
 510          *-----------------------------------------------------------------*/
 511         mfsdram(SDRAM_MEMODE, val);
 512         mtsdram(SDRAM_MEMODE,
 513                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 514                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 515                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 516                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 517
 518         /*------------------------------------------------------------------
 519          * Program Initialization preload registers.
 520          *-----------------------------------------------------------------*/
 521         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 522                         selected_cas, write_recovery);
 523
 524         /*------------------------------------------------------------------
 525          * Delay to ensure 200usec have elapsed since reset.
 526          *-----------------------------------------------------------------*/
 527         udelay(400);
 528
 529         /*------------------------------------------------------------------
 530          * Set the memory queue core base addr.
 531          *-----------------------------------------------------------------*/
 532         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 533
 534         /*------------------------------------------------------------------
 535          * Program SDRAM controller options 2 register
 536          * Enable the memory controller.
 537          *-----------------------------------------------------------------*/
 538         mfsdram(SDRAM_MCOPT2, val);
 539         mtsdram(SDRAM_MCOPT2,
 540                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 541                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 542                 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
 543
 544         /*------------------------------------------------------------------
 545          * Wait for SDRAM_CFG0_DC_EN to complete.
 546          *-----------------------------------------------------------------*/
 547         do {
 548                 mfsdram(SDRAM_MCSTAT, val);
 549         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 550
 551         /* get installed memory size */
 552         dram_size = sdram_memsize();
 553
 554         /* and program tlb entries for this size (dynamic) */
 555
 556         /*
 557          * Program TLB entries with caches enabled, for best performace
 558          * while auto-calibrating and ECC generation
 559          */
 560         program_tlb(0, 0, dram_size, 0);
 561
 562         /*------------------------------------------------------------------
 563          * DQS calibration.
 564          *-----------------------------------------------------------------*/
 565         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 566
 567 #ifdef CONFIG_DDR_ECC
 568         /*------------------------------------------------------------------
 569          * If ecc is enabled, initialize the parity bits.
 570          *-----------------------------------------------------------------*/
 571         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 572 #endif
 573
 574         /*
 575          * Now after initialization (auto-calibration and ECC generation)
 576          * remove the TLB entries with caches enabled and program again with
 577          * desired cache functionality
 578          */
 579         remove_tlb(0, dram_size);
 580         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 581
 582         ppc440sp_sdram_register_dump();
 583
 584         return dram_size;
 585 }
 586
 587 static void get_spd_info(unsigned long *dimm_populated,
 588                          unsigned char *iic0_dimm_addr,
 589                          unsigned long num_dimm_banks)
 590 {
 591         unsigned long dimm_num;
 592         unsigned long dimm_found;
 593         unsigned char num_of_bytes;
 594         unsigned char total_size;
 595
 596         dimm_found = FALSE;
 597         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 598                 num_of_bytes = 0;
 599                 total_size = 0;
 600
 601                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 602                 debug("\nspd_read(0x%x) returned %d\n",
 603                       iic0_dimm_addr[dimm_num], num_of_bytes);
 604                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 605                 debug("spd_read(0x%x) returned %d\n",
 606                       iic0_dimm_addr[dimm_num], total_size);
 607
 608                 if ((num_of_bytes != 0) && (total_size != 0)) {
 609                         dimm_populated[dimm_num] = TRUE;
 610                         dimm_found = TRUE;
 611                         debug("DIMM slot %lu: populated\n", dimm_num);
 612                 } else {
 613                         dimm_populated[dimm_num] = FALSE;
 614                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 615                 }
 616         }
 617
 618         if (dimm_found == FALSE) {
 619                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 620                 spd_ddr_init_hang ();
 621         }
 622 }
 623
 624 void board_add_ram_info(int use_default)
 625 {
 626         PPC4xx_SYS_INFO board_cfg;
 627         u32 val;
 628
 629         if (is_ecc_enabled())
 630                 puts(" (ECC");
 631         else
 632                 puts(" (ECC not");
 633
 634         get_sys_info(&board_cfg);
 635
 636         mfsdr(SDR0_DDR0, val);
 637         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 638         printf(" enabled, %d MHz", (val * 2) / 1000000);
 639
 640         mfsdram(SDRAM_MMODE, val);
 641         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 642         printf(", CL%d)", val);
 643 }
 644
 645 /*------------------------------------------------------------------
 646  * For the memory DIMMs installed, this routine verifies that they
 647  * really are DDR specific DIMMs.
 648  *-----------------------------------------------------------------*/
 649 static void check_mem_type(unsigned long *dimm_populated,
 650                            unsigned char *iic0_dimm_addr,
 651                            unsigned long num_dimm_banks)
 652 {
 653         unsigned long dimm_num;
 654         unsigned long dimm_type;
 655
 656         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 657                 if (dimm_populated[dimm_num] == TRUE) {
 658                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 659                         switch (dimm_type) {
 660                         case 1:
 661                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 662                                        "slot %d.\n", (unsigned int)dimm_num);
 663                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 664                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 665                                 spd_ddr_init_hang ();
 666                                 break;
 667                         case 2:
 668                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 669                                        (unsigned int)dimm_num);
 670                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 671                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 672                                 spd_ddr_init_hang ();
 673                                 break;
 674                         case 3:
 675                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 676                                        (unsigned int)dimm_num);
 677                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 678                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 679                                 spd_ddr_init_hang ();
 680                                 break;
 681                         case 4:
 682                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 683                                        (unsigned int)dimm_num);
 684                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 685                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 686                                 spd_ddr_init_hang ();
 687                                 break;
 688                         case 5:
 689                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 690                                        (unsigned int)dimm_num);
 691                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 692                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 693                                 spd_ddr_init_hang ();
 694                                 break;
 695                         case 6:
 696                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 697                                        (unsigned int)dimm_num);
 698                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 699                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 700                                 spd_ddr_init_hang ();
 701                                 break;
 702                         case 7:
 703                                 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
 704                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 705                                 break;
 706                         case 8:
 707                                 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
 708                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 709                                 break;
 710                         default:
 711                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 712                                        (unsigned int)dimm_num);
 713                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 714                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 715                                 spd_ddr_init_hang ();
 716                                 break;
 717                         }
 718                 }
 719         }
 720         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 721                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 722                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 723                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 724                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 725                         spd_ddr_init_hang ();
 726                 }
 727         }
 728 }
 729
 730 /*------------------------------------------------------------------
 731  * For the memory DIMMs installed, this routine verifies that
 732  * frequency previously calculated is supported.
 733  *-----------------------------------------------------------------*/
 734 static void check_frequency(unsigned long *dimm_populated,
 735                             unsigned char *iic0_dimm_addr,
 736                             unsigned long num_dimm_banks)
 737 {
 738         unsigned long dimm_num;
 739         unsigned long tcyc_reg;
 740         unsigned long cycle_time;
 741         unsigned long calc_cycle_time;
 742         unsigned long sdram_freq;
 743         unsigned long sdr_ddrpll;
 744         PPC4xx_SYS_INFO board_cfg;
 745
 746         /*------------------------------------------------------------------
 747          * Get the board configuration info.
 748          *-----------------------------------------------------------------*/
 749         get_sys_info(&board_cfg);
 750
 751         mfsdr(SDR0_DDR0, sdr_ddrpll);
 752         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 753
 754         /*
 755          * calc_cycle_time is calculated from DDR frequency set by board/chip
 756          * and is expressed in multiple of 10 picoseconds
 757          * to match the way DIMM cycle time is calculated below.
 758          */
 759         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 760
 761         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 762                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 763                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 764                         /*
 765                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 766                          * the higher order nibble (bits 4-7) designates the cycle time
 767                          * to a granularity of 1ns;
 768                          * the value presented by the lower order nibble (bits 0-3)
 769                          * has a granularity of .1ns and is added to the value designated
 770                          * by the higher nibble. In addition, four lines of the lower order
 771                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 772                          */
 773                          /* Convert from hex to decimal */
 774                         if ((tcyc_reg & 0x0F) == 0x0D)
 775                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 776                         else if ((tcyc_reg & 0x0F) == 0x0C)
 777                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 778                         else if ((tcyc_reg & 0x0F) == 0x0B)
 779                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 780                         else if ((tcyc_reg & 0x0F) == 0x0A)
 781                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 782                         else
 783                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 784                                         ((tcyc_reg & 0x0F)*10);
 785                         debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
 786
 787                         if  (cycle_time > (calc_cycle_time + 10)) {
 788                                 /*
 789                                  * the provided sdram cycle_time is too small
 790                                  * for the available DIMM cycle_time.
 791                                  * The additionnal 100ps is here to accept a small incertainty.
 792                                  */
 793                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 794                                        "slot %d \n while calculated cycle time is %d ps.\n",
 795                                        (unsigned int)(cycle_time*10),
 796                                        (unsigned int)dimm_num,
 797                                        (unsigned int)(calc_cycle_time*10));
 798                                 printf("Replace the DIMM, or change DDR frequency via "
 799                                        "strapping bits.\n\n");
 800                                 spd_ddr_init_hang ();
 801                         }
 802                 }
 803         }
 804 }
 805
 806 /*------------------------------------------------------------------
 807  * For the memory DIMMs installed, this routine verifies two
 808  * ranks/banks maximum are availables.
 809  *-----------------------------------------------------------------*/
 810 static void check_rank_number(unsigned long *dimm_populated,
 811                               unsigned char *iic0_dimm_addr,
 812                               unsigned long num_dimm_banks)
 813 {
 814         unsigned long dimm_num;
 815         unsigned long dimm_rank;
 816         unsigned long total_rank = 0;
 817
 818         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 819                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 820                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 821                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 822                                 dimm_rank = (dimm_rank & 0x0F) +1;
 823                         else
 824                                 dimm_rank = dimm_rank & 0x0F;
 825
 826
 827                         if (dimm_rank > MAXRANKS) {
 828                                 printf("ERROR: DRAM DIMM detected with %d ranks in "
 829                                        "slot %d is not supported.\n", dimm_rank, dimm_num);
 830                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 831                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 832                                 spd_ddr_init_hang ();
 833                         } else
 834                                 total_rank += dimm_rank;
 835                 }
 836                 if (total_rank > MAXRANKS) {
 837                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 838                                "for all slots.\n", (unsigned int)total_rank);
 839                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 840                         printf("Remove one of the DIMM modules.\n\n");
 841                         spd_ddr_init_hang ();
 842                 }
 843         }
 844 }
 845
 846 /*------------------------------------------------------------------
 847  * only support 2.5V modules.
 848  * This routine verifies this.
 849  *-----------------------------------------------------------------*/
 850 static void check_voltage_type(unsigned long *dimm_populated,
 851                                unsigned char *iic0_dimm_addr,
 852                                unsigned long num_dimm_banks)
 853 {
 854         unsigned long dimm_num;
 855         unsigned long voltage_type;
 856
 857         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 858                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 859                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 860                         switch (voltage_type) {
 861                         case 0x00:
 862                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 863                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 864                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 865                                        (unsigned int)dimm_num);
 866                                 spd_ddr_init_hang ();
 867                                 break;
 868                         case 0x01:
 869                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 870                                 printf("This DIMM is LVTTL.\n");
 871                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 872                                        (unsigned int)dimm_num);
 873                                 spd_ddr_init_hang ();
 874                                 break;
 875                         case 0x02:
 876                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 877                                 printf("This DIMM is 1.5 Volt.\n");
 878                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 879                                        (unsigned int)dimm_num);
 880                                 spd_ddr_init_hang ();
 881                                 break;
 882                         case 0x03:
 883                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 884                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 885                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 886                                        (unsigned int)dimm_num);
 887                                 spd_ddr_init_hang ();
 888                                 break;
 889                         case 0x04:
 890                                 /* 2.5 Voltage only for DDR1 */
 891                                 break;
 892                         case 0x05:
 893                                 /* 1.8 Voltage only for DDR2 */
 894                                 break;
 895                         default:
 896                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 897                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 898                                        (unsigned int)dimm_num);
 899                                 spd_ddr_init_hang ();
 900                                 break;
 901                         }
 902                 }
 903         }
 904 }
 905
 906 /*-----------------------------------------------------------------------------+
 907  * program_copt1.
 908  *-----------------------------------------------------------------------------*/
 909 static void program_copt1(unsigned long *dimm_populated,
 910                           unsigned char *iic0_dimm_addr,
 911                           unsigned long num_dimm_banks)
 912 {
 913         unsigned long dimm_num;
 914         unsigned long mcopt1;
 915         unsigned long ecc_enabled;
 916         unsigned long ecc = 0;
 917         unsigned long data_width = 0;
 918         unsigned long dimm_32bit;
 919         unsigned long dimm_64bit;
 920         unsigned long registered = 0;
 921         unsigned long attribute = 0;
 922         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 923         unsigned long bankcount;
 924         unsigned long ddrtype;
 925         unsigned long val;
 926
 927 #ifdef CONFIG_DDR_ECC
 928         ecc_enabled = TRUE;
 929 #else
 930         ecc_enabled = FALSE;
 931 #endif
 932         dimm_32bit = FALSE;
 933         dimm_64bit = FALSE;
 934         buf0 = FALSE;
 935         buf1 = FALSE;
 936
 937         /*------------------------------------------------------------------
 938          * Set memory controller options reg 1, SDRAM_MCOPT1.
 939          *-----------------------------------------------------------------*/
 940         mfsdram(SDRAM_MCOPT1, val);
 941         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 942                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 943                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 944                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 945                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
 946                          SDRAM_MCOPT1_DREF_MASK);
 947
 948         mcopt1 |= SDRAM_MCOPT1_QDEP;
 949         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
 950         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
 951         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
 952         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
 953         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
 954
 955         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 956                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 957                         /* test ecc support */
 958                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 959                         if (ecc != 0x02) /* ecc not supported */
 960                                 ecc_enabled = FALSE;
 961
 962                         /* test bank count */
 963                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
 964                         if (bankcount == 0x04) /* bank count = 4 */
 965                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
 966                         else /* bank count = 8 */
 967                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
 968
 969                         /* test DDR type */
 970                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
 971                         /* test for buffered/unbuffered, registered, differential clocks */
 972                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
 973                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
 974
 975                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 976                         if (dimm_num == 0) {
 977                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
 978                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
 979                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
 980                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
 981                                 if (registered == 1) { /* DDR2 always buffered */
 982                                         /* TODO: what about above  comments ? */
 983                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
 984                                         buf0 = TRUE;
 985                                 } else {
 986                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
 987                                         if ((attribute & 0x02) == 0x00) {
 988                                                 /* buffered not supported */
 989                                                 buf0 = FALSE;
 990                                         } else {
 991                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
 992                                                 buf0 = TRUE;
 993                                         }
 994                                 }
 995                         }
 996                         else if (dimm_num == 1) {
 997                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
 998                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
 999                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1000                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1001                                 if (registered == 1) {
1002                                         /* DDR2 always buffered */
1003                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1004                                         buf1 = TRUE;
1005                                 } else {
1006                                         if ((attribute & 0x02) == 0x00) {
1007                                                 /* buffered not supported */
1008                                                 buf1 = FALSE;
1009                                         } else {
1010                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1011                                                 buf1 = TRUE;
1012                                         }
1013                                 }
1014                         }
1015
1016                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1017                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1018                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1019
1020                         switch (data_width) {
1021                         case 72:
1022                         case 64:
1023                                 dimm_64bit = TRUE;
1024                                 break;
1025                         case 40:
1026                         case 32:
1027                                 dimm_32bit = TRUE;
1028                                 break;
1029                         default:
1030                                 printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
1031                                        data_width);
1032                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1033                                 break;
1034                         }
1035                 }
1036         }
1037
1038         /* verify matching properties */
1039         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1040                 if (buf0 != buf1) {
1041                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1042                         spd_ddr_init_hang ();
1043                 }
1044         }
1045
1046         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1047                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1048                 spd_ddr_init_hang ();
1049         }
1050         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1051                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1052         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1053                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1054         } else {
1055                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1056                 spd_ddr_init_hang ();
1057         }
1058
1059         if (ecc_enabled == TRUE)
1060                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1061         else
1062                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1063
1064         mtsdram(SDRAM_MCOPT1, mcopt1);
1065 }
1066
1067 /*-----------------------------------------------------------------------------+
1068  * program_codt.
1069  *-----------------------------------------------------------------------------*/
1070 static void program_codt(unsigned long *dimm_populated,
1071                          unsigned char *iic0_dimm_addr,
1072                          unsigned long num_dimm_banks)
1073 {
1074         unsigned long codt;
1075         unsigned long modt0 = 0;
1076         unsigned long modt1 = 0;
1077         unsigned long modt2 = 0;
1078         unsigned long modt3 = 0;
1079         unsigned char dimm_num;
1080         unsigned char dimm_rank;
1081         unsigned char total_rank = 0;
1082         unsigned char total_dimm = 0;
1083         unsigned char dimm_type = 0;
1084         unsigned char firstSlot = 0;
1085
1086         /*------------------------------------------------------------------
1087          * Set the SDRAM Controller On Die Termination Register
1088          *-----------------------------------------------------------------*/
1089         mfsdram(SDRAM_CODT, codt);
1090         codt |= (SDRAM_CODT_IO_NMODE
1091                  & (~SDRAM_CODT_DQS_SINGLE_END
1092                     & ~SDRAM_CODT_CKSE_SINGLE_END
1093                     & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1094                     & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1095
1096         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1097                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1098                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1099                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1100                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1101                                 dimm_type = SDRAM_DDR2;
1102                         } else {
1103                                 dimm_rank = dimm_rank & 0x0F;
1104                                 dimm_type = SDRAM_DDR1;
1105                         }
1106
1107                         total_rank += dimm_rank;
1108                         total_dimm++;
1109                         if ((dimm_num == 0) && (total_dimm == 1))
1110                                 firstSlot = TRUE;
1111                         else
1112                                 firstSlot = FALSE;
1113                 }
1114         }
1115         if (dimm_type == SDRAM_DDR2) {
1116                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1117                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1118                         if (total_rank == 1) {
1119                                 codt |= CALC_ODT_R(0);
1120                                 modt0 = CALC_ODT_W(0);
1121                                 modt1 = 0x00000000;
1122                                 modt2 = 0x00000000;
1123                                 modt3 = 0x00000000;
1124                         }
1125                         if (total_rank == 2) {
1126                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1127                                 modt0 = CALC_ODT_W(0);
1128                                 modt1 = CALC_ODT_W(0);
1129                                 modt2 = 0x00000000;
1130                                 modt3 = 0x00000000;
1131                         }
1132                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1133                         if (total_rank == 1) {
1134                                 codt |= CALC_ODT_R(2);
1135                                 modt0 = 0x00000000;
1136                                 modt1 = 0x00000000;
1137                                 modt2 = CALC_ODT_W(2);
1138                                 modt3 = 0x00000000;
1139                         }
1140                         if (total_rank == 2) {
1141                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1142                                 modt0 = 0x00000000;
1143                                 modt1 = 0x00000000;
1144                                 modt2 = CALC_ODT_W(2);
1145                                 modt3 = CALC_ODT_W(2);
1146                         }
1147                 }
1148                 if (total_dimm == 2) {
1149                         if (total_rank == 2) {
1150                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1151                                 modt0 = CALC_ODT_RW(2);
1152                                 modt1 = 0x00000000;
1153                                 modt2 = CALC_ODT_RW(0);
1154                                 modt3 = 0x00000000;
1155                         }
1156                         if (total_rank == 4) {
1157                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1158                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1159                                 modt0 = CALC_ODT_RW(2);
1160                                 modt1 = 0x00000000;
1161                                 modt2 = CALC_ODT_RW(0);
1162                                 modt3 = 0x00000000;
1163                         }
1164                 }
1165         } else {
1166                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1167                 modt0 = 0x00000000;
1168                 modt1 = 0x00000000;
1169                 modt2 = 0x00000000;
1170                 modt3 = 0x00000000;
1171
1172                 if (total_dimm == 1) {
1173                         if (total_rank == 1)
1174                                 codt |= 0x00800000;
1175                         if (total_rank == 2)
1176                                 codt |= 0x02800000;
1177                 }
1178                 if (total_dimm == 2) {
1179                         if (total_rank == 2)
1180                                 codt |= 0x08800000;
1181                         if (total_rank == 4)
1182                                 codt |= 0x2a800000;
1183                 }
1184         }
1185
1186         debug("nb of dimm %d\n", total_dimm);
1187         debug("nb of rank %d\n", total_rank);
1188         if (total_dimm == 1)
1189                 debug("dimm in slot %d\n", firstSlot);
1190
1191         mtsdram(SDRAM_CODT, codt);
1192         mtsdram(SDRAM_MODT0, modt0);
1193         mtsdram(SDRAM_MODT1, modt1);
1194         mtsdram(SDRAM_MODT2, modt2);
1195         mtsdram(SDRAM_MODT3, modt3);
1196 }
1197
1198 /*-----------------------------------------------------------------------------+
1199  * program_initplr.
1200  *-----------------------------------------------------------------------------*/
1201 static void program_initplr(unsigned long *dimm_populated,
1202                             unsigned char *iic0_dimm_addr,
1203                             unsigned long num_dimm_banks,
1204                             ddr_cas_id_t selected_cas,
1205                             int write_recovery)
1206 {
1207         u32 cas = 0;
1208         u32 odt = 0;
1209         u32 ods = 0;
1210         u32 mr;
1211         u32 wr;
1212         u32 emr;
1213         u32 emr2;
1214         u32 emr3;
1215         int dimm_num;
1216         int total_dimm = 0;
1217
1218         /******************************************************
1219          ** Assumption: if more than one DIMM, all DIMMs are the same
1220          **             as already checked in check_memory_type
1221          ******************************************************/
1222
1223         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1224                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1225                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1226                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1227                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1228                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1229                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1230                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1231                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1232         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1233                 switch (selected_cas) {
1234                 case DDR_CAS_3:
1235                         cas = 3 << 4;
1236                         break;
1237                 case DDR_CAS_4:
1238                         cas = 4 << 4;
1239                         break;
1240                 case DDR_CAS_5:
1241                         cas = 5 << 4;
1242                         break;
1243                 default:
1244                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1245                         spd_ddr_init_hang ();
1246                         break;
1247                 }
1248
1249 #if 0
1250                 /*
1251                  * ToDo - Still a problem with the write recovery:
1252                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1253                  * in the INITPLR reg to the value calculated in program_mode()
1254                  * results in not correctly working DDR2 memory (crash after
1255                  * relocation).
1256                  *
1257                  * So for now, set the write recovery to 3. This seems to work
1258                  * on the Corair module too.
1259                  *
1260                  * 2007-03-01, sr
1261                  */
1262                 switch (write_recovery) {
1263                 case 3:
1264                         wr = WRITE_RECOV_3;
1265                         break;
1266                 case 4:
1267                         wr = WRITE_RECOV_4;
1268                         break;
1269                 case 5:
1270                         wr = WRITE_RECOV_5;
1271                         break;
1272                 case 6:
1273                         wr = WRITE_RECOV_6;
1274                         break;
1275                 default:
1276                         printf("ERROR: write recovery not support (%d)", write_recovery);
1277                         spd_ddr_init_hang ();
1278                         break;
1279                 }
1280 #else
1281                 wr = WRITE_RECOV_3; /* test-only, see description above */
1282 #endif
1283
1284                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1285                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1286                                 total_dimm++;
1287                 if (total_dimm == 1) {
1288                         odt = ODT_150_OHM;
1289                         ods = ODS_FULL;
1290                 } else if (total_dimm == 2) {
1291                         odt = ODT_75_OHM;
1292                         ods = ODS_REDUCED;
1293                 } else {
1294                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1295                         spd_ddr_init_hang ();
1296                 }
1297
1298                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1299                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1300                 emr2 = CMD_EMR | SELECT_EMR2;
1301                 emr3 = CMD_EMR | SELECT_EMR3;
1302                 mtsdram(SDRAM_INITPLR0,  0xB5000000 | CMD_NOP);         /* NOP */
1303                 udelay(1000);
1304                 mtsdram(SDRAM_INITPLR1,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1305                 mtsdram(SDRAM_INITPLR2,  0x80800000 | emr2);            /* EMR2 */
1306                 mtsdram(SDRAM_INITPLR3,  0x80800000 | emr3);            /* EMR3 */
1307                 mtsdram(SDRAM_INITPLR4,  0x80800000 | emr);             /* EMR DLL ENABLE */
1308                 mtsdram(SDRAM_INITPLR5,  0x80800000 | mr | DLL_RESET);  /* MR w/ DLL reset */
1309                 udelay(1000);
1310                 mtsdram(SDRAM_INITPLR6,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1311                 mtsdram(SDRAM_INITPLR7,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1312                 mtsdram(SDRAM_INITPLR8,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1313                 mtsdram(SDRAM_INITPLR9,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1314                 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1315                 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr);              /* MR w/o DLL reset */
1316                 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr);             /* EMR OCD Default */
1317                 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr);             /* EMR OCD Exit */
1318         } else {
1319                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1320                 spd_ddr_init_hang ();
1321         }
1322 }
1323
1324 /*------------------------------------------------------------------
1325  * This routine programs the SDRAM_MMODE register.
1326  * the selected_cas is an output parameter, that will be passed
1327  * by caller to call the above program_initplr( )
1328  *-----------------------------------------------------------------*/
1329 static void program_mode(unsigned long *dimm_populated,
1330                          unsigned char *iic0_dimm_addr,
1331                          unsigned long num_dimm_banks,
1332                          ddr_cas_id_t *selected_cas,
1333                          int *write_recovery)
1334 {
1335         unsigned long dimm_num;
1336         unsigned long sdram_ddr1;
1337         unsigned long t_wr_ns;
1338         unsigned long t_wr_clk;
1339         unsigned long cas_bit;
1340         unsigned long cas_index;
1341         unsigned long sdram_freq;
1342         unsigned long ddr_check;
1343         unsigned long mmode;
1344         unsigned long tcyc_reg;
1345         unsigned long cycle_2_0_clk;
1346         unsigned long cycle_2_5_clk;
1347         unsigned long cycle_3_0_clk;
1348         unsigned long cycle_4_0_clk;
1349         unsigned long cycle_5_0_clk;
1350         unsigned long max_2_0_tcyc_ns_x_100;
1351         unsigned long max_2_5_tcyc_ns_x_100;
1352         unsigned long max_3_0_tcyc_ns_x_100;
1353         unsigned long max_4_0_tcyc_ns_x_100;
1354         unsigned long max_5_0_tcyc_ns_x_100;
1355         unsigned long cycle_time_ns_x_100[3];
1356         PPC4xx_SYS_INFO board_cfg;
1357         unsigned char cas_2_0_available;
1358         unsigned char cas_2_5_available;
1359         unsigned char cas_3_0_available;
1360         unsigned char cas_4_0_available;
1361         unsigned char cas_5_0_available;
1362         unsigned long sdr_ddrpll;
1363
1364         /*------------------------------------------------------------------
1365          * Get the board configuration info.
1366          *-----------------------------------------------------------------*/
1367         get_sys_info(&board_cfg);
1368
1369         mfsdr(SDR0_DDR0, sdr_ddrpll);
1370         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1371         debug("sdram_freq=%d\n", sdram_freq);
1372
1373         /*------------------------------------------------------------------
1374          * Handle the timing.  We need to find the worst case timing of all
1375          * the dimm modules installed.
1376          *-----------------------------------------------------------------*/
1377         t_wr_ns = 0;
1378         cas_2_0_available = TRUE;
1379         cas_2_5_available = TRUE;
1380         cas_3_0_available = TRUE;
1381         cas_4_0_available = TRUE;
1382         cas_5_0_available = TRUE;
1383         max_2_0_tcyc_ns_x_100 = 10;
1384         max_2_5_tcyc_ns_x_100 = 10;
1385         max_3_0_tcyc_ns_x_100 = 10;
1386         max_4_0_tcyc_ns_x_100 = 10;
1387         max_5_0_tcyc_ns_x_100 = 10;
1388         sdram_ddr1 = TRUE;
1389
1390         /* loop through all the DIMM slots on the board */
1391         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1392                 /* If a dimm is installed in a particular slot ... */
1393                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1394                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1395                                 sdram_ddr1 = TRUE;
1396                         else
1397                                 sdram_ddr1 = FALSE;
1398
1399                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1400                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1401                         debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1402
1403                         /* For a particular DIMM, grab the three CAS values it supports */
1404                         for (cas_index = 0; cas_index < 3; cas_index++) {
1405                                 switch (cas_index) {
1406                                 case 0:
1407                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1408                                         break;
1409                                 case 1:
1410                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1411                                         break;
1412                                 default:
1413                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1414                                         break;
1415                                 }
1416
1417                                 if ((tcyc_reg & 0x0F) >= 10) {
1418                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1419                                                 /* Convert from hex to decimal */
1420                                                 cycle_time_ns_x_100[cas_index] =
1421                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1422                                         } else {
1423                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1424                                                        "in slot %d\n", (unsigned int)dimm_num);
1425                                                 spd_ddr_init_hang ();
1426                                         }
1427                                 } else {
1428                                         /* Convert from hex to decimal */
1429                                         cycle_time_ns_x_100[cas_index] =
1430                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1431                                                 ((tcyc_reg & 0x0F)*10);
1432                                 }
1433                                 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1434                                       cycle_time_ns_x_100[cas_index]);
1435                         }
1436
1437                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1438                         /* supported for a particular DIMM. */
1439                         cas_index = 0;
1440
1441                         if (sdram_ddr1) {
1442                                 /*
1443                                  * DDR devices use the following bitmask for CAS latency:
1444                                  *  Bit   7    6    5    4    3    2    1    0
1445                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1446                                  */
1447                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1448                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1449                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1450                                                                     cycle_time_ns_x_100[cas_index]);
1451                                         cas_index++;
1452                                 } else {
1453                                         if (cas_index != 0)
1454                                                 cas_index++;
1455                                         cas_4_0_available = FALSE;
1456                                 }
1457
1458                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1459                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1460                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1461                                                                     cycle_time_ns_x_100[cas_index]);
1462                                         cas_index++;
1463                                 } else {
1464                                         if (cas_index != 0)
1465                                                 cas_index++;
1466                                         cas_3_0_available = FALSE;
1467                                 }
1468
1469                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1470                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1471                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1472                                                                     cycle_time_ns_x_100[cas_index]);
1473                                         cas_index++;
1474                                 } else {
1475                                         if (cas_index != 0)
1476                                                 cas_index++;
1477                                         cas_2_5_available = FALSE;
1478                                 }
1479
1480                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1481                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1482                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1483                                                                     cycle_time_ns_x_100[cas_index]);
1484                                         cas_index++;
1485                                 } else {
1486                                         if (cas_index != 0)
1487                                                 cas_index++;
1488                                         cas_2_0_available = FALSE;
1489                                 }
1490                         } else {
1491                                 /*
1492                                  * DDR2 devices use the following bitmask for CAS latency:
1493                                  *  Bit   7    6    5    4    3    2    1    0
1494                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1495                                  */
1496                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1497                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1498                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1499                                                                     cycle_time_ns_x_100[cas_index]);
1500                                         cas_index++;
1501                                 } else {
1502                                         if (cas_index != 0)
1503                                                 cas_index++;
1504                                         cas_5_0_available = FALSE;
1505                                 }
1506
1507                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1508                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1509                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1510                                                                     cycle_time_ns_x_100[cas_index]);
1511                                         cas_index++;
1512                                 } else {
1513                                         if (cas_index != 0)
1514                                                 cas_index++;
1515                                         cas_4_0_available = FALSE;
1516                                 }
1517
1518                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1519                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1520                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1521                                                                     cycle_time_ns_x_100[cas_index]);
1522                                         cas_index++;
1523                                 } else {
1524                                         if (cas_index != 0)
1525                                                 cas_index++;
1526                                         cas_3_0_available = FALSE;
1527                                 }
1528                         }
1529                 }
1530         }
1531
1532         /*------------------------------------------------------------------
1533          * Set the SDRAM mode, SDRAM_MMODE
1534          *-----------------------------------------------------------------*/
1535         mfsdram(SDRAM_MMODE, mmode);
1536         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1537
1538         /* add 10 here because of rounding problems */
1539         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1540         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1541         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1542         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1543         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1544         debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1545         debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1546         debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1547
1548         if (sdram_ddr1 == TRUE) { /* DDR1 */
1549                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1550                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1551                         *selected_cas = DDR_CAS_2;
1552                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1553                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1554                         *selected_cas = DDR_CAS_2_5;
1555                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1556                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1557                         *selected_cas = DDR_CAS_3;
1558                 } else {
1559                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1560                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1561                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1562                         spd_ddr_init_hang ();
1563                 }
1564         } else { /* DDR2 */
1565                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1566                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1567                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1568                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1569                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1570                         *selected_cas = DDR_CAS_3;
1571                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1572                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1573                         *selected_cas = DDR_CAS_4;
1574                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1575                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1576                         *selected_cas = DDR_CAS_5;
1577                 } else {
1578                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1579                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1580                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1581                         printf("cas3=%d cas4=%d cas5=%d\n",
1582                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1583                         printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
1584                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1585                         spd_ddr_init_hang ();
1586                 }
1587         }
1588
1589         if (sdram_ddr1 == TRUE)
1590                 mmode |= SDRAM_MMODE_WR_DDR1;
1591         else {
1592
1593                 /* loop through all the DIMM slots on the board */
1594                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1595                         /* If a dimm is installed in a particular slot ... */
1596                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1597                                 t_wr_ns = max(t_wr_ns,
1598                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1599                 }
1600
1601                 /*
1602                  * convert from nanoseconds to ddr clocks
1603                  * round up if necessary
1604                  */
1605                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1606                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1607                 if (sdram_freq != ddr_check)
1608                         t_wr_clk++;
1609
1610                 switch (t_wr_clk) {
1611                 case 0:
1612                 case 1:
1613                 case 2:
1614                 case 3:
1615                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1616                         break;
1617                 case 4:
1618                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1619                         break;
1620                 case 5:
1621                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1622                         break;
1623                 default:
1624                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1625                         break;
1626                 }
1627                 *write_recovery = t_wr_clk;
1628         }
1629
1630         debug("CAS latency = %d\n", *selected_cas);
1631         debug("Write recovery = %d\n", *write_recovery);
1632
1633         mtsdram(SDRAM_MMODE, mmode);
1634 }
1635
1636 /*-----------------------------------------------------------------------------+
1637  * program_rtr.
1638  *-----------------------------------------------------------------------------*/
1639 static void program_rtr(unsigned long *dimm_populated,
1640                         unsigned char *iic0_dimm_addr,
1641                         unsigned long num_dimm_banks)
1642 {
1643         PPC4xx_SYS_INFO board_cfg;
1644         unsigned long max_refresh_rate;
1645         unsigned long dimm_num;
1646         unsigned long refresh_rate_type;
1647         unsigned long refresh_rate;
1648         unsigned long rint;
1649         unsigned long sdram_freq;
1650         unsigned long sdr_ddrpll;
1651         unsigned long val;
1652
1653         /*------------------------------------------------------------------
1654          * Get the board configuration info.
1655          *-----------------------------------------------------------------*/
1656         get_sys_info(&board_cfg);
1657
1658         /*------------------------------------------------------------------
1659          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1660          *-----------------------------------------------------------------*/
1661         mfsdr(SDR0_DDR0, sdr_ddrpll);
1662         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1663
1664         max_refresh_rate = 0;
1665         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1666                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1667
1668                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1669                         refresh_rate_type &= 0x7F;
1670                         switch (refresh_rate_type) {
1671                         case 0:
1672                                 refresh_rate =  15625;
1673                                 break;
1674                         case 1:
1675                                 refresh_rate =   3906;
1676                                 break;
1677                         case 2:
1678                                 refresh_rate =   7812;
1679                                 break;
1680                         case 3:
1681                                 refresh_rate =  31250;
1682                                 break;
1683                         case 4:
1684                                 refresh_rate =  62500;
1685                                 break;
1686                         case 5:
1687                                 refresh_rate = 125000;
1688                                 break;
1689                         default:
1690                                 refresh_rate = 0;
1691                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1692                                        (unsigned int)dimm_num);
1693                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1694                                 spd_ddr_init_hang ();
1695                                 break;
1696                         }
1697
1698                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1699                 }
1700         }
1701
1702         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1703         mfsdram(SDRAM_RTR, val);
1704         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1705                 (SDRAM_RTR_RINT_ENCODE(rint)));
1706 }
1707
1708 /*------------------------------------------------------------------
1709  * This routine programs the SDRAM_TRx registers.
1710  *-----------------------------------------------------------------*/
1711 static void program_tr(unsigned long *dimm_populated,
1712                        unsigned char *iic0_dimm_addr,
1713                        unsigned long num_dimm_banks)
1714 {
1715         unsigned long dimm_num;
1716         unsigned long sdram_ddr1;
1717         unsigned long t_rp_ns;
1718         unsigned long t_rcd_ns;
1719         unsigned long t_rrd_ns;
1720         unsigned long t_ras_ns;
1721         unsigned long t_rc_ns;
1722         unsigned long t_rfc_ns;
1723         unsigned long t_wpc_ns;
1724         unsigned long t_wtr_ns;
1725         unsigned long t_rpc_ns;
1726         unsigned long t_rp_clk;
1727         unsigned long t_rcd_clk;
1728         unsigned long t_rrd_clk;
1729         unsigned long t_ras_clk;
1730         unsigned long t_rc_clk;
1731         unsigned long t_rfc_clk;
1732         unsigned long t_wpc_clk;
1733         unsigned long t_wtr_clk;
1734         unsigned long t_rpc_clk;
1735         unsigned long sdtr1, sdtr2, sdtr3;
1736         unsigned long ddr_check;
1737         unsigned long sdram_freq;
1738         unsigned long sdr_ddrpll;
1739
1740         PPC4xx_SYS_INFO board_cfg;
1741
1742         /*------------------------------------------------------------------
1743          * Get the board configuration info.
1744          *-----------------------------------------------------------------*/
1745         get_sys_info(&board_cfg);
1746
1747         mfsdr(SDR0_DDR0, sdr_ddrpll);
1748         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1749
1750         /*------------------------------------------------------------------
1751          * Handle the timing.  We need to find the worst case timing of all
1752          * the dimm modules installed.
1753          *-----------------------------------------------------------------*/
1754         t_rp_ns = 0;
1755         t_rrd_ns = 0;
1756         t_rcd_ns = 0;
1757         t_ras_ns = 0;
1758         t_rc_ns = 0;
1759         t_rfc_ns = 0;
1760         t_wpc_ns = 0;
1761         t_wtr_ns = 0;
1762         t_rpc_ns = 0;
1763         sdram_ddr1 = TRUE;
1764
1765         /* loop through all the DIMM slots on the board */
1766         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1767                 /* If a dimm is installed in a particular slot ... */
1768                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1769                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1770                                 sdram_ddr1 = TRUE;
1771                         else
1772                                 sdram_ddr1 = FALSE;
1773
1774                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1775                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1776                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1777                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1778                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1779                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1780                 }
1781         }
1782
1783         /*------------------------------------------------------------------
1784          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1785          *-----------------------------------------------------------------*/
1786         mfsdram(SDRAM_SDTR1, sdtr1);
1787         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1788                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1789
1790         /* default values */
1791         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1792         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1793
1794         /* normal operations */
1795         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1796         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1797
1798         mtsdram(SDRAM_SDTR1, sdtr1);
1799
1800         /*------------------------------------------------------------------
1801          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1802          *-----------------------------------------------------------------*/
1803         mfsdram(SDRAM_SDTR2, sdtr2);
1804         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1805                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1806                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1807                    SDRAM_SDTR2_RRD_MASK);
1808
1809         /*
1810          * convert t_rcd from nanoseconds to ddr clocks
1811          * round up if necessary
1812          */
1813         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1814         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1815         if (sdram_freq != ddr_check)
1816                 t_rcd_clk++;
1817
1818         switch (t_rcd_clk) {
1819         case 0:
1820         case 1:
1821                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1822                 break;
1823         case 2:
1824                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1825                 break;
1826         case 3:
1827                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1828                 break;
1829         case 4:
1830                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1831                 break;
1832         default:
1833                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1834                 break;
1835         }
1836
1837         if (sdram_ddr1 == TRUE) { /* DDR1 */
1838                 if (sdram_freq < 200000000) {
1839                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1840                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1841                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1842                 } else {
1843                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1844                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1845                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1846                 }
1847         } else { /* DDR2 */
1848                 /* loop through all the DIMM slots on the board */
1849                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1850                         /* If a dimm is installed in a particular slot ... */
1851                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1852                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1853                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1854                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1855                         }
1856                 }
1857
1858                 /*
1859                  * convert from nanoseconds to ddr clocks
1860                  * round up if necessary
1861                  */
1862                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1863                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1864                 if (sdram_freq != ddr_check)
1865                         t_wpc_clk++;
1866
1867                 switch (t_wpc_clk) {
1868                 case 0:
1869                 case 1:
1870                 case 2:
1871                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1872                         break;
1873                 case 3:
1874                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1875                         break;
1876                 case 4:
1877                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1878                         break;
1879                 case 5:
1880                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1881                         break;
1882                 default:
1883                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1884                         break;
1885                 }
1886
1887                 /*
1888                  * convert from nanoseconds to ddr clocks
1889                  * round up if necessary
1890                  */
1891                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1892                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1893                 if (sdram_freq != ddr_check)
1894                         t_wtr_clk++;
1895
1896                 switch (t_wtr_clk) {
1897                 case 0:
1898                 case 1:
1899                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1900                         break;
1901                 case 2:
1902                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1903                         break;
1904                 case 3:
1905                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1906                         break;
1907                 default:
1908                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1909                         break;
1910                 }
1911
1912                 /*
1913                  * convert from nanoseconds to ddr clocks
1914                  * round up if necessary
1915                  */
1916                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1917                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1918                 if (sdram_freq != ddr_check)
1919                         t_rpc_clk++;
1920
1921                 switch (t_rpc_clk) {
1922                 case 0:
1923                 case 1:
1924                 case 2:
1925                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1926                         break;
1927                 case 3:
1928                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1929                         break;
1930                 default:
1931                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1932                         break;
1933                 }
1934         }
1935
1936         /* default value */
1937         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1938
1939         /*
1940          * convert t_rrd from nanoseconds to ddr clocks
1941          * round up if necessary
1942          */
1943         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1944         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1945         if (sdram_freq != ddr_check)
1946                 t_rrd_clk++;
1947
1948         if (t_rrd_clk == 3)
1949                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1950         else
1951                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1952
1953         /*
1954          * convert t_rp from nanoseconds to ddr clocks
1955          * round up if necessary
1956          */
1957         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1958         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1959         if (sdram_freq != ddr_check)
1960                 t_rp_clk++;
1961
1962         switch (t_rp_clk) {
1963         case 0:
1964         case 1:
1965         case 2:
1966         case 3:
1967                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
1968                 break;
1969         case 4:
1970                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
1971                 break;
1972         case 5:
1973                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
1974                 break;
1975         case 6:
1976                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
1977                 break;
1978         default:
1979                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
1980                 break;
1981         }
1982
1983         mtsdram(SDRAM_SDTR2, sdtr2);
1984
1985         /*------------------------------------------------------------------
1986          * Set the SDRAM Timing Reg 3, SDRAM_TR3
1987          *-----------------------------------------------------------------*/
1988         mfsdram(SDRAM_SDTR3, sdtr3);
1989         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
1990                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
1991
1992         /*
1993          * convert t_ras from nanoseconds to ddr clocks
1994          * round up if necessary
1995          */
1996         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
1997         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
1998         if (sdram_freq != ddr_check)
1999                 t_ras_clk++;
2000
2001         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2002
2003         /*
2004          * convert t_rc from nanoseconds to ddr clocks
2005          * round up if necessary
2006          */
2007         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2008         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2009         if (sdram_freq != ddr_check)
2010                 t_rc_clk++;
2011
2012         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2013
2014         /* default xcs value */
2015         sdtr3 |= SDRAM_SDTR3_XCS;
2016
2017         /*
2018          * convert t_rfc from nanoseconds to ddr clocks
2019          * round up if necessary
2020          */
2021         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2022         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2023         if (sdram_freq != ddr_check)
2024                 t_rfc_clk++;
2025
2026         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2027
2028         mtsdram(SDRAM_SDTR3, sdtr3);
2029 }
2030
2031 /*-----------------------------------------------------------------------------+
2032  * program_bxcf.
2033  *-----------------------------------------------------------------------------*/
2034 static void program_bxcf(unsigned long *dimm_populated,
2035                          unsigned char *iic0_dimm_addr,
2036                          unsigned long num_dimm_banks)
2037 {
2038         unsigned long dimm_num;
2039         unsigned long num_col_addr;
2040         unsigned long num_ranks;
2041         unsigned long num_banks;
2042         unsigned long mode;
2043         unsigned long ind_rank;
2044         unsigned long ind;
2045         unsigned long ind_bank;
2046         unsigned long bank_0_populated;
2047
2048         /*------------------------------------------------------------------
2049          * Set the BxCF regs.  First, wipe out the bank config registers.
2050          *-----------------------------------------------------------------*/
2051         mtsdram(SDRAM_MB0CF, 0x00000000);
2052         mtsdram(SDRAM_MB1CF, 0x00000000);
2053         mtsdram(SDRAM_MB2CF, 0x00000000);
2054         mtsdram(SDRAM_MB3CF, 0x00000000);
2055
2056         mode = SDRAM_BXCF_M_BE_ENABLE;
2057
2058         bank_0_populated = 0;
2059
2060         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2061                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2062                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2063                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2064                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2065                                 num_ranks = (num_ranks & 0x0F) +1;
2066                         else
2067                                 num_ranks = num_ranks & 0x0F;
2068
2069                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2070
2071                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2072                                 if (num_banks == 4)
2073                                         ind = 0;
2074                                 else
2075                                         ind = 5;
2076                                 switch (num_col_addr) {
2077                                 case 0x08:
2078                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2079                                         break;
2080                                 case 0x09:
2081                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2082                                         break;
2083                                 case 0x0A:
2084                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2085                                         break;
2086                                 case 0x0B:
2087                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2088                                         break;
2089                                 case 0x0C:
2090                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2091                                         break;
2092                                 default:
2093                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2094                                                (unsigned int)dimm_num);
2095                                         printf("ERROR: Unsupported value for number of "
2096                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2097                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2098                                         spd_ddr_init_hang ();
2099                                 }
2100                         }
2101
2102                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2103                                 bank_0_populated = 1;
2104
2105                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2106                                 mtsdram(SDRAM_MB0CF +
2107                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2108                                         mode);
2109                         }
2110                 }
2111         }
2112 }
2113
2114 /*------------------------------------------------------------------
2115  * program memory queue.
2116  *-----------------------------------------------------------------*/
2117 static void program_memory_queue(unsigned long *dimm_populated,
2118                                  unsigned char *iic0_dimm_addr,
2119                                  unsigned long num_dimm_banks)
2120 {
2121         unsigned long dimm_num;
2122         unsigned long rank_base_addr;
2123         unsigned long rank_reg;
2124         unsigned long rank_size_bytes;
2125         unsigned long rank_size_id;
2126         unsigned long num_ranks;
2127         unsigned long baseadd_size;
2128         unsigned long i;
2129         unsigned long bank_0_populated = 0;
2130
2131         /*------------------------------------------------------------------
2132          * Reset the rank_base_address.
2133          *-----------------------------------------------------------------*/
2134         rank_reg   = SDRAM_R0BAS;
2135
2136         rank_base_addr = 0x00000000;
2137
2138         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2139                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2140                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2141                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2142                                 num_ranks = (num_ranks & 0x0F) + 1;
2143                         else
2144                                 num_ranks = num_ranks & 0x0F;
2145
2146                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2147
2148                         /*------------------------------------------------------------------
2149                          * Set the sizes
2150                          *-----------------------------------------------------------------*/
2151                         baseadd_size = 0;
2152                         rank_size_bytes = 4 * 1024 * 1024 * rank_size_id;
2153                         switch (rank_size_id) {
2154                         case 0x02:
2155                                 baseadd_size |= SDRAM_RXBAS_SDSZ_8;
2156                                 break;
2157                         case 0x04:
2158                                 baseadd_size |= SDRAM_RXBAS_SDSZ_16;
2159                                 break;
2160                         case 0x08:
2161                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2162                                 break;
2163                         case 0x10:
2164                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2165                                 break;
2166                         case 0x20:
2167                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2168                                 break;
2169                         case 0x40:
2170                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2171                                 break;
2172                         case 0x80:
2173                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2174                                 break;
2175                         default:
2176                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2177                                        (unsigned int)dimm_num);
2178                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2179                                        (unsigned int)rank_size_id);
2180                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2181                                 spd_ddr_init_hang ();
2182                         }
2183
2184                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2185                                 bank_0_populated = 1;
2186
2187                         for (i = 0; i < num_ranks; i++) {
2188                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2189                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2190                                            baseadd_size));
2191                                 rank_base_addr += rank_size_bytes;
2192                         }
2193                 }
2194         }
2195 }
2196
2197 /*-----------------------------------------------------------------------------+
2198  * is_ecc_enabled.
2199  *-----------------------------------------------------------------------------*/
2200 static unsigned long is_ecc_enabled(void)
2201 {
2202         unsigned long dimm_num;
2203         unsigned long ecc;
2204         unsigned long val;
2205
2206         ecc = 0;
2207         /* loop through all the DIMM slots on the board */
2208         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2209                 mfsdram(SDRAM_MCOPT1, val);
2210                 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2211         }
2212
2213         return ecc;
2214 }
2215
2216 static void blank_string(int size)
2217 {
2218         int i;
2219
2220         for (i=0; i<size; i++)
2221                 putc('\b');
2222         for (i=0; i<size; i++)
2223                 putc(' ');
2224         for (i=0; i<size; i++)
2225                 putc('\b');
2226 }
2227
2228 #ifdef CONFIG_DDR_ECC
2229 /*-----------------------------------------------------------------------------+
2230  * program_ecc.
2231  *-----------------------------------------------------------------------------*/
2232 static void program_ecc(unsigned long *dimm_populated,
2233                         unsigned char *iic0_dimm_addr,
2234                         unsigned long num_dimm_banks,
2235                         unsigned long tlb_word2_i_value)
2236 {
2237         unsigned long mcopt1;
2238         unsigned long mcopt2;
2239         unsigned long mcstat;
2240         unsigned long dimm_num;
2241         unsigned long ecc;
2242
2243         ecc = 0;
2244         /* loop through all the DIMM slots on the board */
2245         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2246                 /* If a dimm is installed in a particular slot ... */
2247                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2248                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2249         }
2250         if (ecc == 0)
2251                 return;
2252
2253         mfsdram(SDRAM_MCOPT1, mcopt1);
2254         mfsdram(SDRAM_MCOPT2, mcopt2);
2255
2256         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2257                 /* DDR controller must be enabled and not in self-refresh. */
2258                 mfsdram(SDRAM_MCSTAT, mcstat);
2259                 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2260                     && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2261                     && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2262                         == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2263
2264                         program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2265                 }
2266         }
2267
2268         return;
2269 }
2270
2271 #ifdef CONFIG_ECC_ERROR_RESET
2272 /*
2273  * Check for ECC errors and reset board upon any error here
2274  *
2275  * On the Katmai 440SPe eval board, from time to time, the first
2276  * lword write access after DDR2 initializazion with ECC checking
2277  * enabled, leads to an ECC error. I couldn't find a configuration
2278  * without this happening. On my board with the current setup it
2279  * happens about 1 from 10 times.
2280  *
2281  * The ECC modules used for testing are:
2282  * - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's)
2283  *
2284  * This has to get fixed for the Katmai and tested for the other
2285  * board (440SP/440SPe) that will eventually use this code in the
2286  * future.
2287  *
2288  * 2007-03-01, sr
2289  */
2290 static void check_ecc(void)
2291 {
2292         u32 val;
2293
2294         mfsdram(SDRAM_ECCCR, val);
2295         if (val != 0) {
2296                 printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n",
2297                        val, mfdcr(0x4c), mfdcr(0x4e));
2298                 printf("ECC error occured, resetting board...\n");
2299                 do_reset(NULL, 0, 0, NULL);
2300         }
2301 }
2302 #endif
2303
2304 static void wait_ddr_idle(void)
2305 {
2306         u32 val;
2307
2308         do {
2309                 mfsdram(SDRAM_MCSTAT, val);
2310         } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2311 }
2312
2313 /*-----------------------------------------------------------------------------+
2314  * program_ecc_addr.
2315  *-----------------------------------------------------------------------------*/
2316 static void program_ecc_addr(unsigned long start_address,
2317                              unsigned long num_bytes,
2318                              unsigned long tlb_word2_i_value)
2319 {
2320         unsigned long current_address;
2321         unsigned long end_address;
2322         unsigned long address_increment;
2323         unsigned long mcopt1;
2324         char str[] = "ECC generation -";
2325         char slash[] = "\\|/-\\|/-";
2326         int loop = 0;
2327         int loopi = 0;
2328
2329         current_address = start_address;
2330         mfsdram(SDRAM_MCOPT1, mcopt1);
2331         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2332                 mtsdram(SDRAM_MCOPT1,
2333                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2334                 sync();
2335                 eieio();
2336                 wait_ddr_idle();
2337
2338                 puts(str);
2339                 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2340                         /* ECC bit set method for non-cached memory */
2341                         if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2342                                 address_increment = 4;
2343                         else
2344                                 address_increment = 8;
2345                         end_address = current_address + num_bytes;
2346
2347                         while (current_address < end_address) {
2348                                 *((unsigned long *)current_address) = 0x00000000;
2349                                 current_address += address_increment;
2350
2351                                 if ((loop++ % (2 << 20)) == 0) {
2352                                         putc('\b');
2353                                         putc(slash[loopi++ % 8]);
2354                                 }
2355                         }
2356
2357                 } else {
2358                         /* ECC bit set method for cached memory */
2359                         dcbz_area(start_address, num_bytes);
2360                         dflush();
2361                 }
2362
2363                 blank_string(strlen(str));
2364
2365                 sync();
2366                 eieio();
2367                 wait_ddr_idle();
2368
2369                 /* clear ECC error repoting registers */
2370                 mtsdram(SDRAM_ECCCR, 0xffffffff);
2371                 mtdcr(0x4c, 0xffffffff);
2372
2373                 mtsdram(SDRAM_MCOPT1,
2374                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2375                 sync();
2376                 eieio();
2377                 wait_ddr_idle();
2378
2379 #ifdef CONFIG_ECC_ERROR_RESET
2380                 /*
2381                  * One write to 0 is enough to trigger this ECC error
2382                  * (see description above)
2383                  */
2384                 out_be32(0, 0x12345678);
2385                 check_ecc();
2386 #endif
2387         }
2388 }
2389 #endif
2390
2391 /*-----------------------------------------------------------------------------+
2392  * program_DQS_calibration.
2393  *-----------------------------------------------------------------------------*/
2394 static void program_DQS_calibration(unsigned long *dimm_populated,
2395                                     unsigned char *iic0_dimm_addr,
2396                                     unsigned long num_dimm_banks)
2397 {
2398         unsigned long val;
2399
2400 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2401         mtsdram(SDRAM_RQDC, 0x80000037);
2402         mtsdram(SDRAM_RDCC, 0x40000000);
2403         mtsdram(SDRAM_RFDC, 0x000001DF);
2404
2405         test();
2406 #else
2407         /*------------------------------------------------------------------
2408          * Program RDCC register
2409          * Read sample cycle auto-update enable
2410          *-----------------------------------------------------------------*/
2411
2412         /*
2413          * Modified for the Katmai platform:  with some DIMMs, the DDR2
2414          * controller automatically selects the T2 read cycle, but this
2415          * proves unreliable.  Go ahead and force the DDR2 controller
2416          * to use the T4 sample and disable the automatic update of the
2417          * RDSS field.
2418          */
2419         mfsdram(SDRAM_RDCC, val);
2420         mtsdram(SDRAM_RDCC,
2421                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2422                 | (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
2423
2424         /*------------------------------------------------------------------
2425          * Program RQDC register
2426          * Internal DQS delay mechanism enable
2427          *-----------------------------------------------------------------*/
2428         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2429
2430         /*------------------------------------------------------------------
2431          * Program RFDC register
2432          * Set Feedback Fractional Oversample
2433          * Auto-detect read sample cycle enable
2434          *-----------------------------------------------------------------*/
2435         mfsdram(SDRAM_RFDC, val);
2436         mtsdram(SDRAM_RFDC,
2437                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2438                          SDRAM_RFDC_RFFD_MASK))
2439                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2440                    SDRAM_RFDC_RFFD_ENCODE(0)));
2441
2442         DQS_calibration_process();
2443 #endif
2444 }
2445
2446 static int short_mem_test(void)
2447 {
2448         u32 *membase;
2449         u32 bxcr_num;
2450         u32 bxcf;
2451         int i;
2452         int j;
2453         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2454                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2455                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2456                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2457                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2458                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2459                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2460                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2461                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2462                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2463                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2464                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2465                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2466                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2467                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2468                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2469                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2470         int l;
2471
2472         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2473                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2474
2475                 /* Banks enabled */
2476                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2477                         /* Bank is enabled */
2478
2479                         /*------------------------------------------------------------------
2480                          * Run the short memory test.
2481                          *-----------------------------------------------------------------*/
2482                         membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
2483
2484                         for (i = 0; i < NUMMEMTESTS; i++) {
2485                                 for (j = 0; j < NUMMEMWORDS; j++) {
2486                                         membase[j] = test[i][j];
2487                                         ppcDcbf((u32)&(membase[j]));
2488                                 }
2489                                 sync();
2490                                 for (l=0; l<NUMLOOPS; l++) {
2491                                         for (j = 0; j < NUMMEMWORDS; j++) {
2492                                                 if (membase[j] != test[i][j]) {
2493                                                         ppcDcbf((u32)&(membase[j]));
2494                                                         return 0;
2495                                                 }
2496                                                 ppcDcbf((u32)&(membase[j]));
2497                                         }
2498                                         sync();
2499                                 }
2500                         }
2501                 }       /* if bank enabled */
2502         }               /* for bxcf_num */
2503
2504         return 1;
2505 }
2506
2507 #ifndef HARD_CODED_DQS
2508 /*-----------------------------------------------------------------------------+
2509  * DQS_calibration_process.
2510  *-----------------------------------------------------------------------------*/
2511 static void DQS_calibration_process(void)
2512 {
2513         unsigned long rfdc_reg;
2514         unsigned long rffd;
2515         unsigned long rqdc_reg;
2516         unsigned long rqfd;
2517         unsigned long val;
2518         long rqfd_average;
2519         long rffd_average;
2520         long max_start;
2521         long min_end;
2522         unsigned long begin_rqfd[MAXRANKS];
2523         unsigned long begin_rffd[MAXRANKS];
2524         unsigned long end_rqfd[MAXRANKS];
2525         unsigned long end_rffd[MAXRANKS];
2526         char window_found;
2527         unsigned long dlycal;
2528         unsigned long dly_val;
2529         unsigned long max_pass_length;
2530         unsigned long current_pass_length;
2531         unsigned long current_fail_length;
2532         unsigned long current_start;
2533         long max_end;
2534         unsigned char fail_found;
2535         unsigned char pass_found;
2536         u32 rqfd_start;
2537         char str[] = "Auto calibration -";
2538         char slash[] = "\\|/-\\|/-";
2539         int loopi = 0;
2540
2541         /*------------------------------------------------------------------
2542          * Test to determine the best read clock delay tuning bits.
2543          *
2544          * Before the DDR controller can be used, the read clock delay needs to be
2545          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2546          * This value cannot be hardcoded into the program because it changes
2547          * depending on the board's setup and environment.
2548          * To do this, all delay values are tested to see if they
2549          * work or not.  By doing this, you get groups of fails with groups of
2550          * passing values.  The idea is to find the start and end of a passing
2551          * window and take the center of it to use as the read clock delay.
2552          *
2553          * A failure has to be seen first so that when we hit a pass, we know
2554          * that it is truely the start of the window.  If we get passing values
2555          * to start off with, we don't know if we are at the start of the window.
2556          *
2557          * The code assumes that a failure will always be found.
2558          * If a failure is not found, there is no easy way to get the middle
2559          * of the passing window.  I guess we can pretty much pick any value
2560          * but some values will be better than others.  Since the lowest speed
2561          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2562          * from experimentation it is safe to say you will always have a failure.
2563          *-----------------------------------------------------------------*/
2564
2565         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2566         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2567
2568         puts(str);
2569
2570 calibration_loop:
2571         mfsdram(SDRAM_RQDC, rqdc_reg);
2572         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2573                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2574
2575         max_start = 0;
2576         min_end = 0;
2577         begin_rqfd[0] = 0;
2578         begin_rffd[0] = 0;
2579         begin_rqfd[1] = 0;
2580         begin_rffd[1] = 0;
2581         end_rqfd[0] = 0;
2582         end_rffd[0] = 0;
2583         end_rqfd[1] = 0;
2584         end_rffd[1] = 0;
2585         window_found = FALSE;
2586
2587         max_pass_length = 0;
2588         max_start = 0;
2589         max_end = 0;
2590         current_pass_length = 0;
2591         current_fail_length = 0;
2592         current_start = 0;
2593         window_found = FALSE;
2594         fail_found = FALSE;
2595         pass_found = FALSE;
2596
2597         /*
2598          * get the delay line calibration register value
2599          */
2600         mfsdram(SDRAM_DLCR, dlycal);
2601         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2602
2603         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2604                 mfsdram(SDRAM_RFDC, rfdc_reg);
2605                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2606
2607                 /*------------------------------------------------------------------
2608                  * Set the timing reg for the test.
2609                  *-----------------------------------------------------------------*/
2610                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2611
2612                 /*------------------------------------------------------------------
2613                  * See if the rffd value passed.
2614                  *-----------------------------------------------------------------*/
2615                 if (short_mem_test()) {
2616                         if (fail_found == TRUE) {
2617                                 pass_found = TRUE;
2618                                 if (current_pass_length == 0)
2619                                         current_start = rffd;
2620
2621                                 current_fail_length = 0;
2622                                 current_pass_length++;
2623
2624                                 if (current_pass_length > max_pass_length) {
2625                                         max_pass_length = current_pass_length;
2626                                         max_start = current_start;
2627                                         max_end = rffd;
2628                                 }
2629                         }
2630                 } else {
2631                         current_pass_length = 0;
2632                         current_fail_length++;
2633
2634                         if (current_fail_length >= (dly_val >> 2)) {
2635                                 if (fail_found == FALSE) {
2636                                         fail_found = TRUE;
2637                                 } else if (pass_found == TRUE) {
2638                                         window_found = TRUE;
2639                                         break;
2640                                 }
2641                         }
2642                 }
2643         }               /* for rffd */
2644
2645         /*------------------------------------------------------------------
2646          * Set the average RFFD value
2647          *-----------------------------------------------------------------*/
2648         rffd_average = ((max_start + max_end) >> 1);
2649
2650         if (rffd_average < 0)
2651                 rffd_average = 0;
2652
2653         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2654                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2655         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2656         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2657
2658         max_pass_length = 0;
2659         max_start = 0;
2660         max_end = 0;
2661         current_pass_length = 0;
2662         current_fail_length = 0;
2663         current_start = 0;
2664         window_found = FALSE;
2665         fail_found = FALSE;
2666         pass_found = FALSE;
2667
2668         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2669                 mfsdram(SDRAM_RQDC, rqdc_reg);
2670                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2671
2672                 /*------------------------------------------------------------------
2673                  * Set the timing reg for the test.
2674                  *-----------------------------------------------------------------*/
2675                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2676
2677                 /*------------------------------------------------------------------
2678                  * See if the rffd value passed.
2679                  *-----------------------------------------------------------------*/
2680                 if (short_mem_test()) {
2681                         if (fail_found == TRUE) {
2682                                 pass_found = TRUE;
2683                                 if (current_pass_length == 0)
2684                                         current_start = rqfd;
2685
2686                                 current_fail_length = 0;
2687                                 current_pass_length++;
2688
2689                                 if (current_pass_length > max_pass_length) {
2690                                         max_pass_length = current_pass_length;
2691                                         max_start = current_start;
2692                                         max_end = rqfd;
2693                                 }
2694                         }
2695                 } else {
2696                         current_pass_length = 0;
2697                         current_fail_length++;
2698
2699                         if (fail_found == FALSE) {
2700                                 fail_found = TRUE;
2701                         } else if (pass_found == TRUE) {
2702                                 window_found = TRUE;
2703                                 break;
2704                         }
2705                 }
2706         }
2707
2708         rqfd_average = ((max_start + max_end) >> 1);
2709
2710         /*------------------------------------------------------------------
2711          * Make sure we found the valid read passing window.  Halt if not
2712          *-----------------------------------------------------------------*/
2713         if (window_found == FALSE) {
2714                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2715                         putc('\b');
2716                         putc(slash[loopi++ % 8]);
2717
2718                         /* try again from with a different RQFD start value */
2719                         rqfd_start++;
2720                         goto calibration_loop;
2721                 }
2722
2723                 printf("\nERROR: Cannot determine a common read delay for the "
2724                        "DIMM(s) installed.\n");
2725                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2726                 ppc440sp_sdram_register_dump();
2727                 spd_ddr_init_hang ();
2728         }
2729
2730         blank_string(strlen(str));
2731
2732         if (rqfd_average < 0)
2733                 rqfd_average = 0;
2734
2735         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2736                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2737
2738         mtsdram(SDRAM_RQDC,
2739                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2740                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2741
2742         mfsdram(SDRAM_DLCR, val);
2743         debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2744         mfsdram(SDRAM_RQDC, val);
2745         debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2746         mfsdram(SDRAM_RFDC, val);
2747         debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2748 }
2749 #else /* calibration test with hardvalues */
2750 /*-----------------------------------------------------------------------------+
2751  * DQS_calibration_process.
2752  *-----------------------------------------------------------------------------*/
2753 static void test(void)
2754 {
2755         unsigned long dimm_num;
2756         unsigned long ecc_temp;
2757         unsigned long i, j;
2758         unsigned long *membase;
2759         unsigned long bxcf[MAXRANKS];
2760         unsigned long val;
2761         char window_found;
2762         char begin_found[MAXDIMMS];
2763         char end_found[MAXDIMMS];
2764         char search_end[MAXDIMMS];
2765         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2766                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2767                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2768                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2769                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2770                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2771                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2772                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2773                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2774                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2775                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2776                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2777                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2778                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2779                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2780                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2781                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2782
2783         /*------------------------------------------------------------------
2784          * Test to determine the best read clock delay tuning bits.
2785          *
2786          * Before the DDR controller can be used, the read clock delay needs to be
2787          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2788          * This value cannot be hardcoded into the program because it changes
2789          * depending on the board's setup and environment.
2790          * To do this, all delay values are tested to see if they
2791          * work or not.  By doing this, you get groups of fails with groups of
2792          * passing values.  The idea is to find the start and end of a passing
2793          * window and take the center of it to use as the read clock delay.
2794          *
2795          * A failure has to be seen first so that when we hit a pass, we know
2796          * that it is truely the start of the window.  If we get passing values
2797          * to start off with, we don't know if we are at the start of the window.
2798          *
2799          * The code assumes that a failure will always be found.
2800          * If a failure is not found, there is no easy way to get the middle
2801          * of the passing window.  I guess we can pretty much pick any value
2802          * but some values will be better than others.  Since the lowest speed
2803          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2804          * from experimentation it is safe to say you will always have a failure.
2805          *-----------------------------------------------------------------*/
2806         mfsdram(SDRAM_MCOPT1, ecc_temp);
2807         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2808         mfsdram(SDRAM_MCOPT1, val);
2809         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2810                 SDRAM_MCOPT1_MCHK_NON);
2811
2812         window_found = FALSE;
2813         begin_found[0] = FALSE;
2814         end_found[0] = FALSE;
2815         search_end[0] = FALSE;
2816         begin_found[1] = FALSE;
2817         end_found[1] = FALSE;
2818         search_end[1] = FALSE;
2819
2820         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2821                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2822
2823                 /* Banks enabled */
2824                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2825
2826                         /* Bank is enabled */
2827                         membase =
2828                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2829
2830                         /*------------------------------------------------------------------
2831                          * Run the short memory test.
2832                          *-----------------------------------------------------------------*/
2833                         for (i = 0; i < NUMMEMTESTS; i++) {
2834                                 for (j = 0; j < NUMMEMWORDS; j++) {
2835                                         membase[j] = test[i][j];
2836                                         ppcDcbf((u32)&(membase[j]));
2837                                 }
2838                                 sync();
2839                                 for (j = 0; j < NUMMEMWORDS; j++) {
2840                                         if (membase[j] != test[i][j]) {
2841                                                 ppcDcbf((u32)&(membase[j]));
2842                                                 break;
2843                                         }
2844                                         ppcDcbf((u32)&(membase[j]));
2845                                 }
2846                                 sync();
2847                                 if (j < NUMMEMWORDS)
2848                                         break;
2849                         }
2850
2851                         /*------------------------------------------------------------------
2852                          * See if the rffd value passed.
2853                          *-----------------------------------------------------------------*/
2854                         if (i < NUMMEMTESTS) {
2855                                 if ((end_found[dimm_num] == FALSE) &&
2856                                     (search_end[dimm_num] == TRUE)) {
2857                                         end_found[dimm_num] = TRUE;
2858                                 }
2859                                 if ((end_found[0] == TRUE) &&
2860                                     (end_found[1] == TRUE))
2861                                         break;
2862                         } else {
2863                                 if (begin_found[dimm_num] == FALSE) {
2864                                         begin_found[dimm_num] = TRUE;
2865                                         search_end[dimm_num] = TRUE;
2866                                 }
2867                         }
2868                 } else {
2869                         begin_found[dimm_num] = TRUE;
2870                         end_found[dimm_num] = TRUE;
2871                 }
2872         }
2873
2874         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2875                 window_found = TRUE;
2876
2877         /*------------------------------------------------------------------
2878          * Make sure we found the valid read passing window.  Halt if not
2879          *-----------------------------------------------------------------*/
2880         if (window_found == FALSE) {
2881                 printf("ERROR: Cannot determine a common read delay for the "
2882                        "DIMM(s) installed.\n");
2883                 spd_ddr_init_hang ();
2884         }
2885
2886         /*------------------------------------------------------------------
2887          * Restore the ECC variable to what it originally was
2888          *-----------------------------------------------------------------*/
2889         mtsdram(SDRAM_MCOPT1,
2890                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2891                 | ecc_temp);
2892 }
2893 #endif
2894
2895 #if defined(DEBUG)
2896 static void ppc440sp_sdram_register_dump(void)
2897 {
2898         unsigned int sdram_reg;
2899         unsigned int sdram_data;
2900         unsigned int dcr_data;
2901
2902         printf("\n  Register Dump:\n");
2903         sdram_reg = SDRAM_MCSTAT;
2904         mfsdram(sdram_reg, sdram_data);
2905         printf("        SDRAM_MCSTAT    = 0x%08X", sdram_data);
2906         sdram_reg = SDRAM_MCOPT1;
2907         mfsdram(sdram_reg, sdram_data);
2908         printf("        SDRAM_MCOPT1    = 0x%08X\n", sdram_data);
2909         sdram_reg = SDRAM_MCOPT2;
2910         mfsdram(sdram_reg, sdram_data);
2911         printf("        SDRAM_MCOPT2    = 0x%08X", sdram_data);
2912         sdram_reg = SDRAM_MODT0;
2913         mfsdram(sdram_reg, sdram_data);
2914         printf("        SDRAM_MODT0     = 0x%08X\n", sdram_data);
2915         sdram_reg = SDRAM_MODT1;
2916         mfsdram(sdram_reg, sdram_data);
2917         printf("        SDRAM_MODT1     = 0x%08X", sdram_data);
2918         sdram_reg = SDRAM_MODT2;
2919         mfsdram(sdram_reg, sdram_data);
2920         printf("        SDRAM_MODT2     = 0x%08X\n", sdram_data);
2921         sdram_reg = SDRAM_MODT3;
2922         mfsdram(sdram_reg, sdram_data);
2923         printf("        SDRAM_MODT3     = 0x%08X", sdram_data);
2924         sdram_reg = SDRAM_CODT;
2925         mfsdram(sdram_reg, sdram_data);
2926         printf("        SDRAM_CODT      = 0x%08X\n", sdram_data);
2927         sdram_reg = SDRAM_VVPR;
2928         mfsdram(sdram_reg, sdram_data);
2929         printf("        SDRAM_VVPR      = 0x%08X", sdram_data);
2930         sdram_reg = SDRAM_OPARS;
2931         mfsdram(sdram_reg, sdram_data);
2932         printf("        SDRAM_OPARS     = 0x%08X\n", sdram_data);
2933         /*
2934          * OPAR2 is only used as a trigger register.
2935          * No data is contained in this register, and reading or writing
2936          * to is can cause bad things to happen (hangs).  Just skip it
2937          * and report NA
2938          * sdram_reg = SDRAM_OPAR2;
2939          * mfsdram(sdram_reg, sdram_data);
2940          * printf("        SDRAM_OPAR2     = 0x%08X\n", sdram_data);
2941          */
2942         printf("        SDRAM_OPART     = N/A       ");
2943         sdram_reg = SDRAM_RTR;
2944         mfsdram(sdram_reg, sdram_data);
2945         printf("        SDRAM_RTR       = 0x%08X\n", sdram_data);
2946         sdram_reg = SDRAM_MB0CF;
2947         mfsdram(sdram_reg, sdram_data);
2948         printf("        SDRAM_MB0CF     = 0x%08X", sdram_data);
2949         sdram_reg = SDRAM_MB1CF;
2950         mfsdram(sdram_reg, sdram_data);
2951         printf("        SDRAM_MB1CF     = 0x%08X\n", sdram_data);
2952         sdram_reg = SDRAM_MB2CF;
2953         mfsdram(sdram_reg, sdram_data);
2954         printf("        SDRAM_MB2CF     = 0x%08X", sdram_data);
2955         sdram_reg = SDRAM_MB3CF;
2956         mfsdram(sdram_reg, sdram_data);
2957         printf("        SDRAM_MB3CF     = 0x%08X\n", sdram_data);
2958         sdram_reg = SDRAM_INITPLR0;
2959         mfsdram(sdram_reg, sdram_data);
2960         printf("        SDRAM_INITPLR0  = 0x%08X", sdram_data);
2961         sdram_reg = SDRAM_INITPLR1;
2962         mfsdram(sdram_reg, sdram_data);
2963         printf("        SDRAM_INITPLR1  = 0x%08X\n", sdram_data);
2964         sdram_reg = SDRAM_INITPLR2;
2965         mfsdram(sdram_reg, sdram_data);
2966         printf("        SDRAM_INITPLR2  = 0x%08X", sdram_data);
2967         sdram_reg = SDRAM_INITPLR3;
2968         mfsdram(sdram_reg, sdram_data);
2969         printf("        SDRAM_INITPLR3  = 0x%08X\n", sdram_data);
2970         sdram_reg = SDRAM_INITPLR4;
2971         mfsdram(sdram_reg, sdram_data);
2972         printf("        SDRAM_INITPLR4  = 0x%08X", sdram_data);
2973         sdram_reg = SDRAM_INITPLR5;
2974         mfsdram(sdram_reg, sdram_data);
2975         printf("        SDRAM_INITPLR5  = 0x%08X\n", sdram_data);
2976         sdram_reg = SDRAM_INITPLR6;
2977         mfsdram(sdram_reg, sdram_data);
2978         printf("        SDRAM_INITPLR6  = 0x%08X", sdram_data);
2979         sdram_reg = SDRAM_INITPLR7;
2980         mfsdram(sdram_reg, sdram_data);
2981         printf("        SDRAM_INITPLR7  = 0x%08X\n", sdram_data);
2982         sdram_reg = SDRAM_INITPLR8;
2983         mfsdram(sdram_reg, sdram_data);
2984         printf("        SDRAM_INITPLR8  = 0x%08X", sdram_data);
2985         sdram_reg = SDRAM_INITPLR9;
2986         mfsdram(sdram_reg, sdram_data);
2987         printf("        SDRAM_INITPLR9  = 0x%08X\n", sdram_data);
2988         sdram_reg = SDRAM_INITPLR10;
2989         mfsdram(sdram_reg, sdram_data);
2990         printf("        SDRAM_INITPLR10 = 0x%08X", sdram_data);
2991         sdram_reg = SDRAM_INITPLR11;
2992         mfsdram(sdram_reg, sdram_data);
2993         printf("        SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
2994         sdram_reg = SDRAM_INITPLR12;
2995         mfsdram(sdram_reg, sdram_data);
2996         printf("        SDRAM_INITPLR12 = 0x%08X", sdram_data);
2997         sdram_reg = SDRAM_INITPLR13;
2998         mfsdram(sdram_reg, sdram_data);
2999         printf("        SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
3000         sdram_reg = SDRAM_INITPLR14;
3001         mfsdram(sdram_reg, sdram_data);
3002         printf("        SDRAM_INITPLR14 = 0x%08X", sdram_data);
3003         sdram_reg = SDRAM_INITPLR15;
3004         mfsdram(sdram_reg, sdram_data);
3005         printf("        SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
3006         sdram_reg = SDRAM_RQDC;
3007         mfsdram(sdram_reg, sdram_data);
3008         printf("        SDRAM_RQDC      = 0x%08X", sdram_data);
3009         sdram_reg = SDRAM_RFDC;
3010         mfsdram(sdram_reg, sdram_data);
3011         printf("        SDRAM_RFDC      = 0x%08X\n", sdram_data);
3012         sdram_reg = SDRAM_RDCC;
3013         mfsdram(sdram_reg, sdram_data);
3014         printf("        SDRAM_RDCC      = 0x%08X", sdram_data);
3015         sdram_reg = SDRAM_DLCR;
3016         mfsdram(sdram_reg, sdram_data);
3017         printf("        SDRAM_DLCR      = 0x%08X\n", sdram_data);
3018         sdram_reg = SDRAM_CLKTR;
3019         mfsdram(sdram_reg, sdram_data);
3020         printf("        SDRAM_CLKTR     = 0x%08X", sdram_data);
3021         sdram_reg = SDRAM_WRDTR;
3022         mfsdram(sdram_reg, sdram_data);
3023         printf("        SDRAM_WRDTR     = 0x%08X\n", sdram_data);
3024         sdram_reg = SDRAM_SDTR1;
3025         mfsdram(sdram_reg, sdram_data);
3026         printf("        SDRAM_SDTR1     = 0x%08X", sdram_data);
3027         sdram_reg = SDRAM_SDTR2;
3028         mfsdram(sdram_reg, sdram_data);
3029         printf("        SDRAM_SDTR2     = 0x%08X\n", sdram_data);
3030         sdram_reg = SDRAM_SDTR3;
3031         mfsdram(sdram_reg, sdram_data);
3032         printf("        SDRAM_SDTR3     = 0x%08X", sdram_data);
3033         sdram_reg = SDRAM_MMODE;
3034         mfsdram(sdram_reg, sdram_data);
3035         printf("        SDRAM_MMODE     = 0x%08X\n", sdram_data);
3036         sdram_reg = SDRAM_MEMODE;
3037         mfsdram(sdram_reg, sdram_data);
3038         printf("        SDRAM_MEMODE    = 0x%08X", sdram_data);
3039         sdram_reg = SDRAM_ECCCR;
3040         mfsdram(sdram_reg, sdram_data);
3041         printf("        SDRAM_ECCCR     = 0x%08X\n\n", sdram_data);
3042
3043         dcr_data = mfdcr(SDRAM_R0BAS);
3044         printf("        MQ0_B0BAS       = 0x%08X", dcr_data);
3045         dcr_data = mfdcr(SDRAM_R1BAS);
3046         printf("        MQ1_B0BAS       = 0x%08X\n", dcr_data);
3047         dcr_data = mfdcr(SDRAM_R2BAS);
3048         printf("        MQ2_B0BAS       = 0x%08X", dcr_data);
3049         dcr_data = mfdcr(SDRAM_R3BAS);
3050         printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
3051 }
3052 #else
3053 static void ppc440sp_sdram_register_dump(void)
3054 {
3055 }
3056 #endif
3057 #endif /* CONFIG_SPD_EEPROM */