cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX(r)
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * Copyright (c) 2008 Nuovation System Designs, LLC
  10  *   Grant Erickson <gerickson@nuovations.com>
  11
  12  * (C) Copyright 2007-2008
  13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14  *
  15  * COPYRIGHT   AMCC   CORPORATION 2004
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  *
  35  */
  36
  37 /* define DEBUG for debugging output (obviously ;-)) */
  38 #if 0
  39 #define DEBUG
  40 #endif
  41
  42 #include <common.h>
  43 #include <command.h>
  44 #include <ppc4xx.h>
  45 #include <i2c.h>
  46 #include <asm/io.h>
  47 #include <asm/processor.h>
  48 #include <asm/mmu.h>
  49 #include <asm/cache.h>
  50
  51 #include "ecc.h"
  52
  53 #if defined(CONFIG_SPD_EEPROM) &&                               \
  54         (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  55          defined(CONFIG_460EX) || defined(CONFIG_460GT))
  56
  57 /*-----------------------------------------------------------------------------+
  58  * Defines
  59  *-----------------------------------------------------------------------------*/
  60 #ifndef TRUE
  61 #define TRUE            1
  62 #endif
  63 #ifndef FALSE
  64 #define FALSE           0
  65 #endif
  66
  67 #define SDRAM_DDR1      1
  68 #define SDRAM_DDR2      2
  69 #define SDRAM_NONE      0
  70
  71 #define MAXDIMMS        2
  72 #define MAXRANKS        4
  73 #define MAXBXCF         4
  74 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
  75
  76 #define ONE_BILLION     1000000000
  77
  78 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  79
  80 #define CMD_NOP         (7 << 19)
  81 #define CMD_PRECHARGE   (2 << 19)
  82 #define CMD_REFRESH     (1 << 19)
  83 #define CMD_EMR         (0 << 19)
  84 #define CMD_READ        (5 << 19)
  85 #define CMD_WRITE       (4 << 19)
  86
  87 #define SELECT_MR       (0 << 16)
  88 #define SELECT_EMR      (1 << 16)
  89 #define SELECT_EMR2     (2 << 16)
  90 #define SELECT_EMR3     (3 << 16)
  91
  92 /* MR */
  93 #define DLL_RESET       0x00000100
  94
  95 #define WRITE_RECOV_2   (1 << 9)
  96 #define WRITE_RECOV_3   (2 << 9)
  97 #define WRITE_RECOV_4   (3 << 9)
  98 #define WRITE_RECOV_5   (4 << 9)
  99 #define WRITE_RECOV_6   (5 << 9)
 100
 101 #define BURST_LEN_4     0x00000002
 102
 103 /* EMR */
 104 #define ODT_0_OHM       0x00000000
 105 #define ODT_50_OHM      0x00000044
 106 #define ODT_75_OHM      0x00000004
 107 #define ODT_150_OHM     0x00000040
 108
 109 #define ODS_FULL        0x00000000
 110 #define ODS_REDUCED     0x00000002
 111
 112 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 113 #define ODT_EB0R        (0x80000000 >> 8)
 114 #define ODT_EB0W        (0x80000000 >> 7)
 115 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 116 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 117 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 118
 119 /* Defines for the Read Cycle Delay test */
 120 #define NUMMEMTESTS     8
 121 #define NUMMEMWORDS     8
 122 #define NUMLOOPS        64              /* memory test loops */
 123
 124 /*
 125  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
 126  * region. Right now the cache should still be disabled in U-Boot because of the
 127  * EMAC driver, that need it's buffer descriptor to be located in non cached
 128  * memory.
 129  *
 130  * If at some time this restriction doesn't apply anymore, just define
 131  * CONFIG_4xx_DCACHE in the board config file and this code should setup
 132  * everything correctly.
 133  */
 134 #ifdef CONFIG_4xx_DCACHE
 135 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
 136 #else
 137 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 138 #endif
 139
 140 /*
 141  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
 142  * To support such configurations, we "only" map the first 2GB via the TLB's. We
 143  * need some free virtual address space for the remaining peripherals like, SoC
 144  * devices, FLASH etc.
 145  *
 146  * Note that ECC is currently not supported on configurations with more than 2GB
 147  * SDRAM. This is because we only map the first 2GB on such systems, and therefore
 148  * the ECC parity byte of the remaining area can't be written.
 149  */
 150 #ifndef CONFIG_MAX_MEM_MAPPED
 151 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)2 << 30)
 152 #endif
 153
 154 /*
 155  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 156  */
 157 void __spd_ddr_init_hang (void)
 158 {
 159         hang ();
 160 }
 161 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 162
 163 /*
 164  * To provide an interface for board specific config values in this common
 165  * DDR setup code, we implement he "weak" default functions here. They return
 166  * the default value back to the caller.
 167  *
 168  * Please see include/configs/yucca.h for an example fora board specific
 169  * implementation.
 170  */
 171 u32 __ddr_wrdtr(u32 default_val)
 172 {
 173         return default_val;
 174 }
 175 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 176
 177 u32 __ddr_clktr(u32 default_val)
 178 {
 179         return default_val;
 180 }
 181 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 182
 183
 184 /* Private Structure Definitions */
 185
 186 /* enum only to ease code for cas latency setting */
 187 typedef enum ddr_cas_id {
 188         DDR_CAS_2      = 20,
 189         DDR_CAS_2_5    = 25,
 190         DDR_CAS_3      = 30,
 191         DDR_CAS_4      = 40,
 192         DDR_CAS_5      = 50
 193 } ddr_cas_id_t;
 194
 195 /*-----------------------------------------------------------------------------+
 196  * Prototypes
 197  *-----------------------------------------------------------------------------*/
 198 static phys_size_t sdram_memsize(void);
 199 static void get_spd_info(unsigned long *dimm_populated,
 200                          unsigned char *iic0_dimm_addr,
 201                          unsigned long num_dimm_banks);
 202 static void check_mem_type(unsigned long *dimm_populated,
 203                            unsigned char *iic0_dimm_addr,
 204                            unsigned long num_dimm_banks);
 205 static void check_frequency(unsigned long *dimm_populated,
 206                             unsigned char *iic0_dimm_addr,
 207                             unsigned long num_dimm_banks);
 208 static void check_rank_number(unsigned long *dimm_populated,
 209                               unsigned char *iic0_dimm_addr,
 210                               unsigned long num_dimm_banks);
 211 static void check_voltage_type(unsigned long *dimm_populated,
 212                                unsigned char *iic0_dimm_addr,
 213                                unsigned long num_dimm_banks);
 214 static void program_memory_queue(unsigned long *dimm_populated,
 215                                  unsigned char *iic0_dimm_addr,
 216                                  unsigned long num_dimm_banks);
 217 static void program_codt(unsigned long *dimm_populated,
 218                          unsigned char *iic0_dimm_addr,
 219                          unsigned long num_dimm_banks);
 220 static void program_mode(unsigned long *dimm_populated,
 221                          unsigned char *iic0_dimm_addr,
 222                          unsigned long num_dimm_banks,
 223                          ddr_cas_id_t *selected_cas,
 224                          int *write_recovery);
 225 static void program_tr(unsigned long *dimm_populated,
 226                        unsigned char *iic0_dimm_addr,
 227                        unsigned long num_dimm_banks);
 228 static void program_rtr(unsigned long *dimm_populated,
 229                         unsigned char *iic0_dimm_addr,
 230                         unsigned long num_dimm_banks);
 231 static void program_bxcf(unsigned long *dimm_populated,
 232                          unsigned char *iic0_dimm_addr,
 233                          unsigned long num_dimm_banks);
 234 static void program_copt1(unsigned long *dimm_populated,
 235                           unsigned char *iic0_dimm_addr,
 236                           unsigned long num_dimm_banks);
 237 static void program_initplr(unsigned long *dimm_populated,
 238                             unsigned char *iic0_dimm_addr,
 239                             unsigned long num_dimm_banks,
 240                             ddr_cas_id_t selected_cas,
 241                             int write_recovery);
 242 static unsigned long is_ecc_enabled(void);
 243 #ifdef CONFIG_DDR_ECC
 244 static void program_ecc(unsigned long *dimm_populated,
 245                         unsigned char *iic0_dimm_addr,
 246                         unsigned long num_dimm_banks,
 247                         unsigned long tlb_word2_i_value);
 248 static void program_ecc_addr(unsigned long start_address,
 249                              unsigned long num_bytes,
 250                              unsigned long tlb_word2_i_value);
 251 #endif
 252 static void program_DQS_calibration(unsigned long *dimm_populated,
 253                                     unsigned char *iic0_dimm_addr,
 254                                     unsigned long num_dimm_banks);
 255 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 256 static void     test(void);
 257 #else
 258 static void     DQS_calibration_process(void);
 259 #endif
 260 static void ppc440sp_sdram_register_dump(void);
 261 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 262 void dcbz_area(u32 start_address, u32 num_bytes);
 263
 264 static u32 mfdcr_any(u32 dcr)
 265 {
 266         u32 val;
 267
 268         switch (dcr) {
 269         case SDRAM_R0BAS + 0:
 270                 val = mfdcr(SDRAM_R0BAS + 0);
 271                 break;
 272         case SDRAM_R0BAS + 1:
 273                 val = mfdcr(SDRAM_R0BAS + 1);
 274                 break;
 275         case SDRAM_R0BAS + 2:
 276                 val = mfdcr(SDRAM_R0BAS + 2);
 277                 break;
 278         case SDRAM_R0BAS + 3:
 279                 val = mfdcr(SDRAM_R0BAS + 3);
 280                 break;
 281         default:
 282                 printf("DCR %d not defined in case statement!!!\n", dcr);
 283                 val = 0; /* just to satisfy the compiler */
 284         }
 285
 286         return val;
 287 }
 288
 289 static void mtdcr_any(u32 dcr, u32 val)
 290 {
 291         switch (dcr) {
 292         case SDRAM_R0BAS + 0:
 293                 mtdcr(SDRAM_R0BAS + 0, val);
 294                 break;
 295         case SDRAM_R0BAS + 1:
 296                 mtdcr(SDRAM_R0BAS + 1, val);
 297                 break;
 298         case SDRAM_R0BAS + 2:
 299                 mtdcr(SDRAM_R0BAS + 2, val);
 300                 break;
 301         case SDRAM_R0BAS + 3:
 302                 mtdcr(SDRAM_R0BAS + 3, val);
 303                 break;
 304         default:
 305                 printf("DCR %d not defined in case statement!!!\n", dcr);
 306         }
 307 }
 308
 309 static unsigned char spd_read(uchar chip, uint addr)
 310 {
 311         unsigned char data[2];
 312
 313         if (i2c_probe(chip) == 0)
 314                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 315                         return data[0];
 316
 317         return 0;
 318 }
 319
 320 /*-----------------------------------------------------------------------------+
 321  * sdram_memsize
 322  *-----------------------------------------------------------------------------*/
 323 static phys_size_t sdram_memsize(void)
 324 {
 325         phys_size_t mem_size;
 326         unsigned long mcopt2;
 327         unsigned long mcstat;
 328         unsigned long mb0cf;
 329         unsigned long sdsz;
 330         unsigned long i;
 331
 332         mem_size = 0;
 333
 334         mfsdram(SDRAM_MCOPT2, mcopt2);
 335         mfsdram(SDRAM_MCSTAT, mcstat);
 336
 337         /* DDR controller must be enabled and not in self-refresh. */
 338         /* Otherwise memsize is zero. */
 339         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 340             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 341             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 342                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 343                 for (i = 0; i < MAXBXCF; i++) {
 344                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 345                         /* Banks enabled */
 346                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 347                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 348
 349                                 switch(sdsz) {
 350                                 case SDRAM_RXBAS_SDSZ_8:
 351                                         mem_size+=8;
 352                                         break;
 353                                 case SDRAM_RXBAS_SDSZ_16:
 354                                         mem_size+=16;
 355                                         break;
 356                                 case SDRAM_RXBAS_SDSZ_32:
 357                                         mem_size+=32;
 358                                         break;
 359                                 case SDRAM_RXBAS_SDSZ_64:
 360                                         mem_size+=64;
 361                                         break;
 362                                 case SDRAM_RXBAS_SDSZ_128:
 363                                         mem_size+=128;
 364                                         break;
 365                                 case SDRAM_RXBAS_SDSZ_256:
 366                                         mem_size+=256;
 367                                         break;
 368                                 case SDRAM_RXBAS_SDSZ_512:
 369                                         mem_size+=512;
 370                                         break;
 371                                 case SDRAM_RXBAS_SDSZ_1024:
 372                                         mem_size+=1024;
 373                                         break;
 374                                 case SDRAM_RXBAS_SDSZ_2048:
 375                                         mem_size+=2048;
 376                                         break;
 377                                 case SDRAM_RXBAS_SDSZ_4096:
 378                                         mem_size+=4096;
 379                                         break;
 380                                 default:
 381                                         printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
 382                                                , sdsz);
 383                                         mem_size=0;
 384                                         break;
 385                                 }
 386                         }
 387                 }
 388         }
 389
 390         return mem_size << 20;
 391 }
 392
 393 /*-----------------------------------------------------------------------------+
 394  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 395  * Note: This routine runs from flash with a stack set up in the chip's
 396  * sram space.  It is important that the routine does not require .sbss, .bss or
 397  * .data sections.  It also cannot call routines that require these sections.
 398  *-----------------------------------------------------------------------------*/
 399 /*-----------------------------------------------------------------------------
 400  * Function:     initdram
 401  * Description:  Configures SDRAM memory banks for DDR operation.
 402  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 403  *               via the IIC bus and then configures the DDR SDRAM memory
 404  *               banks appropriately. If Auto Memory Configuration is
 405  *               not used, it is assumed that no DIMM is plugged
 406  *-----------------------------------------------------------------------------*/
 407 phys_size_t initdram(int board_type)
 408 {
 409         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 410         unsigned char spd0[MAX_SPD_BYTES];
 411         unsigned char spd1[MAX_SPD_BYTES];
 412         unsigned char *dimm_spd[MAXDIMMS];
 413         unsigned long dimm_populated[MAXDIMMS];
 414         unsigned long num_dimm_banks;           /* on board dimm banks */
 415         unsigned long val;
 416         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 417         int write_recovery;
 418         phys_size_t dram_size = 0;
 419
 420         num_dimm_banks = sizeof(iic0_dimm_addr);
 421
 422         /*------------------------------------------------------------------
 423          * Set up an array of SPD matrixes.
 424          *-----------------------------------------------------------------*/
 425         dimm_spd[0] = spd0;
 426         dimm_spd[1] = spd1;
 427
 428         /*------------------------------------------------------------------
 429          * Reset the DDR-SDRAM controller.
 430          *-----------------------------------------------------------------*/
 431         mtsdr(SDR0_SRST, (0x80000000 >> 10));
 432         mtsdr(SDR0_SRST, 0x00000000);
 433
 434         /*
 435          * Make sure I2C controller is initialized
 436          * before continuing.
 437          */
 438
 439         /* switch to correct I2C bus */
 440         I2C_SET_BUS(CFG_SPD_BUS_NUM);
 441         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 442
 443         /*------------------------------------------------------------------
 444          * Clear out the serial presence detect buffers.
 445          * Perform IIC reads from the dimm.  Fill in the spds.
 446          * Check to see if the dimm slots are populated
 447          *-----------------------------------------------------------------*/
 448         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 449
 450         /*------------------------------------------------------------------
 451          * Check the memory type for the dimms plugged.
 452          *-----------------------------------------------------------------*/
 453         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 454
 455         /*------------------------------------------------------------------
 456          * Check the frequency supported for the dimms plugged.
 457          *-----------------------------------------------------------------*/
 458         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 459
 460         /*------------------------------------------------------------------
 461          * Check the total rank number.
 462          *-----------------------------------------------------------------*/
 463         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 464
 465         /*------------------------------------------------------------------
 466          * Check the voltage type for the dimms plugged.
 467          *-----------------------------------------------------------------*/
 468         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 469
 470         /*------------------------------------------------------------------
 471          * Program SDRAM controller options 2 register
 472          * Except Enabling of the memory controller.
 473          *-----------------------------------------------------------------*/
 474         mfsdram(SDRAM_MCOPT2, val);
 475         mtsdram(SDRAM_MCOPT2,
 476                 (val &
 477                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 478                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 479                    SDRAM_MCOPT2_ISIE_MASK))
 480                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 481                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 482                    SDRAM_MCOPT2_ISIE_ENABLE));
 483
 484         /*------------------------------------------------------------------
 485          * Program SDRAM controller options 1 register
 486          * Note: Does not enable the memory controller.
 487          *-----------------------------------------------------------------*/
 488         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 489
 490         /*------------------------------------------------------------------
 491          * Set the SDRAM Controller On Die Termination Register
 492          *-----------------------------------------------------------------*/
 493         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 494
 495         /*------------------------------------------------------------------
 496          * Program SDRAM refresh register.
 497          *-----------------------------------------------------------------*/
 498         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 499
 500         /*------------------------------------------------------------------
 501          * Program SDRAM mode register.
 502          *-----------------------------------------------------------------*/
 503         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 504                      &selected_cas, &write_recovery);
 505
 506         /*------------------------------------------------------------------
 507          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 508          *-----------------------------------------------------------------*/
 509         mfsdram(SDRAM_WRDTR, val);
 510         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 511                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 512
 513         /*------------------------------------------------------------------
 514          * Set the SDRAM Clock Timing Register
 515          *-----------------------------------------------------------------*/
 516         mfsdram(SDRAM_CLKTR, val);
 517         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 518                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 519
 520         /*------------------------------------------------------------------
 521          * Program the BxCF registers.
 522          *-----------------------------------------------------------------*/
 523         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 524
 525         /*------------------------------------------------------------------
 526          * Program SDRAM timing registers.
 527          *-----------------------------------------------------------------*/
 528         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 529
 530         /*------------------------------------------------------------------
 531          * Set the Extended Mode register
 532          *-----------------------------------------------------------------*/
 533         mfsdram(SDRAM_MEMODE, val);
 534         mtsdram(SDRAM_MEMODE,
 535                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 536                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 537                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 538                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 539
 540         /*------------------------------------------------------------------
 541          * Program Initialization preload registers.
 542          *-----------------------------------------------------------------*/
 543         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 544                         selected_cas, write_recovery);
 545
 546         /*------------------------------------------------------------------
 547          * Delay to ensure 200usec have elapsed since reset.
 548          *-----------------------------------------------------------------*/
 549         udelay(400);
 550
 551         /*------------------------------------------------------------------
 552          * Set the memory queue core base addr.
 553          *-----------------------------------------------------------------*/
 554         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 555
 556         /*------------------------------------------------------------------
 557          * Program SDRAM controller options 2 register
 558          * Enable the memory controller.
 559          *-----------------------------------------------------------------*/
 560         mfsdram(SDRAM_MCOPT2, val);
 561         mtsdram(SDRAM_MCOPT2,
 562                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 563                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 564                 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
 565
 566         /*------------------------------------------------------------------
 567          * Wait for SDRAM_CFG0_DC_EN to complete.
 568          *-----------------------------------------------------------------*/
 569         do {
 570                 mfsdram(SDRAM_MCSTAT, val);
 571         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 572
 573         /* get installed memory size */
 574         dram_size = sdram_memsize();
 575
 576         /*
 577          * Limit size to 2GB
 578          */
 579         if (dram_size > CONFIG_MAX_MEM_MAPPED)
 580                 dram_size = CONFIG_MAX_MEM_MAPPED;
 581
 582         /* and program tlb entries for this size (dynamic) */
 583
 584         /*
 585          * Program TLB entries with caches enabled, for best performace
 586          * while auto-calibrating and ECC generation
 587          */
 588         program_tlb(0, 0, dram_size, 0);
 589
 590         /*------------------------------------------------------------------
 591          * DQS calibration.
 592          *-----------------------------------------------------------------*/
 593         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 594
 595 #ifdef CONFIG_DDR_ECC
 596         /*------------------------------------------------------------------
 597          * If ecc is enabled, initialize the parity bits.
 598          *-----------------------------------------------------------------*/
 599         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 600 #endif
 601
 602         /*
 603          * Now after initialization (auto-calibration and ECC generation)
 604          * remove the TLB entries with caches enabled and program again with
 605          * desired cache functionality
 606          */
 607         remove_tlb(0, dram_size);
 608         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 609
 610         ppc440sp_sdram_register_dump();
 611
 612         /*
 613          * Clear potential errors resulting from auto-calibration.
 614          * If not done, then we could get an interrupt later on when
 615          * exceptions are enabled.
 616          */
 617         set_mcsr(get_mcsr());
 618
 619         return sdram_memsize();
 620 }
 621
 622 static void get_spd_info(unsigned long *dimm_populated,
 623                          unsigned char *iic0_dimm_addr,
 624                          unsigned long num_dimm_banks)
 625 {
 626         unsigned long dimm_num;
 627         unsigned long dimm_found;
 628         unsigned char num_of_bytes;
 629         unsigned char total_size;
 630
 631         dimm_found = FALSE;
 632         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 633                 num_of_bytes = 0;
 634                 total_size = 0;
 635
 636                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 637                 debug("\nspd_read(0x%x) returned %d\n",
 638                       iic0_dimm_addr[dimm_num], num_of_bytes);
 639                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 640                 debug("spd_read(0x%x) returned %d\n",
 641                       iic0_dimm_addr[dimm_num], total_size);
 642
 643                 if ((num_of_bytes != 0) && (total_size != 0)) {
 644                         dimm_populated[dimm_num] = TRUE;
 645                         dimm_found = TRUE;
 646                         debug("DIMM slot %lu: populated\n", dimm_num);
 647                 } else {
 648                         dimm_populated[dimm_num] = FALSE;
 649                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 650                 }
 651         }
 652
 653         if (dimm_found == FALSE) {
 654                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 655                 spd_ddr_init_hang ();
 656         }
 657 }
 658
 659 void board_add_ram_info(int use_default)
 660 {
 661         PPC4xx_SYS_INFO board_cfg;
 662         u32 val;
 663
 664         if (is_ecc_enabled())
 665                 puts(" (ECC");
 666         else
 667                 puts(" (ECC not");
 668
 669         get_sys_info(&board_cfg);
 670
 671         mfsdr(SDR0_DDR0, val);
 672         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 673         printf(" enabled, %d MHz", (val * 2) / 1000000);
 674
 675         mfsdram(SDRAM_MMODE, val);
 676         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 677         printf(", CL%d)", val);
 678 }
 679
 680 /*------------------------------------------------------------------
 681  * For the memory DIMMs installed, this routine verifies that they
 682  * really are DDR specific DIMMs.
 683  *-----------------------------------------------------------------*/
 684 static void check_mem_type(unsigned long *dimm_populated,
 685                            unsigned char *iic0_dimm_addr,
 686                            unsigned long num_dimm_banks)
 687 {
 688         unsigned long dimm_num;
 689         unsigned long dimm_type;
 690
 691         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 692                 if (dimm_populated[dimm_num] == TRUE) {
 693                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 694                         switch (dimm_type) {
 695                         case 1:
 696                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 697                                        "slot %d.\n", (unsigned int)dimm_num);
 698                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 699                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 700                                 spd_ddr_init_hang ();
 701                                 break;
 702                         case 2:
 703                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 704                                        (unsigned int)dimm_num);
 705                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 706                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 707                                 spd_ddr_init_hang ();
 708                                 break;
 709                         case 3:
 710                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 711                                        (unsigned int)dimm_num);
 712                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 713                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 714                                 spd_ddr_init_hang ();
 715                                 break;
 716                         case 4:
 717                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 718                                        (unsigned int)dimm_num);
 719                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 720                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 721                                 spd_ddr_init_hang ();
 722                                 break;
 723                         case 5:
 724                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 725                                        (unsigned int)dimm_num);
 726                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 727                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 728                                 spd_ddr_init_hang ();
 729                                 break;
 730                         case 6:
 731                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 732                                        (unsigned int)dimm_num);
 733                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 734                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 735                                 spd_ddr_init_hang ();
 736                                 break;
 737                         case 7:
 738                                 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
 739                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 740                                 break;
 741                         case 8:
 742                                 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
 743                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 744                                 break;
 745                         default:
 746                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 747                                        (unsigned int)dimm_num);
 748                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 749                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 750                                 spd_ddr_init_hang ();
 751                                 break;
 752                         }
 753                 }
 754         }
 755         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 756                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 757                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 758                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 759                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 760                         spd_ddr_init_hang ();
 761                 }
 762         }
 763 }
 764
 765 /*------------------------------------------------------------------
 766  * For the memory DIMMs installed, this routine verifies that
 767  * frequency previously calculated is supported.
 768  *-----------------------------------------------------------------*/
 769 static void check_frequency(unsigned long *dimm_populated,
 770                             unsigned char *iic0_dimm_addr,
 771                             unsigned long num_dimm_banks)
 772 {
 773         unsigned long dimm_num;
 774         unsigned long tcyc_reg;
 775         unsigned long cycle_time;
 776         unsigned long calc_cycle_time;
 777         unsigned long sdram_freq;
 778         unsigned long sdr_ddrpll;
 779         PPC4xx_SYS_INFO board_cfg;
 780
 781         /*------------------------------------------------------------------
 782          * Get the board configuration info.
 783          *-----------------------------------------------------------------*/
 784         get_sys_info(&board_cfg);
 785
 786         mfsdr(SDR0_DDR0, sdr_ddrpll);
 787         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 788
 789         /*
 790          * calc_cycle_time is calculated from DDR frequency set by board/chip
 791          * and is expressed in multiple of 10 picoseconds
 792          * to match the way DIMM cycle time is calculated below.
 793          */
 794         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 795
 796         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 797                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 798                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 799                         /*
 800                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 801                          * the higher order nibble (bits 4-7) designates the cycle time
 802                          * to a granularity of 1ns;
 803                          * the value presented by the lower order nibble (bits 0-3)
 804                          * has a granularity of .1ns and is added to the value designated
 805                          * by the higher nibble. In addition, four lines of the lower order
 806                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 807                          */
 808                          /* Convert from hex to decimal */
 809                         if ((tcyc_reg & 0x0F) == 0x0D)
 810                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 811                         else if ((tcyc_reg & 0x0F) == 0x0C)
 812                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 813                         else if ((tcyc_reg & 0x0F) == 0x0B)
 814                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 815                         else if ((tcyc_reg & 0x0F) == 0x0A)
 816                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 817                         else
 818                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 819                                         ((tcyc_reg & 0x0F)*10);
 820                         debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
 821
 822                         if  (cycle_time > (calc_cycle_time + 10)) {
 823                                 /*
 824                                  * the provided sdram cycle_time is too small
 825                                  * for the available DIMM cycle_time.
 826                                  * The additionnal 100ps is here to accept a small incertainty.
 827                                  */
 828                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 829                                        "slot %d \n while calculated cycle time is %d ps.\n",
 830                                        (unsigned int)(cycle_time*10),
 831                                        (unsigned int)dimm_num,
 832                                        (unsigned int)(calc_cycle_time*10));
 833                                 printf("Replace the DIMM, or change DDR frequency via "
 834                                        "strapping bits.\n\n");
 835                                 spd_ddr_init_hang ();
 836                         }
 837                 }
 838         }
 839 }
 840
 841 /*------------------------------------------------------------------
 842  * For the memory DIMMs installed, this routine verifies two
 843  * ranks/banks maximum are availables.
 844  *-----------------------------------------------------------------*/
 845 static void check_rank_number(unsigned long *dimm_populated,
 846                               unsigned char *iic0_dimm_addr,
 847                               unsigned long num_dimm_banks)
 848 {
 849         unsigned long dimm_num;
 850         unsigned long dimm_rank;
 851         unsigned long total_rank = 0;
 852
 853         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 854                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 855                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 856                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 857                                 dimm_rank = (dimm_rank & 0x0F) +1;
 858                         else
 859                                 dimm_rank = dimm_rank & 0x0F;
 860
 861
 862                         if (dimm_rank > MAXRANKS) {
 863                                 printf("ERROR: DRAM DIMM detected with %lu ranks in "
 864                                        "slot %lu is not supported.\n", dimm_rank, dimm_num);
 865                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 866                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 867                                 spd_ddr_init_hang ();
 868                         } else
 869                                 total_rank += dimm_rank;
 870                 }
 871                 if (total_rank > MAXRANKS) {
 872                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 873                                "for all slots.\n", (unsigned int)total_rank);
 874                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 875                         printf("Remove one of the DIMM modules.\n\n");
 876                         spd_ddr_init_hang ();
 877                 }
 878         }
 879 }
 880
 881 /*------------------------------------------------------------------
 882  * only support 2.5V modules.
 883  * This routine verifies this.
 884  *-----------------------------------------------------------------*/
 885 static void check_voltage_type(unsigned long *dimm_populated,
 886                                unsigned char *iic0_dimm_addr,
 887                                unsigned long num_dimm_banks)
 888 {
 889         unsigned long dimm_num;
 890         unsigned long voltage_type;
 891
 892         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 893                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 894                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 895                         switch (voltage_type) {
 896                         case 0x00:
 897                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 898                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 899                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 900                                        (unsigned int)dimm_num);
 901                                 spd_ddr_init_hang ();
 902                                 break;
 903                         case 0x01:
 904                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 905                                 printf("This DIMM is LVTTL.\n");
 906                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 907                                        (unsigned int)dimm_num);
 908                                 spd_ddr_init_hang ();
 909                                 break;
 910                         case 0x02:
 911                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 912                                 printf("This DIMM is 1.5 Volt.\n");
 913                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 914                                        (unsigned int)dimm_num);
 915                                 spd_ddr_init_hang ();
 916                                 break;
 917                         case 0x03:
 918                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 919                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 920                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 921                                        (unsigned int)dimm_num);
 922                                 spd_ddr_init_hang ();
 923                                 break;
 924                         case 0x04:
 925                                 /* 2.5 Voltage only for DDR1 */
 926                                 break;
 927                         case 0x05:
 928                                 /* 1.8 Voltage only for DDR2 */
 929                                 break;
 930                         default:
 931                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 932                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 933                                        (unsigned int)dimm_num);
 934                                 spd_ddr_init_hang ();
 935                                 break;
 936                         }
 937                 }
 938         }
 939 }
 940
 941 /*-----------------------------------------------------------------------------+
 942  * program_copt1.
 943  *-----------------------------------------------------------------------------*/
 944 static void program_copt1(unsigned long *dimm_populated,
 945                           unsigned char *iic0_dimm_addr,
 946                           unsigned long num_dimm_banks)
 947 {
 948         unsigned long dimm_num;
 949         unsigned long mcopt1;
 950         unsigned long ecc_enabled;
 951         unsigned long ecc = 0;
 952         unsigned long data_width = 0;
 953         unsigned long dimm_32bit;
 954         unsigned long dimm_64bit;
 955         unsigned long registered = 0;
 956         unsigned long attribute = 0;
 957         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 958         unsigned long bankcount;
 959         unsigned long ddrtype;
 960         unsigned long val;
 961
 962 #ifdef CONFIG_DDR_ECC
 963         ecc_enabled = TRUE;
 964 #else
 965         ecc_enabled = FALSE;
 966 #endif
 967         dimm_32bit = FALSE;
 968         dimm_64bit = FALSE;
 969         buf0 = FALSE;
 970         buf1 = FALSE;
 971
 972         /*------------------------------------------------------------------
 973          * Set memory controller options reg 1, SDRAM_MCOPT1.
 974          *-----------------------------------------------------------------*/
 975         mfsdram(SDRAM_MCOPT1, val);
 976         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 977                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 978                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 979                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 980                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
 981                          SDRAM_MCOPT1_DREF_MASK);
 982
 983         mcopt1 |= SDRAM_MCOPT1_QDEP;
 984         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
 985         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
 986         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
 987         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
 988         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
 989
 990         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 991                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 992                         /* test ecc support */
 993                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 994                         if (ecc != 0x02) /* ecc not supported */
 995                                 ecc_enabled = FALSE;
 996
 997                         /* test bank count */
 998                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
 999                         if (bankcount == 0x04) /* bank count = 4 */
1000                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1001                         else /* bank count = 8 */
1002                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1003
1004                         /* test DDR type */
1005                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
1006                         /* test for buffered/unbuffered, registered, differential clocks */
1007                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1008                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1009
1010                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1011                         if (dimm_num == 0) {
1012                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1013                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1014                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1015                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1016                                 if (registered == 1) { /* DDR2 always buffered */
1017                                         /* TODO: what about above  comments ? */
1018                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1019                                         buf0 = TRUE;
1020                                 } else {
1021                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1022                                         if ((attribute & 0x02) == 0x00) {
1023                                                 /* buffered not supported */
1024                                                 buf0 = FALSE;
1025                                         } else {
1026                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1027                                                 buf0 = TRUE;
1028                                         }
1029                                 }
1030                         }
1031                         else if (dimm_num == 1) {
1032                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1033                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1034                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1035                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1036                                 if (registered == 1) {
1037                                         /* DDR2 always buffered */
1038                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1039                                         buf1 = TRUE;
1040                                 } else {
1041                                         if ((attribute & 0x02) == 0x00) {
1042                                                 /* buffered not supported */
1043                                                 buf1 = FALSE;
1044                                         } else {
1045                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1046                                                 buf1 = TRUE;
1047                                         }
1048                                 }
1049                         }
1050
1051                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1052                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1053                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1054
1055                         switch (data_width) {
1056                         case 72:
1057                         case 64:
1058                                 dimm_64bit = TRUE;
1059                                 break;
1060                         case 40:
1061                         case 32:
1062                                 dimm_32bit = TRUE;
1063                                 break;
1064                         default:
1065                                 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1066                                        data_width);
1067                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1068                                 break;
1069                         }
1070                 }
1071         }
1072
1073         /* verify matching properties */
1074         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1075                 if (buf0 != buf1) {
1076                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1077                         spd_ddr_init_hang ();
1078                 }
1079         }
1080
1081         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1082                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1083                 spd_ddr_init_hang ();
1084         }
1085         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1086                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1087         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1088                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1089         } else {
1090                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1091                 spd_ddr_init_hang ();
1092         }
1093
1094         if (ecc_enabled == TRUE)
1095                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1096         else
1097                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1098
1099         mtsdram(SDRAM_MCOPT1, mcopt1);
1100 }
1101
1102 /*-----------------------------------------------------------------------------+
1103  * program_codt.
1104  *-----------------------------------------------------------------------------*/
1105 static void program_codt(unsigned long *dimm_populated,
1106                          unsigned char *iic0_dimm_addr,
1107                          unsigned long num_dimm_banks)
1108 {
1109         unsigned long codt;
1110         unsigned long modt0 = 0;
1111         unsigned long modt1 = 0;
1112         unsigned long modt2 = 0;
1113         unsigned long modt3 = 0;
1114         unsigned char dimm_num;
1115         unsigned char dimm_rank;
1116         unsigned char total_rank = 0;
1117         unsigned char total_dimm = 0;
1118         unsigned char dimm_type = 0;
1119         unsigned char firstSlot = 0;
1120
1121         /*------------------------------------------------------------------
1122          * Set the SDRAM Controller On Die Termination Register
1123          *-----------------------------------------------------------------*/
1124         mfsdram(SDRAM_CODT, codt);
1125         codt |= (SDRAM_CODT_IO_NMODE
1126                  & (~SDRAM_CODT_DQS_SINGLE_END
1127                     & ~SDRAM_CODT_CKSE_SINGLE_END
1128                     & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1129                     & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1130
1131         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1132                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1133                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1134                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1135                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1136                                 dimm_type = SDRAM_DDR2;
1137                         } else {
1138                                 dimm_rank = dimm_rank & 0x0F;
1139                                 dimm_type = SDRAM_DDR1;
1140                         }
1141
1142                         total_rank += dimm_rank;
1143                         total_dimm++;
1144                         if ((dimm_num == 0) && (total_dimm == 1))
1145                                 firstSlot = TRUE;
1146                         else
1147                                 firstSlot = FALSE;
1148                 }
1149         }
1150         if (dimm_type == SDRAM_DDR2) {
1151                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1152                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1153                         if (total_rank == 1) {  /* PUUU */
1154                                 codt |= CALC_ODT_R(0);
1155                                 modt0 = CALC_ODT_W(0);
1156                                 modt1 = 0x00000000;
1157                                 modt2 = 0x00000000;
1158                                 modt3 = 0x00000000;
1159                         }
1160                         if (total_rank == 2) {  /* PPUU */
1161                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1162                                 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1163                                 modt1 = 0x00000000;
1164                                 modt2 = 0x00000000;
1165                                 modt3 = 0x00000000;
1166                         }
1167                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1168                         if (total_rank == 1) {  /* UUPU */
1169                                 codt |= CALC_ODT_R(2);
1170                                 modt0 = 0x00000000;
1171                                 modt1 = 0x00000000;
1172                                 modt2 = CALC_ODT_W(2);
1173                                 modt3 = 0x00000000;
1174                         }
1175                         if (total_rank == 2) {  /* UUPP */
1176                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1177                                 modt0 = 0x00000000;
1178                                 modt1 = 0x00000000;
1179                                 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1180                                 modt3 = 0x00000000;
1181                         }
1182                 }
1183                 if (total_dimm == 2) {
1184                         if (total_rank == 2) {  /* PUPU */
1185                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1186                                 modt0 = CALC_ODT_RW(2);
1187                                 modt1 = 0x00000000;
1188                                 modt2 = CALC_ODT_RW(0);
1189                                 modt3 = 0x00000000;
1190                         }
1191                         if (total_rank == 4) {  /* PPPP */
1192                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1193                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1194                                 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1195                                 modt1 = 0x00000000;
1196                                 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1197                                 modt3 = 0x00000000;
1198                         }
1199                 }
1200         } else {
1201                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1202                 modt0 = 0x00000000;
1203                 modt1 = 0x00000000;
1204                 modt2 = 0x00000000;
1205                 modt3 = 0x00000000;
1206
1207                 if (total_dimm == 1) {
1208                         if (total_rank == 1)
1209                                 codt |= 0x00800000;
1210                         if (total_rank == 2)
1211                                 codt |= 0x02800000;
1212                 }
1213                 if (total_dimm == 2) {
1214                         if (total_rank == 2)
1215                                 codt |= 0x08800000;
1216                         if (total_rank == 4)
1217                                 codt |= 0x2a800000;
1218                 }
1219         }
1220
1221         debug("nb of dimm %d\n", total_dimm);
1222         debug("nb of rank %d\n", total_rank);
1223         if (total_dimm == 1)
1224                 debug("dimm in slot %d\n", firstSlot);
1225
1226         mtsdram(SDRAM_CODT, codt);
1227         mtsdram(SDRAM_MODT0, modt0);
1228         mtsdram(SDRAM_MODT1, modt1);
1229         mtsdram(SDRAM_MODT2, modt2);
1230         mtsdram(SDRAM_MODT3, modt3);
1231 }
1232
1233 /*-----------------------------------------------------------------------------+
1234  * program_initplr.
1235  *-----------------------------------------------------------------------------*/
1236 static void program_initplr(unsigned long *dimm_populated,
1237                             unsigned char *iic0_dimm_addr,
1238                             unsigned long num_dimm_banks,
1239                             ddr_cas_id_t selected_cas,
1240                             int write_recovery)
1241 {
1242         u32 cas = 0;
1243         u32 odt = 0;
1244         u32 ods = 0;
1245         u32 mr;
1246         u32 wr;
1247         u32 emr;
1248         u32 emr2;
1249         u32 emr3;
1250         int dimm_num;
1251         int total_dimm = 0;
1252
1253         /******************************************************
1254          ** Assumption: if more than one DIMM, all DIMMs are the same
1255          **             as already checked in check_memory_type
1256          ******************************************************/
1257
1258         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1259                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1260                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1261                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1262                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1263                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1264                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1265                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1266                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1267         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1268                 switch (selected_cas) {
1269                 case DDR_CAS_3:
1270                         cas = 3 << 4;
1271                         break;
1272                 case DDR_CAS_4:
1273                         cas = 4 << 4;
1274                         break;
1275                 case DDR_CAS_5:
1276                         cas = 5 << 4;
1277                         break;
1278                 default:
1279                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1280                         spd_ddr_init_hang ();
1281                         break;
1282                 }
1283
1284 #if 0
1285                 /*
1286                  * ToDo - Still a problem with the write recovery:
1287                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1288                  * in the INITPLR reg to the value calculated in program_mode()
1289                  * results in not correctly working DDR2 memory (crash after
1290                  * relocation).
1291                  *
1292                  * So for now, set the write recovery to 3. This seems to work
1293                  * on the Corair module too.
1294                  *
1295                  * 2007-03-01, sr
1296                  */
1297                 switch (write_recovery) {
1298                 case 3:
1299                         wr = WRITE_RECOV_3;
1300                         break;
1301                 case 4:
1302                         wr = WRITE_RECOV_4;
1303                         break;
1304                 case 5:
1305                         wr = WRITE_RECOV_5;
1306                         break;
1307                 case 6:
1308                         wr = WRITE_RECOV_6;
1309                         break;
1310                 default:
1311                         printf("ERROR: write recovery not support (%d)", write_recovery);
1312                         spd_ddr_init_hang ();
1313                         break;
1314                 }
1315 #else
1316                 wr = WRITE_RECOV_3; /* test-only, see description above */
1317 #endif
1318
1319                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1320                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1321                                 total_dimm++;
1322                 if (total_dimm == 1) {
1323                         odt = ODT_150_OHM;
1324                         ods = ODS_FULL;
1325                 } else if (total_dimm == 2) {
1326                         odt = ODT_75_OHM;
1327                         ods = ODS_REDUCED;
1328                 } else {
1329                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1330                         spd_ddr_init_hang ();
1331                 }
1332
1333                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1334                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1335                 emr2 = CMD_EMR | SELECT_EMR2;
1336                 emr3 = CMD_EMR | SELECT_EMR3;
1337                 mtsdram(SDRAM_INITPLR0,  0xB5000000 | CMD_NOP);         /* NOP */
1338                 udelay(1000);
1339                 mtsdram(SDRAM_INITPLR1,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1340                 mtsdram(SDRAM_INITPLR2,  0x80800000 | emr2);            /* EMR2 */
1341                 mtsdram(SDRAM_INITPLR3,  0x80800000 | emr3);            /* EMR3 */
1342                 mtsdram(SDRAM_INITPLR4,  0x80800000 | emr);             /* EMR DLL ENABLE */
1343                 mtsdram(SDRAM_INITPLR5,  0x80800000 | mr | DLL_RESET);  /* MR w/ DLL reset */
1344                 udelay(1000);
1345                 mtsdram(SDRAM_INITPLR6,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1346                 mtsdram(SDRAM_INITPLR7,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1347                 mtsdram(SDRAM_INITPLR8,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1348                 mtsdram(SDRAM_INITPLR9,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1349                 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1350                 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr);              /* MR w/o DLL reset */
1351                 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr);             /* EMR OCD Default */
1352                 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr);             /* EMR OCD Exit */
1353         } else {
1354                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1355                 spd_ddr_init_hang ();
1356         }
1357 }
1358
1359 /*------------------------------------------------------------------
1360  * This routine programs the SDRAM_MMODE register.
1361  * the selected_cas is an output parameter, that will be passed
1362  * by caller to call the above program_initplr( )
1363  *-----------------------------------------------------------------*/
1364 static void program_mode(unsigned long *dimm_populated,
1365                          unsigned char *iic0_dimm_addr,
1366                          unsigned long num_dimm_banks,
1367                          ddr_cas_id_t *selected_cas,
1368                          int *write_recovery)
1369 {
1370         unsigned long dimm_num;
1371         unsigned long sdram_ddr1;
1372         unsigned long t_wr_ns;
1373         unsigned long t_wr_clk;
1374         unsigned long cas_bit;
1375         unsigned long cas_index;
1376         unsigned long sdram_freq;
1377         unsigned long ddr_check;
1378         unsigned long mmode;
1379         unsigned long tcyc_reg;
1380         unsigned long cycle_2_0_clk;
1381         unsigned long cycle_2_5_clk;
1382         unsigned long cycle_3_0_clk;
1383         unsigned long cycle_4_0_clk;
1384         unsigned long cycle_5_0_clk;
1385         unsigned long max_2_0_tcyc_ns_x_100;
1386         unsigned long max_2_5_tcyc_ns_x_100;
1387         unsigned long max_3_0_tcyc_ns_x_100;
1388         unsigned long max_4_0_tcyc_ns_x_100;
1389         unsigned long max_5_0_tcyc_ns_x_100;
1390         unsigned long cycle_time_ns_x_100[3];
1391         PPC4xx_SYS_INFO board_cfg;
1392         unsigned char cas_2_0_available;
1393         unsigned char cas_2_5_available;
1394         unsigned char cas_3_0_available;
1395         unsigned char cas_4_0_available;
1396         unsigned char cas_5_0_available;
1397         unsigned long sdr_ddrpll;
1398
1399         /*------------------------------------------------------------------
1400          * Get the board configuration info.
1401          *-----------------------------------------------------------------*/
1402         get_sys_info(&board_cfg);
1403
1404         mfsdr(SDR0_DDR0, sdr_ddrpll);
1405         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1406         debug("sdram_freq=%d\n", sdram_freq);
1407
1408         /*------------------------------------------------------------------
1409          * Handle the timing.  We need to find the worst case timing of all
1410          * the dimm modules installed.
1411          *-----------------------------------------------------------------*/
1412         t_wr_ns = 0;
1413         cas_2_0_available = TRUE;
1414         cas_2_5_available = TRUE;
1415         cas_3_0_available = TRUE;
1416         cas_4_0_available = TRUE;
1417         cas_5_0_available = TRUE;
1418         max_2_0_tcyc_ns_x_100 = 10;
1419         max_2_5_tcyc_ns_x_100 = 10;
1420         max_3_0_tcyc_ns_x_100 = 10;
1421         max_4_0_tcyc_ns_x_100 = 10;
1422         max_5_0_tcyc_ns_x_100 = 10;
1423         sdram_ddr1 = TRUE;
1424
1425         /* loop through all the DIMM slots on the board */
1426         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1427                 /* If a dimm is installed in a particular slot ... */
1428                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1429                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1430                                 sdram_ddr1 = TRUE;
1431                         else
1432                                 sdram_ddr1 = FALSE;
1433
1434                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1435                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1436                         debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1437
1438                         /* For a particular DIMM, grab the three CAS values it supports */
1439                         for (cas_index = 0; cas_index < 3; cas_index++) {
1440                                 switch (cas_index) {
1441                                 case 0:
1442                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1443                                         break;
1444                                 case 1:
1445                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1446                                         break;
1447                                 default:
1448                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1449                                         break;
1450                                 }
1451
1452                                 if ((tcyc_reg & 0x0F) >= 10) {
1453                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1454                                                 /* Convert from hex to decimal */
1455                                                 cycle_time_ns_x_100[cas_index] =
1456                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1457                                         } else {
1458                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1459                                                        "in slot %d\n", (unsigned int)dimm_num);
1460                                                 spd_ddr_init_hang ();
1461                                         }
1462                                 } else {
1463                                         /* Convert from hex to decimal */
1464                                         cycle_time_ns_x_100[cas_index] =
1465                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1466                                                 ((tcyc_reg & 0x0F)*10);
1467                                 }
1468                                 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1469                                       cycle_time_ns_x_100[cas_index]);
1470                         }
1471
1472                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1473                         /* supported for a particular DIMM. */
1474                         cas_index = 0;
1475
1476                         if (sdram_ddr1) {
1477                                 /*
1478                                  * DDR devices use the following bitmask for CAS latency:
1479                                  *  Bit   7    6    5    4    3    2    1    0
1480                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1481                                  */
1482                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1483                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1484                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1485                                                                     cycle_time_ns_x_100[cas_index]);
1486                                         cas_index++;
1487                                 } else {
1488                                         if (cas_index != 0)
1489                                                 cas_index++;
1490                                         cas_4_0_available = FALSE;
1491                                 }
1492
1493                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1494                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1495                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1496                                                                     cycle_time_ns_x_100[cas_index]);
1497                                         cas_index++;
1498                                 } else {
1499                                         if (cas_index != 0)
1500                                                 cas_index++;
1501                                         cas_3_0_available = FALSE;
1502                                 }
1503
1504                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1505                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1506                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1507                                                                     cycle_time_ns_x_100[cas_index]);
1508                                         cas_index++;
1509                                 } else {
1510                                         if (cas_index != 0)
1511                                                 cas_index++;
1512                                         cas_2_5_available = FALSE;
1513                                 }
1514
1515                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1516                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1517                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1518                                                                     cycle_time_ns_x_100[cas_index]);
1519                                         cas_index++;
1520                                 } else {
1521                                         if (cas_index != 0)
1522                                                 cas_index++;
1523                                         cas_2_0_available = FALSE;
1524                                 }
1525                         } else {
1526                                 /*
1527                                  * DDR2 devices use the following bitmask for CAS latency:
1528                                  *  Bit   7    6    5    4    3    2    1    0
1529                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1530                                  */
1531                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1532                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1533                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1534                                                                     cycle_time_ns_x_100[cas_index]);
1535                                         cas_index++;
1536                                 } else {
1537                                         if (cas_index != 0)
1538                                                 cas_index++;
1539                                         cas_5_0_available = FALSE;
1540                                 }
1541
1542                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1543                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1544                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1545                                                                     cycle_time_ns_x_100[cas_index]);
1546                                         cas_index++;
1547                                 } else {
1548                                         if (cas_index != 0)
1549                                                 cas_index++;
1550                                         cas_4_0_available = FALSE;
1551                                 }
1552
1553                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1554                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1555                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1556                                                                     cycle_time_ns_x_100[cas_index]);
1557                                         cas_index++;
1558                                 } else {
1559                                         if (cas_index != 0)
1560                                                 cas_index++;
1561                                         cas_3_0_available = FALSE;
1562                                 }
1563                         }
1564                 }
1565         }
1566
1567         /*------------------------------------------------------------------
1568          * Set the SDRAM mode, SDRAM_MMODE
1569          *-----------------------------------------------------------------*/
1570         mfsdram(SDRAM_MMODE, mmode);
1571         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1572
1573         /* add 10 here because of rounding problems */
1574         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1575         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1576         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1577         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1578         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1579         debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1580         debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1581         debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1582
1583         if (sdram_ddr1 == TRUE) { /* DDR1 */
1584                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1585                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1586                         *selected_cas = DDR_CAS_2;
1587                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1588                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1589                         *selected_cas = DDR_CAS_2_5;
1590                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1591                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1592                         *selected_cas = DDR_CAS_3;
1593                 } else {
1594                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1595                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1596                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1597                         spd_ddr_init_hang ();
1598                 }
1599         } else { /* DDR2 */
1600                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1601                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1602                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1603                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1604                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1605                         *selected_cas = DDR_CAS_3;
1606                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1607                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1608                         *selected_cas = DDR_CAS_4;
1609                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1610                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1611                         *selected_cas = DDR_CAS_5;
1612                 } else {
1613                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1614                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1615                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1616                         printf("cas3=%d cas4=%d cas5=%d\n",
1617                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1618                         printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1619                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1620                         spd_ddr_init_hang ();
1621                 }
1622         }
1623
1624         if (sdram_ddr1 == TRUE)
1625                 mmode |= SDRAM_MMODE_WR_DDR1;
1626         else {
1627
1628                 /* loop through all the DIMM slots on the board */
1629                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1630                         /* If a dimm is installed in a particular slot ... */
1631                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1632                                 t_wr_ns = max(t_wr_ns,
1633                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1634                 }
1635
1636                 /*
1637                  * convert from nanoseconds to ddr clocks
1638                  * round up if necessary
1639                  */
1640                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1641                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1642                 if (sdram_freq != ddr_check)
1643                         t_wr_clk++;
1644
1645                 switch (t_wr_clk) {
1646                 case 0:
1647                 case 1:
1648                 case 2:
1649                 case 3:
1650                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1651                         break;
1652                 case 4:
1653                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1654                         break;
1655                 case 5:
1656                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1657                         break;
1658                 default:
1659                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1660                         break;
1661                 }
1662                 *write_recovery = t_wr_clk;
1663         }
1664
1665         debug("CAS latency = %d\n", *selected_cas);
1666         debug("Write recovery = %d\n", *write_recovery);
1667
1668         mtsdram(SDRAM_MMODE, mmode);
1669 }
1670
1671 /*-----------------------------------------------------------------------------+
1672  * program_rtr.
1673  *-----------------------------------------------------------------------------*/
1674 static void program_rtr(unsigned long *dimm_populated,
1675                         unsigned char *iic0_dimm_addr,
1676                         unsigned long num_dimm_banks)
1677 {
1678         PPC4xx_SYS_INFO board_cfg;
1679         unsigned long max_refresh_rate;
1680         unsigned long dimm_num;
1681         unsigned long refresh_rate_type;
1682         unsigned long refresh_rate;
1683         unsigned long rint;
1684         unsigned long sdram_freq;
1685         unsigned long sdr_ddrpll;
1686         unsigned long val;
1687
1688         /*------------------------------------------------------------------
1689          * Get the board configuration info.
1690          *-----------------------------------------------------------------*/
1691         get_sys_info(&board_cfg);
1692
1693         /*------------------------------------------------------------------
1694          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1695          *-----------------------------------------------------------------*/
1696         mfsdr(SDR0_DDR0, sdr_ddrpll);
1697         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1698
1699         max_refresh_rate = 0;
1700         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1701                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1702
1703                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1704                         refresh_rate_type &= 0x7F;
1705                         switch (refresh_rate_type) {
1706                         case 0:
1707                                 refresh_rate =  15625;
1708                                 break;
1709                         case 1:
1710                                 refresh_rate =   3906;
1711                                 break;
1712                         case 2:
1713                                 refresh_rate =   7812;
1714                                 break;
1715                         case 3:
1716                                 refresh_rate =  31250;
1717                                 break;
1718                         case 4:
1719                                 refresh_rate =  62500;
1720                                 break;
1721                         case 5:
1722                                 refresh_rate = 125000;
1723                                 break;
1724                         default:
1725                                 refresh_rate = 0;
1726                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1727                                        (unsigned int)dimm_num);
1728                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1729                                 spd_ddr_init_hang ();
1730                                 break;
1731                         }
1732
1733                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1734                 }
1735         }
1736
1737         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1738         mfsdram(SDRAM_RTR, val);
1739         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1740                 (SDRAM_RTR_RINT_ENCODE(rint)));
1741 }
1742
1743 /*------------------------------------------------------------------
1744  * This routine programs the SDRAM_TRx registers.
1745  *-----------------------------------------------------------------*/
1746 static void program_tr(unsigned long *dimm_populated,
1747                        unsigned char *iic0_dimm_addr,
1748                        unsigned long num_dimm_banks)
1749 {
1750         unsigned long dimm_num;
1751         unsigned long sdram_ddr1;
1752         unsigned long t_rp_ns;
1753         unsigned long t_rcd_ns;
1754         unsigned long t_rrd_ns;
1755         unsigned long t_ras_ns;
1756         unsigned long t_rc_ns;
1757         unsigned long t_rfc_ns;
1758         unsigned long t_wpc_ns;
1759         unsigned long t_wtr_ns;
1760         unsigned long t_rpc_ns;
1761         unsigned long t_rp_clk;
1762         unsigned long t_rcd_clk;
1763         unsigned long t_rrd_clk;
1764         unsigned long t_ras_clk;
1765         unsigned long t_rc_clk;
1766         unsigned long t_rfc_clk;
1767         unsigned long t_wpc_clk;
1768         unsigned long t_wtr_clk;
1769         unsigned long t_rpc_clk;
1770         unsigned long sdtr1, sdtr2, sdtr3;
1771         unsigned long ddr_check;
1772         unsigned long sdram_freq;
1773         unsigned long sdr_ddrpll;
1774
1775         PPC4xx_SYS_INFO board_cfg;
1776
1777         /*------------------------------------------------------------------
1778          * Get the board configuration info.
1779          *-----------------------------------------------------------------*/
1780         get_sys_info(&board_cfg);
1781
1782         mfsdr(SDR0_DDR0, sdr_ddrpll);
1783         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1784
1785         /*------------------------------------------------------------------
1786          * Handle the timing.  We need to find the worst case timing of all
1787          * the dimm modules installed.
1788          *-----------------------------------------------------------------*/
1789         t_rp_ns = 0;
1790         t_rrd_ns = 0;
1791         t_rcd_ns = 0;
1792         t_ras_ns = 0;
1793         t_rc_ns = 0;
1794         t_rfc_ns = 0;
1795         t_wpc_ns = 0;
1796         t_wtr_ns = 0;
1797         t_rpc_ns = 0;
1798         sdram_ddr1 = TRUE;
1799
1800         /* loop through all the DIMM slots on the board */
1801         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1802                 /* If a dimm is installed in a particular slot ... */
1803                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1804                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1805                                 sdram_ddr1 = TRUE;
1806                         else
1807                                 sdram_ddr1 = FALSE;
1808
1809                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1810                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1811                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1812                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1813                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1814                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1815                 }
1816         }
1817
1818         /*------------------------------------------------------------------
1819          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1820          *-----------------------------------------------------------------*/
1821         mfsdram(SDRAM_SDTR1, sdtr1);
1822         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1823                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1824
1825         /* default values */
1826         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1827         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1828
1829         /* normal operations */
1830         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1831         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1832
1833         mtsdram(SDRAM_SDTR1, sdtr1);
1834
1835         /*------------------------------------------------------------------
1836          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1837          *-----------------------------------------------------------------*/
1838         mfsdram(SDRAM_SDTR2, sdtr2);
1839         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1840                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1841                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1842                    SDRAM_SDTR2_RRD_MASK);
1843
1844         /*
1845          * convert t_rcd from nanoseconds to ddr clocks
1846          * round up if necessary
1847          */
1848         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1849         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1850         if (sdram_freq != ddr_check)
1851                 t_rcd_clk++;
1852
1853         switch (t_rcd_clk) {
1854         case 0:
1855         case 1:
1856                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1857                 break;
1858         case 2:
1859                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1860                 break;
1861         case 3:
1862                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1863                 break;
1864         case 4:
1865                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1866                 break;
1867         default:
1868                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1869                 break;
1870         }
1871
1872         if (sdram_ddr1 == TRUE) { /* DDR1 */
1873                 if (sdram_freq < 200000000) {
1874                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1875                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1876                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1877                 } else {
1878                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1879                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1880                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1881                 }
1882         } else { /* DDR2 */
1883                 /* loop through all the DIMM slots on the board */
1884                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1885                         /* If a dimm is installed in a particular slot ... */
1886                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1887                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1888                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1889                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1890                         }
1891                 }
1892
1893                 /*
1894                  * convert from nanoseconds to ddr clocks
1895                  * round up if necessary
1896                  */
1897                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1898                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1899                 if (sdram_freq != ddr_check)
1900                         t_wpc_clk++;
1901
1902                 switch (t_wpc_clk) {
1903                 case 0:
1904                 case 1:
1905                 case 2:
1906                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1907                         break;
1908                 case 3:
1909                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1910                         break;
1911                 case 4:
1912                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1913                         break;
1914                 case 5:
1915                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1916                         break;
1917                 default:
1918                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1919                         break;
1920                 }
1921
1922                 /*
1923                  * convert from nanoseconds to ddr clocks
1924                  * round up if necessary
1925                  */
1926                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1927                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1928                 if (sdram_freq != ddr_check)
1929                         t_wtr_clk++;
1930
1931                 switch (t_wtr_clk) {
1932                 case 0:
1933                 case 1:
1934                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1935                         break;
1936                 case 2:
1937                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1938                         break;
1939                 case 3:
1940                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1941                         break;
1942                 default:
1943                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1944                         break;
1945                 }
1946
1947                 /*
1948                  * convert from nanoseconds to ddr clocks
1949                  * round up if necessary
1950                  */
1951                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1952                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1953                 if (sdram_freq != ddr_check)
1954                         t_rpc_clk++;
1955
1956                 switch (t_rpc_clk) {
1957                 case 0:
1958                 case 1:
1959                 case 2:
1960                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1961                         break;
1962                 case 3:
1963                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1964                         break;
1965                 default:
1966                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1967                         break;
1968                 }
1969         }
1970
1971         /* default value */
1972         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1973
1974         /*
1975          * convert t_rrd from nanoseconds to ddr clocks
1976          * round up if necessary
1977          */
1978         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1979         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1980         if (sdram_freq != ddr_check)
1981                 t_rrd_clk++;
1982
1983         if (t_rrd_clk == 3)
1984                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1985         else
1986                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1987
1988         /*
1989          * convert t_rp from nanoseconds to ddr clocks
1990          * round up if necessary
1991          */
1992         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1993         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1994         if (sdram_freq != ddr_check)
1995                 t_rp_clk++;
1996
1997         switch (t_rp_clk) {
1998         case 0:
1999         case 1:
2000         case 2:
2001         case 3:
2002                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2003                 break;
2004         case 4:
2005                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2006                 break;
2007         case 5:
2008                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2009                 break;
2010         case 6:
2011                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2012                 break;
2013         default:
2014                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2015                 break;
2016         }
2017
2018         mtsdram(SDRAM_SDTR2, sdtr2);
2019
2020         /*------------------------------------------------------------------
2021          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2022          *-----------------------------------------------------------------*/
2023         mfsdram(SDRAM_SDTR3, sdtr3);
2024         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2025                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2026
2027         /*
2028          * convert t_ras from nanoseconds to ddr clocks
2029          * round up if necessary
2030          */
2031         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2032         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2033         if (sdram_freq != ddr_check)
2034                 t_ras_clk++;
2035
2036         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2037
2038         /*
2039          * convert t_rc from nanoseconds to ddr clocks
2040          * round up if necessary
2041          */
2042         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2043         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2044         if (sdram_freq != ddr_check)
2045                 t_rc_clk++;
2046
2047         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2048
2049         /* default xcs value */
2050         sdtr3 |= SDRAM_SDTR3_XCS;
2051
2052         /*
2053          * convert t_rfc from nanoseconds to ddr clocks
2054          * round up if necessary
2055          */
2056         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2057         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2058         if (sdram_freq != ddr_check)
2059                 t_rfc_clk++;
2060
2061         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2062
2063         mtsdram(SDRAM_SDTR3, sdtr3);
2064 }
2065
2066 /*-----------------------------------------------------------------------------+
2067  * program_bxcf.
2068  *-----------------------------------------------------------------------------*/
2069 static void program_bxcf(unsigned long *dimm_populated,
2070                          unsigned char *iic0_dimm_addr,
2071                          unsigned long num_dimm_banks)
2072 {
2073         unsigned long dimm_num;
2074         unsigned long num_col_addr;
2075         unsigned long num_ranks;
2076         unsigned long num_banks;
2077         unsigned long mode;
2078         unsigned long ind_rank;
2079         unsigned long ind;
2080         unsigned long ind_bank;
2081         unsigned long bank_0_populated;
2082
2083         /*------------------------------------------------------------------
2084          * Set the BxCF regs.  First, wipe out the bank config registers.
2085          *-----------------------------------------------------------------*/
2086         mtsdram(SDRAM_MB0CF, 0x00000000);
2087         mtsdram(SDRAM_MB1CF, 0x00000000);
2088         mtsdram(SDRAM_MB2CF, 0x00000000);
2089         mtsdram(SDRAM_MB3CF, 0x00000000);
2090
2091         mode = SDRAM_BXCF_M_BE_ENABLE;
2092
2093         bank_0_populated = 0;
2094
2095         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2096                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2097                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2098                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2099                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2100                                 num_ranks = (num_ranks & 0x0F) +1;
2101                         else
2102                                 num_ranks = num_ranks & 0x0F;
2103
2104                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2105
2106                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2107                                 if (num_banks == 4)
2108                                         ind = 0;
2109                                 else
2110                                         ind = 5 << 8;
2111                                 switch (num_col_addr) {
2112                                 case 0x08:
2113                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2114                                         break;
2115                                 case 0x09:
2116                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2117                                         break;
2118                                 case 0x0A:
2119                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2120                                         break;
2121                                 case 0x0B:
2122                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2123                                         break;
2124                                 case 0x0C:
2125                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2126                                         break;
2127                                 default:
2128                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2129                                                (unsigned int)dimm_num);
2130                                         printf("ERROR: Unsupported value for number of "
2131                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2132                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2133                                         spd_ddr_init_hang ();
2134                                 }
2135                         }
2136
2137                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2138                                 bank_0_populated = 1;
2139
2140                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2141                                 mtsdram(SDRAM_MB0CF +
2142                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2143                                         mode);
2144                         }
2145                 }
2146         }
2147 }
2148
2149 /*------------------------------------------------------------------
2150  * program memory queue.
2151  *-----------------------------------------------------------------*/
2152 static void program_memory_queue(unsigned long *dimm_populated,
2153                                  unsigned char *iic0_dimm_addr,
2154                                  unsigned long num_dimm_banks)
2155 {
2156         unsigned long dimm_num;
2157         phys_size_t rank_base_addr;
2158         unsigned long rank_reg;
2159         phys_size_t rank_size_bytes;
2160         unsigned long rank_size_id;
2161         unsigned long num_ranks;
2162         unsigned long baseadd_size;
2163         unsigned long i;
2164         unsigned long bank_0_populated = 0;
2165         phys_size_t total_size = 0;
2166
2167         /*------------------------------------------------------------------
2168          * Reset the rank_base_address.
2169          *-----------------------------------------------------------------*/
2170         rank_reg   = SDRAM_R0BAS;
2171
2172         rank_base_addr = 0x00000000;
2173
2174         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2175                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2176                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2177                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2178                                 num_ranks = (num_ranks & 0x0F) + 1;
2179                         else
2180                                 num_ranks = num_ranks & 0x0F;
2181
2182                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2183
2184                         /*------------------------------------------------------------------
2185                          * Set the sizes
2186                          *-----------------------------------------------------------------*/
2187                         baseadd_size = 0;
2188                         switch (rank_size_id) {
2189                         case 0x01:
2190                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2191                                 total_size = 1024;
2192                                 break;
2193                         case 0x02:
2194                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2195                                 total_size = 2048;
2196                                 break;
2197                         case 0x04:
2198                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2199                                 total_size = 4096;
2200                                 break;
2201                         case 0x08:
2202                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2203                                 total_size = 32;
2204                                 break;
2205                         case 0x10:
2206                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2207                                 total_size = 64;
2208                                 break;
2209                         case 0x20:
2210                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2211                                 total_size = 128;
2212                                 break;
2213                         case 0x40:
2214                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2215                                 total_size = 256;
2216                                 break;
2217                         case 0x80:
2218                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2219                                 total_size = 512;
2220                                 break;
2221                         default:
2222                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2223                                        (unsigned int)dimm_num);
2224                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2225                                        (unsigned int)rank_size_id);
2226                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2227                                 spd_ddr_init_hang ();
2228                         }
2229                         rank_size_bytes = total_size << 20;
2230
2231                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2232                                 bank_0_populated = 1;
2233
2234                         for (i = 0; i < num_ranks; i++) {
2235                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2236                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2237                                            baseadd_size));
2238                                 rank_base_addr += rank_size_bytes;
2239                         }
2240                 }
2241         }
2242
2243 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
2244         /*
2245          * Enable high bandwidth access on 460EX/GT.
2246          * This should/could probably be done on other
2247          * PPC's too, like 440SPe.
2248          * This is currently not used, but with this setup
2249          * it is possible to use it later on in e.g. the Linux
2250          * EMAC driver for performance gain.
2251          */
2252         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2253         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2254 #endif
2255 }
2256
2257 /*-----------------------------------------------------------------------------+
2258  * is_ecc_enabled.
2259  *-----------------------------------------------------------------------------*/
2260 static unsigned long is_ecc_enabled(void)
2261 {
2262         unsigned long dimm_num;
2263         unsigned long ecc;
2264         unsigned long val;
2265
2266         ecc = 0;
2267         /* loop through all the DIMM slots on the board */
2268         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2269                 mfsdram(SDRAM_MCOPT1, val);
2270                 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2271         }
2272
2273         return ecc;
2274 }
2275
2276 static void blank_string(int size)
2277 {
2278         int i;
2279
2280         for (i=0; i<size; i++)
2281                 putc('\b');
2282         for (i=0; i<size; i++)
2283                 putc(' ');
2284         for (i=0; i<size; i++)
2285                 putc('\b');
2286 }
2287
2288 #ifdef CONFIG_DDR_ECC
2289 /*-----------------------------------------------------------------------------+
2290  * program_ecc.
2291  *-----------------------------------------------------------------------------*/
2292 static void program_ecc(unsigned long *dimm_populated,
2293                         unsigned char *iic0_dimm_addr,
2294                         unsigned long num_dimm_banks,
2295                         unsigned long tlb_word2_i_value)
2296 {
2297         unsigned long mcopt1;
2298         unsigned long mcopt2;
2299         unsigned long mcstat;
2300         unsigned long dimm_num;
2301         unsigned long ecc;
2302
2303         ecc = 0;
2304         /* loop through all the DIMM slots on the board */
2305         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2306                 /* If a dimm is installed in a particular slot ... */
2307                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2308                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2309         }
2310         if (ecc == 0)
2311                 return;
2312
2313         if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
2314                 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
2315                 return;
2316         }
2317
2318         mfsdram(SDRAM_MCOPT1, mcopt1);
2319         mfsdram(SDRAM_MCOPT2, mcopt2);
2320
2321         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2322                 /* DDR controller must be enabled and not in self-refresh. */
2323                 mfsdram(SDRAM_MCSTAT, mcstat);
2324                 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2325                     && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2326                     && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2327                         == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2328
2329                         program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2330                 }
2331         }
2332
2333         return;
2334 }
2335
2336 static void wait_ddr_idle(void)
2337 {
2338         u32 val;
2339
2340         do {
2341                 mfsdram(SDRAM_MCSTAT, val);
2342         } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2343 }
2344
2345 /*-----------------------------------------------------------------------------+
2346  * program_ecc_addr.
2347  *-----------------------------------------------------------------------------*/
2348 static void program_ecc_addr(unsigned long start_address,
2349                              unsigned long num_bytes,
2350                              unsigned long tlb_word2_i_value)
2351 {
2352         unsigned long current_address;
2353         unsigned long end_address;
2354         unsigned long address_increment;
2355         unsigned long mcopt1;
2356         char str[] = "ECC generation -";
2357         char slash[] = "\\|/-\\|/-";
2358         int loop = 0;
2359         int loopi = 0;
2360
2361         current_address = start_address;
2362         mfsdram(SDRAM_MCOPT1, mcopt1);
2363         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2364                 mtsdram(SDRAM_MCOPT1,
2365                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2366                 sync();
2367                 eieio();
2368                 wait_ddr_idle();
2369
2370                 puts(str);
2371                 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2372                         /* ECC bit set method for non-cached memory */
2373                         if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2374                                 address_increment = 4;
2375                         else
2376                                 address_increment = 8;
2377                         end_address = current_address + num_bytes;
2378
2379                         while (current_address < end_address) {
2380                                 *((unsigned long *)current_address) = 0x00000000;
2381                                 current_address += address_increment;
2382
2383                                 if ((loop++ % (2 << 20)) == 0) {
2384                                         putc('\b');
2385                                         putc(slash[loopi++ % 8]);
2386                                 }
2387                         }
2388
2389                 } else {
2390                         /* ECC bit set method for cached memory */
2391                         dcbz_area(start_address, num_bytes);
2392                         /* Write modified dcache lines back to memory */
2393                         clean_dcache_range(start_address, start_address + num_bytes);
2394                 }
2395
2396                 blank_string(strlen(str));
2397
2398                 sync();
2399                 eieio();
2400                 wait_ddr_idle();
2401
2402                 /* clear ECC error repoting registers */
2403                 mtsdram(SDRAM_ECCCR, 0xffffffff);
2404                 mtdcr(0x4c, 0xffffffff);
2405
2406                 mtsdram(SDRAM_MCOPT1,
2407                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2408                 sync();
2409                 eieio();
2410                 wait_ddr_idle();
2411         }
2412 }
2413 #endif
2414
2415 /*-----------------------------------------------------------------------------+
2416  * program_DQS_calibration.
2417  *-----------------------------------------------------------------------------*/
2418 static void program_DQS_calibration(unsigned long *dimm_populated,
2419                                     unsigned char *iic0_dimm_addr,
2420                                     unsigned long num_dimm_banks)
2421 {
2422         unsigned long val;
2423
2424 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2425         mtsdram(SDRAM_RQDC, 0x80000037);
2426         mtsdram(SDRAM_RDCC, 0x40000000);
2427         mtsdram(SDRAM_RFDC, 0x000001DF);
2428
2429         test();
2430 #else
2431         /*------------------------------------------------------------------
2432          * Program RDCC register
2433          * Read sample cycle auto-update enable
2434          *-----------------------------------------------------------------*/
2435
2436         mfsdram(SDRAM_RDCC, val);
2437         mtsdram(SDRAM_RDCC,
2438                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2439                 | SDRAM_RDCC_RSAE_ENABLE);
2440
2441         /*------------------------------------------------------------------
2442          * Program RQDC register
2443          * Internal DQS delay mechanism enable
2444          *-----------------------------------------------------------------*/
2445         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2446
2447         /*------------------------------------------------------------------
2448          * Program RFDC register
2449          * Set Feedback Fractional Oversample
2450          * Auto-detect read sample cycle enable
2451          *-----------------------------------------------------------------*/
2452         mfsdram(SDRAM_RFDC, val);
2453         mtsdram(SDRAM_RFDC,
2454                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2455                          SDRAM_RFDC_RFFD_MASK))
2456                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2457                    SDRAM_RFDC_RFFD_ENCODE(0)));
2458
2459         DQS_calibration_process();
2460 #endif
2461 }
2462
2463 static int short_mem_test(void)
2464 {
2465         u32 *membase;
2466         u32 bxcr_num;
2467         u32 bxcf;
2468         int i;
2469         int j;
2470         phys_size_t base_addr;
2471         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2472                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2473                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2474                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2475                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2476                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2477                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2478                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2479                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2480                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2481                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2482                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2483                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2484                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2485                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2486                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2487                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2488         int l;
2489
2490         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2491                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2492
2493                 /* Banks enabled */
2494                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2495                         /* Bank is enabled */
2496
2497                         /*
2498                          * Only run test on accessable memory (below 2GB)
2499                          */
2500                         base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2501                         if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2502                                 continue;
2503
2504                         /*------------------------------------------------------------------
2505                          * Run the short memory test.
2506                          *-----------------------------------------------------------------*/
2507                         membase = (u32 *)(u32)base_addr;
2508
2509                         for (i = 0; i < NUMMEMTESTS; i++) {
2510                                 for (j = 0; j < NUMMEMWORDS; j++) {
2511                                         membase[j] = test[i][j];
2512                                         ppcDcbf((u32)&(membase[j]));
2513                                 }
2514                                 sync();
2515                                 for (l=0; l<NUMLOOPS; l++) {
2516                                         for (j = 0; j < NUMMEMWORDS; j++) {
2517                                                 if (membase[j] != test[i][j]) {
2518                                                         ppcDcbf((u32)&(membase[j]));
2519                                                         return 0;
2520                                                 }
2521                                                 ppcDcbf((u32)&(membase[j]));
2522                                         }
2523                                         sync();
2524                                 }
2525                         }
2526                 }       /* if bank enabled */
2527         }               /* for bxcf_num */
2528
2529         return 1;
2530 }
2531
2532 #ifndef HARD_CODED_DQS
2533 /*-----------------------------------------------------------------------------+
2534  * DQS_calibration_process.
2535  *-----------------------------------------------------------------------------*/
2536 static void DQS_calibration_process(void)
2537 {
2538         unsigned long rfdc_reg;
2539         unsigned long rffd;
2540         unsigned long val;
2541         long rffd_average;
2542         long max_start;
2543         long min_end;
2544         unsigned long begin_rqfd[MAXRANKS];
2545         unsigned long begin_rffd[MAXRANKS];
2546         unsigned long end_rqfd[MAXRANKS];
2547         unsigned long end_rffd[MAXRANKS];
2548         char window_found;
2549         unsigned long dlycal;
2550         unsigned long dly_val;
2551         unsigned long max_pass_length;
2552         unsigned long current_pass_length;
2553         unsigned long current_fail_length;
2554         unsigned long current_start;
2555         long max_end;
2556         unsigned char fail_found;
2557         unsigned char pass_found;
2558 #if !defined(CONFIG_DDR_RQDC_FIXED)
2559         u32 rqdc_reg;
2560         u32 rqfd;
2561         u32 rqfd_start;
2562         u32 rqfd_average;
2563         int loopi = 0;
2564         char str[] = "Auto calibration -";
2565         char slash[] = "\\|/-\\|/-";
2566
2567         /*------------------------------------------------------------------
2568          * Test to determine the best read clock delay tuning bits.
2569          *
2570          * Before the DDR controller can be used, the read clock delay needs to be
2571          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2572          * This value cannot be hardcoded into the program because it changes
2573          * depending on the board's setup and environment.
2574          * To do this, all delay values are tested to see if they
2575          * work or not.  By doing this, you get groups of fails with groups of
2576          * passing values.  The idea is to find the start and end of a passing
2577          * window and take the center of it to use as the read clock delay.
2578          *
2579          * A failure has to be seen first so that when we hit a pass, we know
2580          * that it is truely the start of the window.  If we get passing values
2581          * to start off with, we don't know if we are at the start of the window.
2582          *
2583          * The code assumes that a failure will always be found.
2584          * If a failure is not found, there is no easy way to get the middle
2585          * of the passing window.  I guess we can pretty much pick any value
2586          * but some values will be better than others.  Since the lowest speed
2587          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2588          * from experimentation it is safe to say you will always have a failure.
2589          *-----------------------------------------------------------------*/
2590
2591         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2592         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2593
2594         puts(str);
2595
2596 calibration_loop:
2597         mfsdram(SDRAM_RQDC, rqdc_reg);
2598         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2599                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2600 #else /* CONFIG_DDR_RQDC_FIXED */
2601         /*
2602          * On Katmai the complete auto-calibration somehow doesn't seem to
2603          * produce the best results, meaning optimal values for RQFD/RFFD.
2604          * This was discovered by GDA using a high bandwidth scope,
2605          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2606          * so now on Katmai "only" RFFD is auto-calibrated.
2607          */
2608         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2609 #endif /* CONFIG_DDR_RQDC_FIXED */
2610
2611         max_start = 0;
2612         min_end = 0;
2613         begin_rqfd[0] = 0;
2614         begin_rffd[0] = 0;
2615         begin_rqfd[1] = 0;
2616         begin_rffd[1] = 0;
2617         end_rqfd[0] = 0;
2618         end_rffd[0] = 0;
2619         end_rqfd[1] = 0;
2620         end_rffd[1] = 0;
2621         window_found = FALSE;
2622
2623         max_pass_length = 0;
2624         max_start = 0;
2625         max_end = 0;
2626         current_pass_length = 0;
2627         current_fail_length = 0;
2628         current_start = 0;
2629         window_found = FALSE;
2630         fail_found = FALSE;
2631         pass_found = FALSE;
2632
2633         /*
2634          * get the delay line calibration register value
2635          */
2636         mfsdram(SDRAM_DLCR, dlycal);
2637         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2638
2639         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2640                 mfsdram(SDRAM_RFDC, rfdc_reg);
2641                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2642
2643                 /*------------------------------------------------------------------
2644                  * Set the timing reg for the test.
2645                  *-----------------------------------------------------------------*/
2646                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2647
2648                 /*------------------------------------------------------------------
2649                  * See if the rffd value passed.
2650                  *-----------------------------------------------------------------*/
2651                 if (short_mem_test()) {
2652                         if (fail_found == TRUE) {
2653                                 pass_found = TRUE;
2654                                 if (current_pass_length == 0)
2655                                         current_start = rffd;
2656
2657                                 current_fail_length = 0;
2658                                 current_pass_length++;
2659
2660                                 if (current_pass_length > max_pass_length) {
2661                                         max_pass_length = current_pass_length;
2662                                         max_start = current_start;
2663                                         max_end = rffd;
2664                                 }
2665                         }
2666                 } else {
2667                         current_pass_length = 0;
2668                         current_fail_length++;
2669
2670                         if (current_fail_length >= (dly_val >> 2)) {
2671                                 if (fail_found == FALSE) {
2672                                         fail_found = TRUE;
2673                                 } else if (pass_found == TRUE) {
2674                                         window_found = TRUE;
2675                                         break;
2676                                 }
2677                         }
2678                 }
2679         }               /* for rffd */
2680
2681         /*------------------------------------------------------------------
2682          * Set the average RFFD value
2683          *-----------------------------------------------------------------*/
2684         rffd_average = ((max_start + max_end) >> 1);
2685
2686         if (rffd_average < 0)
2687                 rffd_average = 0;
2688
2689         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2690                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2691         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2692         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2693
2694 #if !defined(CONFIG_DDR_RQDC_FIXED)
2695         max_pass_length = 0;
2696         max_start = 0;
2697         max_end = 0;
2698         current_pass_length = 0;
2699         current_fail_length = 0;
2700         current_start = 0;
2701         window_found = FALSE;
2702         fail_found = FALSE;
2703         pass_found = FALSE;
2704
2705         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2706                 mfsdram(SDRAM_RQDC, rqdc_reg);
2707                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2708
2709                 /*------------------------------------------------------------------
2710                  * Set the timing reg for the test.
2711                  *-----------------------------------------------------------------*/
2712                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2713
2714                 /*------------------------------------------------------------------
2715                  * See if the rffd value passed.
2716                  *-----------------------------------------------------------------*/
2717                 if (short_mem_test()) {
2718                         if (fail_found == TRUE) {
2719                                 pass_found = TRUE;
2720                                 if (current_pass_length == 0)
2721                                         current_start = rqfd;
2722
2723                                 current_fail_length = 0;
2724                                 current_pass_length++;
2725
2726                                 if (current_pass_length > max_pass_length) {
2727                                         max_pass_length = current_pass_length;
2728                                         max_start = current_start;
2729                                         max_end = rqfd;
2730                                 }
2731                         }
2732                 } else {
2733                         current_pass_length = 0;
2734                         current_fail_length++;
2735
2736                         if (fail_found == FALSE) {
2737                                 fail_found = TRUE;
2738                         } else if (pass_found == TRUE) {
2739                                 window_found = TRUE;
2740                                 break;
2741                         }
2742                 }
2743         }
2744
2745         rqfd_average = ((max_start + max_end) >> 1);
2746
2747         /*------------------------------------------------------------------
2748          * Make sure we found the valid read passing window.  Halt if not
2749          *-----------------------------------------------------------------*/
2750         if (window_found == FALSE) {
2751                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2752                         putc('\b');
2753                         putc(slash[loopi++ % 8]);
2754
2755                         /* try again from with a different RQFD start value */
2756                         rqfd_start++;
2757                         goto calibration_loop;
2758                 }
2759
2760                 printf("\nERROR: Cannot determine a common read delay for the "
2761                        "DIMM(s) installed.\n");
2762                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2763                 ppc440sp_sdram_register_dump();
2764                 spd_ddr_init_hang ();
2765         }
2766
2767         if (rqfd_average < 0)
2768                 rqfd_average = 0;
2769
2770         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2771                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2772
2773         mtsdram(SDRAM_RQDC,
2774                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2775                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2776
2777         blank_string(strlen(str));
2778 #endif /* CONFIG_DDR_RQDC_FIXED */
2779
2780         /*
2781          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2782          * PowerPC440SP/SPe DDR2 application note:
2783          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2784          */
2785         mfsdram(SDRAM_RTSR, val);
2786         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2787                 mfsdram(SDRAM_RDCC, val);
2788                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2789                         val += 0x40000000;
2790                         mtsdram(SDRAM_RDCC, val);
2791                 }
2792         }
2793
2794         mfsdram(SDRAM_DLCR, val);
2795         debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2796         mfsdram(SDRAM_RQDC, val);
2797         debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2798         mfsdram(SDRAM_RFDC, val);
2799         debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2800         mfsdram(SDRAM_RDCC, val);
2801         debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2802 }
2803 #else /* calibration test with hardvalues */
2804 /*-----------------------------------------------------------------------------+
2805  * DQS_calibration_process.
2806  *-----------------------------------------------------------------------------*/
2807 static void test(void)
2808 {
2809         unsigned long dimm_num;
2810         unsigned long ecc_temp;
2811         unsigned long i, j;
2812         unsigned long *membase;
2813         unsigned long bxcf[MAXRANKS];
2814         unsigned long val;
2815         char window_found;
2816         char begin_found[MAXDIMMS];
2817         char end_found[MAXDIMMS];
2818         char search_end[MAXDIMMS];
2819         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2820                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2821                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2822                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2823                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2824                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2825                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2826                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2827                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2828                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2829                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2830                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2831                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2832                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2833                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2834                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2835                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2836
2837         /*------------------------------------------------------------------
2838          * Test to determine the best read clock delay tuning bits.
2839          *
2840          * Before the DDR controller can be used, the read clock delay needs to be
2841          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2842          * This value cannot be hardcoded into the program because it changes
2843          * depending on the board's setup and environment.
2844          * To do this, all delay values are tested to see if they
2845          * work or not.  By doing this, you get groups of fails with groups of
2846          * passing values.  The idea is to find the start and end of a passing
2847          * window and take the center of it to use as the read clock delay.
2848          *
2849          * A failure has to be seen first so that when we hit a pass, we know
2850          * that it is truely the start of the window.  If we get passing values
2851          * to start off with, we don't know if we are at the start of the window.
2852          *
2853          * The code assumes that a failure will always be found.
2854          * If a failure is not found, there is no easy way to get the middle
2855          * of the passing window.  I guess we can pretty much pick any value
2856          * but some values will be better than others.  Since the lowest speed
2857          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2858          * from experimentation it is safe to say you will always have a failure.
2859          *-----------------------------------------------------------------*/
2860         mfsdram(SDRAM_MCOPT1, ecc_temp);
2861         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2862         mfsdram(SDRAM_MCOPT1, val);
2863         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2864                 SDRAM_MCOPT1_MCHK_NON);
2865
2866         window_found = FALSE;
2867         begin_found[0] = FALSE;
2868         end_found[0] = FALSE;
2869         search_end[0] = FALSE;
2870         begin_found[1] = FALSE;
2871         end_found[1] = FALSE;
2872         search_end[1] = FALSE;
2873
2874         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2875                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2876
2877                 /* Banks enabled */
2878                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2879
2880                         /* Bank is enabled */
2881                         membase =
2882                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2883
2884                         /*------------------------------------------------------------------
2885                          * Run the short memory test.
2886                          *-----------------------------------------------------------------*/
2887                         for (i = 0; i < NUMMEMTESTS; i++) {
2888                                 for (j = 0; j < NUMMEMWORDS; j++) {
2889                                         membase[j] = test[i][j];
2890                                         ppcDcbf((u32)&(membase[j]));
2891                                 }
2892                                 sync();
2893                                 for (j = 0; j < NUMMEMWORDS; j++) {
2894                                         if (membase[j] != test[i][j]) {
2895                                                 ppcDcbf((u32)&(membase[j]));
2896                                                 break;
2897                                         }
2898                                         ppcDcbf((u32)&(membase[j]));
2899                                 }
2900                                 sync();
2901                                 if (j < NUMMEMWORDS)
2902                                         break;
2903                         }
2904
2905                         /*------------------------------------------------------------------
2906                          * See if the rffd value passed.
2907                          *-----------------------------------------------------------------*/
2908                         if (i < NUMMEMTESTS) {
2909                                 if ((end_found[dimm_num] == FALSE) &&
2910                                     (search_end[dimm_num] == TRUE)) {
2911                                         end_found[dimm_num] = TRUE;
2912                                 }
2913                                 if ((end_found[0] == TRUE) &&
2914                                     (end_found[1] == TRUE))
2915                                         break;
2916                         } else {
2917                                 if (begin_found[dimm_num] == FALSE) {
2918                                         begin_found[dimm_num] = TRUE;
2919                                         search_end[dimm_num] = TRUE;
2920                                 }
2921                         }
2922                 } else {
2923                         begin_found[dimm_num] = TRUE;
2924                         end_found[dimm_num] = TRUE;
2925                 }
2926         }
2927
2928         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2929                 window_found = TRUE;
2930
2931         /*------------------------------------------------------------------
2932          * Make sure we found the valid read passing window.  Halt if not
2933          *-----------------------------------------------------------------*/
2934         if (window_found == FALSE) {
2935                 printf("ERROR: Cannot determine a common read delay for the "
2936                        "DIMM(s) installed.\n");
2937                 spd_ddr_init_hang ();
2938         }
2939
2940         /*------------------------------------------------------------------
2941          * Restore the ECC variable to what it originally was
2942          *-----------------------------------------------------------------*/
2943         mtsdram(SDRAM_MCOPT1,
2944                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2945                 | ecc_temp);
2946 }
2947 #endif
2948
2949 #if defined(DEBUG)
2950 static void ppc440sp_sdram_register_dump(void)
2951 {
2952         unsigned int sdram_reg;
2953         unsigned int sdram_data;
2954         unsigned int dcr_data;
2955
2956         printf("\n  Register Dump:\n");
2957         sdram_reg = SDRAM_MCSTAT;
2958         mfsdram(sdram_reg, sdram_data);
2959         printf("        SDRAM_MCSTAT    = 0x%08X", sdram_data);
2960         sdram_reg = SDRAM_MCOPT1;
2961         mfsdram(sdram_reg, sdram_data);
2962         printf("        SDRAM_MCOPT1    = 0x%08X\n", sdram_data);
2963         sdram_reg = SDRAM_MCOPT2;
2964         mfsdram(sdram_reg, sdram_data);
2965         printf("        SDRAM_MCOPT2    = 0x%08X", sdram_data);
2966         sdram_reg = SDRAM_MODT0;
2967         mfsdram(sdram_reg, sdram_data);
2968         printf("        SDRAM_MODT0     = 0x%08X\n", sdram_data);
2969         sdram_reg = SDRAM_MODT1;
2970         mfsdram(sdram_reg, sdram_data);
2971         printf("        SDRAM_MODT1     = 0x%08X", sdram_data);
2972         sdram_reg = SDRAM_MODT2;
2973         mfsdram(sdram_reg, sdram_data);
2974         printf("        SDRAM_MODT2     = 0x%08X\n", sdram_data);
2975         sdram_reg = SDRAM_MODT3;
2976         mfsdram(sdram_reg, sdram_data);
2977         printf("        SDRAM_MODT3     = 0x%08X", sdram_data);
2978         sdram_reg = SDRAM_CODT;
2979         mfsdram(sdram_reg, sdram_data);
2980         printf("        SDRAM_CODT      = 0x%08X\n", sdram_data);
2981         sdram_reg = SDRAM_VVPR;
2982         mfsdram(sdram_reg, sdram_data);
2983         printf("        SDRAM_VVPR      = 0x%08X", sdram_data);
2984         sdram_reg = SDRAM_OPARS;
2985         mfsdram(sdram_reg, sdram_data);
2986         printf("        SDRAM_OPARS     = 0x%08X\n", sdram_data);
2987         /*
2988          * OPAR2 is only used as a trigger register.
2989          * No data is contained in this register, and reading or writing
2990          * to is can cause bad things to happen (hangs).  Just skip it
2991          * and report NA
2992          * sdram_reg = SDRAM_OPAR2;
2993          * mfsdram(sdram_reg, sdram_data);
2994          * printf("        SDRAM_OPAR2     = 0x%08X\n", sdram_data);
2995          */
2996         printf("        SDRAM_OPART     = N/A       ");
2997         sdram_reg = SDRAM_RTR;
2998         mfsdram(sdram_reg, sdram_data);
2999         printf("        SDRAM_RTR       = 0x%08X\n", sdram_data);
3000         sdram_reg = SDRAM_MB0CF;
3001         mfsdram(sdram_reg, sdram_data);
3002         printf("        SDRAM_MB0CF     = 0x%08X", sdram_data);
3003         sdram_reg = SDRAM_MB1CF;
3004         mfsdram(sdram_reg, sdram_data);
3005         printf("        SDRAM_MB1CF     = 0x%08X\n", sdram_data);
3006         sdram_reg = SDRAM_MB2CF;
3007         mfsdram(sdram_reg, sdram_data);
3008         printf("        SDRAM_MB2CF     = 0x%08X", sdram_data);
3009         sdram_reg = SDRAM_MB3CF;
3010         mfsdram(sdram_reg, sdram_data);
3011         printf("        SDRAM_MB3CF     = 0x%08X\n", sdram_data);
3012         sdram_reg = SDRAM_INITPLR0;
3013         mfsdram(sdram_reg, sdram_data);
3014         printf("        SDRAM_INITPLR0  = 0x%08X", sdram_data);
3015         sdram_reg = SDRAM_INITPLR1;
3016         mfsdram(sdram_reg, sdram_data);
3017         printf("        SDRAM_INITPLR1  = 0x%08X\n", sdram_data);
3018         sdram_reg = SDRAM_INITPLR2;
3019         mfsdram(sdram_reg, sdram_data);
3020         printf("        SDRAM_INITPLR2  = 0x%08X", sdram_data);
3021         sdram_reg = SDRAM_INITPLR3;
3022         mfsdram(sdram_reg, sdram_data);
3023         printf("        SDRAM_INITPLR3  = 0x%08X\n", sdram_data);
3024         sdram_reg = SDRAM_INITPLR4;
3025         mfsdram(sdram_reg, sdram_data);
3026         printf("        SDRAM_INITPLR4  = 0x%08X", sdram_data);
3027         sdram_reg = SDRAM_INITPLR5;
3028         mfsdram(sdram_reg, sdram_data);
3029         printf("        SDRAM_INITPLR5  = 0x%08X\n", sdram_data);
3030         sdram_reg = SDRAM_INITPLR6;
3031         mfsdram(sdram_reg, sdram_data);
3032         printf("        SDRAM_INITPLR6  = 0x%08X", sdram_data);
3033         sdram_reg = SDRAM_INITPLR7;
3034         mfsdram(sdram_reg, sdram_data);
3035         printf("        SDRAM_INITPLR7  = 0x%08X\n", sdram_data);
3036         sdram_reg = SDRAM_INITPLR8;
3037         mfsdram(sdram_reg, sdram_data);
3038         printf("        SDRAM_INITPLR8  = 0x%08X", sdram_data);
3039         sdram_reg = SDRAM_INITPLR9;
3040         mfsdram(sdram_reg, sdram_data);
3041         printf("        SDRAM_INITPLR9  = 0x%08X\n", sdram_data);
3042         sdram_reg = SDRAM_INITPLR10;
3043         mfsdram(sdram_reg, sdram_data);
3044         printf("        SDRAM_INITPLR10 = 0x%08X", sdram_data);
3045         sdram_reg = SDRAM_INITPLR11;
3046         mfsdram(sdram_reg, sdram_data);
3047         printf("        SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
3048         sdram_reg = SDRAM_INITPLR12;
3049         mfsdram(sdram_reg, sdram_data);
3050         printf("        SDRAM_INITPLR12 = 0x%08X", sdram_data);
3051         sdram_reg = SDRAM_INITPLR13;
3052         mfsdram(sdram_reg, sdram_data);
3053         printf("        SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
3054         sdram_reg = SDRAM_INITPLR14;
3055         mfsdram(sdram_reg, sdram_data);
3056         printf("        SDRAM_INITPLR14 = 0x%08X", sdram_data);
3057         sdram_reg = SDRAM_INITPLR15;
3058         mfsdram(sdram_reg, sdram_data);
3059         printf("        SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
3060         sdram_reg = SDRAM_RQDC;
3061         mfsdram(sdram_reg, sdram_data);
3062         printf("        SDRAM_RQDC      = 0x%08X", sdram_data);
3063         sdram_reg = SDRAM_RFDC;
3064         mfsdram(sdram_reg, sdram_data);
3065         printf("        SDRAM_RFDC      = 0x%08X\n", sdram_data);
3066         sdram_reg = SDRAM_RDCC;
3067         mfsdram(sdram_reg, sdram_data);
3068         printf("        SDRAM_RDCC      = 0x%08X", sdram_data);
3069         sdram_reg = SDRAM_DLCR;
3070         mfsdram(sdram_reg, sdram_data);
3071         printf("        SDRAM_DLCR      = 0x%08X\n", sdram_data);
3072         sdram_reg = SDRAM_CLKTR;
3073         mfsdram(sdram_reg, sdram_data);
3074         printf("        SDRAM_CLKTR     = 0x%08X", sdram_data);
3075         sdram_reg = SDRAM_WRDTR;
3076         mfsdram(sdram_reg, sdram_data);
3077         printf("        SDRAM_WRDTR     = 0x%08X\n", sdram_data);
3078         sdram_reg = SDRAM_SDTR1;
3079         mfsdram(sdram_reg, sdram_data);
3080         printf("        SDRAM_SDTR1     = 0x%08X", sdram_data);
3081         sdram_reg = SDRAM_SDTR2;
3082         mfsdram(sdram_reg, sdram_data);
3083         printf("        SDRAM_SDTR2     = 0x%08X\n", sdram_data);
3084         sdram_reg = SDRAM_SDTR3;
3085         mfsdram(sdram_reg, sdram_data);
3086         printf("        SDRAM_SDTR3     = 0x%08X", sdram_data);
3087         sdram_reg = SDRAM_MMODE;
3088         mfsdram(sdram_reg, sdram_data);
3089         printf("        SDRAM_MMODE     = 0x%08X\n", sdram_data);
3090         sdram_reg = SDRAM_MEMODE;
3091         mfsdram(sdram_reg, sdram_data);
3092         printf("        SDRAM_MEMODE    = 0x%08X", sdram_data);
3093         sdram_reg = SDRAM_ECCCR;
3094         mfsdram(sdram_reg, sdram_data);
3095         printf("        SDRAM_ECCCR     = 0x%08X\n\n", sdram_data);
3096
3097         dcr_data = mfdcr(SDRAM_R0BAS);
3098         printf("        MQ0_B0BAS       = 0x%08X", dcr_data);
3099         dcr_data = mfdcr(SDRAM_R1BAS);
3100         printf("        MQ1_B0BAS       = 0x%08X\n", dcr_data);
3101         dcr_data = mfdcr(SDRAM_R2BAS);
3102         printf("        MQ2_B0BAS       = 0x%08X", dcr_data);
3103         dcr_data = mfdcr(SDRAM_R3BAS);
3104         printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
3105 }
3106 #else /* !defined(DEBUG) */
3107 static void ppc440sp_sdram_register_dump(void)
3108 {
3109 }
3110 #endif /* defined(DEBUG) */
3111 #elif defined(CONFIG_405EX)
3112 /*-----------------------------------------------------------------------------
3113  * Function:    initdram
3114  * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
3115  *              banks. The configuration is performed using static, compile-
3116  *              time parameters.
3117  *---------------------------------------------------------------------------*/
3118 phys_size_t initdram(int board_type)
3119 {
3120         /*
3121          * Only run this SDRAM init code once. For NAND booting
3122          * targets like Kilauea, we call initdram() early from the
3123          * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
3124          * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
3125          * which calls initdram() again. This time the controller
3126          * mustn't be reconfigured again since we're already running
3127          * from SDRAM.
3128          */
3129 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
3130         unsigned long val;
3131
3132         /* Set Memory Bank Configuration Registers */
3133
3134         mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
3135         mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
3136         mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
3137         mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
3138
3139         /* Set Memory Clock Timing Register */
3140
3141         mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
3142
3143         /* Set Refresh Time Register */
3144
3145         mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
3146
3147         /* Set SDRAM Timing Registers */
3148
3149         mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
3150         mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
3151         mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
3152
3153         /* Set Mode and Extended Mode Registers */
3154
3155         mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
3156         mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
3157
3158         /* Set Memory Controller Options 1 Register */
3159
3160         mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
3161
3162         /* Set Manual Initialization Control Registers */
3163
3164         mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
3165         mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
3166         mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
3167         mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
3168         mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
3169         mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
3170         mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
3171         mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
3172         mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
3173         mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
3174         mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
3175         mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
3176         mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
3177         mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
3178         mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
3179         mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
3180
3181         /* Set On-Die Termination Registers */
3182
3183         mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
3184         mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
3185         mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
3186
3187         /* Set Write Timing Register */
3188
3189         mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
3190
3191         /*
3192          * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3193          * SDRAM0_MCOPT2[IPTR] = 1
3194          */
3195
3196         mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3197                                SDRAM_MCOPT2_IPTR_EXECUTE));
3198
3199         /*
3200          * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3201          * completion of initialization.
3202          */
3203
3204         do {
3205                 mfsdram(SDRAM_MCSTAT, val);
3206         } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3207
3208         /* Set Delay Control Registers */
3209
3210         mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
3211         mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
3212         mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
3213         mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
3214
3215         /*
3216          * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3217          */
3218
3219         mfsdram(SDRAM_MCOPT2, val);
3220         mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3221
3222 #if defined(CONFIG_DDR_ECC)
3223         ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
3224 #endif /* defined(CONFIG_DDR_ECC) */
3225 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3226
3227         return (CFG_MBYTES_SDRAM << 20);
3228 }
3229 #endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */