cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those are 440SP/SPe.
   5  *
   6  * (C) Copyright 2007-2008
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * COPYRIGHT   AMCC   CORPORATION 2004
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  *
  29  */
  30
  31 /* define DEBUG for debugging output (obviously ;-)) */
  32 #if 0
  33 #define DEBUG
  34 #endif
  35
  36 #include <common.h>
  37 #include <command.h>
  38 #include <ppc4xx.h>
  39 #include <i2c.h>
  40 #include <asm/io.h>
  41 #include <asm/processor.h>
  42 #include <asm/mmu.h>
  43 #include <asm/cache.h>
  44
  45 #if defined(CONFIG_SPD_EEPROM) &&                               \
  46         (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  47          defined(CONFIG_460EX) || defined(CONFIG_460GT))
  48
  49 /*-----------------------------------------------------------------------------+
  50  * Defines
  51  *-----------------------------------------------------------------------------*/
  52 #ifndef TRUE
  53 #define TRUE            1
  54 #endif
  55 #ifndef FALSE
  56 #define FALSE           0
  57 #endif
  58
  59 #define SDRAM_DDR1      1
  60 #define SDRAM_DDR2      2
  61 #define SDRAM_NONE      0
  62
  63 #define MAXDIMMS        2
  64 #define MAXRANKS        4
  65 #define MAXBXCF         4
  66 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
  67
  68 #define ONE_BILLION     1000000000
  69
  70 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  71
  72 #define CMD_NOP         (7 << 19)
  73 #define CMD_PRECHARGE   (2 << 19)
  74 #define CMD_REFRESH     (1 << 19)
  75 #define CMD_EMR         (0 << 19)
  76 #define CMD_READ        (5 << 19)
  77 #define CMD_WRITE       (4 << 19)
  78
  79 #define SELECT_MR       (0 << 16)
  80 #define SELECT_EMR      (1 << 16)
  81 #define SELECT_EMR2     (2 << 16)
  82 #define SELECT_EMR3     (3 << 16)
  83
  84 /* MR */
  85 #define DLL_RESET       0x00000100
  86
  87 #define WRITE_RECOV_2   (1 << 9)
  88 #define WRITE_RECOV_3   (2 << 9)
  89 #define WRITE_RECOV_4   (3 << 9)
  90 #define WRITE_RECOV_5   (4 << 9)
  91 #define WRITE_RECOV_6   (5 << 9)
  92
  93 #define BURST_LEN_4     0x00000002
  94
  95 /* EMR */
  96 #define ODT_0_OHM       0x00000000
  97 #define ODT_50_OHM      0x00000044
  98 #define ODT_75_OHM      0x00000004
  99 #define ODT_150_OHM     0x00000040
 100
 101 #define ODS_FULL        0x00000000
 102 #define ODS_REDUCED     0x00000002
 103
 104 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 105 #define ODT_EB0R        (0x80000000 >> 8)
 106 #define ODT_EB0W        (0x80000000 >> 7)
 107 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 108 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 109 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 110
 111 /* Defines for the Read Cycle Delay test */
 112 #define NUMMEMTESTS     8
 113 #define NUMMEMWORDS     8
 114 #define NUMLOOPS        64              /* memory test loops */
 115
 116 /*
 117  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
 118  * region. Right now the cache should still be disabled in U-Boot because of the
 119  * EMAC driver, that need it's buffer descriptor to be located in non cached
 120  * memory.
 121  *
 122  * If at some time this restriction doesn't apply anymore, just define
 123  * CONFIG_4xx_DCACHE in the board config file and this code should setup
 124  * everything correctly.
 125  */
 126 #ifdef CONFIG_4xx_DCACHE
 127 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
 128 #else
 129 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 130 #endif
 131
 132 /*
 133  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 134  */
 135 void __spd_ddr_init_hang (void)
 136 {
 137         hang ();
 138 }
 139 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 140
 141 /*
 142  * To provide an interface for board specific config values in this common
 143  * DDR setup code, we implement he "weak" default functions here. They return
 144  * the default value back to the caller.
 145  *
 146  * Please see include/configs/yucca.h for an example fora board specific
 147  * implementation.
 148  */
 149 u32 __ddr_wrdtr(u32 default_val)
 150 {
 151         return default_val;
 152 }
 153 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 154
 155 u32 __ddr_clktr(u32 default_val)
 156 {
 157         return default_val;
 158 }
 159 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 160
 161
 162 /* Private Structure Definitions */
 163
 164 /* enum only to ease code for cas latency setting */
 165 typedef enum ddr_cas_id {
 166         DDR_CAS_2      = 20,
 167         DDR_CAS_2_5    = 25,
 168         DDR_CAS_3      = 30,
 169         DDR_CAS_4      = 40,
 170         DDR_CAS_5      = 50
 171 } ddr_cas_id_t;
 172
 173 /*-----------------------------------------------------------------------------+
 174  * Prototypes
 175  *-----------------------------------------------------------------------------*/
 176 static unsigned long sdram_memsize(void);
 177 static void get_spd_info(unsigned long *dimm_populated,
 178                          unsigned char *iic0_dimm_addr,
 179                          unsigned long num_dimm_banks);
 180 static void check_mem_type(unsigned long *dimm_populated,
 181                            unsigned char *iic0_dimm_addr,
 182                            unsigned long num_dimm_banks);
 183 static void check_frequency(unsigned long *dimm_populated,
 184                             unsigned char *iic0_dimm_addr,
 185                             unsigned long num_dimm_banks);
 186 static void check_rank_number(unsigned long *dimm_populated,
 187                               unsigned char *iic0_dimm_addr,
 188                               unsigned long num_dimm_banks);
 189 static void check_voltage_type(unsigned long *dimm_populated,
 190                                unsigned char *iic0_dimm_addr,
 191                                unsigned long num_dimm_banks);
 192 static void program_memory_queue(unsigned long *dimm_populated,
 193                                  unsigned char *iic0_dimm_addr,
 194                                  unsigned long num_dimm_banks);
 195 static void program_codt(unsigned long *dimm_populated,
 196                          unsigned char *iic0_dimm_addr,
 197                          unsigned long num_dimm_banks);
 198 static void program_mode(unsigned long *dimm_populated,
 199                          unsigned char *iic0_dimm_addr,
 200                          unsigned long num_dimm_banks,
 201                          ddr_cas_id_t *selected_cas,
 202                          int *write_recovery);
 203 static void program_tr(unsigned long *dimm_populated,
 204                        unsigned char *iic0_dimm_addr,
 205                        unsigned long num_dimm_banks);
 206 static void program_rtr(unsigned long *dimm_populated,
 207                         unsigned char *iic0_dimm_addr,
 208                         unsigned long num_dimm_banks);
 209 static void program_bxcf(unsigned long *dimm_populated,
 210                          unsigned char *iic0_dimm_addr,
 211                          unsigned long num_dimm_banks);
 212 static void program_copt1(unsigned long *dimm_populated,
 213                           unsigned char *iic0_dimm_addr,
 214                           unsigned long num_dimm_banks);
 215 static void program_initplr(unsigned long *dimm_populated,
 216                             unsigned char *iic0_dimm_addr,
 217                             unsigned long num_dimm_banks,
 218                             ddr_cas_id_t selected_cas,
 219                             int write_recovery);
 220 static unsigned long is_ecc_enabled(void);
 221 #ifdef CONFIG_DDR_ECC
 222 static void program_ecc(unsigned long *dimm_populated,
 223                         unsigned char *iic0_dimm_addr,
 224                         unsigned long num_dimm_banks,
 225                         unsigned long tlb_word2_i_value);
 226 static void program_ecc_addr(unsigned long start_address,
 227                              unsigned long num_bytes,
 228                              unsigned long tlb_word2_i_value);
 229 #endif
 230 static void program_DQS_calibration(unsigned long *dimm_populated,
 231                                     unsigned char *iic0_dimm_addr,
 232                                     unsigned long num_dimm_banks);
 233 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 234 static void     test(void);
 235 #else
 236 static void     DQS_calibration_process(void);
 237 #endif
 238 static void ppc440sp_sdram_register_dump(void);
 239 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 240 void dcbz_area(u32 start_address, u32 num_bytes);
 241
 242 static u32 mfdcr_any(u32 dcr)
 243 {
 244         u32 val;
 245
 246         switch (dcr) {
 247         case SDRAM_R0BAS + 0:
 248                 val = mfdcr(SDRAM_R0BAS + 0);
 249                 break;
 250         case SDRAM_R0BAS + 1:
 251                 val = mfdcr(SDRAM_R0BAS + 1);
 252                 break;
 253         case SDRAM_R0BAS + 2:
 254                 val = mfdcr(SDRAM_R0BAS + 2);
 255                 break;
 256         case SDRAM_R0BAS + 3:
 257                 val = mfdcr(SDRAM_R0BAS + 3);
 258                 break;
 259         default:
 260                 printf("DCR %d not defined in case statement!!!\n", dcr);
 261                 val = 0; /* just to satisfy the compiler */
 262         }
 263
 264         return val;
 265 }
 266
 267 static void mtdcr_any(u32 dcr, u32 val)
 268 {
 269         switch (dcr) {
 270         case SDRAM_R0BAS + 0:
 271                 mtdcr(SDRAM_R0BAS + 0, val);
 272                 break;
 273         case SDRAM_R0BAS + 1:
 274                 mtdcr(SDRAM_R0BAS + 1, val);
 275                 break;
 276         case SDRAM_R0BAS + 2:
 277                 mtdcr(SDRAM_R0BAS + 2, val);
 278                 break;
 279         case SDRAM_R0BAS + 3:
 280                 mtdcr(SDRAM_R0BAS + 3, val);
 281                 break;
 282         default:
 283                 printf("DCR %d not defined in case statement!!!\n", dcr);
 284         }
 285 }
 286
 287 static unsigned char spd_read(uchar chip, uint addr)
 288 {
 289         unsigned char data[2];
 290
 291         if (i2c_probe(chip) == 0)
 292                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 293                         return data[0];
 294
 295         return 0;
 296 }
 297
 298 /*-----------------------------------------------------------------------------+
 299  * sdram_memsize
 300  *-----------------------------------------------------------------------------*/
 301 static unsigned long sdram_memsize(void)
 302 {
 303         unsigned long mem_size;
 304         unsigned long mcopt2;
 305         unsigned long mcstat;
 306         unsigned long mb0cf;
 307         unsigned long sdsz;
 308         unsigned long i;
 309
 310         mem_size = 0;
 311
 312         mfsdram(SDRAM_MCOPT2, mcopt2);
 313         mfsdram(SDRAM_MCSTAT, mcstat);
 314
 315         /* DDR controller must be enabled and not in self-refresh. */
 316         /* Otherwise memsize is zero. */
 317         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 318             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 319             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 320                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 321                 for (i = 0; i < MAXBXCF; i++) {
 322                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 323                         /* Banks enabled */
 324                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 325                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 326
 327                                 switch(sdsz) {
 328                                 case SDRAM_RXBAS_SDSZ_8:
 329                                         mem_size+=8;
 330                                         break;
 331                                 case SDRAM_RXBAS_SDSZ_16:
 332                                         mem_size+=16;
 333                                         break;
 334                                 case SDRAM_RXBAS_SDSZ_32:
 335                                         mem_size+=32;
 336                                         break;
 337                                 case SDRAM_RXBAS_SDSZ_64:
 338                                         mem_size+=64;
 339                                         break;
 340                                 case SDRAM_RXBAS_SDSZ_128:
 341                                         mem_size+=128;
 342                                         break;
 343                                 case SDRAM_RXBAS_SDSZ_256:
 344                                         mem_size+=256;
 345                                         break;
 346                                 case SDRAM_RXBAS_SDSZ_512:
 347                                         mem_size+=512;
 348                                         break;
 349                                 case SDRAM_RXBAS_SDSZ_1024:
 350                                         mem_size+=1024;
 351                                         break;
 352                                 case SDRAM_RXBAS_SDSZ_2048:
 353                                         mem_size+=2048;
 354                                         break;
 355                                 case SDRAM_RXBAS_SDSZ_4096:
 356                                         mem_size+=4096;
 357                                         break;
 358                                 default:
 359                                         mem_size=0;
 360                                         break;
 361                                 }
 362                         }
 363                 }
 364         }
 365
 366         mem_size *= 1024 * 1024;
 367         return(mem_size);
 368 }
 369
 370 /*-----------------------------------------------------------------------------+
 371  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 372  * Note: This routine runs from flash with a stack set up in the chip's
 373  * sram space.  It is important that the routine does not require .sbss, .bss or
 374  * .data sections.  It also cannot call routines that require these sections.
 375  *-----------------------------------------------------------------------------*/
 376 /*-----------------------------------------------------------------------------
 377  * Function:     initdram
 378  * Description:  Configures SDRAM memory banks for DDR operation.
 379  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 380  *               via the IIC bus and then configures the DDR SDRAM memory
 381  *               banks appropriately. If Auto Memory Configuration is
 382  *               not used, it is assumed that no DIMM is plugged
 383  *-----------------------------------------------------------------------------*/
 384 long int initdram(int board_type)
 385 {
 386         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 387         unsigned char spd0[MAX_SPD_BYTES];
 388         unsigned char spd1[MAX_SPD_BYTES];
 389         unsigned char *dimm_spd[MAXDIMMS];
 390         unsigned long dimm_populated[MAXDIMMS];
 391         unsigned long num_dimm_banks;           /* on board dimm banks */
 392         unsigned long val;
 393         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 394         int write_recovery;
 395         unsigned long dram_size = 0;
 396
 397         num_dimm_banks = sizeof(iic0_dimm_addr);
 398
 399         /*------------------------------------------------------------------
 400          * Set up an array of SPD matrixes.
 401          *-----------------------------------------------------------------*/
 402         dimm_spd[0] = spd0;
 403         dimm_spd[1] = spd1;
 404
 405         /*------------------------------------------------------------------
 406          * Reset the DDR-SDRAM controller.
 407          *-----------------------------------------------------------------*/
 408         mtsdr(SDR0_SRST, (0x80000000 >> 10));
 409         mtsdr(SDR0_SRST, 0x00000000);
 410
 411         /*
 412          * Make sure I2C controller is initialized
 413          * before continuing.
 414          */
 415
 416         /* switch to correct I2C bus */
 417         I2C_SET_BUS(CFG_SPD_BUS_NUM);
 418         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 419
 420         /*------------------------------------------------------------------
 421          * Clear out the serial presence detect buffers.
 422          * Perform IIC reads from the dimm.  Fill in the spds.
 423          * Check to see if the dimm slots are populated
 424          *-----------------------------------------------------------------*/
 425         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 426
 427         /*------------------------------------------------------------------
 428          * Check the memory type for the dimms plugged.
 429          *-----------------------------------------------------------------*/
 430         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 431
 432         /*------------------------------------------------------------------
 433          * Check the frequency supported for the dimms plugged.
 434          *-----------------------------------------------------------------*/
 435         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 436
 437         /*------------------------------------------------------------------
 438          * Check the total rank number.
 439          *-----------------------------------------------------------------*/
 440         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 441
 442         /*------------------------------------------------------------------
 443          * Check the voltage type for the dimms plugged.
 444          *-----------------------------------------------------------------*/
 445         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 446
 447         /*------------------------------------------------------------------
 448          * Program SDRAM controller options 2 register
 449          * Except Enabling of the memory controller.
 450          *-----------------------------------------------------------------*/
 451         mfsdram(SDRAM_MCOPT2, val);
 452         mtsdram(SDRAM_MCOPT2,
 453                 (val &
 454                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 455                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 456                    SDRAM_MCOPT2_ISIE_MASK))
 457                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 458                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 459                    SDRAM_MCOPT2_ISIE_ENABLE));
 460
 461         /*------------------------------------------------------------------
 462          * Program SDRAM controller options 1 register
 463          * Note: Does not enable the memory controller.
 464          *-----------------------------------------------------------------*/
 465         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 466
 467         /*------------------------------------------------------------------
 468          * Set the SDRAM Controller On Die Termination Register
 469          *-----------------------------------------------------------------*/
 470         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 471
 472         /*------------------------------------------------------------------
 473          * Program SDRAM refresh register.
 474          *-----------------------------------------------------------------*/
 475         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 476
 477         /*------------------------------------------------------------------
 478          * Program SDRAM mode register.
 479          *-----------------------------------------------------------------*/
 480         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 481                      &selected_cas, &write_recovery);
 482
 483         /*------------------------------------------------------------------
 484          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 485          *-----------------------------------------------------------------*/
 486         mfsdram(SDRAM_WRDTR, val);
 487         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 488                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 489
 490         /*------------------------------------------------------------------
 491          * Set the SDRAM Clock Timing Register
 492          *-----------------------------------------------------------------*/
 493         mfsdram(SDRAM_CLKTR, val);
 494         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 495                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 496
 497         /*------------------------------------------------------------------
 498          * Program the BxCF registers.
 499          *-----------------------------------------------------------------*/
 500         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 501
 502         /*------------------------------------------------------------------
 503          * Program SDRAM timing registers.
 504          *-----------------------------------------------------------------*/
 505         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 506
 507         /*------------------------------------------------------------------
 508          * Set the Extended Mode register
 509          *-----------------------------------------------------------------*/
 510         mfsdram(SDRAM_MEMODE, val);
 511         mtsdram(SDRAM_MEMODE,
 512                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 513                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 514                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 515                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 516
 517         /*------------------------------------------------------------------
 518          * Program Initialization preload registers.
 519          *-----------------------------------------------------------------*/
 520         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 521                         selected_cas, write_recovery);
 522
 523         /*------------------------------------------------------------------
 524          * Delay to ensure 200usec have elapsed since reset.
 525          *-----------------------------------------------------------------*/
 526         udelay(400);
 527
 528         /*------------------------------------------------------------------
 529          * Set the memory queue core base addr.
 530          *-----------------------------------------------------------------*/
 531         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 532
 533         /*------------------------------------------------------------------
 534          * Program SDRAM controller options 2 register
 535          * Enable the memory controller.
 536          *-----------------------------------------------------------------*/
 537         mfsdram(SDRAM_MCOPT2, val);
 538         mtsdram(SDRAM_MCOPT2,
 539                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 540                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 541                 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
 542
 543         /*------------------------------------------------------------------
 544          * Wait for SDRAM_CFG0_DC_EN to complete.
 545          *-----------------------------------------------------------------*/
 546         do {
 547                 mfsdram(SDRAM_MCSTAT, val);
 548         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 549
 550         /* get installed memory size */
 551         dram_size = sdram_memsize();
 552
 553         /* and program tlb entries for this size (dynamic) */
 554
 555         /*
 556          * Program TLB entries with caches enabled, for best performace
 557          * while auto-calibrating and ECC generation
 558          */
 559         program_tlb(0, 0, dram_size, 0);
 560
 561         /*------------------------------------------------------------------
 562          * DQS calibration.
 563          *-----------------------------------------------------------------*/
 564         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 565
 566 #ifdef CONFIG_DDR_ECC
 567         /*------------------------------------------------------------------
 568          * If ecc is enabled, initialize the parity bits.
 569          *-----------------------------------------------------------------*/
 570         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 571 #endif
 572
 573         /*
 574          * Now after initialization (auto-calibration and ECC generation)
 575          * remove the TLB entries with caches enabled and program again with
 576          * desired cache functionality
 577          */
 578         remove_tlb(0, dram_size);
 579         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 580
 581         ppc440sp_sdram_register_dump();
 582
 583         /*
 584          * Clear potential errors resulting from auto-calibration.
 585          * If not done, then we could get an interrupt later on when
 586          * exceptions are enabled.
 587          */
 588         set_mcsr(get_mcsr());
 589
 590         return dram_size;
 591 }
 592
 593 static void get_spd_info(unsigned long *dimm_populated,
 594                          unsigned char *iic0_dimm_addr,
 595                          unsigned long num_dimm_banks)
 596 {
 597         unsigned long dimm_num;
 598         unsigned long dimm_found;
 599         unsigned char num_of_bytes;
 600         unsigned char total_size;
 601
 602         dimm_found = FALSE;
 603         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 604                 num_of_bytes = 0;
 605                 total_size = 0;
 606
 607                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 608                 debug("\nspd_read(0x%x) returned %d\n",
 609                       iic0_dimm_addr[dimm_num], num_of_bytes);
 610                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 611                 debug("spd_read(0x%x) returned %d\n",
 612                       iic0_dimm_addr[dimm_num], total_size);
 613
 614                 if ((num_of_bytes != 0) && (total_size != 0)) {
 615                         dimm_populated[dimm_num] = TRUE;
 616                         dimm_found = TRUE;
 617                         debug("DIMM slot %lu: populated\n", dimm_num);
 618                 } else {
 619                         dimm_populated[dimm_num] = FALSE;
 620                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 621                 }
 622         }
 623
 624         if (dimm_found == FALSE) {
 625                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 626                 spd_ddr_init_hang ();
 627         }
 628 }
 629
 630 void board_add_ram_info(int use_default)
 631 {
 632         PPC4xx_SYS_INFO board_cfg;
 633         u32 val;
 634
 635         if (is_ecc_enabled())
 636                 puts(" (ECC");
 637         else
 638                 puts(" (ECC not");
 639
 640         get_sys_info(&board_cfg);
 641
 642         mfsdr(SDR0_DDR0, val);
 643         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 644         printf(" enabled, %d MHz", (val * 2) / 1000000);
 645
 646         mfsdram(SDRAM_MMODE, val);
 647         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 648         printf(", CL%d)", val);
 649 }
 650
 651 /*------------------------------------------------------------------
 652  * For the memory DIMMs installed, this routine verifies that they
 653  * really are DDR specific DIMMs.
 654  *-----------------------------------------------------------------*/
 655 static void check_mem_type(unsigned long *dimm_populated,
 656                            unsigned char *iic0_dimm_addr,
 657                            unsigned long num_dimm_banks)
 658 {
 659         unsigned long dimm_num;
 660         unsigned long dimm_type;
 661
 662         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 663                 if (dimm_populated[dimm_num] == TRUE) {
 664                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 665                         switch (dimm_type) {
 666                         case 1:
 667                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 668                                        "slot %d.\n", (unsigned int)dimm_num);
 669                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 670                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 671                                 spd_ddr_init_hang ();
 672                                 break;
 673                         case 2:
 674                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 675                                        (unsigned int)dimm_num);
 676                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 677                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 678                                 spd_ddr_init_hang ();
 679                                 break;
 680                         case 3:
 681                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 682                                        (unsigned int)dimm_num);
 683                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 684                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 685                                 spd_ddr_init_hang ();
 686                                 break;
 687                         case 4:
 688                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 689                                        (unsigned int)dimm_num);
 690                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 691                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 692                                 spd_ddr_init_hang ();
 693                                 break;
 694                         case 5:
 695                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 696                                        (unsigned int)dimm_num);
 697                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 698                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 699                                 spd_ddr_init_hang ();
 700                                 break;
 701                         case 6:
 702                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 703                                        (unsigned int)dimm_num);
 704                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 705                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 706                                 spd_ddr_init_hang ();
 707                                 break;
 708                         case 7:
 709                                 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
 710                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 711                                 break;
 712                         case 8:
 713                                 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
 714                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 715                                 break;
 716                         default:
 717                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 718                                        (unsigned int)dimm_num);
 719                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 720                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 721                                 spd_ddr_init_hang ();
 722                                 break;
 723                         }
 724                 }
 725         }
 726         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 727                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 728                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 729                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 730                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 731                         spd_ddr_init_hang ();
 732                 }
 733         }
 734 }
 735
 736 /*------------------------------------------------------------------
 737  * For the memory DIMMs installed, this routine verifies that
 738  * frequency previously calculated is supported.
 739  *-----------------------------------------------------------------*/
 740 static void check_frequency(unsigned long *dimm_populated,
 741                             unsigned char *iic0_dimm_addr,
 742                             unsigned long num_dimm_banks)
 743 {
 744         unsigned long dimm_num;
 745         unsigned long tcyc_reg;
 746         unsigned long cycle_time;
 747         unsigned long calc_cycle_time;
 748         unsigned long sdram_freq;
 749         unsigned long sdr_ddrpll;
 750         PPC4xx_SYS_INFO board_cfg;
 751
 752         /*------------------------------------------------------------------
 753          * Get the board configuration info.
 754          *-----------------------------------------------------------------*/
 755         get_sys_info(&board_cfg);
 756
 757         mfsdr(SDR0_DDR0, sdr_ddrpll);
 758         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 759
 760         /*
 761          * calc_cycle_time is calculated from DDR frequency set by board/chip
 762          * and is expressed in multiple of 10 picoseconds
 763          * to match the way DIMM cycle time is calculated below.
 764          */
 765         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 766
 767         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 768                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 769                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 770                         /*
 771                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 772                          * the higher order nibble (bits 4-7) designates the cycle time
 773                          * to a granularity of 1ns;
 774                          * the value presented by the lower order nibble (bits 0-3)
 775                          * has a granularity of .1ns and is added to the value designated
 776                          * by the higher nibble. In addition, four lines of the lower order
 777                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 778                          */
 779                          /* Convert from hex to decimal */
 780                         if ((tcyc_reg & 0x0F) == 0x0D)
 781                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 782                         else if ((tcyc_reg & 0x0F) == 0x0C)
 783                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 784                         else if ((tcyc_reg & 0x0F) == 0x0B)
 785                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 786                         else if ((tcyc_reg & 0x0F) == 0x0A)
 787                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 788                         else
 789                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 790                                         ((tcyc_reg & 0x0F)*10);
 791                         debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
 792
 793                         if  (cycle_time > (calc_cycle_time + 10)) {
 794                                 /*
 795                                  * the provided sdram cycle_time is too small
 796                                  * for the available DIMM cycle_time.
 797                                  * The additionnal 100ps is here to accept a small incertainty.
 798                                  */
 799                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 800                                        "slot %d \n while calculated cycle time is %d ps.\n",
 801                                        (unsigned int)(cycle_time*10),
 802                                        (unsigned int)dimm_num,
 803                                        (unsigned int)(calc_cycle_time*10));
 804                                 printf("Replace the DIMM, or change DDR frequency via "
 805                                        "strapping bits.\n\n");
 806                                 spd_ddr_init_hang ();
 807                         }
 808                 }
 809         }
 810 }
 811
 812 /*------------------------------------------------------------------
 813  * For the memory DIMMs installed, this routine verifies two
 814  * ranks/banks maximum are availables.
 815  *-----------------------------------------------------------------*/
 816 static void check_rank_number(unsigned long *dimm_populated,
 817                               unsigned char *iic0_dimm_addr,
 818                               unsigned long num_dimm_banks)
 819 {
 820         unsigned long dimm_num;
 821         unsigned long dimm_rank;
 822         unsigned long total_rank = 0;
 823
 824         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 825                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 826                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 827                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 828                                 dimm_rank = (dimm_rank & 0x0F) +1;
 829                         else
 830                                 dimm_rank = dimm_rank & 0x0F;
 831
 832
 833                         if (dimm_rank > MAXRANKS) {
 834                                 printf("ERROR: DRAM DIMM detected with %d ranks in "
 835                                        "slot %d is not supported.\n", dimm_rank, dimm_num);
 836                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 837                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 838                                 spd_ddr_init_hang ();
 839                         } else
 840                                 total_rank += dimm_rank;
 841                 }
 842                 if (total_rank > MAXRANKS) {
 843                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 844                                "for all slots.\n", (unsigned int)total_rank);
 845                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 846                         printf("Remove one of the DIMM modules.\n\n");
 847                         spd_ddr_init_hang ();
 848                 }
 849         }
 850 }
 851
 852 /*------------------------------------------------------------------
 853  * only support 2.5V modules.
 854  * This routine verifies this.
 855  *-----------------------------------------------------------------*/
 856 static void check_voltage_type(unsigned long *dimm_populated,
 857                                unsigned char *iic0_dimm_addr,
 858                                unsigned long num_dimm_banks)
 859 {
 860         unsigned long dimm_num;
 861         unsigned long voltage_type;
 862
 863         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 864                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 865                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 866                         switch (voltage_type) {
 867                         case 0x00:
 868                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 869                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 870                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 871                                        (unsigned int)dimm_num);
 872                                 spd_ddr_init_hang ();
 873                                 break;
 874                         case 0x01:
 875                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 876                                 printf("This DIMM is LVTTL.\n");
 877                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 878                                        (unsigned int)dimm_num);
 879                                 spd_ddr_init_hang ();
 880                                 break;
 881                         case 0x02:
 882                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 883                                 printf("This DIMM is 1.5 Volt.\n");
 884                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 885                                        (unsigned int)dimm_num);
 886                                 spd_ddr_init_hang ();
 887                                 break;
 888                         case 0x03:
 889                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 890                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 891                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 892                                        (unsigned int)dimm_num);
 893                                 spd_ddr_init_hang ();
 894                                 break;
 895                         case 0x04:
 896                                 /* 2.5 Voltage only for DDR1 */
 897                                 break;
 898                         case 0x05:
 899                                 /* 1.8 Voltage only for DDR2 */
 900                                 break;
 901                         default:
 902                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 903                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 904                                        (unsigned int)dimm_num);
 905                                 spd_ddr_init_hang ();
 906                                 break;
 907                         }
 908                 }
 909         }
 910 }
 911
 912 /*-----------------------------------------------------------------------------+
 913  * program_copt1.
 914  *-----------------------------------------------------------------------------*/
 915 static void program_copt1(unsigned long *dimm_populated,
 916                           unsigned char *iic0_dimm_addr,
 917                           unsigned long num_dimm_banks)
 918 {
 919         unsigned long dimm_num;
 920         unsigned long mcopt1;
 921         unsigned long ecc_enabled;
 922         unsigned long ecc = 0;
 923         unsigned long data_width = 0;
 924         unsigned long dimm_32bit;
 925         unsigned long dimm_64bit;
 926         unsigned long registered = 0;
 927         unsigned long attribute = 0;
 928         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 929         unsigned long bankcount;
 930         unsigned long ddrtype;
 931         unsigned long val;
 932
 933 #ifdef CONFIG_DDR_ECC
 934         ecc_enabled = TRUE;
 935 #else
 936         ecc_enabled = FALSE;
 937 #endif
 938         dimm_32bit = FALSE;
 939         dimm_64bit = FALSE;
 940         buf0 = FALSE;
 941         buf1 = FALSE;
 942
 943         /*------------------------------------------------------------------
 944          * Set memory controller options reg 1, SDRAM_MCOPT1.
 945          *-----------------------------------------------------------------*/
 946         mfsdram(SDRAM_MCOPT1, val);
 947         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 948                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 949                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 950                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 951                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
 952                          SDRAM_MCOPT1_DREF_MASK);
 953
 954         mcopt1 |= SDRAM_MCOPT1_QDEP;
 955         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
 956         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
 957         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
 958         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
 959         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
 960
 961         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 962                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 963                         /* test ecc support */
 964                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 965                         if (ecc != 0x02) /* ecc not supported */
 966                                 ecc_enabled = FALSE;
 967
 968                         /* test bank count */
 969                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
 970                         if (bankcount == 0x04) /* bank count = 4 */
 971                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
 972                         else /* bank count = 8 */
 973                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
 974
 975                         /* test DDR type */
 976                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
 977                         /* test for buffered/unbuffered, registered, differential clocks */
 978                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
 979                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
 980
 981                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 982                         if (dimm_num == 0) {
 983                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
 984                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
 985                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
 986                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
 987                                 if (registered == 1) { /* DDR2 always buffered */
 988                                         /* TODO: what about above  comments ? */
 989                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
 990                                         buf0 = TRUE;
 991                                 } else {
 992                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
 993                                         if ((attribute & 0x02) == 0x00) {
 994                                                 /* buffered not supported */
 995                                                 buf0 = FALSE;
 996                                         } else {
 997                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
 998                                                 buf0 = TRUE;
 999                                         }
1000                                 }
1001                         }
1002                         else if (dimm_num == 1) {
1003                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1004                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1005                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1006                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1007                                 if (registered == 1) {
1008                                         /* DDR2 always buffered */
1009                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1010                                         buf1 = TRUE;
1011                                 } else {
1012                                         if ((attribute & 0x02) == 0x00) {
1013                                                 /* buffered not supported */
1014                                                 buf1 = FALSE;
1015                                         } else {
1016                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1017                                                 buf1 = TRUE;
1018                                         }
1019                                 }
1020                         }
1021
1022                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1023                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1024                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1025
1026                         switch (data_width) {
1027                         case 72:
1028                         case 64:
1029                                 dimm_64bit = TRUE;
1030                                 break;
1031                         case 40:
1032                         case 32:
1033                                 dimm_32bit = TRUE;
1034                                 break;
1035                         default:
1036                                 printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
1037                                        data_width);
1038                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1039                                 break;
1040                         }
1041                 }
1042         }
1043
1044         /* verify matching properties */
1045         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1046                 if (buf0 != buf1) {
1047                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1048                         spd_ddr_init_hang ();
1049                 }
1050         }
1051
1052         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1053                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1054                 spd_ddr_init_hang ();
1055         }
1056         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1057                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1058         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1059                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1060         } else {
1061                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1062                 spd_ddr_init_hang ();
1063         }
1064
1065         if (ecc_enabled == TRUE)
1066                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1067         else
1068                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1069
1070         mtsdram(SDRAM_MCOPT1, mcopt1);
1071 }
1072
1073 /*-----------------------------------------------------------------------------+
1074  * program_codt.
1075  *-----------------------------------------------------------------------------*/
1076 static void program_codt(unsigned long *dimm_populated,
1077                          unsigned char *iic0_dimm_addr,
1078                          unsigned long num_dimm_banks)
1079 {
1080         unsigned long codt;
1081         unsigned long modt0 = 0;
1082         unsigned long modt1 = 0;
1083         unsigned long modt2 = 0;
1084         unsigned long modt3 = 0;
1085         unsigned char dimm_num;
1086         unsigned char dimm_rank;
1087         unsigned char total_rank = 0;
1088         unsigned char total_dimm = 0;
1089         unsigned char dimm_type = 0;
1090         unsigned char firstSlot = 0;
1091
1092         /*------------------------------------------------------------------
1093          * Set the SDRAM Controller On Die Termination Register
1094          *-----------------------------------------------------------------*/
1095         mfsdram(SDRAM_CODT, codt);
1096         codt |= (SDRAM_CODT_IO_NMODE
1097                  & (~SDRAM_CODT_DQS_SINGLE_END
1098                     & ~SDRAM_CODT_CKSE_SINGLE_END
1099                     & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1100                     & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1101
1102         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1103                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1104                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1105                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1106                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1107                                 dimm_type = SDRAM_DDR2;
1108                         } else {
1109                                 dimm_rank = dimm_rank & 0x0F;
1110                                 dimm_type = SDRAM_DDR1;
1111                         }
1112
1113                         total_rank += dimm_rank;
1114                         total_dimm++;
1115                         if ((dimm_num == 0) && (total_dimm == 1))
1116                                 firstSlot = TRUE;
1117                         else
1118                                 firstSlot = FALSE;
1119                 }
1120         }
1121         if (dimm_type == SDRAM_DDR2) {
1122                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1123                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1124                         if (total_rank == 1) {
1125                                 codt |= CALC_ODT_R(0);
1126                                 modt0 = CALC_ODT_W(0);
1127                                 modt1 = 0x00000000;
1128                                 modt2 = 0x00000000;
1129                                 modt3 = 0x00000000;
1130                         }
1131                         if (total_rank == 2) {
1132                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1133                                 modt0 = CALC_ODT_W(0);
1134                                 modt1 = CALC_ODT_W(0);
1135                                 modt2 = 0x00000000;
1136                                 modt3 = 0x00000000;
1137                         }
1138                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1139                         if (total_rank == 1) {
1140                                 codt |= CALC_ODT_R(2);
1141                                 modt0 = 0x00000000;
1142                                 modt1 = 0x00000000;
1143                                 modt2 = CALC_ODT_W(2);
1144                                 modt3 = 0x00000000;
1145                         }
1146                         if (total_rank == 2) {
1147                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1148                                 modt0 = 0x00000000;
1149                                 modt1 = 0x00000000;
1150                                 modt2 = CALC_ODT_W(2);
1151                                 modt3 = CALC_ODT_W(2);
1152                         }
1153                 }
1154                 if (total_dimm == 2) {
1155                         if (total_rank == 2) {
1156                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1157                                 modt0 = CALC_ODT_RW(2);
1158                                 modt1 = 0x00000000;
1159                                 modt2 = CALC_ODT_RW(0);
1160                                 modt3 = 0x00000000;
1161                         }
1162                         if (total_rank == 4) {
1163                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1164                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1165                                 modt0 = CALC_ODT_RW(2);
1166                                 modt1 = 0x00000000;
1167                                 modt2 = CALC_ODT_RW(0);
1168                                 modt3 = 0x00000000;
1169                         }
1170                 }
1171         } else {
1172                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1173                 modt0 = 0x00000000;
1174                 modt1 = 0x00000000;
1175                 modt2 = 0x00000000;
1176                 modt3 = 0x00000000;
1177
1178                 if (total_dimm == 1) {
1179                         if (total_rank == 1)
1180                                 codt |= 0x00800000;
1181                         if (total_rank == 2)
1182                                 codt |= 0x02800000;
1183                 }
1184                 if (total_dimm == 2) {
1185                         if (total_rank == 2)
1186                                 codt |= 0x08800000;
1187                         if (total_rank == 4)
1188                                 codt |= 0x2a800000;
1189                 }
1190         }
1191
1192         debug("nb of dimm %d\n", total_dimm);
1193         debug("nb of rank %d\n", total_rank);
1194         if (total_dimm == 1)
1195                 debug("dimm in slot %d\n", firstSlot);
1196
1197         mtsdram(SDRAM_CODT, codt);
1198         mtsdram(SDRAM_MODT0, modt0);
1199         mtsdram(SDRAM_MODT1, modt1);
1200         mtsdram(SDRAM_MODT2, modt2);
1201         mtsdram(SDRAM_MODT3, modt3);
1202 }
1203
1204 /*-----------------------------------------------------------------------------+
1205  * program_initplr.
1206  *-----------------------------------------------------------------------------*/
1207 static void program_initplr(unsigned long *dimm_populated,
1208                             unsigned char *iic0_dimm_addr,
1209                             unsigned long num_dimm_banks,
1210                             ddr_cas_id_t selected_cas,
1211                             int write_recovery)
1212 {
1213         u32 cas = 0;
1214         u32 odt = 0;
1215         u32 ods = 0;
1216         u32 mr;
1217         u32 wr;
1218         u32 emr;
1219         u32 emr2;
1220         u32 emr3;
1221         int dimm_num;
1222         int total_dimm = 0;
1223
1224         /******************************************************
1225          ** Assumption: if more than one DIMM, all DIMMs are the same
1226          **             as already checked in check_memory_type
1227          ******************************************************/
1228
1229         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1230                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1231                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1232                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1233                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1234                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1235                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1236                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1237                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1238         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1239                 switch (selected_cas) {
1240                 case DDR_CAS_3:
1241                         cas = 3 << 4;
1242                         break;
1243                 case DDR_CAS_4:
1244                         cas = 4 << 4;
1245                         break;
1246                 case DDR_CAS_5:
1247                         cas = 5 << 4;
1248                         break;
1249                 default:
1250                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1251                         spd_ddr_init_hang ();
1252                         break;
1253                 }
1254
1255 #if 0
1256                 /*
1257                  * ToDo - Still a problem with the write recovery:
1258                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1259                  * in the INITPLR reg to the value calculated in program_mode()
1260                  * results in not correctly working DDR2 memory (crash after
1261                  * relocation).
1262                  *
1263                  * So for now, set the write recovery to 3. This seems to work
1264                  * on the Corair module too.
1265                  *
1266                  * 2007-03-01, sr
1267                  */
1268                 switch (write_recovery) {
1269                 case 3:
1270                         wr = WRITE_RECOV_3;
1271                         break;
1272                 case 4:
1273                         wr = WRITE_RECOV_4;
1274                         break;
1275                 case 5:
1276                         wr = WRITE_RECOV_5;
1277                         break;
1278                 case 6:
1279                         wr = WRITE_RECOV_6;
1280                         break;
1281                 default:
1282                         printf("ERROR: write recovery not support (%d)", write_recovery);
1283                         spd_ddr_init_hang ();
1284                         break;
1285                 }
1286 #else
1287                 wr = WRITE_RECOV_3; /* test-only, see description above */
1288 #endif
1289
1290                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1291                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1292                                 total_dimm++;
1293                 if (total_dimm == 1) {
1294                         odt = ODT_150_OHM;
1295                         ods = ODS_FULL;
1296                 } else if (total_dimm == 2) {
1297                         odt = ODT_75_OHM;
1298                         ods = ODS_REDUCED;
1299                 } else {
1300                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1301                         spd_ddr_init_hang ();
1302                 }
1303
1304                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1305                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1306                 emr2 = CMD_EMR | SELECT_EMR2;
1307                 emr3 = CMD_EMR | SELECT_EMR3;
1308                 mtsdram(SDRAM_INITPLR0,  0xB5000000 | CMD_NOP);         /* NOP */
1309                 udelay(1000);
1310                 mtsdram(SDRAM_INITPLR1,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1311                 mtsdram(SDRAM_INITPLR2,  0x80800000 | emr2);            /* EMR2 */
1312                 mtsdram(SDRAM_INITPLR3,  0x80800000 | emr3);            /* EMR3 */
1313                 mtsdram(SDRAM_INITPLR4,  0x80800000 | emr);             /* EMR DLL ENABLE */
1314                 mtsdram(SDRAM_INITPLR5,  0x80800000 | mr | DLL_RESET);  /* MR w/ DLL reset */
1315                 udelay(1000);
1316                 mtsdram(SDRAM_INITPLR6,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1317                 mtsdram(SDRAM_INITPLR7,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1318                 mtsdram(SDRAM_INITPLR8,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1319                 mtsdram(SDRAM_INITPLR9,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1320                 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1321                 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr);              /* MR w/o DLL reset */
1322                 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr);             /* EMR OCD Default */
1323                 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr);             /* EMR OCD Exit */
1324         } else {
1325                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1326                 spd_ddr_init_hang ();
1327         }
1328 }
1329
1330 /*------------------------------------------------------------------
1331  * This routine programs the SDRAM_MMODE register.
1332  * the selected_cas is an output parameter, that will be passed
1333  * by caller to call the above program_initplr( )
1334  *-----------------------------------------------------------------*/
1335 static void program_mode(unsigned long *dimm_populated,
1336                          unsigned char *iic0_dimm_addr,
1337                          unsigned long num_dimm_banks,
1338                          ddr_cas_id_t *selected_cas,
1339                          int *write_recovery)
1340 {
1341         unsigned long dimm_num;
1342         unsigned long sdram_ddr1;
1343         unsigned long t_wr_ns;
1344         unsigned long t_wr_clk;
1345         unsigned long cas_bit;
1346         unsigned long cas_index;
1347         unsigned long sdram_freq;
1348         unsigned long ddr_check;
1349         unsigned long mmode;
1350         unsigned long tcyc_reg;
1351         unsigned long cycle_2_0_clk;
1352         unsigned long cycle_2_5_clk;
1353         unsigned long cycle_3_0_clk;
1354         unsigned long cycle_4_0_clk;
1355         unsigned long cycle_5_0_clk;
1356         unsigned long max_2_0_tcyc_ns_x_100;
1357         unsigned long max_2_5_tcyc_ns_x_100;
1358         unsigned long max_3_0_tcyc_ns_x_100;
1359         unsigned long max_4_0_tcyc_ns_x_100;
1360         unsigned long max_5_0_tcyc_ns_x_100;
1361         unsigned long cycle_time_ns_x_100[3];
1362         PPC4xx_SYS_INFO board_cfg;
1363         unsigned char cas_2_0_available;
1364         unsigned char cas_2_5_available;
1365         unsigned char cas_3_0_available;
1366         unsigned char cas_4_0_available;
1367         unsigned char cas_5_0_available;
1368         unsigned long sdr_ddrpll;
1369
1370         /*------------------------------------------------------------------
1371          * Get the board configuration info.
1372          *-----------------------------------------------------------------*/
1373         get_sys_info(&board_cfg);
1374
1375         mfsdr(SDR0_DDR0, sdr_ddrpll);
1376         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1377         debug("sdram_freq=%d\n", sdram_freq);
1378
1379         /*------------------------------------------------------------------
1380          * Handle the timing.  We need to find the worst case timing of all
1381          * the dimm modules installed.
1382          *-----------------------------------------------------------------*/
1383         t_wr_ns = 0;
1384         cas_2_0_available = TRUE;
1385         cas_2_5_available = TRUE;
1386         cas_3_0_available = TRUE;
1387         cas_4_0_available = TRUE;
1388         cas_5_0_available = TRUE;
1389         max_2_0_tcyc_ns_x_100 = 10;
1390         max_2_5_tcyc_ns_x_100 = 10;
1391         max_3_0_tcyc_ns_x_100 = 10;
1392         max_4_0_tcyc_ns_x_100 = 10;
1393         max_5_0_tcyc_ns_x_100 = 10;
1394         sdram_ddr1 = TRUE;
1395
1396         /* loop through all the DIMM slots on the board */
1397         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1398                 /* If a dimm is installed in a particular slot ... */
1399                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1400                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1401                                 sdram_ddr1 = TRUE;
1402                         else
1403                                 sdram_ddr1 = FALSE;
1404
1405                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1406                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1407                         debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1408
1409                         /* For a particular DIMM, grab the three CAS values it supports */
1410                         for (cas_index = 0; cas_index < 3; cas_index++) {
1411                                 switch (cas_index) {
1412                                 case 0:
1413                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1414                                         break;
1415                                 case 1:
1416                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1417                                         break;
1418                                 default:
1419                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1420                                         break;
1421                                 }
1422
1423                                 if ((tcyc_reg & 0x0F) >= 10) {
1424                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1425                                                 /* Convert from hex to decimal */
1426                                                 cycle_time_ns_x_100[cas_index] =
1427                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1428                                         } else {
1429                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1430                                                        "in slot %d\n", (unsigned int)dimm_num);
1431                                                 spd_ddr_init_hang ();
1432                                         }
1433                                 } else {
1434                                         /* Convert from hex to decimal */
1435                                         cycle_time_ns_x_100[cas_index] =
1436                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1437                                                 ((tcyc_reg & 0x0F)*10);
1438                                 }
1439                                 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1440                                       cycle_time_ns_x_100[cas_index]);
1441                         }
1442
1443                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1444                         /* supported for a particular DIMM. */
1445                         cas_index = 0;
1446
1447                         if (sdram_ddr1) {
1448                                 /*
1449                                  * DDR devices use the following bitmask for CAS latency:
1450                                  *  Bit   7    6    5    4    3    2    1    0
1451                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1452                                  */
1453                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1454                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1455                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1456                                                                     cycle_time_ns_x_100[cas_index]);
1457                                         cas_index++;
1458                                 } else {
1459                                         if (cas_index != 0)
1460                                                 cas_index++;
1461                                         cas_4_0_available = FALSE;
1462                                 }
1463
1464                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1465                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1466                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1467                                                                     cycle_time_ns_x_100[cas_index]);
1468                                         cas_index++;
1469                                 } else {
1470                                         if (cas_index != 0)
1471                                                 cas_index++;
1472                                         cas_3_0_available = FALSE;
1473                                 }
1474
1475                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1476                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1477                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1478                                                                     cycle_time_ns_x_100[cas_index]);
1479                                         cas_index++;
1480                                 } else {
1481                                         if (cas_index != 0)
1482                                                 cas_index++;
1483                                         cas_2_5_available = FALSE;
1484                                 }
1485
1486                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1487                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1488                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1489                                                                     cycle_time_ns_x_100[cas_index]);
1490                                         cas_index++;
1491                                 } else {
1492                                         if (cas_index != 0)
1493                                                 cas_index++;
1494                                         cas_2_0_available = FALSE;
1495                                 }
1496                         } else {
1497                                 /*
1498                                  * DDR2 devices use the following bitmask for CAS latency:
1499                                  *  Bit   7    6    5    4    3    2    1    0
1500                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1501                                  */
1502                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1503                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1504                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1505                                                                     cycle_time_ns_x_100[cas_index]);
1506                                         cas_index++;
1507                                 } else {
1508                                         if (cas_index != 0)
1509                                                 cas_index++;
1510                                         cas_5_0_available = FALSE;
1511                                 }
1512
1513                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1514                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1515                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1516                                                                     cycle_time_ns_x_100[cas_index]);
1517                                         cas_index++;
1518                                 } else {
1519                                         if (cas_index != 0)
1520                                                 cas_index++;
1521                                         cas_4_0_available = FALSE;
1522                                 }
1523
1524                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1525                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1526                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1527                                                                     cycle_time_ns_x_100[cas_index]);
1528                                         cas_index++;
1529                                 } else {
1530                                         if (cas_index != 0)
1531                                                 cas_index++;
1532                                         cas_3_0_available = FALSE;
1533                                 }
1534                         }
1535                 }
1536         }
1537
1538         /*------------------------------------------------------------------
1539          * Set the SDRAM mode, SDRAM_MMODE
1540          *-----------------------------------------------------------------*/
1541         mfsdram(SDRAM_MMODE, mmode);
1542         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1543
1544         /* add 10 here because of rounding problems */
1545         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1546         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1547         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1548         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1549         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1550         debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1551         debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1552         debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1553
1554         if (sdram_ddr1 == TRUE) { /* DDR1 */
1555                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1556                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1557                         *selected_cas = DDR_CAS_2;
1558                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1559                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1560                         *selected_cas = DDR_CAS_2_5;
1561                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1562                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1563                         *selected_cas = DDR_CAS_3;
1564                 } else {
1565                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1566                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1567                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1568                         spd_ddr_init_hang ();
1569                 }
1570         } else { /* DDR2 */
1571                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1572                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1573                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1574                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1575                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1576                         *selected_cas = DDR_CAS_3;
1577                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1578                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1579                         *selected_cas = DDR_CAS_4;
1580                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1581                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1582                         *selected_cas = DDR_CAS_5;
1583                 } else {
1584                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1585                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1586                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1587                         printf("cas3=%d cas4=%d cas5=%d\n",
1588                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1589                         printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
1590                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1591                         spd_ddr_init_hang ();
1592                 }
1593         }
1594
1595         if (sdram_ddr1 == TRUE)
1596                 mmode |= SDRAM_MMODE_WR_DDR1;
1597         else {
1598
1599                 /* loop through all the DIMM slots on the board */
1600                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1601                         /* If a dimm is installed in a particular slot ... */
1602                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1603                                 t_wr_ns = max(t_wr_ns,
1604                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1605                 }
1606
1607                 /*
1608                  * convert from nanoseconds to ddr clocks
1609                  * round up if necessary
1610                  */
1611                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1612                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1613                 if (sdram_freq != ddr_check)
1614                         t_wr_clk++;
1615
1616                 switch (t_wr_clk) {
1617                 case 0:
1618                 case 1:
1619                 case 2:
1620                 case 3:
1621                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1622                         break;
1623                 case 4:
1624                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1625                         break;
1626                 case 5:
1627                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1628                         break;
1629                 default:
1630                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1631                         break;
1632                 }
1633                 *write_recovery = t_wr_clk;
1634         }
1635
1636         debug("CAS latency = %d\n", *selected_cas);
1637         debug("Write recovery = %d\n", *write_recovery);
1638
1639         mtsdram(SDRAM_MMODE, mmode);
1640 }
1641
1642 /*-----------------------------------------------------------------------------+
1643  * program_rtr.
1644  *-----------------------------------------------------------------------------*/
1645 static void program_rtr(unsigned long *dimm_populated,
1646                         unsigned char *iic0_dimm_addr,
1647                         unsigned long num_dimm_banks)
1648 {
1649         PPC4xx_SYS_INFO board_cfg;
1650         unsigned long max_refresh_rate;
1651         unsigned long dimm_num;
1652         unsigned long refresh_rate_type;
1653         unsigned long refresh_rate;
1654         unsigned long rint;
1655         unsigned long sdram_freq;
1656         unsigned long sdr_ddrpll;
1657         unsigned long val;
1658
1659         /*------------------------------------------------------------------
1660          * Get the board configuration info.
1661          *-----------------------------------------------------------------*/
1662         get_sys_info(&board_cfg);
1663
1664         /*------------------------------------------------------------------
1665          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1666          *-----------------------------------------------------------------*/
1667         mfsdr(SDR0_DDR0, sdr_ddrpll);
1668         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1669
1670         max_refresh_rate = 0;
1671         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1672                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1673
1674                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1675                         refresh_rate_type &= 0x7F;
1676                         switch (refresh_rate_type) {
1677                         case 0:
1678                                 refresh_rate =  15625;
1679                                 break;
1680                         case 1:
1681                                 refresh_rate =   3906;
1682                                 break;
1683                         case 2:
1684                                 refresh_rate =   7812;
1685                                 break;
1686                         case 3:
1687                                 refresh_rate =  31250;
1688                                 break;
1689                         case 4:
1690                                 refresh_rate =  62500;
1691                                 break;
1692                         case 5:
1693                                 refresh_rate = 125000;
1694                                 break;
1695                         default:
1696                                 refresh_rate = 0;
1697                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1698                                        (unsigned int)dimm_num);
1699                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1700                                 spd_ddr_init_hang ();
1701                                 break;
1702                         }
1703
1704                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1705                 }
1706         }
1707
1708         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1709         mfsdram(SDRAM_RTR, val);
1710         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1711                 (SDRAM_RTR_RINT_ENCODE(rint)));
1712 }
1713
1714 /*------------------------------------------------------------------
1715  * This routine programs the SDRAM_TRx registers.
1716  *-----------------------------------------------------------------*/
1717 static void program_tr(unsigned long *dimm_populated,
1718                        unsigned char *iic0_dimm_addr,
1719                        unsigned long num_dimm_banks)
1720 {
1721         unsigned long dimm_num;
1722         unsigned long sdram_ddr1;
1723         unsigned long t_rp_ns;
1724         unsigned long t_rcd_ns;
1725         unsigned long t_rrd_ns;
1726         unsigned long t_ras_ns;
1727         unsigned long t_rc_ns;
1728         unsigned long t_rfc_ns;
1729         unsigned long t_wpc_ns;
1730         unsigned long t_wtr_ns;
1731         unsigned long t_rpc_ns;
1732         unsigned long t_rp_clk;
1733         unsigned long t_rcd_clk;
1734         unsigned long t_rrd_clk;
1735         unsigned long t_ras_clk;
1736         unsigned long t_rc_clk;
1737         unsigned long t_rfc_clk;
1738         unsigned long t_wpc_clk;
1739         unsigned long t_wtr_clk;
1740         unsigned long t_rpc_clk;
1741         unsigned long sdtr1, sdtr2, sdtr3;
1742         unsigned long ddr_check;
1743         unsigned long sdram_freq;
1744         unsigned long sdr_ddrpll;
1745
1746         PPC4xx_SYS_INFO board_cfg;
1747
1748         /*------------------------------------------------------------------
1749          * Get the board configuration info.
1750          *-----------------------------------------------------------------*/
1751         get_sys_info(&board_cfg);
1752
1753         mfsdr(SDR0_DDR0, sdr_ddrpll);
1754         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1755
1756         /*------------------------------------------------------------------
1757          * Handle the timing.  We need to find the worst case timing of all
1758          * the dimm modules installed.
1759          *-----------------------------------------------------------------*/
1760         t_rp_ns = 0;
1761         t_rrd_ns = 0;
1762         t_rcd_ns = 0;
1763         t_ras_ns = 0;
1764         t_rc_ns = 0;
1765         t_rfc_ns = 0;
1766         t_wpc_ns = 0;
1767         t_wtr_ns = 0;
1768         t_rpc_ns = 0;
1769         sdram_ddr1 = TRUE;
1770
1771         /* loop through all the DIMM slots on the board */
1772         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1773                 /* If a dimm is installed in a particular slot ... */
1774                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1775                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1776                                 sdram_ddr1 = TRUE;
1777                         else
1778                                 sdram_ddr1 = FALSE;
1779
1780                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1781                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1782                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1783                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1784                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1785                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1786                 }
1787         }
1788
1789         /*------------------------------------------------------------------
1790          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1791          *-----------------------------------------------------------------*/
1792         mfsdram(SDRAM_SDTR1, sdtr1);
1793         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1794                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1795
1796         /* default values */
1797         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1798         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1799
1800         /* normal operations */
1801         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1802         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1803
1804         mtsdram(SDRAM_SDTR1, sdtr1);
1805
1806         /*------------------------------------------------------------------
1807          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1808          *-----------------------------------------------------------------*/
1809         mfsdram(SDRAM_SDTR2, sdtr2);
1810         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1811                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1812                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1813                    SDRAM_SDTR2_RRD_MASK);
1814
1815         /*
1816          * convert t_rcd from nanoseconds to ddr clocks
1817          * round up if necessary
1818          */
1819         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1820         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1821         if (sdram_freq != ddr_check)
1822                 t_rcd_clk++;
1823
1824         switch (t_rcd_clk) {
1825         case 0:
1826         case 1:
1827                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1828                 break;
1829         case 2:
1830                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1831                 break;
1832         case 3:
1833                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1834                 break;
1835         case 4:
1836                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1837                 break;
1838         default:
1839                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1840                 break;
1841         }
1842
1843         if (sdram_ddr1 == TRUE) { /* DDR1 */
1844                 if (sdram_freq < 200000000) {
1845                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1846                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1847                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1848                 } else {
1849                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1850                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1851                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1852                 }
1853         } else { /* DDR2 */
1854                 /* loop through all the DIMM slots on the board */
1855                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1856                         /* If a dimm is installed in a particular slot ... */
1857                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1858                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1859                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1860                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1861                         }
1862                 }
1863
1864                 /*
1865                  * convert from nanoseconds to ddr clocks
1866                  * round up if necessary
1867                  */
1868                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1869                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1870                 if (sdram_freq != ddr_check)
1871                         t_wpc_clk++;
1872
1873                 switch (t_wpc_clk) {
1874                 case 0:
1875                 case 1:
1876                 case 2:
1877                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1878                         break;
1879                 case 3:
1880                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1881                         break;
1882                 case 4:
1883                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1884                         break;
1885                 case 5:
1886                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1887                         break;
1888                 default:
1889                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1890                         break;
1891                 }
1892
1893                 /*
1894                  * convert from nanoseconds to ddr clocks
1895                  * round up if necessary
1896                  */
1897                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1898                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1899                 if (sdram_freq != ddr_check)
1900                         t_wtr_clk++;
1901
1902                 switch (t_wtr_clk) {
1903                 case 0:
1904                 case 1:
1905                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1906                         break;
1907                 case 2:
1908                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1909                         break;
1910                 case 3:
1911                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1912                         break;
1913                 default:
1914                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1915                         break;
1916                 }
1917
1918                 /*
1919                  * convert from nanoseconds to ddr clocks
1920                  * round up if necessary
1921                  */
1922                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1923                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1924                 if (sdram_freq != ddr_check)
1925                         t_rpc_clk++;
1926
1927                 switch (t_rpc_clk) {
1928                 case 0:
1929                 case 1:
1930                 case 2:
1931                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1932                         break;
1933                 case 3:
1934                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1935                         break;
1936                 default:
1937                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1938                         break;
1939                 }
1940         }
1941
1942         /* default value */
1943         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1944
1945         /*
1946          * convert t_rrd from nanoseconds to ddr clocks
1947          * round up if necessary
1948          */
1949         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1950         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1951         if (sdram_freq != ddr_check)
1952                 t_rrd_clk++;
1953
1954         if (t_rrd_clk == 3)
1955                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1956         else
1957                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1958
1959         /*
1960          * convert t_rp from nanoseconds to ddr clocks
1961          * round up if necessary
1962          */
1963         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1964         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1965         if (sdram_freq != ddr_check)
1966                 t_rp_clk++;
1967
1968         switch (t_rp_clk) {
1969         case 0:
1970         case 1:
1971         case 2:
1972         case 3:
1973                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
1974                 break;
1975         case 4:
1976                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
1977                 break;
1978         case 5:
1979                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
1980                 break;
1981         case 6:
1982                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
1983                 break;
1984         default:
1985                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
1986                 break;
1987         }
1988
1989         mtsdram(SDRAM_SDTR2, sdtr2);
1990
1991         /*------------------------------------------------------------------
1992          * Set the SDRAM Timing Reg 3, SDRAM_TR3
1993          *-----------------------------------------------------------------*/
1994         mfsdram(SDRAM_SDTR3, sdtr3);
1995         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
1996                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
1997
1998         /*
1999          * convert t_ras from nanoseconds to ddr clocks
2000          * round up if necessary
2001          */
2002         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2003         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2004         if (sdram_freq != ddr_check)
2005                 t_ras_clk++;
2006
2007         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2008
2009         /*
2010          * convert t_rc from nanoseconds to ddr clocks
2011          * round up if necessary
2012          */
2013         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2014         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2015         if (sdram_freq != ddr_check)
2016                 t_rc_clk++;
2017
2018         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2019
2020         /* default xcs value */
2021         sdtr3 |= SDRAM_SDTR3_XCS;
2022
2023         /*
2024          * convert t_rfc from nanoseconds to ddr clocks
2025          * round up if necessary
2026          */
2027         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2028         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2029         if (sdram_freq != ddr_check)
2030                 t_rfc_clk++;
2031
2032         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2033
2034         mtsdram(SDRAM_SDTR3, sdtr3);
2035 }
2036
2037 /*-----------------------------------------------------------------------------+
2038  * program_bxcf.
2039  *-----------------------------------------------------------------------------*/
2040 static void program_bxcf(unsigned long *dimm_populated,
2041                          unsigned char *iic0_dimm_addr,
2042                          unsigned long num_dimm_banks)
2043 {
2044         unsigned long dimm_num;
2045         unsigned long num_col_addr;
2046         unsigned long num_ranks;
2047         unsigned long num_banks;
2048         unsigned long mode;
2049         unsigned long ind_rank;
2050         unsigned long ind;
2051         unsigned long ind_bank;
2052         unsigned long bank_0_populated;
2053
2054         /*------------------------------------------------------------------
2055          * Set the BxCF regs.  First, wipe out the bank config registers.
2056          *-----------------------------------------------------------------*/
2057         mtsdram(SDRAM_MB0CF, 0x00000000);
2058         mtsdram(SDRAM_MB1CF, 0x00000000);
2059         mtsdram(SDRAM_MB2CF, 0x00000000);
2060         mtsdram(SDRAM_MB3CF, 0x00000000);
2061
2062         mode = SDRAM_BXCF_M_BE_ENABLE;
2063
2064         bank_0_populated = 0;
2065
2066         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2067                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2068                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2069                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2070                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2071                                 num_ranks = (num_ranks & 0x0F) +1;
2072                         else
2073                                 num_ranks = num_ranks & 0x0F;
2074
2075                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2076
2077                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2078                                 if (num_banks == 4)
2079                                         ind = 0;
2080                                 else
2081                                         ind = 5;
2082                                 switch (num_col_addr) {
2083                                 case 0x08:
2084                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2085                                         break;
2086                                 case 0x09:
2087                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2088                                         break;
2089                                 case 0x0A:
2090                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2091                                         break;
2092                                 case 0x0B:
2093                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2094                                         break;
2095                                 case 0x0C:
2096                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2097                                         break;
2098                                 default:
2099                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2100                                                (unsigned int)dimm_num);
2101                                         printf("ERROR: Unsupported value for number of "
2102                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2103                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2104                                         spd_ddr_init_hang ();
2105                                 }
2106                         }
2107
2108                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2109                                 bank_0_populated = 1;
2110
2111                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2112                                 mtsdram(SDRAM_MB0CF +
2113                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2114                                         mode);
2115                         }
2116                 }
2117         }
2118 }
2119
2120 /*------------------------------------------------------------------
2121  * program memory queue.
2122  *-----------------------------------------------------------------*/
2123 static void program_memory_queue(unsigned long *dimm_populated,
2124                                  unsigned char *iic0_dimm_addr,
2125                                  unsigned long num_dimm_banks)
2126 {
2127         unsigned long dimm_num;
2128         unsigned long rank_base_addr;
2129         unsigned long rank_reg;
2130         unsigned long rank_size_bytes;
2131         unsigned long rank_size_id;
2132         unsigned long num_ranks;
2133         unsigned long baseadd_size;
2134         unsigned long i;
2135         unsigned long bank_0_populated = 0;
2136         unsigned long total_size = 0;
2137
2138         /*------------------------------------------------------------------
2139          * Reset the rank_base_address.
2140          *-----------------------------------------------------------------*/
2141         rank_reg   = SDRAM_R0BAS;
2142
2143         rank_base_addr = 0x00000000;
2144
2145         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2146                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2147                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2148                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2149                                 num_ranks = (num_ranks & 0x0F) + 1;
2150                         else
2151                                 num_ranks = num_ranks & 0x0F;
2152
2153                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2154
2155                         /*------------------------------------------------------------------
2156                          * Set the sizes
2157                          *-----------------------------------------------------------------*/
2158                         baseadd_size = 0;
2159                         switch (rank_size_id) {
2160                         case 0x01:
2161                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2162                                 total_size = 1024;
2163                                 break;
2164                         case 0x02:
2165                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2166                                 total_size = 2048;
2167                                 break;
2168                         case 0x04:
2169                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2170                                 total_size = 4096;
2171                                 break;
2172                         case 0x08:
2173                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2174                                 total_size = 32;
2175                                 break;
2176                         case 0x10:
2177                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2178                                 total_size = 64;
2179                                 break;
2180                         case 0x20:
2181                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2182                                 total_size = 128;
2183                                 break;
2184                         case 0x40:
2185                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2186                                 total_size = 256;
2187                                 break;
2188                         case 0x80:
2189                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2190                                 total_size = 512;
2191                                 break;
2192                         default:
2193                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2194                                        (unsigned int)dimm_num);
2195                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2196                                        (unsigned int)rank_size_id);
2197                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2198                                 spd_ddr_init_hang ();
2199                         }
2200                         rank_size_bytes = total_size << 20;
2201
2202                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2203                                 bank_0_populated = 1;
2204
2205                         for (i = 0; i < num_ranks; i++) {
2206                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2207                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2208                                            baseadd_size));
2209                                 rank_base_addr += rank_size_bytes;
2210                         }
2211                 }
2212         }
2213
2214 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
2215         /*
2216          * Enable high bandwidth access on 460EX/GT.
2217          * This should/could probably be done on other
2218          * PPC's too, like 440SPe.
2219          * This is currently not used, but with this setup
2220          * it is possible to use it later on in e.g. the Linux
2221          * EMAC driver for performance gain.
2222          */
2223         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2224         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2225 #endif
2226 }
2227
2228 /*-----------------------------------------------------------------------------+
2229  * is_ecc_enabled.
2230  *-----------------------------------------------------------------------------*/
2231 static unsigned long is_ecc_enabled(void)
2232 {
2233         unsigned long dimm_num;
2234         unsigned long ecc;
2235         unsigned long val;
2236
2237         ecc = 0;
2238         /* loop through all the DIMM slots on the board */
2239         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2240                 mfsdram(SDRAM_MCOPT1, val);
2241                 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2242         }
2243
2244         return ecc;
2245 }
2246
2247 static void blank_string(int size)
2248 {
2249         int i;
2250
2251         for (i=0; i<size; i++)
2252                 putc('\b');
2253         for (i=0; i<size; i++)
2254                 putc(' ');
2255         for (i=0; i<size; i++)
2256                 putc('\b');
2257 }
2258
2259 #ifdef CONFIG_DDR_ECC
2260 /*-----------------------------------------------------------------------------+
2261  * program_ecc.
2262  *-----------------------------------------------------------------------------*/
2263 static void program_ecc(unsigned long *dimm_populated,
2264                         unsigned char *iic0_dimm_addr,
2265                         unsigned long num_dimm_banks,
2266                         unsigned long tlb_word2_i_value)
2267 {
2268         unsigned long mcopt1;
2269         unsigned long mcopt2;
2270         unsigned long mcstat;
2271         unsigned long dimm_num;
2272         unsigned long ecc;
2273
2274         ecc = 0;
2275         /* loop through all the DIMM slots on the board */
2276         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2277                 /* If a dimm is installed in a particular slot ... */
2278                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2279                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2280         }
2281         if (ecc == 0)
2282                 return;
2283
2284         mfsdram(SDRAM_MCOPT1, mcopt1);
2285         mfsdram(SDRAM_MCOPT2, mcopt2);
2286
2287         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2288                 /* DDR controller must be enabled and not in self-refresh. */
2289                 mfsdram(SDRAM_MCSTAT, mcstat);
2290                 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2291                     && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2292                     && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2293                         == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2294
2295                         program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2296                 }
2297         }
2298
2299         return;
2300 }
2301
2302 static void wait_ddr_idle(void)
2303 {
2304         u32 val;
2305
2306         do {
2307                 mfsdram(SDRAM_MCSTAT, val);
2308         } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2309 }
2310
2311 /*-----------------------------------------------------------------------------+
2312  * program_ecc_addr.
2313  *-----------------------------------------------------------------------------*/
2314 static void program_ecc_addr(unsigned long start_address,
2315                              unsigned long num_bytes,
2316                              unsigned long tlb_word2_i_value)
2317 {
2318         unsigned long current_address;
2319         unsigned long end_address;
2320         unsigned long address_increment;
2321         unsigned long mcopt1;
2322         char str[] = "ECC generation -";
2323         char slash[] = "\\|/-\\|/-";
2324         int loop = 0;
2325         int loopi = 0;
2326
2327         current_address = start_address;
2328         mfsdram(SDRAM_MCOPT1, mcopt1);
2329         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2330                 mtsdram(SDRAM_MCOPT1,
2331                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2332                 sync();
2333                 eieio();
2334                 wait_ddr_idle();
2335
2336                 puts(str);
2337                 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2338                         /* ECC bit set method for non-cached memory */
2339                         if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2340                                 address_increment = 4;
2341                         else
2342                                 address_increment = 8;
2343                         end_address = current_address + num_bytes;
2344
2345                         while (current_address < end_address) {
2346                                 *((unsigned long *)current_address) = 0x00000000;
2347                                 current_address += address_increment;
2348
2349                                 if ((loop++ % (2 << 20)) == 0) {
2350                                         putc('\b');
2351                                         putc(slash[loopi++ % 8]);
2352                                 }
2353                         }
2354
2355                 } else {
2356                         /* ECC bit set method for cached memory */
2357                         dcbz_area(start_address, num_bytes);
2358                         /* Write modified dcache lines back to memory */
2359                         clean_dcache_range(start_address, start_address + num_bytes);
2360                 }
2361
2362                 blank_string(strlen(str));
2363
2364                 sync();
2365                 eieio();
2366                 wait_ddr_idle();
2367
2368                 /* clear ECC error repoting registers */
2369                 mtsdram(SDRAM_ECCCR, 0xffffffff);
2370                 mtdcr(0x4c, 0xffffffff);
2371
2372                 mtsdram(SDRAM_MCOPT1,
2373                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2374                 sync();
2375                 eieio();
2376                 wait_ddr_idle();
2377         }
2378 }
2379 #endif
2380
2381 /*-----------------------------------------------------------------------------+
2382  * program_DQS_calibration.
2383  *-----------------------------------------------------------------------------*/
2384 static void program_DQS_calibration(unsigned long *dimm_populated,
2385                                     unsigned char *iic0_dimm_addr,
2386                                     unsigned long num_dimm_banks)
2387 {
2388         unsigned long val;
2389
2390 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2391         mtsdram(SDRAM_RQDC, 0x80000037);
2392         mtsdram(SDRAM_RDCC, 0x40000000);
2393         mtsdram(SDRAM_RFDC, 0x000001DF);
2394
2395         test();
2396 #else
2397         /*------------------------------------------------------------------
2398          * Program RDCC register
2399          * Read sample cycle auto-update enable
2400          *-----------------------------------------------------------------*/
2401
2402         mfsdram(SDRAM_RDCC, val);
2403         mtsdram(SDRAM_RDCC,
2404                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2405                 | SDRAM_RDCC_RSAE_ENABLE);
2406
2407         /*------------------------------------------------------------------
2408          * Program RQDC register
2409          * Internal DQS delay mechanism enable
2410          *-----------------------------------------------------------------*/
2411         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2412
2413         /*------------------------------------------------------------------
2414          * Program RFDC register
2415          * Set Feedback Fractional Oversample
2416          * Auto-detect read sample cycle enable
2417          *-----------------------------------------------------------------*/
2418         mfsdram(SDRAM_RFDC, val);
2419         mtsdram(SDRAM_RFDC,
2420                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2421                          SDRAM_RFDC_RFFD_MASK))
2422                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2423                    SDRAM_RFDC_RFFD_ENCODE(0)));
2424
2425         DQS_calibration_process();
2426 #endif
2427 }
2428
2429 static int short_mem_test(void)
2430 {
2431         u32 *membase;
2432         u32 bxcr_num;
2433         u32 bxcf;
2434         int i;
2435         int j;
2436         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2437                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2438                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2439                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2440                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2441                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2442                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2443                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2444                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2445                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2446                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2447                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2448                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2449                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2450                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2451                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2452                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2453         int l;
2454
2455         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2456                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2457
2458                 /* Banks enabled */
2459                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2460                         /* Bank is enabled */
2461
2462                         /*------------------------------------------------------------------
2463                          * Run the short memory test.
2464                          *-----------------------------------------------------------------*/
2465                         membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
2466
2467                         for (i = 0; i < NUMMEMTESTS; i++) {
2468                                 for (j = 0; j < NUMMEMWORDS; j++) {
2469                                         membase[j] = test[i][j];
2470                                         ppcDcbf((u32)&(membase[j]));
2471                                 }
2472                                 sync();
2473                                 for (l=0; l<NUMLOOPS; l++) {
2474                                         for (j = 0; j < NUMMEMWORDS; j++) {
2475                                                 if (membase[j] != test[i][j]) {
2476                                                         ppcDcbf((u32)&(membase[j]));
2477                                                         return 0;
2478                                                 }
2479                                                 ppcDcbf((u32)&(membase[j]));
2480                                         }
2481                                         sync();
2482                                 }
2483                         }
2484                 }       /* if bank enabled */
2485         }               /* for bxcf_num */
2486
2487         return 1;
2488 }
2489
2490 #ifndef HARD_CODED_DQS
2491 /*-----------------------------------------------------------------------------+
2492  * DQS_calibration_process.
2493  *-----------------------------------------------------------------------------*/
2494 static void DQS_calibration_process(void)
2495 {
2496         unsigned long rfdc_reg;
2497         unsigned long rffd;
2498         unsigned long val;
2499         long rffd_average;
2500         long max_start;
2501         long min_end;
2502         unsigned long begin_rqfd[MAXRANKS];
2503         unsigned long begin_rffd[MAXRANKS];
2504         unsigned long end_rqfd[MAXRANKS];
2505         unsigned long end_rffd[MAXRANKS];
2506         char window_found;
2507         unsigned long dlycal;
2508         unsigned long dly_val;
2509         unsigned long max_pass_length;
2510         unsigned long current_pass_length;
2511         unsigned long current_fail_length;
2512         unsigned long current_start;
2513         long max_end;
2514         unsigned char fail_found;
2515         unsigned char pass_found;
2516 #if !defined(CONFIG_DDR_RQDC_FIXED)
2517         u32 rqdc_reg;
2518         u32 rqfd;
2519         u32 rqfd_start;
2520         u32 rqfd_average;
2521         int loopi = 0;
2522         char str[] = "Auto calibration -";
2523         char slash[] = "\\|/-\\|/-";
2524
2525         /*------------------------------------------------------------------
2526          * Test to determine the best read clock delay tuning bits.
2527          *
2528          * Before the DDR controller can be used, the read clock delay needs to be
2529          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2530          * This value cannot be hardcoded into the program because it changes
2531          * depending on the board's setup and environment.
2532          * To do this, all delay values are tested to see if they
2533          * work or not.  By doing this, you get groups of fails with groups of
2534          * passing values.  The idea is to find the start and end of a passing
2535          * window and take the center of it to use as the read clock delay.
2536          *
2537          * A failure has to be seen first so that when we hit a pass, we know
2538          * that it is truely the start of the window.  If we get passing values
2539          * to start off with, we don't know if we are at the start of the window.
2540          *
2541          * The code assumes that a failure will always be found.
2542          * If a failure is not found, there is no easy way to get the middle
2543          * of the passing window.  I guess we can pretty much pick any value
2544          * but some values will be better than others.  Since the lowest speed
2545          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2546          * from experimentation it is safe to say you will always have a failure.
2547          *-----------------------------------------------------------------*/
2548
2549         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2550         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2551
2552         puts(str);
2553
2554 calibration_loop:
2555         mfsdram(SDRAM_RQDC, rqdc_reg);
2556         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2557                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2558 #else /* CONFIG_DDR_RQDC_FIXED */
2559         /*
2560          * On Katmai the complete auto-calibration somehow doesn't seem to
2561          * produce the best results, meaning optimal values for RQFD/RFFD.
2562          * This was discovered by GDA using a high bandwidth scope,
2563          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2564          * so now on Katmai "only" RFFD is auto-calibrated.
2565          */
2566         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2567 #endif /* CONFIG_DDR_RQDC_FIXED */
2568
2569         max_start = 0;
2570         min_end = 0;
2571         begin_rqfd[0] = 0;
2572         begin_rffd[0] = 0;
2573         begin_rqfd[1] = 0;
2574         begin_rffd[1] = 0;
2575         end_rqfd[0] = 0;
2576         end_rffd[0] = 0;
2577         end_rqfd[1] = 0;
2578         end_rffd[1] = 0;
2579         window_found = FALSE;
2580
2581         max_pass_length = 0;
2582         max_start = 0;
2583         max_end = 0;
2584         current_pass_length = 0;
2585         current_fail_length = 0;
2586         current_start = 0;
2587         window_found = FALSE;
2588         fail_found = FALSE;
2589         pass_found = FALSE;
2590
2591         /*
2592          * get the delay line calibration register value
2593          */
2594         mfsdram(SDRAM_DLCR, dlycal);
2595         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2596
2597         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2598                 mfsdram(SDRAM_RFDC, rfdc_reg);
2599                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2600
2601                 /*------------------------------------------------------------------
2602                  * Set the timing reg for the test.
2603                  *-----------------------------------------------------------------*/
2604                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2605
2606                 /*------------------------------------------------------------------
2607                  * See if the rffd value passed.
2608                  *-----------------------------------------------------------------*/
2609                 if (short_mem_test()) {
2610                         if (fail_found == TRUE) {
2611                                 pass_found = TRUE;
2612                                 if (current_pass_length == 0)
2613                                         current_start = rffd;
2614
2615                                 current_fail_length = 0;
2616                                 current_pass_length++;
2617
2618                                 if (current_pass_length > max_pass_length) {
2619                                         max_pass_length = current_pass_length;
2620                                         max_start = current_start;
2621                                         max_end = rffd;
2622                                 }
2623                         }
2624                 } else {
2625                         current_pass_length = 0;
2626                         current_fail_length++;
2627
2628                         if (current_fail_length >= (dly_val >> 2)) {
2629                                 if (fail_found == FALSE) {
2630                                         fail_found = TRUE;
2631                                 } else if (pass_found == TRUE) {
2632                                         window_found = TRUE;
2633                                         break;
2634                                 }
2635                         }
2636                 }
2637         }               /* for rffd */
2638
2639         /*------------------------------------------------------------------
2640          * Set the average RFFD value
2641          *-----------------------------------------------------------------*/
2642         rffd_average = ((max_start + max_end) >> 1);
2643
2644         if (rffd_average < 0)
2645                 rffd_average = 0;
2646
2647         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2648                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2649         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2650         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2651
2652 #if !defined(CONFIG_DDR_RQDC_FIXED)
2653         max_pass_length = 0;
2654         max_start = 0;
2655         max_end = 0;
2656         current_pass_length = 0;
2657         current_fail_length = 0;
2658         current_start = 0;
2659         window_found = FALSE;
2660         fail_found = FALSE;
2661         pass_found = FALSE;
2662
2663         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2664                 mfsdram(SDRAM_RQDC, rqdc_reg);
2665                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2666
2667                 /*------------------------------------------------------------------
2668                  * Set the timing reg for the test.
2669                  *-----------------------------------------------------------------*/
2670                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2671
2672                 /*------------------------------------------------------------------
2673                  * See if the rffd value passed.
2674                  *-----------------------------------------------------------------*/
2675                 if (short_mem_test()) {
2676                         if (fail_found == TRUE) {
2677                                 pass_found = TRUE;
2678                                 if (current_pass_length == 0)
2679                                         current_start = rqfd;
2680
2681                                 current_fail_length = 0;
2682                                 current_pass_length++;
2683
2684                                 if (current_pass_length > max_pass_length) {
2685                                         max_pass_length = current_pass_length;
2686                                         max_start = current_start;
2687                                         max_end = rqfd;
2688                                 }
2689                         }
2690                 } else {
2691                         current_pass_length = 0;
2692                         current_fail_length++;
2693
2694                         if (fail_found == FALSE) {
2695                                 fail_found = TRUE;
2696                         } else if (pass_found == TRUE) {
2697                                 window_found = TRUE;
2698                                 break;
2699                         }
2700                 }
2701         }
2702
2703         rqfd_average = ((max_start + max_end) >> 1);
2704
2705         /*------------------------------------------------------------------
2706          * Make sure we found the valid read passing window.  Halt if not
2707          *-----------------------------------------------------------------*/
2708         if (window_found == FALSE) {
2709                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2710                         putc('\b');
2711                         putc(slash[loopi++ % 8]);
2712
2713                         /* try again from with a different RQFD start value */
2714                         rqfd_start++;
2715                         goto calibration_loop;
2716                 }
2717
2718                 printf("\nERROR: Cannot determine a common read delay for the "
2719                        "DIMM(s) installed.\n");
2720                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2721                 ppc440sp_sdram_register_dump();
2722                 spd_ddr_init_hang ();
2723         }
2724
2725         if (rqfd_average < 0)
2726                 rqfd_average = 0;
2727
2728         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2729                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2730
2731         mtsdram(SDRAM_RQDC,
2732                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2733                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2734
2735         blank_string(strlen(str));
2736 #endif /* CONFIG_DDR_RQDC_FIXED */
2737
2738         /*
2739          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2740          * PowerPC440SP/SPe DDR2 application note:
2741          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2742          */
2743         mfsdram(SDRAM_RTSR, val);
2744         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2745                 mfsdram(SDRAM_RDCC, val);
2746                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2747                         val += 0x40000000;
2748                         mtsdram(SDRAM_RDCC, val);
2749                 }
2750         }
2751
2752         mfsdram(SDRAM_DLCR, val);
2753         debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2754         mfsdram(SDRAM_RQDC, val);
2755         debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2756         mfsdram(SDRAM_RFDC, val);
2757         debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2758         mfsdram(SDRAM_RDCC, val);
2759         debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2760 }
2761 #else /* calibration test with hardvalues */
2762 /*-----------------------------------------------------------------------------+
2763  * DQS_calibration_process.
2764  *-----------------------------------------------------------------------------*/
2765 static void test(void)
2766 {
2767         unsigned long dimm_num;
2768         unsigned long ecc_temp;
2769         unsigned long i, j;
2770         unsigned long *membase;
2771         unsigned long bxcf[MAXRANKS];
2772         unsigned long val;
2773         char window_found;
2774         char begin_found[MAXDIMMS];
2775         char end_found[MAXDIMMS];
2776         char search_end[MAXDIMMS];
2777         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2778                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2779                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2780                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2781                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2782                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2783                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2784                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2785                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2786                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2787                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2788                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2789                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2790                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2791                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2792                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2793                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2794
2795         /*------------------------------------------------------------------
2796          * Test to determine the best read clock delay tuning bits.
2797          *
2798          * Before the DDR controller can be used, the read clock delay needs to be
2799          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2800          * This value cannot be hardcoded into the program because it changes
2801          * depending on the board's setup and environment.
2802          * To do this, all delay values are tested to see if they
2803          * work or not.  By doing this, you get groups of fails with groups of
2804          * passing values.  The idea is to find the start and end of a passing
2805          * window and take the center of it to use as the read clock delay.
2806          *
2807          * A failure has to be seen first so that when we hit a pass, we know
2808          * that it is truely the start of the window.  If we get passing values
2809          * to start off with, we don't know if we are at the start of the window.
2810          *
2811          * The code assumes that a failure will always be found.
2812          * If a failure is not found, there is no easy way to get the middle
2813          * of the passing window.  I guess we can pretty much pick any value
2814          * but some values will be better than others.  Since the lowest speed
2815          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2816          * from experimentation it is safe to say you will always have a failure.
2817          *-----------------------------------------------------------------*/
2818         mfsdram(SDRAM_MCOPT1, ecc_temp);
2819         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2820         mfsdram(SDRAM_MCOPT1, val);
2821         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2822                 SDRAM_MCOPT1_MCHK_NON);
2823
2824         window_found = FALSE;
2825         begin_found[0] = FALSE;
2826         end_found[0] = FALSE;
2827         search_end[0] = FALSE;
2828         begin_found[1] = FALSE;
2829         end_found[1] = FALSE;
2830         search_end[1] = FALSE;
2831
2832         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2833                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2834
2835                 /* Banks enabled */
2836                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2837
2838                         /* Bank is enabled */
2839                         membase =
2840                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2841
2842                         /*------------------------------------------------------------------
2843                          * Run the short memory test.
2844                          *-----------------------------------------------------------------*/
2845                         for (i = 0; i < NUMMEMTESTS; i++) {
2846                                 for (j = 0; j < NUMMEMWORDS; j++) {
2847                                         membase[j] = test[i][j];
2848                                         ppcDcbf((u32)&(membase[j]));
2849                                 }
2850                                 sync();
2851                                 for (j = 0; j < NUMMEMWORDS; j++) {
2852                                         if (membase[j] != test[i][j]) {
2853                                                 ppcDcbf((u32)&(membase[j]));
2854                                                 break;
2855                                         }
2856                                         ppcDcbf((u32)&(membase[j]));
2857                                 }
2858                                 sync();
2859                                 if (j < NUMMEMWORDS)
2860                                         break;
2861                         }
2862
2863                         /*------------------------------------------------------------------
2864                          * See if the rffd value passed.
2865                          *-----------------------------------------------------------------*/
2866                         if (i < NUMMEMTESTS) {
2867                                 if ((end_found[dimm_num] == FALSE) &&
2868                                     (search_end[dimm_num] == TRUE)) {
2869                                         end_found[dimm_num] = TRUE;
2870                                 }
2871                                 if ((end_found[0] == TRUE) &&
2872                                     (end_found[1] == TRUE))
2873                                         break;
2874                         } else {
2875                                 if (begin_found[dimm_num] == FALSE) {
2876                                         begin_found[dimm_num] = TRUE;
2877                                         search_end[dimm_num] = TRUE;
2878                                 }
2879                         }
2880                 } else {
2881                         begin_found[dimm_num] = TRUE;
2882                         end_found[dimm_num] = TRUE;
2883                 }
2884         }
2885
2886         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2887                 window_found = TRUE;
2888
2889         /*------------------------------------------------------------------
2890          * Make sure we found the valid read passing window.  Halt if not
2891          *-----------------------------------------------------------------*/
2892         if (window_found == FALSE) {
2893                 printf("ERROR: Cannot determine a common read delay for the "
2894                        "DIMM(s) installed.\n");
2895                 spd_ddr_init_hang ();
2896         }
2897
2898         /*------------------------------------------------------------------
2899          * Restore the ECC variable to what it originally was
2900          *-----------------------------------------------------------------*/
2901         mtsdram(SDRAM_MCOPT1,
2902                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2903                 | ecc_temp);
2904 }
2905 #endif
2906
2907 #if defined(DEBUG)
2908 static void ppc440sp_sdram_register_dump(void)
2909 {
2910         unsigned int sdram_reg;
2911         unsigned int sdram_data;
2912         unsigned int dcr_data;
2913
2914         printf("\n  Register Dump:\n");
2915         sdram_reg = SDRAM_MCSTAT;
2916         mfsdram(sdram_reg, sdram_data);
2917         printf("        SDRAM_MCSTAT    = 0x%08X", sdram_data);
2918         sdram_reg = SDRAM_MCOPT1;
2919         mfsdram(sdram_reg, sdram_data);
2920         printf("        SDRAM_MCOPT1    = 0x%08X\n", sdram_data);
2921         sdram_reg = SDRAM_MCOPT2;
2922         mfsdram(sdram_reg, sdram_data);
2923         printf("        SDRAM_MCOPT2    = 0x%08X", sdram_data);
2924         sdram_reg = SDRAM_MODT0;
2925         mfsdram(sdram_reg, sdram_data);
2926         printf("        SDRAM_MODT0     = 0x%08X\n", sdram_data);
2927         sdram_reg = SDRAM_MODT1;
2928         mfsdram(sdram_reg, sdram_data);
2929         printf("        SDRAM_MODT1     = 0x%08X", sdram_data);
2930         sdram_reg = SDRAM_MODT2;
2931         mfsdram(sdram_reg, sdram_data);
2932         printf("        SDRAM_MODT2     = 0x%08X\n", sdram_data);
2933         sdram_reg = SDRAM_MODT3;
2934         mfsdram(sdram_reg, sdram_data);
2935         printf("        SDRAM_MODT3     = 0x%08X", sdram_data);
2936         sdram_reg = SDRAM_CODT;
2937         mfsdram(sdram_reg, sdram_data);
2938         printf("        SDRAM_CODT      = 0x%08X\n", sdram_data);
2939         sdram_reg = SDRAM_VVPR;
2940         mfsdram(sdram_reg, sdram_data);
2941         printf("        SDRAM_VVPR      = 0x%08X", sdram_data);
2942         sdram_reg = SDRAM_OPARS;
2943         mfsdram(sdram_reg, sdram_data);
2944         printf("        SDRAM_OPARS     = 0x%08X\n", sdram_data);
2945         /*
2946          * OPAR2 is only used as a trigger register.
2947          * No data is contained in this register, and reading or writing
2948          * to is can cause bad things to happen (hangs).  Just skip it
2949          * and report NA
2950          * sdram_reg = SDRAM_OPAR2;
2951          * mfsdram(sdram_reg, sdram_data);
2952          * printf("        SDRAM_OPAR2     = 0x%08X\n", sdram_data);
2953          */
2954         printf("        SDRAM_OPART     = N/A       ");
2955         sdram_reg = SDRAM_RTR;
2956         mfsdram(sdram_reg, sdram_data);
2957         printf("        SDRAM_RTR       = 0x%08X\n", sdram_data);
2958         sdram_reg = SDRAM_MB0CF;
2959         mfsdram(sdram_reg, sdram_data);
2960         printf("        SDRAM_MB0CF     = 0x%08X", sdram_data);
2961         sdram_reg = SDRAM_MB1CF;
2962         mfsdram(sdram_reg, sdram_data);
2963         printf("        SDRAM_MB1CF     = 0x%08X\n", sdram_data);
2964         sdram_reg = SDRAM_MB2CF;
2965         mfsdram(sdram_reg, sdram_data);
2966         printf("        SDRAM_MB2CF     = 0x%08X", sdram_data);
2967         sdram_reg = SDRAM_MB3CF;
2968         mfsdram(sdram_reg, sdram_data);
2969         printf("        SDRAM_MB3CF     = 0x%08X\n", sdram_data);
2970         sdram_reg = SDRAM_INITPLR0;
2971         mfsdram(sdram_reg, sdram_data);
2972         printf("        SDRAM_INITPLR0  = 0x%08X", sdram_data);
2973         sdram_reg = SDRAM_INITPLR1;
2974         mfsdram(sdram_reg, sdram_data);
2975         printf("        SDRAM_INITPLR1  = 0x%08X\n", sdram_data);
2976         sdram_reg = SDRAM_INITPLR2;
2977         mfsdram(sdram_reg, sdram_data);
2978         printf("        SDRAM_INITPLR2  = 0x%08X", sdram_data);
2979         sdram_reg = SDRAM_INITPLR3;
2980         mfsdram(sdram_reg, sdram_data);
2981         printf("        SDRAM_INITPLR3  = 0x%08X\n", sdram_data);
2982         sdram_reg = SDRAM_INITPLR4;
2983         mfsdram(sdram_reg, sdram_data);
2984         printf("        SDRAM_INITPLR4  = 0x%08X", sdram_data);
2985         sdram_reg = SDRAM_INITPLR5;
2986         mfsdram(sdram_reg, sdram_data);
2987         printf("        SDRAM_INITPLR5  = 0x%08X\n", sdram_data);
2988         sdram_reg = SDRAM_INITPLR6;
2989         mfsdram(sdram_reg, sdram_data);
2990         printf("        SDRAM_INITPLR6  = 0x%08X", sdram_data);
2991         sdram_reg = SDRAM_INITPLR7;
2992         mfsdram(sdram_reg, sdram_data);
2993         printf("        SDRAM_INITPLR7  = 0x%08X\n", sdram_data);
2994         sdram_reg = SDRAM_INITPLR8;
2995         mfsdram(sdram_reg, sdram_data);
2996         printf("        SDRAM_INITPLR8  = 0x%08X", sdram_data);
2997         sdram_reg = SDRAM_INITPLR9;
2998         mfsdram(sdram_reg, sdram_data);
2999         printf("        SDRAM_INITPLR9  = 0x%08X\n", sdram_data);
3000         sdram_reg = SDRAM_INITPLR10;
3001         mfsdram(sdram_reg, sdram_data);
3002         printf("        SDRAM_INITPLR10 = 0x%08X", sdram_data);
3003         sdram_reg = SDRAM_INITPLR11;
3004         mfsdram(sdram_reg, sdram_data);
3005         printf("        SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
3006         sdram_reg = SDRAM_INITPLR12;
3007         mfsdram(sdram_reg, sdram_data);
3008         printf("        SDRAM_INITPLR12 = 0x%08X", sdram_data);
3009         sdram_reg = SDRAM_INITPLR13;
3010         mfsdram(sdram_reg, sdram_data);
3011         printf("        SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
3012         sdram_reg = SDRAM_INITPLR14;
3013         mfsdram(sdram_reg, sdram_data);
3014         printf("        SDRAM_INITPLR14 = 0x%08X", sdram_data);
3015         sdram_reg = SDRAM_INITPLR15;
3016         mfsdram(sdram_reg, sdram_data);
3017         printf("        SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
3018         sdram_reg = SDRAM_RQDC;
3019         mfsdram(sdram_reg, sdram_data);
3020         printf("        SDRAM_RQDC      = 0x%08X", sdram_data);
3021         sdram_reg = SDRAM_RFDC;
3022         mfsdram(sdram_reg, sdram_data);
3023         printf("        SDRAM_RFDC      = 0x%08X\n", sdram_data);
3024         sdram_reg = SDRAM_RDCC;
3025         mfsdram(sdram_reg, sdram_data);
3026         printf("        SDRAM_RDCC      = 0x%08X", sdram_data);
3027         sdram_reg = SDRAM_DLCR;
3028         mfsdram(sdram_reg, sdram_data);
3029         printf("        SDRAM_DLCR      = 0x%08X\n", sdram_data);
3030         sdram_reg = SDRAM_CLKTR;
3031         mfsdram(sdram_reg, sdram_data);
3032         printf("        SDRAM_CLKTR     = 0x%08X", sdram_data);
3033         sdram_reg = SDRAM_WRDTR;
3034         mfsdram(sdram_reg, sdram_data);
3035         printf("        SDRAM_WRDTR     = 0x%08X\n", sdram_data);
3036         sdram_reg = SDRAM_SDTR1;
3037         mfsdram(sdram_reg, sdram_data);
3038         printf("        SDRAM_SDTR1     = 0x%08X", sdram_data);
3039         sdram_reg = SDRAM_SDTR2;
3040         mfsdram(sdram_reg, sdram_data);
3041         printf("        SDRAM_SDTR2     = 0x%08X\n", sdram_data);
3042         sdram_reg = SDRAM_SDTR3;
3043         mfsdram(sdram_reg, sdram_data);
3044         printf("        SDRAM_SDTR3     = 0x%08X", sdram_data);
3045         sdram_reg = SDRAM_MMODE;
3046         mfsdram(sdram_reg, sdram_data);
3047         printf("        SDRAM_MMODE     = 0x%08X\n", sdram_data);
3048         sdram_reg = SDRAM_MEMODE;
3049         mfsdram(sdram_reg, sdram_data);
3050         printf("        SDRAM_MEMODE    = 0x%08X", sdram_data);
3051         sdram_reg = SDRAM_ECCCR;
3052         mfsdram(sdram_reg, sdram_data);
3053         printf("        SDRAM_ECCCR     = 0x%08X\n\n", sdram_data);
3054
3055         dcr_data = mfdcr(SDRAM_R0BAS);
3056         printf("        MQ0_B0BAS       = 0x%08X", dcr_data);
3057         dcr_data = mfdcr(SDRAM_R1BAS);
3058         printf("        MQ1_B0BAS       = 0x%08X\n", dcr_data);
3059         dcr_data = mfdcr(SDRAM_R2BAS);
3060         printf("        MQ2_B0BAS       = 0x%08X", dcr_data);
3061         dcr_data = mfdcr(SDRAM_R3BAS);
3062         printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
3063 }
3064 #else
3065 static void ppc440sp_sdram_register_dump(void)
3066 {
3067 }
3068 #endif
3069 #endif /* CONFIG_SPD_EEPROM */