cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX(r)
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * Copyright (c) 2008 Nuovation System Designs, LLC
  10  *   Grant Erickson <gerickson@nuovations.com>
  11
  12  * (C) Copyright 2007-2008
  13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14  *
  15  * COPYRIGHT   AMCC   CORPORATION 2004
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  *
  35  */
  36
  37 /* define DEBUG for debugging output (obviously ;-)) */
  38 #if 0
  39 #define DEBUG
  40 #endif
  41
  42 #include <common.h>
  43 #include <command.h>
  44 #include <ppc4xx.h>
  45 #include <i2c.h>
  46 #include <asm/io.h>
  47 #include <asm/processor.h>
  48 #include <asm/mmu.h>
  49 #include <asm/cache.h>
  50
  51 #include "ecc.h"
  52
  53 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
  54
  55 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                         \
  56         do {                                                            \
  57                 u32 data;                                               \
  58                 mfsdram(SDRAM_##mnemonic, data);                        \
  59                 printf("%20s[%02x] = 0x%08X\n",                         \
  60                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  61         } while (0)
  62
  63 static inline void ppc4xx_ibm_ddr2_register_dump(void);
  64
  65 #if defined(CONFIG_SPD_EEPROM)
  66
  67 /*-----------------------------------------------------------------------------+
  68  * Defines
  69  *-----------------------------------------------------------------------------*/
  70 #ifndef TRUE
  71 #define TRUE            1
  72 #endif
  73 #ifndef FALSE
  74 #define FALSE           0
  75 #endif
  76
  77 #define SDRAM_DDR1      1
  78 #define SDRAM_DDR2      2
  79 #define SDRAM_NONE      0
  80
  81 #define MAXDIMMS        2
  82 #define MAXRANKS        4
  83 #define MAXBXCF         4
  84 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
  85
  86 #define ONE_BILLION     1000000000
  87
  88 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  89
  90 #define CMD_NOP         (7 << 19)
  91 #define CMD_PRECHARGE   (2 << 19)
  92 #define CMD_REFRESH     (1 << 19)
  93 #define CMD_EMR         (0 << 19)
  94 #define CMD_READ        (5 << 19)
  95 #define CMD_WRITE       (4 << 19)
  96
  97 #define SELECT_MR       (0 << 16)
  98 #define SELECT_EMR      (1 << 16)
  99 #define SELECT_EMR2     (2 << 16)
 100 #define SELECT_EMR3     (3 << 16)
 101
 102 /* MR */
 103 #define DLL_RESET       0x00000100
 104
 105 #define WRITE_RECOV_2   (1 << 9)
 106 #define WRITE_RECOV_3   (2 << 9)
 107 #define WRITE_RECOV_4   (3 << 9)
 108 #define WRITE_RECOV_5   (4 << 9)
 109 #define WRITE_RECOV_6   (5 << 9)
 110
 111 #define BURST_LEN_4     0x00000002
 112
 113 /* EMR */
 114 #define ODT_0_OHM       0x00000000
 115 #define ODT_50_OHM      0x00000044
 116 #define ODT_75_OHM      0x00000004
 117 #define ODT_150_OHM     0x00000040
 118
 119 #define ODS_FULL        0x00000000
 120 #define ODS_REDUCED     0x00000002
 121 #define OCD_CALIB_DEF   0x00000380
 122
 123 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 124 #define ODT_EB0R        (0x80000000 >> 8)
 125 #define ODT_EB0W        (0x80000000 >> 7)
 126 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 127 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 128 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 129
 130 /* Defines for the Read Cycle Delay test */
 131 #define NUMMEMTESTS     8
 132 #define NUMMEMWORDS     8
 133 #define NUMLOOPS        64              /* memory test loops */
 134
 135 /*
 136  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
 137  * region. Right now the cache should still be disabled in U-Boot because of the
 138  * EMAC driver, that need it's buffer descriptor to be located in non cached
 139  * memory.
 140  *
 141  * If at some time this restriction doesn't apply anymore, just define
 142  * CONFIG_4xx_DCACHE in the board config file and this code should setup
 143  * everything correctly.
 144  */
 145 #ifdef CONFIG_4xx_DCACHE
 146 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
 147 #else
 148 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 149 #endif
 150
 151 /*
 152  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
 153  * To support such configurations, we "only" map the first 2GB via the TLB's. We
 154  * need some free virtual address space for the remaining peripherals like, SoC
 155  * devices, FLASH etc.
 156  *
 157  * Note that ECC is currently not supported on configurations with more than 2GB
 158  * SDRAM. This is because we only map the first 2GB on such systems, and therefore
 159  * the ECC parity byte of the remaining area can't be written.
 160  */
 161 #ifndef CONFIG_MAX_MEM_MAPPED
 162 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)2 << 30)
 163 #endif
 164
 165 /*
 166  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 167  */
 168 void __spd_ddr_init_hang (void)
 169 {
 170         hang ();
 171 }
 172 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 173
 174 /*
 175  * To provide an interface for board specific config values in this common
 176  * DDR setup code, we implement he "weak" default functions here. They return
 177  * the default value back to the caller.
 178  *
 179  * Please see include/configs/yucca.h for an example fora board specific
 180  * implementation.
 181  */
 182 u32 __ddr_wrdtr(u32 default_val)
 183 {
 184         return default_val;
 185 }
 186 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 187
 188 u32 __ddr_clktr(u32 default_val)
 189 {
 190         return default_val;
 191 }
 192 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 193
 194
 195 /* Private Structure Definitions */
 196
 197 /* enum only to ease code for cas latency setting */
 198 typedef enum ddr_cas_id {
 199         DDR_CAS_2      = 20,
 200         DDR_CAS_2_5    = 25,
 201         DDR_CAS_3      = 30,
 202         DDR_CAS_4      = 40,
 203         DDR_CAS_5      = 50
 204 } ddr_cas_id_t;
 205
 206 /*-----------------------------------------------------------------------------+
 207  * Prototypes
 208  *-----------------------------------------------------------------------------*/
 209 static phys_size_t sdram_memsize(void);
 210 static void get_spd_info(unsigned long *dimm_populated,
 211                          unsigned char *iic0_dimm_addr,
 212                          unsigned long num_dimm_banks);
 213 static void check_mem_type(unsigned long *dimm_populated,
 214                            unsigned char *iic0_dimm_addr,
 215                            unsigned long num_dimm_banks);
 216 static void check_frequency(unsigned long *dimm_populated,
 217                             unsigned char *iic0_dimm_addr,
 218                             unsigned long num_dimm_banks);
 219 static void check_rank_number(unsigned long *dimm_populated,
 220                               unsigned char *iic0_dimm_addr,
 221                               unsigned long num_dimm_banks);
 222 static void check_voltage_type(unsigned long *dimm_populated,
 223                                unsigned char *iic0_dimm_addr,
 224                                unsigned long num_dimm_banks);
 225 static void program_memory_queue(unsigned long *dimm_populated,
 226                                  unsigned char *iic0_dimm_addr,
 227                                  unsigned long num_dimm_banks);
 228 static void program_codt(unsigned long *dimm_populated,
 229                          unsigned char *iic0_dimm_addr,
 230                          unsigned long num_dimm_banks);
 231 static void program_mode(unsigned long *dimm_populated,
 232                          unsigned char *iic0_dimm_addr,
 233                          unsigned long num_dimm_banks,
 234                          ddr_cas_id_t *selected_cas,
 235                          int *write_recovery);
 236 static void program_tr(unsigned long *dimm_populated,
 237                        unsigned char *iic0_dimm_addr,
 238                        unsigned long num_dimm_banks);
 239 static void program_rtr(unsigned long *dimm_populated,
 240                         unsigned char *iic0_dimm_addr,
 241                         unsigned long num_dimm_banks);
 242 static void program_bxcf(unsigned long *dimm_populated,
 243                          unsigned char *iic0_dimm_addr,
 244                          unsigned long num_dimm_banks);
 245 static void program_copt1(unsigned long *dimm_populated,
 246                           unsigned char *iic0_dimm_addr,
 247                           unsigned long num_dimm_banks);
 248 static void program_initplr(unsigned long *dimm_populated,
 249                             unsigned char *iic0_dimm_addr,
 250                             unsigned long num_dimm_banks,
 251                             ddr_cas_id_t selected_cas,
 252                             int write_recovery);
 253 static unsigned long is_ecc_enabled(void);
 254 #ifdef CONFIG_DDR_ECC
 255 static void program_ecc(unsigned long *dimm_populated,
 256                         unsigned char *iic0_dimm_addr,
 257                         unsigned long num_dimm_banks,
 258                         unsigned long tlb_word2_i_value);
 259 static void program_ecc_addr(unsigned long start_address,
 260                              unsigned long num_bytes,
 261                              unsigned long tlb_word2_i_value);
 262 #endif
 263 static void program_DQS_calibration(unsigned long *dimm_populated,
 264                                     unsigned char *iic0_dimm_addr,
 265                                     unsigned long num_dimm_banks);
 266 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 267 static void     test(void);
 268 #else
 269 static void     DQS_calibration_process(void);
 270 #endif
 271 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 272 void dcbz_area(u32 start_address, u32 num_bytes);
 273
 274 static u32 mfdcr_any(u32 dcr)
 275 {
 276         u32 val;
 277
 278         switch (dcr) {
 279         case SDRAM_R0BAS + 0:
 280                 val = mfdcr(SDRAM_R0BAS + 0);
 281                 break;
 282         case SDRAM_R0BAS + 1:
 283                 val = mfdcr(SDRAM_R0BAS + 1);
 284                 break;
 285         case SDRAM_R0BAS + 2:
 286                 val = mfdcr(SDRAM_R0BAS + 2);
 287                 break;
 288         case SDRAM_R0BAS + 3:
 289                 val = mfdcr(SDRAM_R0BAS + 3);
 290                 break;
 291         default:
 292                 printf("DCR %d not defined in case statement!!!\n", dcr);
 293                 val = 0; /* just to satisfy the compiler */
 294         }
 295
 296         return val;
 297 }
 298
 299 static void mtdcr_any(u32 dcr, u32 val)
 300 {
 301         switch (dcr) {
 302         case SDRAM_R0BAS + 0:
 303                 mtdcr(SDRAM_R0BAS + 0, val);
 304                 break;
 305         case SDRAM_R0BAS + 1:
 306                 mtdcr(SDRAM_R0BAS + 1, val);
 307                 break;
 308         case SDRAM_R0BAS + 2:
 309                 mtdcr(SDRAM_R0BAS + 2, val);
 310                 break;
 311         case SDRAM_R0BAS + 3:
 312                 mtdcr(SDRAM_R0BAS + 3, val);
 313                 break;
 314         default:
 315                 printf("DCR %d not defined in case statement!!!\n", dcr);
 316         }
 317 }
 318
 319 static unsigned char spd_read(uchar chip, uint addr)
 320 {
 321         unsigned char data[2];
 322
 323         if (i2c_probe(chip) == 0)
 324                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 325                         return data[0];
 326
 327         return 0;
 328 }
 329
 330 /*-----------------------------------------------------------------------------+
 331  * sdram_memsize
 332  *-----------------------------------------------------------------------------*/
 333 static phys_size_t sdram_memsize(void)
 334 {
 335         phys_size_t mem_size;
 336         unsigned long mcopt2;
 337         unsigned long mcstat;
 338         unsigned long mb0cf;
 339         unsigned long sdsz;
 340         unsigned long i;
 341
 342         mem_size = 0;
 343
 344         mfsdram(SDRAM_MCOPT2, mcopt2);
 345         mfsdram(SDRAM_MCSTAT, mcstat);
 346
 347         /* DDR controller must be enabled and not in self-refresh. */
 348         /* Otherwise memsize is zero. */
 349         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 350             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 351             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 352                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 353                 for (i = 0; i < MAXBXCF; i++) {
 354                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 355                         /* Banks enabled */
 356                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 357                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 358
 359                                 switch(sdsz) {
 360                                 case SDRAM_RXBAS_SDSZ_8:
 361                                         mem_size+=8;
 362                                         break;
 363                                 case SDRAM_RXBAS_SDSZ_16:
 364                                         mem_size+=16;
 365                                         break;
 366                                 case SDRAM_RXBAS_SDSZ_32:
 367                                         mem_size+=32;
 368                                         break;
 369                                 case SDRAM_RXBAS_SDSZ_64:
 370                                         mem_size+=64;
 371                                         break;
 372                                 case SDRAM_RXBAS_SDSZ_128:
 373                                         mem_size+=128;
 374                                         break;
 375                                 case SDRAM_RXBAS_SDSZ_256:
 376                                         mem_size+=256;
 377                                         break;
 378                                 case SDRAM_RXBAS_SDSZ_512:
 379                                         mem_size+=512;
 380                                         break;
 381                                 case SDRAM_RXBAS_SDSZ_1024:
 382                                         mem_size+=1024;
 383                                         break;
 384                                 case SDRAM_RXBAS_SDSZ_2048:
 385                                         mem_size+=2048;
 386                                         break;
 387                                 case SDRAM_RXBAS_SDSZ_4096:
 388                                         mem_size+=4096;
 389                                         break;
 390                                 default:
 391                                         printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
 392                                                , sdsz);
 393                                         mem_size=0;
 394                                         break;
 395                                 }
 396                         }
 397                 }
 398         }
 399
 400         return mem_size << 20;
 401 }
 402
 403 /*-----------------------------------------------------------------------------+
 404  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 405  * Note: This routine runs from flash with a stack set up in the chip's
 406  * sram space.  It is important that the routine does not require .sbss, .bss or
 407  * .data sections.  It also cannot call routines that require these sections.
 408  *-----------------------------------------------------------------------------*/
 409 /*-----------------------------------------------------------------------------
 410  * Function:     initdram
 411  * Description:  Configures SDRAM memory banks for DDR operation.
 412  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 413  *               via the IIC bus and then configures the DDR SDRAM memory
 414  *               banks appropriately. If Auto Memory Configuration is
 415  *               not used, it is assumed that no DIMM is plugged
 416  *-----------------------------------------------------------------------------*/
 417 phys_size_t initdram(int board_type)
 418 {
 419         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 420         unsigned char spd0[MAX_SPD_BYTES];
 421         unsigned char spd1[MAX_SPD_BYTES];
 422         unsigned char *dimm_spd[MAXDIMMS];
 423         unsigned long dimm_populated[MAXDIMMS];
 424         unsigned long num_dimm_banks;           /* on board dimm banks */
 425         unsigned long val;
 426         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 427         int write_recovery;
 428         phys_size_t dram_size = 0;
 429
 430         num_dimm_banks = sizeof(iic0_dimm_addr);
 431
 432         /*------------------------------------------------------------------
 433          * Set up an array of SPD matrixes.
 434          *-----------------------------------------------------------------*/
 435         dimm_spd[0] = spd0;
 436         dimm_spd[1] = spd1;
 437
 438         /*------------------------------------------------------------------
 439          * Reset the DDR-SDRAM controller.
 440          *-----------------------------------------------------------------*/
 441         mtsdr(SDR0_SRST, (0x80000000 >> 10));
 442         mtsdr(SDR0_SRST, 0x00000000);
 443
 444         /*
 445          * Make sure I2C controller is initialized
 446          * before continuing.
 447          */
 448
 449         /* switch to correct I2C bus */
 450         I2C_SET_BUS(CFG_SPD_BUS_NUM);
 451         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 452
 453         /*------------------------------------------------------------------
 454          * Clear out the serial presence detect buffers.
 455          * Perform IIC reads from the dimm.  Fill in the spds.
 456          * Check to see if the dimm slots are populated
 457          *-----------------------------------------------------------------*/
 458         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 459
 460         /*------------------------------------------------------------------
 461          * Check the memory type for the dimms plugged.
 462          *-----------------------------------------------------------------*/
 463         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 464
 465         /*------------------------------------------------------------------
 466          * Check the frequency supported for the dimms plugged.
 467          *-----------------------------------------------------------------*/
 468         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 469
 470         /*------------------------------------------------------------------
 471          * Check the total rank number.
 472          *-----------------------------------------------------------------*/
 473         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 474
 475         /*------------------------------------------------------------------
 476          * Check the voltage type for the dimms plugged.
 477          *-----------------------------------------------------------------*/
 478         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 479
 480         /*------------------------------------------------------------------
 481          * Program SDRAM controller options 2 register
 482          * Except Enabling of the memory controller.
 483          *-----------------------------------------------------------------*/
 484         mfsdram(SDRAM_MCOPT2, val);
 485         mtsdram(SDRAM_MCOPT2,
 486                 (val &
 487                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 488                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 489                    SDRAM_MCOPT2_ISIE_MASK))
 490                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 491                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 492                    SDRAM_MCOPT2_ISIE_ENABLE));
 493
 494         /*------------------------------------------------------------------
 495          * Program SDRAM controller options 1 register
 496          * Note: Does not enable the memory controller.
 497          *-----------------------------------------------------------------*/
 498         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 499
 500         /*------------------------------------------------------------------
 501          * Set the SDRAM Controller On Die Termination Register
 502          *-----------------------------------------------------------------*/
 503         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 504
 505         /*------------------------------------------------------------------
 506          * Program SDRAM refresh register.
 507          *-----------------------------------------------------------------*/
 508         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 509
 510         /*------------------------------------------------------------------
 511          * Program SDRAM mode register.
 512          *-----------------------------------------------------------------*/
 513         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 514                      &selected_cas, &write_recovery);
 515
 516         /*------------------------------------------------------------------
 517          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 518          *-----------------------------------------------------------------*/
 519         mfsdram(SDRAM_WRDTR, val);
 520         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 521                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 522
 523         /*------------------------------------------------------------------
 524          * Set the SDRAM Clock Timing Register
 525          *-----------------------------------------------------------------*/
 526         mfsdram(SDRAM_CLKTR, val);
 527         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 528                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 529
 530         /*------------------------------------------------------------------
 531          * Program the BxCF registers.
 532          *-----------------------------------------------------------------*/
 533         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 534
 535         /*------------------------------------------------------------------
 536          * Program SDRAM timing registers.
 537          *-----------------------------------------------------------------*/
 538         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 539
 540         /*------------------------------------------------------------------
 541          * Set the Extended Mode register
 542          *-----------------------------------------------------------------*/
 543         mfsdram(SDRAM_MEMODE, val);
 544         mtsdram(SDRAM_MEMODE,
 545                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 546                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 547                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 548                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 549
 550         /*------------------------------------------------------------------
 551          * Program Initialization preload registers.
 552          *-----------------------------------------------------------------*/
 553         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 554                         selected_cas, write_recovery);
 555
 556         /*------------------------------------------------------------------
 557          * Delay to ensure 200usec have elapsed since reset.
 558          *-----------------------------------------------------------------*/
 559         udelay(400);
 560
 561         /*------------------------------------------------------------------
 562          * Set the memory queue core base addr.
 563          *-----------------------------------------------------------------*/
 564         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 565
 566         /*------------------------------------------------------------------
 567          * Program SDRAM controller options 2 register
 568          * Enable the memory controller.
 569          *-----------------------------------------------------------------*/
 570         mfsdram(SDRAM_MCOPT2, val);
 571         mtsdram(SDRAM_MCOPT2,
 572                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 573                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 574                          SDRAM_MCOPT2_IPTR_EXECUTE);
 575
 576         /*------------------------------------------------------------------
 577          * Wait for IPTR_EXECUTE init sequence to complete.
 578          *-----------------------------------------------------------------*/
 579         do {
 580                 mfsdram(SDRAM_MCSTAT, val);
 581         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 582
 583         /* enable the controller only after init sequence completes */
 584         mfsdram(SDRAM_MCOPT2, val);
 585         mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
 586
 587         /* Make sure delay-line calibration is done before proceeding */
 588         do {
 589                 mfsdram(SDRAM_DLCR, val);
 590         } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
 591
 592         /* get installed memory size */
 593         dram_size = sdram_memsize();
 594
 595         /*
 596          * Limit size to 2GB
 597          */
 598         if (dram_size > CONFIG_MAX_MEM_MAPPED)
 599                 dram_size = CONFIG_MAX_MEM_MAPPED;
 600
 601         /* and program tlb entries for this size (dynamic) */
 602
 603         /*
 604          * Program TLB entries with caches enabled, for best performace
 605          * while auto-calibrating and ECC generation
 606          */
 607         program_tlb(0, 0, dram_size, 0);
 608
 609         /*------------------------------------------------------------------
 610          * DQS calibration.
 611          *-----------------------------------------------------------------*/
 612         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 613
 614 #ifdef CONFIG_DDR_ECC
 615         /*------------------------------------------------------------------
 616          * If ecc is enabled, initialize the parity bits.
 617          *-----------------------------------------------------------------*/
 618         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 619 #endif
 620
 621         /*
 622          * Now after initialization (auto-calibration and ECC generation)
 623          * remove the TLB entries with caches enabled and program again with
 624          * desired cache functionality
 625          */
 626         remove_tlb(0, dram_size);
 627         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 628
 629         ppc4xx_ibm_ddr2_register_dump();
 630
 631         /*
 632          * Clear potential errors resulting from auto-calibration.
 633          * If not done, then we could get an interrupt later on when
 634          * exceptions are enabled.
 635          */
 636         set_mcsr(get_mcsr());
 637
 638         return sdram_memsize();
 639 }
 640
 641 static void get_spd_info(unsigned long *dimm_populated,
 642                          unsigned char *iic0_dimm_addr,
 643                          unsigned long num_dimm_banks)
 644 {
 645         unsigned long dimm_num;
 646         unsigned long dimm_found;
 647         unsigned char num_of_bytes;
 648         unsigned char total_size;
 649
 650         dimm_found = FALSE;
 651         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 652                 num_of_bytes = 0;
 653                 total_size = 0;
 654
 655                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 656                 debug("\nspd_read(0x%x) returned %d\n",
 657                       iic0_dimm_addr[dimm_num], num_of_bytes);
 658                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 659                 debug("spd_read(0x%x) returned %d\n",
 660                       iic0_dimm_addr[dimm_num], total_size);
 661
 662                 if ((num_of_bytes != 0) && (total_size != 0)) {
 663                         dimm_populated[dimm_num] = TRUE;
 664                         dimm_found = TRUE;
 665                         debug("DIMM slot %lu: populated\n", dimm_num);
 666                 } else {
 667                         dimm_populated[dimm_num] = FALSE;
 668                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 669                 }
 670         }
 671
 672         if (dimm_found == FALSE) {
 673                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 674                 spd_ddr_init_hang ();
 675         }
 676 }
 677
 678 void board_add_ram_info(int use_default)
 679 {
 680         PPC4xx_SYS_INFO board_cfg;
 681         u32 val;
 682
 683         if (is_ecc_enabled())
 684                 puts(" (ECC");
 685         else
 686                 puts(" (ECC not");
 687
 688         get_sys_info(&board_cfg);
 689
 690         mfsdr(SDR0_DDR0, val);
 691         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 692         printf(" enabled, %d MHz", (val * 2) / 1000000);
 693
 694         mfsdram(SDRAM_MMODE, val);
 695         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 696         printf(", CL%d)", val);
 697 }
 698
 699 /*------------------------------------------------------------------
 700  * For the memory DIMMs installed, this routine verifies that they
 701  * really are DDR specific DIMMs.
 702  *-----------------------------------------------------------------*/
 703 static void check_mem_type(unsigned long *dimm_populated,
 704                            unsigned char *iic0_dimm_addr,
 705                            unsigned long num_dimm_banks)
 706 {
 707         unsigned long dimm_num;
 708         unsigned long dimm_type;
 709
 710         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 711                 if (dimm_populated[dimm_num] == TRUE) {
 712                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 713                         switch (dimm_type) {
 714                         case 1:
 715                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 716                                        "slot %d.\n", (unsigned int)dimm_num);
 717                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 718                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 719                                 spd_ddr_init_hang ();
 720                                 break;
 721                         case 2:
 722                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 723                                        (unsigned int)dimm_num);
 724                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 725                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 726                                 spd_ddr_init_hang ();
 727                                 break;
 728                         case 3:
 729                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 730                                        (unsigned int)dimm_num);
 731                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 732                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 733                                 spd_ddr_init_hang ();
 734                                 break;
 735                         case 4:
 736                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 737                                        (unsigned int)dimm_num);
 738                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 739                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 740                                 spd_ddr_init_hang ();
 741                                 break;
 742                         case 5:
 743                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 744                                        (unsigned int)dimm_num);
 745                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 746                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 747                                 spd_ddr_init_hang ();
 748                                 break;
 749                         case 6:
 750                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 751                                        (unsigned int)dimm_num);
 752                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 753                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 754                                 spd_ddr_init_hang ();
 755                                 break;
 756                         case 7:
 757                                 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
 758                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 759                                 break;
 760                         case 8:
 761                                 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
 762                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 763                                 break;
 764                         default:
 765                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 766                                        (unsigned int)dimm_num);
 767                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 768                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 769                                 spd_ddr_init_hang ();
 770                                 break;
 771                         }
 772                 }
 773         }
 774         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 775                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 776                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 777                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 778                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 779                         spd_ddr_init_hang ();
 780                 }
 781         }
 782 }
 783
 784 /*------------------------------------------------------------------
 785  * For the memory DIMMs installed, this routine verifies that
 786  * frequency previously calculated is supported.
 787  *-----------------------------------------------------------------*/
 788 static void check_frequency(unsigned long *dimm_populated,
 789                             unsigned char *iic0_dimm_addr,
 790                             unsigned long num_dimm_banks)
 791 {
 792         unsigned long dimm_num;
 793         unsigned long tcyc_reg;
 794         unsigned long cycle_time;
 795         unsigned long calc_cycle_time;
 796         unsigned long sdram_freq;
 797         unsigned long sdr_ddrpll;
 798         PPC4xx_SYS_INFO board_cfg;
 799
 800         /*------------------------------------------------------------------
 801          * Get the board configuration info.
 802          *-----------------------------------------------------------------*/
 803         get_sys_info(&board_cfg);
 804
 805         mfsdr(SDR0_DDR0, sdr_ddrpll);
 806         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 807
 808         /*
 809          * calc_cycle_time is calculated from DDR frequency set by board/chip
 810          * and is expressed in multiple of 10 picoseconds
 811          * to match the way DIMM cycle time is calculated below.
 812          */
 813         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 814
 815         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 816                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 817                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 818                         /*
 819                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 820                          * the higher order nibble (bits 4-7) designates the cycle time
 821                          * to a granularity of 1ns;
 822                          * the value presented by the lower order nibble (bits 0-3)
 823                          * has a granularity of .1ns and is added to the value designated
 824                          * by the higher nibble. In addition, four lines of the lower order
 825                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 826                          */
 827                          /* Convert from hex to decimal */
 828                         if ((tcyc_reg & 0x0F) == 0x0D)
 829                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 830                         else if ((tcyc_reg & 0x0F) == 0x0C)
 831                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 832                         else if ((tcyc_reg & 0x0F) == 0x0B)
 833                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 834                         else if ((tcyc_reg & 0x0F) == 0x0A)
 835                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 836                         else
 837                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 838                                         ((tcyc_reg & 0x0F)*10);
 839                         debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
 840
 841                         if  (cycle_time > (calc_cycle_time + 10)) {
 842                                 /*
 843                                  * the provided sdram cycle_time is too small
 844                                  * for the available DIMM cycle_time.
 845                                  * The additionnal 100ps is here to accept a small incertainty.
 846                                  */
 847                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 848                                        "slot %d \n while calculated cycle time is %d ps.\n",
 849                                        (unsigned int)(cycle_time*10),
 850                                        (unsigned int)dimm_num,
 851                                        (unsigned int)(calc_cycle_time*10));
 852                                 printf("Replace the DIMM, or change DDR frequency via "
 853                                        "strapping bits.\n\n");
 854                                 spd_ddr_init_hang ();
 855                         }
 856                 }
 857         }
 858 }
 859
 860 /*------------------------------------------------------------------
 861  * For the memory DIMMs installed, this routine verifies two
 862  * ranks/banks maximum are availables.
 863  *-----------------------------------------------------------------*/
 864 static void check_rank_number(unsigned long *dimm_populated,
 865                               unsigned char *iic0_dimm_addr,
 866                               unsigned long num_dimm_banks)
 867 {
 868         unsigned long dimm_num;
 869         unsigned long dimm_rank;
 870         unsigned long total_rank = 0;
 871
 872         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 873                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 874                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 875                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 876                                 dimm_rank = (dimm_rank & 0x0F) +1;
 877                         else
 878                                 dimm_rank = dimm_rank & 0x0F;
 879
 880
 881                         if (dimm_rank > MAXRANKS) {
 882                                 printf("ERROR: DRAM DIMM detected with %lu ranks in "
 883                                        "slot %lu is not supported.\n", dimm_rank, dimm_num);
 884                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 885                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 886                                 spd_ddr_init_hang ();
 887                         } else
 888                                 total_rank += dimm_rank;
 889                 }
 890                 if (total_rank > MAXRANKS) {
 891                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 892                                "for all slots.\n", (unsigned int)total_rank);
 893                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 894                         printf("Remove one of the DIMM modules.\n\n");
 895                         spd_ddr_init_hang ();
 896                 }
 897         }
 898 }
 899
 900 /*------------------------------------------------------------------
 901  * only support 2.5V modules.
 902  * This routine verifies this.
 903  *-----------------------------------------------------------------*/
 904 static void check_voltage_type(unsigned long *dimm_populated,
 905                                unsigned char *iic0_dimm_addr,
 906                                unsigned long num_dimm_banks)
 907 {
 908         unsigned long dimm_num;
 909         unsigned long voltage_type;
 910
 911         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 912                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 913                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 914                         switch (voltage_type) {
 915                         case 0x00:
 916                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 917                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 918                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 919                                        (unsigned int)dimm_num);
 920                                 spd_ddr_init_hang ();
 921                                 break;
 922                         case 0x01:
 923                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 924                                 printf("This DIMM is LVTTL.\n");
 925                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 926                                        (unsigned int)dimm_num);
 927                                 spd_ddr_init_hang ();
 928                                 break;
 929                         case 0x02:
 930                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 931                                 printf("This DIMM is 1.5 Volt.\n");
 932                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 933                                        (unsigned int)dimm_num);
 934                                 spd_ddr_init_hang ();
 935                                 break;
 936                         case 0x03:
 937                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 938                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 939                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 940                                        (unsigned int)dimm_num);
 941                                 spd_ddr_init_hang ();
 942                                 break;
 943                         case 0x04:
 944                                 /* 2.5 Voltage only for DDR1 */
 945                                 break;
 946                         case 0x05:
 947                                 /* 1.8 Voltage only for DDR2 */
 948                                 break;
 949                         default:
 950                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 951                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 952                                        (unsigned int)dimm_num);
 953                                 spd_ddr_init_hang ();
 954                                 break;
 955                         }
 956                 }
 957         }
 958 }
 959
 960 /*-----------------------------------------------------------------------------+
 961  * program_copt1.
 962  *-----------------------------------------------------------------------------*/
 963 static void program_copt1(unsigned long *dimm_populated,
 964                           unsigned char *iic0_dimm_addr,
 965                           unsigned long num_dimm_banks)
 966 {
 967         unsigned long dimm_num;
 968         unsigned long mcopt1;
 969         unsigned long ecc_enabled;
 970         unsigned long ecc = 0;
 971         unsigned long data_width = 0;
 972         unsigned long dimm_32bit;
 973         unsigned long dimm_64bit;
 974         unsigned long registered = 0;
 975         unsigned long attribute = 0;
 976         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 977         unsigned long bankcount;
 978         unsigned long ddrtype;
 979         unsigned long val;
 980
 981 #ifdef CONFIG_DDR_ECC
 982         ecc_enabled = TRUE;
 983 #else
 984         ecc_enabled = FALSE;
 985 #endif
 986         dimm_32bit = FALSE;
 987         dimm_64bit = FALSE;
 988         buf0 = FALSE;
 989         buf1 = FALSE;
 990
 991         /*------------------------------------------------------------------
 992          * Set memory controller options reg 1, SDRAM_MCOPT1.
 993          *-----------------------------------------------------------------*/
 994         mfsdram(SDRAM_MCOPT1, val);
 995         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 996                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 997                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 998                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 999                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
1000                          SDRAM_MCOPT1_DREF_MASK);
1001
1002         mcopt1 |= SDRAM_MCOPT1_QDEP;
1003         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
1004         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
1005         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
1006         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
1007         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
1008
1009         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1010                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1011                         /* test ecc support */
1012                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1013                         if (ecc != 0x02) /* ecc not supported */
1014                                 ecc_enabled = FALSE;
1015
1016                         /* test bank count */
1017                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1018                         if (bankcount == 0x04) /* bank count = 4 */
1019                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1020                         else /* bank count = 8 */
1021                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1022
1023                         /* test DDR type */
1024                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
1025                         /* test for buffered/unbuffered, registered, differential clocks */
1026                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1027                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1028
1029                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1030                         if (dimm_num == 0) {
1031                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1032                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1033                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1034                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1035                                 if (registered == 1) { /* DDR2 always buffered */
1036                                         /* TODO: what about above  comments ? */
1037                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1038                                         buf0 = TRUE;
1039                                 } else {
1040                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1041                                         if ((attribute & 0x02) == 0x00) {
1042                                                 /* buffered not supported */
1043                                                 buf0 = FALSE;
1044                                         } else {
1045                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1046                                                 buf0 = TRUE;
1047                                         }
1048                                 }
1049                         }
1050                         else if (dimm_num == 1) {
1051                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1052                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1053                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1054                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1055                                 if (registered == 1) {
1056                                         /* DDR2 always buffered */
1057                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1058                                         buf1 = TRUE;
1059                                 } else {
1060                                         if ((attribute & 0x02) == 0x00) {
1061                                                 /* buffered not supported */
1062                                                 buf1 = FALSE;
1063                                         } else {
1064                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1065                                                 buf1 = TRUE;
1066                                         }
1067                                 }
1068                         }
1069
1070                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1071                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1072                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1073
1074                         switch (data_width) {
1075                         case 72:
1076                         case 64:
1077                                 dimm_64bit = TRUE;
1078                                 break;
1079                         case 40:
1080                         case 32:
1081                                 dimm_32bit = TRUE;
1082                                 break;
1083                         default:
1084                                 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1085                                        data_width);
1086                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1087                                 break;
1088                         }
1089                 }
1090         }
1091
1092         /* verify matching properties */
1093         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1094                 if (buf0 != buf1) {
1095                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1096                         spd_ddr_init_hang ();
1097                 }
1098         }
1099
1100         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1101                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1102                 spd_ddr_init_hang ();
1103         }
1104         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1105                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1106         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1107                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1108         } else {
1109                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1110                 spd_ddr_init_hang ();
1111         }
1112
1113         if (ecc_enabled == TRUE)
1114                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1115         else
1116                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1117
1118         mtsdram(SDRAM_MCOPT1, mcopt1);
1119 }
1120
1121 /*-----------------------------------------------------------------------------+
1122  * program_codt.
1123  *-----------------------------------------------------------------------------*/
1124 static void program_codt(unsigned long *dimm_populated,
1125                          unsigned char *iic0_dimm_addr,
1126                          unsigned long num_dimm_banks)
1127 {
1128         unsigned long codt;
1129         unsigned long modt0 = 0;
1130         unsigned long modt1 = 0;
1131         unsigned long modt2 = 0;
1132         unsigned long modt3 = 0;
1133         unsigned char dimm_num;
1134         unsigned char dimm_rank;
1135         unsigned char total_rank = 0;
1136         unsigned char total_dimm = 0;
1137         unsigned char dimm_type = 0;
1138         unsigned char firstSlot = 0;
1139
1140         /*------------------------------------------------------------------
1141          * Set the SDRAM Controller On Die Termination Register
1142          *-----------------------------------------------------------------*/
1143         mfsdram(SDRAM_CODT, codt);
1144         codt |= (SDRAM_CODT_IO_NMODE
1145                  & (~SDRAM_CODT_DQS_SINGLE_END
1146                     & ~SDRAM_CODT_CKSE_SINGLE_END
1147                     & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1148                     & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1149
1150         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1151                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1152                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1153                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1154                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1155                                 dimm_type = SDRAM_DDR2;
1156                         } else {
1157                                 dimm_rank = dimm_rank & 0x0F;
1158                                 dimm_type = SDRAM_DDR1;
1159                         }
1160
1161                         total_rank += dimm_rank;
1162                         total_dimm++;
1163                         if ((dimm_num == 0) && (total_dimm == 1))
1164                                 firstSlot = TRUE;
1165                         else
1166                                 firstSlot = FALSE;
1167                 }
1168         }
1169         if (dimm_type == SDRAM_DDR2) {
1170                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1171                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1172                         if (total_rank == 1) {  /* PUUU */
1173                                 codt |= CALC_ODT_R(0);
1174                                 modt0 = CALC_ODT_W(0);
1175                                 modt1 = 0x00000000;
1176                                 modt2 = 0x00000000;
1177                                 modt3 = 0x00000000;
1178                         }
1179                         if (total_rank == 2) {  /* PPUU */
1180                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1181                                 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1182                                 modt1 = 0x00000000;
1183                                 modt2 = 0x00000000;
1184                                 modt3 = 0x00000000;
1185                         }
1186                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1187                         if (total_rank == 1) {  /* UUPU */
1188                                 codt |= CALC_ODT_R(2);
1189                                 modt0 = 0x00000000;
1190                                 modt1 = 0x00000000;
1191                                 modt2 = CALC_ODT_W(2);
1192                                 modt3 = 0x00000000;
1193                         }
1194                         if (total_rank == 2) {  /* UUPP */
1195                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1196                                 modt0 = 0x00000000;
1197                                 modt1 = 0x00000000;
1198                                 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1199                                 modt3 = 0x00000000;
1200                         }
1201                 }
1202                 if (total_dimm == 2) {
1203                         if (total_rank == 2) {  /* PUPU */
1204                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1205                                 modt0 = CALC_ODT_RW(2);
1206                                 modt1 = 0x00000000;
1207                                 modt2 = CALC_ODT_RW(0);
1208                                 modt3 = 0x00000000;
1209                         }
1210                         if (total_rank == 4) {  /* PPPP */
1211                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1212                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1213                                 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1214                                 modt1 = 0x00000000;
1215                                 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1216                                 modt3 = 0x00000000;
1217                         }
1218                 }
1219         } else {
1220                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1221                 modt0 = 0x00000000;
1222                 modt1 = 0x00000000;
1223                 modt2 = 0x00000000;
1224                 modt3 = 0x00000000;
1225
1226                 if (total_dimm == 1) {
1227                         if (total_rank == 1)
1228                                 codt |= 0x00800000;
1229                         if (total_rank == 2)
1230                                 codt |= 0x02800000;
1231                 }
1232                 if (total_dimm == 2) {
1233                         if (total_rank == 2)
1234                                 codt |= 0x08800000;
1235                         if (total_rank == 4)
1236                                 codt |= 0x2a800000;
1237                 }
1238         }
1239
1240         debug("nb of dimm %d\n", total_dimm);
1241         debug("nb of rank %d\n", total_rank);
1242         if (total_dimm == 1)
1243                 debug("dimm in slot %d\n", firstSlot);
1244
1245         mtsdram(SDRAM_CODT, codt);
1246         mtsdram(SDRAM_MODT0, modt0);
1247         mtsdram(SDRAM_MODT1, modt1);
1248         mtsdram(SDRAM_MODT2, modt2);
1249         mtsdram(SDRAM_MODT3, modt3);
1250 }
1251
1252 /*-----------------------------------------------------------------------------+
1253  * program_initplr.
1254  *-----------------------------------------------------------------------------*/
1255 static void program_initplr(unsigned long *dimm_populated,
1256                             unsigned char *iic0_dimm_addr,
1257                             unsigned long num_dimm_banks,
1258                             ddr_cas_id_t selected_cas,
1259                             int write_recovery)
1260 {
1261         u32 cas = 0;
1262         u32 odt = 0;
1263         u32 ods = 0;
1264         u32 mr;
1265         u32 wr;
1266         u32 emr;
1267         u32 emr2;
1268         u32 emr3;
1269         int dimm_num;
1270         int total_dimm = 0;
1271
1272         /******************************************************
1273          ** Assumption: if more than one DIMM, all DIMMs are the same
1274          **             as already checked in check_memory_type
1275          ******************************************************/
1276
1277         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1278                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1279                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1280                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1281                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1282                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1283                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1284                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1285                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1286         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1287                 switch (selected_cas) {
1288                 case DDR_CAS_3:
1289                         cas = 3 << 4;
1290                         break;
1291                 case DDR_CAS_4:
1292                         cas = 4 << 4;
1293                         break;
1294                 case DDR_CAS_5:
1295                         cas = 5 << 4;
1296                         break;
1297                 default:
1298                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1299                         spd_ddr_init_hang ();
1300                         break;
1301                 }
1302
1303 #if 0
1304                 /*
1305                  * ToDo - Still a problem with the write recovery:
1306                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1307                  * in the INITPLR reg to the value calculated in program_mode()
1308                  * results in not correctly working DDR2 memory (crash after
1309                  * relocation).
1310                  *
1311                  * So for now, set the write recovery to 3. This seems to work
1312                  * on the Corair module too.
1313                  *
1314                  * 2007-03-01, sr
1315                  */
1316                 switch (write_recovery) {
1317                 case 3:
1318                         wr = WRITE_RECOV_3;
1319                         break;
1320                 case 4:
1321                         wr = WRITE_RECOV_4;
1322                         break;
1323                 case 5:
1324                         wr = WRITE_RECOV_5;
1325                         break;
1326                 case 6:
1327                         wr = WRITE_RECOV_6;
1328                         break;
1329                 default:
1330                         printf("ERROR: write recovery not support (%d)", write_recovery);
1331                         spd_ddr_init_hang ();
1332                         break;
1333                 }
1334 #else
1335                 wr = WRITE_RECOV_3; /* test-only, see description above */
1336 #endif
1337
1338                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1339                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1340                                 total_dimm++;
1341                 if (total_dimm == 1) {
1342                         odt = ODT_150_OHM;
1343                         ods = ODS_FULL;
1344                 } else if (total_dimm == 2) {
1345                         odt = ODT_75_OHM;
1346                         ods = ODS_REDUCED;
1347                 } else {
1348                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1349                         spd_ddr_init_hang ();
1350                 }
1351
1352                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1353                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1354                 emr2 = CMD_EMR | SELECT_EMR2;
1355                 emr3 = CMD_EMR | SELECT_EMR3;
1356                 /* NOP - Wait 106 MemClk cycles */
1357                 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1358                                         SDRAM_INITPLR_IMWT_ENCODE(106));
1359                 udelay(1000);
1360                 /* precharge 4 MemClk cycles */
1361                 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1362                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1363                 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1364                 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1365                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1366                 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1367                 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1368                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1369                 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1370                 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1371                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1372                 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1373                 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1374                                         SDRAM_INITPLR_IMWT_ENCODE(200));
1375                 udelay(1000);
1376                 /* precharge 4 MemClk cycles */
1377                 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1378                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1379                 /* Refresh 25 MemClk cycles */
1380                 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1381                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1382                 /* Refresh 25 MemClk cycles */
1383                 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1384                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1385                 /* Refresh 25 MemClk cycles */
1386                 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1387                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1388                 /* Refresh 25 MemClk cycles */
1389                 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1390                                          SDRAM_INITPLR_IMWT_ENCODE(25));
1391                 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1392                 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1393                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1394                 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1395                 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1396                                          SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1397                 /* EMR OCD Exit */
1398                 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1399                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1400         } else {
1401                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1402                 spd_ddr_init_hang ();
1403         }
1404 }
1405
1406 /*------------------------------------------------------------------
1407  * This routine programs the SDRAM_MMODE register.
1408  * the selected_cas is an output parameter, that will be passed
1409  * by caller to call the above program_initplr( )
1410  *-----------------------------------------------------------------*/
1411 static void program_mode(unsigned long *dimm_populated,
1412                          unsigned char *iic0_dimm_addr,
1413                          unsigned long num_dimm_banks,
1414                          ddr_cas_id_t *selected_cas,
1415                          int *write_recovery)
1416 {
1417         unsigned long dimm_num;
1418         unsigned long sdram_ddr1;
1419         unsigned long t_wr_ns;
1420         unsigned long t_wr_clk;
1421         unsigned long cas_bit;
1422         unsigned long cas_index;
1423         unsigned long sdram_freq;
1424         unsigned long ddr_check;
1425         unsigned long mmode;
1426         unsigned long tcyc_reg;
1427         unsigned long cycle_2_0_clk;
1428         unsigned long cycle_2_5_clk;
1429         unsigned long cycle_3_0_clk;
1430         unsigned long cycle_4_0_clk;
1431         unsigned long cycle_5_0_clk;
1432         unsigned long max_2_0_tcyc_ns_x_100;
1433         unsigned long max_2_5_tcyc_ns_x_100;
1434         unsigned long max_3_0_tcyc_ns_x_100;
1435         unsigned long max_4_0_tcyc_ns_x_100;
1436         unsigned long max_5_0_tcyc_ns_x_100;
1437         unsigned long cycle_time_ns_x_100[3];
1438         PPC4xx_SYS_INFO board_cfg;
1439         unsigned char cas_2_0_available;
1440         unsigned char cas_2_5_available;
1441         unsigned char cas_3_0_available;
1442         unsigned char cas_4_0_available;
1443         unsigned char cas_5_0_available;
1444         unsigned long sdr_ddrpll;
1445
1446         /*------------------------------------------------------------------
1447          * Get the board configuration info.
1448          *-----------------------------------------------------------------*/
1449         get_sys_info(&board_cfg);
1450
1451         mfsdr(SDR0_DDR0, sdr_ddrpll);
1452         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1453         debug("sdram_freq=%d\n", sdram_freq);
1454
1455         /*------------------------------------------------------------------
1456          * Handle the timing.  We need to find the worst case timing of all
1457          * the dimm modules installed.
1458          *-----------------------------------------------------------------*/
1459         t_wr_ns = 0;
1460         cas_2_0_available = TRUE;
1461         cas_2_5_available = TRUE;
1462         cas_3_0_available = TRUE;
1463         cas_4_0_available = TRUE;
1464         cas_5_0_available = TRUE;
1465         max_2_0_tcyc_ns_x_100 = 10;
1466         max_2_5_tcyc_ns_x_100 = 10;
1467         max_3_0_tcyc_ns_x_100 = 10;
1468         max_4_0_tcyc_ns_x_100 = 10;
1469         max_5_0_tcyc_ns_x_100 = 10;
1470         sdram_ddr1 = TRUE;
1471
1472         /* loop through all the DIMM slots on the board */
1473         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1474                 /* If a dimm is installed in a particular slot ... */
1475                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1476                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1477                                 sdram_ddr1 = TRUE;
1478                         else
1479                                 sdram_ddr1 = FALSE;
1480
1481                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1482                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1483                         debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1484
1485                         /* For a particular DIMM, grab the three CAS values it supports */
1486                         for (cas_index = 0; cas_index < 3; cas_index++) {
1487                                 switch (cas_index) {
1488                                 case 0:
1489                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1490                                         break;
1491                                 case 1:
1492                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1493                                         break;
1494                                 default:
1495                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1496                                         break;
1497                                 }
1498
1499                                 if ((tcyc_reg & 0x0F) >= 10) {
1500                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1501                                                 /* Convert from hex to decimal */
1502                                                 cycle_time_ns_x_100[cas_index] =
1503                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1504                                         } else {
1505                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1506                                                        "in slot %d\n", (unsigned int)dimm_num);
1507                                                 spd_ddr_init_hang ();
1508                                         }
1509                                 } else {
1510                                         /* Convert from hex to decimal */
1511                                         cycle_time_ns_x_100[cas_index] =
1512                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1513                                                 ((tcyc_reg & 0x0F)*10);
1514                                 }
1515                                 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1516                                       cycle_time_ns_x_100[cas_index]);
1517                         }
1518
1519                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1520                         /* supported for a particular DIMM. */
1521                         cas_index = 0;
1522
1523                         if (sdram_ddr1) {
1524                                 /*
1525                                  * DDR devices use the following bitmask for CAS latency:
1526                                  *  Bit   7    6    5    4    3    2    1    0
1527                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1528                                  */
1529                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1530                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1531                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1532                                                                     cycle_time_ns_x_100[cas_index]);
1533                                         cas_index++;
1534                                 } else {
1535                                         if (cas_index != 0)
1536                                                 cas_index++;
1537                                         cas_4_0_available = FALSE;
1538                                 }
1539
1540                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1541                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1542                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1543                                                                     cycle_time_ns_x_100[cas_index]);
1544                                         cas_index++;
1545                                 } else {
1546                                         if (cas_index != 0)
1547                                                 cas_index++;
1548                                         cas_3_0_available = FALSE;
1549                                 }
1550
1551                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1552                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1553                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1554                                                                     cycle_time_ns_x_100[cas_index]);
1555                                         cas_index++;
1556                                 } else {
1557                                         if (cas_index != 0)
1558                                                 cas_index++;
1559                                         cas_2_5_available = FALSE;
1560                                 }
1561
1562                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1563                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1564                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1565                                                                     cycle_time_ns_x_100[cas_index]);
1566                                         cas_index++;
1567                                 } else {
1568                                         if (cas_index != 0)
1569                                                 cas_index++;
1570                                         cas_2_0_available = FALSE;
1571                                 }
1572                         } else {
1573                                 /*
1574                                  * DDR2 devices use the following bitmask for CAS latency:
1575                                  *  Bit   7    6    5    4    3    2    1    0
1576                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1577                                  */
1578                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1579                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1580                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1581                                                                     cycle_time_ns_x_100[cas_index]);
1582                                         cas_index++;
1583                                 } else {
1584                                         if (cas_index != 0)
1585                                                 cas_index++;
1586                                         cas_5_0_available = FALSE;
1587                                 }
1588
1589                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1590                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1591                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1592                                                                     cycle_time_ns_x_100[cas_index]);
1593                                         cas_index++;
1594                                 } else {
1595                                         if (cas_index != 0)
1596                                                 cas_index++;
1597                                         cas_4_0_available = FALSE;
1598                                 }
1599
1600                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1601                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1602                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1603                                                                     cycle_time_ns_x_100[cas_index]);
1604                                         cas_index++;
1605                                 } else {
1606                                         if (cas_index != 0)
1607                                                 cas_index++;
1608                                         cas_3_0_available = FALSE;
1609                                 }
1610                         }
1611                 }
1612         }
1613
1614         /*------------------------------------------------------------------
1615          * Set the SDRAM mode, SDRAM_MMODE
1616          *-----------------------------------------------------------------*/
1617         mfsdram(SDRAM_MMODE, mmode);
1618         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1619
1620         /* add 10 here because of rounding problems */
1621         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1622         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1623         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1624         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1625         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1626         debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1627         debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1628         debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1629
1630         if (sdram_ddr1 == TRUE) { /* DDR1 */
1631                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1632                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1633                         *selected_cas = DDR_CAS_2;
1634                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1635                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1636                         *selected_cas = DDR_CAS_2_5;
1637                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1638                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1639                         *selected_cas = DDR_CAS_3;
1640                 } else {
1641                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1642                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1643                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1644                         spd_ddr_init_hang ();
1645                 }
1646         } else { /* DDR2 */
1647                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1648                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1649                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1650                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1651                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1652                         *selected_cas = DDR_CAS_3;
1653                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1654                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1655                         *selected_cas = DDR_CAS_4;
1656                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1657                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1658                         *selected_cas = DDR_CAS_5;
1659                 } else {
1660                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1661                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1662                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1663                         printf("cas3=%d cas4=%d cas5=%d\n",
1664                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1665                         printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1666                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1667                         spd_ddr_init_hang ();
1668                 }
1669         }
1670
1671         if (sdram_ddr1 == TRUE)
1672                 mmode |= SDRAM_MMODE_WR_DDR1;
1673         else {
1674
1675                 /* loop through all the DIMM slots on the board */
1676                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1677                         /* If a dimm is installed in a particular slot ... */
1678                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1679                                 t_wr_ns = max(t_wr_ns,
1680                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1681                 }
1682
1683                 /*
1684                  * convert from nanoseconds to ddr clocks
1685                  * round up if necessary
1686                  */
1687                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1688                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1689                 if (sdram_freq != ddr_check)
1690                         t_wr_clk++;
1691
1692                 switch (t_wr_clk) {
1693                 case 0:
1694                 case 1:
1695                 case 2:
1696                 case 3:
1697                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1698                         break;
1699                 case 4:
1700                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1701                         break;
1702                 case 5:
1703                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1704                         break;
1705                 default:
1706                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1707                         break;
1708                 }
1709                 *write_recovery = t_wr_clk;
1710         }
1711
1712         debug("CAS latency = %d\n", *selected_cas);
1713         debug("Write recovery = %d\n", *write_recovery);
1714
1715         mtsdram(SDRAM_MMODE, mmode);
1716 }
1717
1718 /*-----------------------------------------------------------------------------+
1719  * program_rtr.
1720  *-----------------------------------------------------------------------------*/
1721 static void program_rtr(unsigned long *dimm_populated,
1722                         unsigned char *iic0_dimm_addr,
1723                         unsigned long num_dimm_banks)
1724 {
1725         PPC4xx_SYS_INFO board_cfg;
1726         unsigned long max_refresh_rate;
1727         unsigned long dimm_num;
1728         unsigned long refresh_rate_type;
1729         unsigned long refresh_rate;
1730         unsigned long rint;
1731         unsigned long sdram_freq;
1732         unsigned long sdr_ddrpll;
1733         unsigned long val;
1734
1735         /*------------------------------------------------------------------
1736          * Get the board configuration info.
1737          *-----------------------------------------------------------------*/
1738         get_sys_info(&board_cfg);
1739
1740         /*------------------------------------------------------------------
1741          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1742          *-----------------------------------------------------------------*/
1743         mfsdr(SDR0_DDR0, sdr_ddrpll);
1744         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1745
1746         max_refresh_rate = 0;
1747         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1748                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1749
1750                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1751                         refresh_rate_type &= 0x7F;
1752                         switch (refresh_rate_type) {
1753                         case 0:
1754                                 refresh_rate =  15625;
1755                                 break;
1756                         case 1:
1757                                 refresh_rate =   3906;
1758                                 break;
1759                         case 2:
1760                                 refresh_rate =   7812;
1761                                 break;
1762                         case 3:
1763                                 refresh_rate =  31250;
1764                                 break;
1765                         case 4:
1766                                 refresh_rate =  62500;
1767                                 break;
1768                         case 5:
1769                                 refresh_rate = 125000;
1770                                 break;
1771                         default:
1772                                 refresh_rate = 0;
1773                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1774                                        (unsigned int)dimm_num);
1775                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1776                                 spd_ddr_init_hang ();
1777                                 break;
1778                         }
1779
1780                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1781                 }
1782         }
1783
1784         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1785         mfsdram(SDRAM_RTR, val);
1786         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1787                 (SDRAM_RTR_RINT_ENCODE(rint)));
1788 }
1789
1790 /*------------------------------------------------------------------
1791  * This routine programs the SDRAM_TRx registers.
1792  *-----------------------------------------------------------------*/
1793 static void program_tr(unsigned long *dimm_populated,
1794                        unsigned char *iic0_dimm_addr,
1795                        unsigned long num_dimm_banks)
1796 {
1797         unsigned long dimm_num;
1798         unsigned long sdram_ddr1;
1799         unsigned long t_rp_ns;
1800         unsigned long t_rcd_ns;
1801         unsigned long t_rrd_ns;
1802         unsigned long t_ras_ns;
1803         unsigned long t_rc_ns;
1804         unsigned long t_rfc_ns;
1805         unsigned long t_wpc_ns;
1806         unsigned long t_wtr_ns;
1807         unsigned long t_rpc_ns;
1808         unsigned long t_rp_clk;
1809         unsigned long t_rcd_clk;
1810         unsigned long t_rrd_clk;
1811         unsigned long t_ras_clk;
1812         unsigned long t_rc_clk;
1813         unsigned long t_rfc_clk;
1814         unsigned long t_wpc_clk;
1815         unsigned long t_wtr_clk;
1816         unsigned long t_rpc_clk;
1817         unsigned long sdtr1, sdtr2, sdtr3;
1818         unsigned long ddr_check;
1819         unsigned long sdram_freq;
1820         unsigned long sdr_ddrpll;
1821
1822         PPC4xx_SYS_INFO board_cfg;
1823
1824         /*------------------------------------------------------------------
1825          * Get the board configuration info.
1826          *-----------------------------------------------------------------*/
1827         get_sys_info(&board_cfg);
1828
1829         mfsdr(SDR0_DDR0, sdr_ddrpll);
1830         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1831
1832         /*------------------------------------------------------------------
1833          * Handle the timing.  We need to find the worst case timing of all
1834          * the dimm modules installed.
1835          *-----------------------------------------------------------------*/
1836         t_rp_ns = 0;
1837         t_rrd_ns = 0;
1838         t_rcd_ns = 0;
1839         t_ras_ns = 0;
1840         t_rc_ns = 0;
1841         t_rfc_ns = 0;
1842         t_wpc_ns = 0;
1843         t_wtr_ns = 0;
1844         t_rpc_ns = 0;
1845         sdram_ddr1 = TRUE;
1846
1847         /* loop through all the DIMM slots on the board */
1848         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1849                 /* If a dimm is installed in a particular slot ... */
1850                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1851                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1852                                 sdram_ddr1 = TRUE;
1853                         else
1854                                 sdram_ddr1 = FALSE;
1855
1856                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1857                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1858                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1859                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1860                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1861                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1862                 }
1863         }
1864
1865         /*------------------------------------------------------------------
1866          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1867          *-----------------------------------------------------------------*/
1868         mfsdram(SDRAM_SDTR1, sdtr1);
1869         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1870                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1871
1872         /* default values */
1873         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1874         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1875
1876         /* normal operations */
1877         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1878         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1879
1880         mtsdram(SDRAM_SDTR1, sdtr1);
1881
1882         /*------------------------------------------------------------------
1883          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1884          *-----------------------------------------------------------------*/
1885         mfsdram(SDRAM_SDTR2, sdtr2);
1886         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1887                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1888                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1889                    SDRAM_SDTR2_RRD_MASK);
1890
1891         /*
1892          * convert t_rcd from nanoseconds to ddr clocks
1893          * round up if necessary
1894          */
1895         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1896         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1897         if (sdram_freq != ddr_check)
1898                 t_rcd_clk++;
1899
1900         switch (t_rcd_clk) {
1901         case 0:
1902         case 1:
1903                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1904                 break;
1905         case 2:
1906                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1907                 break;
1908         case 3:
1909                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1910                 break;
1911         case 4:
1912                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1913                 break;
1914         default:
1915                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1916                 break;
1917         }
1918
1919         if (sdram_ddr1 == TRUE) { /* DDR1 */
1920                 if (sdram_freq < 200000000) {
1921                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1922                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1923                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1924                 } else {
1925                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1926                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1927                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1928                 }
1929         } else { /* DDR2 */
1930                 /* loop through all the DIMM slots on the board */
1931                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1932                         /* If a dimm is installed in a particular slot ... */
1933                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1934                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1935                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1936                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1937                         }
1938                 }
1939
1940                 /*
1941                  * convert from nanoseconds to ddr clocks
1942                  * round up if necessary
1943                  */
1944                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1945                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1946                 if (sdram_freq != ddr_check)
1947                         t_wpc_clk++;
1948
1949                 switch (t_wpc_clk) {
1950                 case 0:
1951                 case 1:
1952                 case 2:
1953                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1954                         break;
1955                 case 3:
1956                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1957                         break;
1958                 case 4:
1959                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1960                         break;
1961                 case 5:
1962                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1963                         break;
1964                 default:
1965                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1966                         break;
1967                 }
1968
1969                 /*
1970                  * convert from nanoseconds to ddr clocks
1971                  * round up if necessary
1972                  */
1973                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1974                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1975                 if (sdram_freq != ddr_check)
1976                         t_wtr_clk++;
1977
1978                 switch (t_wtr_clk) {
1979                 case 0:
1980                 case 1:
1981                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1982                         break;
1983                 case 2:
1984                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1985                         break;
1986                 case 3:
1987                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1988                         break;
1989                 default:
1990                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1991                         break;
1992                 }
1993
1994                 /*
1995                  * convert from nanoseconds to ddr clocks
1996                  * round up if necessary
1997                  */
1998                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1999                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
2000                 if (sdram_freq != ddr_check)
2001                         t_rpc_clk++;
2002
2003                 switch (t_rpc_clk) {
2004                 case 0:
2005                 case 1:
2006                 case 2:
2007                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
2008                         break;
2009                 case 3:
2010                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
2011                         break;
2012                 default:
2013                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
2014                         break;
2015                 }
2016         }
2017
2018         /* default value */
2019         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
2020
2021         /*
2022          * convert t_rrd from nanoseconds to ddr clocks
2023          * round up if necessary
2024          */
2025         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
2026         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
2027         if (sdram_freq != ddr_check)
2028                 t_rrd_clk++;
2029
2030         if (t_rrd_clk == 3)
2031                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
2032         else
2033                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2034
2035         /*
2036          * convert t_rp from nanoseconds to ddr clocks
2037          * round up if necessary
2038          */
2039         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2040         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2041         if (sdram_freq != ddr_check)
2042                 t_rp_clk++;
2043
2044         switch (t_rp_clk) {
2045         case 0:
2046         case 1:
2047         case 2:
2048         case 3:
2049                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2050                 break;
2051         case 4:
2052                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2053                 break;
2054         case 5:
2055                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2056                 break;
2057         case 6:
2058                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2059                 break;
2060         default:
2061                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2062                 break;
2063         }
2064
2065         mtsdram(SDRAM_SDTR2, sdtr2);
2066
2067         /*------------------------------------------------------------------
2068          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2069          *-----------------------------------------------------------------*/
2070         mfsdram(SDRAM_SDTR3, sdtr3);
2071         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2072                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2073
2074         /*
2075          * convert t_ras from nanoseconds to ddr clocks
2076          * round up if necessary
2077          */
2078         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2079         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2080         if (sdram_freq != ddr_check)
2081                 t_ras_clk++;
2082
2083         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2084
2085         /*
2086          * convert t_rc from nanoseconds to ddr clocks
2087          * round up if necessary
2088          */
2089         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2090         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2091         if (sdram_freq != ddr_check)
2092                 t_rc_clk++;
2093
2094         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2095
2096         /* default xcs value */
2097         sdtr3 |= SDRAM_SDTR3_XCS;
2098
2099         /*
2100          * convert t_rfc from nanoseconds to ddr clocks
2101          * round up if necessary
2102          */
2103         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2104         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2105         if (sdram_freq != ddr_check)
2106                 t_rfc_clk++;
2107
2108         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2109
2110         mtsdram(SDRAM_SDTR3, sdtr3);
2111 }
2112
2113 /*-----------------------------------------------------------------------------+
2114  * program_bxcf.
2115  *-----------------------------------------------------------------------------*/
2116 static void program_bxcf(unsigned long *dimm_populated,
2117                          unsigned char *iic0_dimm_addr,
2118                          unsigned long num_dimm_banks)
2119 {
2120         unsigned long dimm_num;
2121         unsigned long num_col_addr;
2122         unsigned long num_ranks;
2123         unsigned long num_banks;
2124         unsigned long mode;
2125         unsigned long ind_rank;
2126         unsigned long ind;
2127         unsigned long ind_bank;
2128         unsigned long bank_0_populated;
2129
2130         /*------------------------------------------------------------------
2131          * Set the BxCF regs.  First, wipe out the bank config registers.
2132          *-----------------------------------------------------------------*/
2133         mtsdram(SDRAM_MB0CF, 0x00000000);
2134         mtsdram(SDRAM_MB1CF, 0x00000000);
2135         mtsdram(SDRAM_MB2CF, 0x00000000);
2136         mtsdram(SDRAM_MB3CF, 0x00000000);
2137
2138         mode = SDRAM_BXCF_M_BE_ENABLE;
2139
2140         bank_0_populated = 0;
2141
2142         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2143                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2144                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2145                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2146                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2147                                 num_ranks = (num_ranks & 0x0F) +1;
2148                         else
2149                                 num_ranks = num_ranks & 0x0F;
2150
2151                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2152
2153                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2154                                 if (num_banks == 4)
2155                                         ind = 0;
2156                                 else
2157                                         ind = 5 << 8;
2158                                 switch (num_col_addr) {
2159                                 case 0x08:
2160                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2161                                         break;
2162                                 case 0x09:
2163                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2164                                         break;
2165                                 case 0x0A:
2166                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2167                                         break;
2168                                 case 0x0B:
2169                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2170                                         break;
2171                                 case 0x0C:
2172                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2173                                         break;
2174                                 default:
2175                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2176                                                (unsigned int)dimm_num);
2177                                         printf("ERROR: Unsupported value for number of "
2178                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2179                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2180                                         spd_ddr_init_hang ();
2181                                 }
2182                         }
2183
2184                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2185                                 bank_0_populated = 1;
2186
2187                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2188                                 mtsdram(SDRAM_MB0CF +
2189                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2190                                         mode);
2191                         }
2192                 }
2193         }
2194 }
2195
2196 /*------------------------------------------------------------------
2197  * program memory queue.
2198  *-----------------------------------------------------------------*/
2199 static void program_memory_queue(unsigned long *dimm_populated,
2200                                  unsigned char *iic0_dimm_addr,
2201                                  unsigned long num_dimm_banks)
2202 {
2203         unsigned long dimm_num;
2204         phys_size_t rank_base_addr;
2205         unsigned long rank_reg;
2206         phys_size_t rank_size_bytes;
2207         unsigned long rank_size_id;
2208         unsigned long num_ranks;
2209         unsigned long baseadd_size;
2210         unsigned long i;
2211         unsigned long bank_0_populated = 0;
2212         phys_size_t total_size = 0;
2213
2214         /*------------------------------------------------------------------
2215          * Reset the rank_base_address.
2216          *-----------------------------------------------------------------*/
2217         rank_reg   = SDRAM_R0BAS;
2218
2219         rank_base_addr = 0x00000000;
2220
2221         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2222                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2223                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2224                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2225                                 num_ranks = (num_ranks & 0x0F) + 1;
2226                         else
2227                                 num_ranks = num_ranks & 0x0F;
2228
2229                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2230
2231                         /*------------------------------------------------------------------
2232                          * Set the sizes
2233                          *-----------------------------------------------------------------*/
2234                         baseadd_size = 0;
2235                         switch (rank_size_id) {
2236                         case 0x01:
2237                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2238                                 total_size = 1024;
2239                                 break;
2240                         case 0x02:
2241                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2242                                 total_size = 2048;
2243                                 break;
2244                         case 0x04:
2245                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2246                                 total_size = 4096;
2247                                 break;
2248                         case 0x08:
2249                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2250                                 total_size = 32;
2251                                 break;
2252                         case 0x10:
2253                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2254                                 total_size = 64;
2255                                 break;
2256                         case 0x20:
2257                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2258                                 total_size = 128;
2259                                 break;
2260                         case 0x40:
2261                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2262                                 total_size = 256;
2263                                 break;
2264                         case 0x80:
2265                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2266                                 total_size = 512;
2267                                 break;
2268                         default:
2269                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2270                                        (unsigned int)dimm_num);
2271                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2272                                        (unsigned int)rank_size_id);
2273                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2274                                 spd_ddr_init_hang ();
2275                         }
2276                         rank_size_bytes = total_size << 20;
2277
2278                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2279                                 bank_0_populated = 1;
2280
2281                         for (i = 0; i < num_ranks; i++) {
2282                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2283                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2284                                            baseadd_size));
2285                                 rank_base_addr += rank_size_bytes;
2286                         }
2287                 }
2288         }
2289
2290 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2291     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2292     defined(CONFIG_460SX)
2293         /*
2294          * Enable high bandwidth access
2295          * This is currently not used, but with this setup
2296          * it is possible to use it later on in e.g. the Linux
2297          * EMAC driver for performance gain.
2298          */
2299         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2300         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2301
2302         /*
2303          * Set optimal value for Memory Queue HB/LL Configuration registers
2304          */
2305         mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
2306               SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
2307         mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
2308               SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
2309         mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2310 #endif
2311 }
2312
2313 /*-----------------------------------------------------------------------------+
2314  * is_ecc_enabled.
2315  *-----------------------------------------------------------------------------*/
2316 static unsigned long is_ecc_enabled(void)
2317 {
2318         unsigned long dimm_num;
2319         unsigned long ecc;
2320         unsigned long val;
2321
2322         ecc = 0;
2323         /* loop through all the DIMM slots on the board */
2324         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2325                 mfsdram(SDRAM_MCOPT1, val);
2326                 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2327         }
2328
2329         return ecc;
2330 }
2331
2332 static void blank_string(int size)
2333 {
2334         int i;
2335
2336         for (i=0; i<size; i++)
2337                 putc('\b');
2338         for (i=0; i<size; i++)
2339                 putc(' ');
2340         for (i=0; i<size; i++)
2341                 putc('\b');
2342 }
2343
2344 #ifdef CONFIG_DDR_ECC
2345 /*-----------------------------------------------------------------------------+
2346  * program_ecc.
2347  *-----------------------------------------------------------------------------*/
2348 static void program_ecc(unsigned long *dimm_populated,
2349                         unsigned char *iic0_dimm_addr,
2350                         unsigned long num_dimm_banks,
2351                         unsigned long tlb_word2_i_value)
2352 {
2353         unsigned long mcopt1;
2354         unsigned long mcopt2;
2355         unsigned long mcstat;
2356         unsigned long dimm_num;
2357         unsigned long ecc;
2358
2359         ecc = 0;
2360         /* loop through all the DIMM slots on the board */
2361         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2362                 /* If a dimm is installed in a particular slot ... */
2363                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2364                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2365         }
2366         if (ecc == 0)
2367                 return;
2368
2369         if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
2370                 printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
2371                 return;
2372         }
2373
2374         mfsdram(SDRAM_MCOPT1, mcopt1);
2375         mfsdram(SDRAM_MCOPT2, mcopt2);
2376
2377         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2378                 /* DDR controller must be enabled and not in self-refresh. */
2379                 mfsdram(SDRAM_MCSTAT, mcstat);
2380                 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2381                     && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2382                     && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2383                         == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2384
2385                         program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2386                 }
2387         }
2388
2389         return;
2390 }
2391
2392 static void wait_ddr_idle(void)
2393 {
2394         u32 val;
2395
2396         do {
2397                 mfsdram(SDRAM_MCSTAT, val);
2398         } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2399 }
2400
2401 /*-----------------------------------------------------------------------------+
2402  * program_ecc_addr.
2403  *-----------------------------------------------------------------------------*/
2404 static void program_ecc_addr(unsigned long start_address,
2405                              unsigned long num_bytes,
2406                              unsigned long tlb_word2_i_value)
2407 {
2408         unsigned long current_address;
2409         unsigned long end_address;
2410         unsigned long address_increment;
2411         unsigned long mcopt1;
2412         char str[] = "ECC generation -";
2413         char slash[] = "\\|/-\\|/-";
2414         int loop = 0;
2415         int loopi = 0;
2416
2417         current_address = start_address;
2418         mfsdram(SDRAM_MCOPT1, mcopt1);
2419         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2420                 mtsdram(SDRAM_MCOPT1,
2421                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2422                 sync();
2423                 eieio();
2424                 wait_ddr_idle();
2425
2426                 puts(str);
2427                 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2428                         /* ECC bit set method for non-cached memory */
2429                         if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2430                                 address_increment = 4;
2431                         else
2432                                 address_increment = 8;
2433                         end_address = current_address + num_bytes;
2434
2435                         while (current_address < end_address) {
2436                                 *((unsigned long *)current_address) = 0x00000000;
2437                                 current_address += address_increment;
2438
2439                                 if ((loop++ % (2 << 20)) == 0) {
2440                                         putc('\b');
2441                                         putc(slash[loopi++ % 8]);
2442                                 }
2443                         }
2444
2445                 } else {
2446                         /* ECC bit set method for cached memory */
2447                         dcbz_area(start_address, num_bytes);
2448                         /* Write modified dcache lines back to memory */
2449                         clean_dcache_range(start_address, start_address + num_bytes);
2450                 }
2451
2452                 blank_string(strlen(str));
2453
2454                 sync();
2455                 eieio();
2456                 wait_ddr_idle();
2457
2458                 /* clear ECC error repoting registers */
2459                 mtsdram(SDRAM_ECCCR, 0xffffffff);
2460                 mtdcr(0x4c, 0xffffffff);
2461
2462                 mtsdram(SDRAM_MCOPT1,
2463                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2464                 sync();
2465                 eieio();
2466                 wait_ddr_idle();
2467         }
2468 }
2469 #endif
2470
2471 /*-----------------------------------------------------------------------------+
2472  * program_DQS_calibration.
2473  *-----------------------------------------------------------------------------*/
2474 static void program_DQS_calibration(unsigned long *dimm_populated,
2475                                     unsigned char *iic0_dimm_addr,
2476                                     unsigned long num_dimm_banks)
2477 {
2478         unsigned long val;
2479
2480 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2481         mtsdram(SDRAM_RQDC, 0x80000037);
2482         mtsdram(SDRAM_RDCC, 0x40000000);
2483         mtsdram(SDRAM_RFDC, 0x000001DF);
2484
2485         test();
2486 #else
2487         /*------------------------------------------------------------------
2488          * Program RDCC register
2489          * Read sample cycle auto-update enable
2490          *-----------------------------------------------------------------*/
2491
2492         mfsdram(SDRAM_RDCC, val);
2493         mtsdram(SDRAM_RDCC,
2494                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2495                 | SDRAM_RDCC_RSAE_ENABLE);
2496
2497         /*------------------------------------------------------------------
2498          * Program RQDC register
2499          * Internal DQS delay mechanism enable
2500          *-----------------------------------------------------------------*/
2501         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2502
2503         /*------------------------------------------------------------------
2504          * Program RFDC register
2505          * Set Feedback Fractional Oversample
2506          * Auto-detect read sample cycle enable
2507          * Set RFOS to 1/4 of memclk cycle (0x3f)
2508          *-----------------------------------------------------------------*/
2509         mfsdram(SDRAM_RFDC, val);
2510         mtsdram(SDRAM_RFDC,
2511                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2512                          SDRAM_RFDC_RFFD_MASK))
2513                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2514                    SDRAM_RFDC_RFFD_ENCODE(0)));
2515
2516         DQS_calibration_process();
2517 #endif
2518 }
2519
2520 static int short_mem_test(void)
2521 {
2522         u32 *membase;
2523         u32 bxcr_num;
2524         u32 bxcf;
2525         int i;
2526         int j;
2527         phys_size_t base_addr;
2528         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2529                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2530                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2531                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2532                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2533                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2534                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2535                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2536                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2537                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2538                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2539                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2540                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2541                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2542                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2543                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2544                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2545         int l;
2546
2547         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2548                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2549
2550                 /* Banks enabled */
2551                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2552                         /* Bank is enabled */
2553
2554                         /*
2555                          * Only run test on accessable memory (below 2GB)
2556                          */
2557                         base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2558                         if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2559                                 continue;
2560
2561                         /*------------------------------------------------------------------
2562                          * Run the short memory test.
2563                          *-----------------------------------------------------------------*/
2564                         membase = (u32 *)(u32)base_addr;
2565
2566                         for (i = 0; i < NUMMEMTESTS; i++) {
2567                                 for (j = 0; j < NUMMEMWORDS; j++) {
2568                                         membase[j] = test[i][j];
2569                                         ppcDcbf((u32)&(membase[j]));
2570                                 }
2571                                 sync();
2572                                 for (l=0; l<NUMLOOPS; l++) {
2573                                         for (j = 0; j < NUMMEMWORDS; j++) {
2574                                                 if (membase[j] != test[i][j]) {
2575                                                         ppcDcbf((u32)&(membase[j]));
2576                                                         return 0;
2577                                                 }
2578                                                 ppcDcbf((u32)&(membase[j]));
2579                                         }
2580                                         sync();
2581                                 }
2582                         }
2583                 }       /* if bank enabled */
2584         }               /* for bxcf_num */
2585
2586         return 1;
2587 }
2588
2589 #ifndef HARD_CODED_DQS
2590 /*-----------------------------------------------------------------------------+
2591  * DQS_calibration_process.
2592  *-----------------------------------------------------------------------------*/
2593 static void DQS_calibration_process(void)
2594 {
2595         unsigned long rfdc_reg;
2596         unsigned long rffd;
2597         unsigned long val;
2598         long rffd_average;
2599         long max_start;
2600         long min_end;
2601         unsigned long begin_rqfd[MAXRANKS];
2602         unsigned long begin_rffd[MAXRANKS];
2603         unsigned long end_rqfd[MAXRANKS];
2604         unsigned long end_rffd[MAXRANKS];
2605         char window_found;
2606         unsigned long dlycal;
2607         unsigned long dly_val;
2608         unsigned long max_pass_length;
2609         unsigned long current_pass_length;
2610         unsigned long current_fail_length;
2611         unsigned long current_start;
2612         long max_end;
2613         unsigned char fail_found;
2614         unsigned char pass_found;
2615 #if !defined(CONFIG_DDR_RQDC_FIXED)
2616         u32 rqdc_reg;
2617         u32 rqfd;
2618         u32 rqfd_start;
2619         u32 rqfd_average;
2620         int loopi = 0;
2621         char str[] = "Auto calibration -";
2622         char slash[] = "\\|/-\\|/-";
2623
2624         /*------------------------------------------------------------------
2625          * Test to determine the best read clock delay tuning bits.
2626          *
2627          * Before the DDR controller can be used, the read clock delay needs to be
2628          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2629          * This value cannot be hardcoded into the program because it changes
2630          * depending on the board's setup and environment.
2631          * To do this, all delay values are tested to see if they
2632          * work or not.  By doing this, you get groups of fails with groups of
2633          * passing values.  The idea is to find the start and end of a passing
2634          * window and take the center of it to use as the read clock delay.
2635          *
2636          * A failure has to be seen first so that when we hit a pass, we know
2637          * that it is truely the start of the window.  If we get passing values
2638          * to start off with, we don't know if we are at the start of the window.
2639          *
2640          * The code assumes that a failure will always be found.
2641          * If a failure is not found, there is no easy way to get the middle
2642          * of the passing window.  I guess we can pretty much pick any value
2643          * but some values will be better than others.  Since the lowest speed
2644          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2645          * from experimentation it is safe to say you will always have a failure.
2646          *-----------------------------------------------------------------*/
2647
2648         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2649         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2650
2651         puts(str);
2652
2653 calibration_loop:
2654         mfsdram(SDRAM_RQDC, rqdc_reg);
2655         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2656                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2657 #else /* CONFIG_DDR_RQDC_FIXED */
2658         /*
2659          * On Katmai the complete auto-calibration somehow doesn't seem to
2660          * produce the best results, meaning optimal values for RQFD/RFFD.
2661          * This was discovered by GDA using a high bandwidth scope,
2662          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2663          * so now on Katmai "only" RFFD is auto-calibrated.
2664          */
2665         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2666 #endif /* CONFIG_DDR_RQDC_FIXED */
2667
2668         max_start = 0;
2669         min_end = 0;
2670         begin_rqfd[0] = 0;
2671         begin_rffd[0] = 0;
2672         begin_rqfd[1] = 0;
2673         begin_rffd[1] = 0;
2674         end_rqfd[0] = 0;
2675         end_rffd[0] = 0;
2676         end_rqfd[1] = 0;
2677         end_rffd[1] = 0;
2678         window_found = FALSE;
2679
2680         max_pass_length = 0;
2681         max_start = 0;
2682         max_end = 0;
2683         current_pass_length = 0;
2684         current_fail_length = 0;
2685         current_start = 0;
2686         window_found = FALSE;
2687         fail_found = FALSE;
2688         pass_found = FALSE;
2689
2690         /*
2691          * get the delay line calibration register value
2692          */
2693         mfsdram(SDRAM_DLCR, dlycal);
2694         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2695
2696         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2697                 mfsdram(SDRAM_RFDC, rfdc_reg);
2698                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2699
2700                 /*------------------------------------------------------------------
2701                  * Set the timing reg for the test.
2702                  *-----------------------------------------------------------------*/
2703                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2704
2705                 /*------------------------------------------------------------------
2706                  * See if the rffd value passed.
2707                  *-----------------------------------------------------------------*/
2708                 if (short_mem_test()) {
2709                         if (fail_found == TRUE) {
2710                                 pass_found = TRUE;
2711                                 if (current_pass_length == 0)
2712                                         current_start = rffd;
2713
2714                                 current_fail_length = 0;
2715                                 current_pass_length++;
2716
2717                                 if (current_pass_length > max_pass_length) {
2718                                         max_pass_length = current_pass_length;
2719                                         max_start = current_start;
2720                                         max_end = rffd;
2721                                 }
2722                         }
2723                 } else {
2724                         current_pass_length = 0;
2725                         current_fail_length++;
2726
2727                         if (current_fail_length >= (dly_val >> 2)) {
2728                                 if (fail_found == FALSE) {
2729                                         fail_found = TRUE;
2730                                 } else if (pass_found == TRUE) {
2731                                         window_found = TRUE;
2732                                         break;
2733                                 }
2734                         }
2735                 }
2736         }               /* for rffd */
2737
2738         /*------------------------------------------------------------------
2739          * Set the average RFFD value
2740          *-----------------------------------------------------------------*/
2741         rffd_average = ((max_start + max_end) >> 1);
2742
2743         if (rffd_average < 0)
2744                 rffd_average = 0;
2745
2746         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2747                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2748         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2749         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2750
2751 #if !defined(CONFIG_DDR_RQDC_FIXED)
2752         max_pass_length = 0;
2753         max_start = 0;
2754         max_end = 0;
2755         current_pass_length = 0;
2756         current_fail_length = 0;
2757         current_start = 0;
2758         window_found = FALSE;
2759         fail_found = FALSE;
2760         pass_found = FALSE;
2761
2762         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2763                 mfsdram(SDRAM_RQDC, rqdc_reg);
2764                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2765
2766                 /*------------------------------------------------------------------
2767                  * Set the timing reg for the test.
2768                  *-----------------------------------------------------------------*/
2769                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2770
2771                 /*------------------------------------------------------------------
2772                  * See if the rffd value passed.
2773                  *-----------------------------------------------------------------*/
2774                 if (short_mem_test()) {
2775                         if (fail_found == TRUE) {
2776                                 pass_found = TRUE;
2777                                 if (current_pass_length == 0)
2778                                         current_start = rqfd;
2779
2780                                 current_fail_length = 0;
2781                                 current_pass_length++;
2782
2783                                 if (current_pass_length > max_pass_length) {
2784                                         max_pass_length = current_pass_length;
2785                                         max_start = current_start;
2786                                         max_end = rqfd;
2787                                 }
2788                         }
2789                 } else {
2790                         current_pass_length = 0;
2791                         current_fail_length++;
2792
2793                         if (fail_found == FALSE) {
2794                                 fail_found = TRUE;
2795                         } else if (pass_found == TRUE) {
2796                                 window_found = TRUE;
2797                                 break;
2798                         }
2799                 }
2800         }
2801
2802         rqfd_average = ((max_start + max_end) >> 1);
2803
2804         /*------------------------------------------------------------------
2805          * Make sure we found the valid read passing window.  Halt if not
2806          *-----------------------------------------------------------------*/
2807         if (window_found == FALSE) {
2808                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2809                         putc('\b');
2810                         putc(slash[loopi++ % 8]);
2811
2812                         /* try again from with a different RQFD start value */
2813                         rqfd_start++;
2814                         goto calibration_loop;
2815                 }
2816
2817                 printf("\nERROR: Cannot determine a common read delay for the "
2818                        "DIMM(s) installed.\n");
2819                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2820                 ppc4xx_ibm_ddr2_register_dump();
2821                 spd_ddr_init_hang ();
2822         }
2823
2824         if (rqfd_average < 0)
2825                 rqfd_average = 0;
2826
2827         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2828                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2829
2830         mtsdram(SDRAM_RQDC,
2831                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2832                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2833
2834         blank_string(strlen(str));
2835 #endif /* CONFIG_DDR_RQDC_FIXED */
2836
2837         /*
2838          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2839          * PowerPC440SP/SPe DDR2 application note:
2840          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2841          */
2842         mfsdram(SDRAM_RTSR, val);
2843         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2844                 mfsdram(SDRAM_RDCC, val);
2845                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2846                         val += 0x40000000;
2847                         mtsdram(SDRAM_RDCC, val);
2848                 }
2849         }
2850
2851         mfsdram(SDRAM_DLCR, val);
2852         debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2853         mfsdram(SDRAM_RQDC, val);
2854         debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2855         mfsdram(SDRAM_RFDC, val);
2856         debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2857         mfsdram(SDRAM_RDCC, val);
2858         debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2859 }
2860 #else /* calibration test with hardvalues */
2861 /*-----------------------------------------------------------------------------+
2862  * DQS_calibration_process.
2863  *-----------------------------------------------------------------------------*/
2864 static void test(void)
2865 {
2866         unsigned long dimm_num;
2867         unsigned long ecc_temp;
2868         unsigned long i, j;
2869         unsigned long *membase;
2870         unsigned long bxcf[MAXRANKS];
2871         unsigned long val;
2872         char window_found;
2873         char begin_found[MAXDIMMS];
2874         char end_found[MAXDIMMS];
2875         char search_end[MAXDIMMS];
2876         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2877                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2878                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2879                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2880                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2881                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2882                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2883                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2884                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2885                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2886                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2887                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2888                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2889                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2890                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2891                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2892                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2893
2894         /*------------------------------------------------------------------
2895          * Test to determine the best read clock delay tuning bits.
2896          *
2897          * Before the DDR controller can be used, the read clock delay needs to be
2898          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2899          * This value cannot be hardcoded into the program because it changes
2900          * depending on the board's setup and environment.
2901          * To do this, all delay values are tested to see if they
2902          * work or not.  By doing this, you get groups of fails with groups of
2903          * passing values.  The idea is to find the start and end of a passing
2904          * window and take the center of it to use as the read clock delay.
2905          *
2906          * A failure has to be seen first so that when we hit a pass, we know
2907          * that it is truely the start of the window.  If we get passing values
2908          * to start off with, we don't know if we are at the start of the window.
2909          *
2910          * The code assumes that a failure will always be found.
2911          * If a failure is not found, there is no easy way to get the middle
2912          * of the passing window.  I guess we can pretty much pick any value
2913          * but some values will be better than others.  Since the lowest speed
2914          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2915          * from experimentation it is safe to say you will always have a failure.
2916          *-----------------------------------------------------------------*/
2917         mfsdram(SDRAM_MCOPT1, ecc_temp);
2918         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2919         mfsdram(SDRAM_MCOPT1, val);
2920         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2921                 SDRAM_MCOPT1_MCHK_NON);
2922
2923         window_found = FALSE;
2924         begin_found[0] = FALSE;
2925         end_found[0] = FALSE;
2926         search_end[0] = FALSE;
2927         begin_found[1] = FALSE;
2928         end_found[1] = FALSE;
2929         search_end[1] = FALSE;
2930
2931         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2932                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2933
2934                 /* Banks enabled */
2935                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2936
2937                         /* Bank is enabled */
2938                         membase =
2939                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2940
2941                         /*------------------------------------------------------------------
2942                          * Run the short memory test.
2943                          *-----------------------------------------------------------------*/
2944                         for (i = 0; i < NUMMEMTESTS; i++) {
2945                                 for (j = 0; j < NUMMEMWORDS; j++) {
2946                                         membase[j] = test[i][j];
2947                                         ppcDcbf((u32)&(membase[j]));
2948                                 }
2949                                 sync();
2950                                 for (j = 0; j < NUMMEMWORDS; j++) {
2951                                         if (membase[j] != test[i][j]) {
2952                                                 ppcDcbf((u32)&(membase[j]));
2953                                                 break;
2954                                         }
2955                                         ppcDcbf((u32)&(membase[j]));
2956                                 }
2957                                 sync();
2958                                 if (j < NUMMEMWORDS)
2959                                         break;
2960                         }
2961
2962                         /*------------------------------------------------------------------
2963                          * See if the rffd value passed.
2964                          *-----------------------------------------------------------------*/
2965                         if (i < NUMMEMTESTS) {
2966                                 if ((end_found[dimm_num] == FALSE) &&
2967                                     (search_end[dimm_num] == TRUE)) {
2968                                         end_found[dimm_num] = TRUE;
2969                                 }
2970                                 if ((end_found[0] == TRUE) &&
2971                                     (end_found[1] == TRUE))
2972                                         break;
2973                         } else {
2974                                 if (begin_found[dimm_num] == FALSE) {
2975                                         begin_found[dimm_num] = TRUE;
2976                                         search_end[dimm_num] = TRUE;
2977                                 }
2978                         }
2979                 } else {
2980                         begin_found[dimm_num] = TRUE;
2981                         end_found[dimm_num] = TRUE;
2982                 }
2983         }
2984
2985         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2986                 window_found = TRUE;
2987
2988         /*------------------------------------------------------------------
2989          * Make sure we found the valid read passing window.  Halt if not
2990          *-----------------------------------------------------------------*/
2991         if (window_found == FALSE) {
2992                 printf("ERROR: Cannot determine a common read delay for the "
2993                        "DIMM(s) installed.\n");
2994                 spd_ddr_init_hang ();
2995         }
2996
2997         /*------------------------------------------------------------------
2998          * Restore the ECC variable to what it originally was
2999          *-----------------------------------------------------------------*/
3000         mtsdram(SDRAM_MCOPT1,
3001                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
3002                 | ecc_temp);
3003 }
3004 #endif
3005
3006 #else /* CONFIG_SPD_EEPROM */
3007
3008 /*-----------------------------------------------------------------------------
3009  * Function:    initdram
3010  * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
3011  *              banks. The configuration is performed using static, compile-
3012  *              time parameters.
3013  *---------------------------------------------------------------------------*/
3014 phys_size_t initdram(int board_type)
3015 {
3016         /*
3017          * Only run this SDRAM init code once. For NAND booting
3018          * targets like Kilauea, we call initdram() early from the
3019          * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
3020          * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
3021          * which calls initdram() again. This time the controller
3022          * mustn't be reconfigured again since we're already running
3023          * from SDRAM.
3024          */
3025 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
3026         unsigned long val;
3027
3028         /* Set Memory Bank Configuration Registers */
3029
3030         mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
3031         mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
3032         mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
3033         mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
3034
3035         /* Set Memory Clock Timing Register */
3036
3037         mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
3038
3039         /* Set Refresh Time Register */
3040
3041         mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
3042
3043         /* Set SDRAM Timing Registers */
3044
3045         mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
3046         mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
3047         mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
3048
3049         /* Set Mode and Extended Mode Registers */
3050
3051         mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
3052         mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
3053
3054         /* Set Memory Controller Options 1 Register */
3055
3056         mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
3057
3058         /* Set Manual Initialization Control Registers */
3059
3060         mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
3061         mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
3062         mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
3063         mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
3064         mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
3065         mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
3066         mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
3067         mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
3068         mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
3069         mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
3070         mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
3071         mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
3072         mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
3073         mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
3074         mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
3075         mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
3076
3077         /* Set On-Die Termination Registers */
3078
3079         mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
3080         mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
3081         mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
3082
3083         /* Set Write Timing Register */
3084
3085         mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
3086
3087         /*
3088          * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
3089          * SDRAM0_MCOPT2[IPTR] = 1
3090          */
3091
3092         mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
3093                                SDRAM_MCOPT2_IPTR_EXECUTE));
3094
3095         /*
3096          * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
3097          * completion of initialization.
3098          */
3099
3100         do {
3101                 mfsdram(SDRAM_MCSTAT, val);
3102         } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
3103
3104         /* Set Delay Control Registers */
3105
3106         mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
3107         mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
3108         mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
3109         mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
3110
3111         /*
3112          * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3113          */
3114
3115         mfsdram(SDRAM_MCOPT2, val);
3116         mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3117
3118 #if defined(CONFIG_DDR_ECC)
3119         ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
3120 #endif /* defined(CONFIG_DDR_ECC) */
3121
3122         ppc4xx_ibm_ddr2_register_dump();
3123 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3124
3125         return (CFG_MBYTES_SDRAM << 20);
3126 }
3127 #endif /* CONFIG_SPD_EEPROM */
3128
3129 static inline void ppc4xx_ibm_ddr2_register_dump(void)
3130 {
3131 #if defined(DEBUG)
3132         printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3133
3134 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3135      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3136         PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS);
3137         PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS);
3138         PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS);
3139         PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS);
3140 #endif /* (defined(CONFIG_440SP) || ... */
3141 #if defined(CONFIG_405EX)
3142         PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3143         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3144         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3145         PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3146         PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3147         PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3148 #endif /* defined(CONFIG_405EX) */
3149         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3150         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3151         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3152         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3153         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3154         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3155         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3156         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3157         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3158         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3159         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3160         PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3161 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3162      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3163         PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3164         PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3165         /*
3166          * OPART is only used as a trigger register.
3167          *
3168          * No data is contained in this register, and reading or writing
3169          * to is can cause bad things to happen (hangs). Just skip it and
3170          * report "N/A".
3171          */
3172         printf("%20s = N/A\n", "SDRAM_OPART");
3173 #endif /* defined(CONFIG_440SP) || ... */
3174         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3175         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3176         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3177         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3178         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3179         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3180         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3181         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3182         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3183         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3184         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3185         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3186         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3187         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3188         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3189         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3190         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3191         PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3192         PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3193         PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3194         PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3195         PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3196         PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3197         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3198         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3199         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3200         PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3201         PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3202         PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
3203 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3204      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3205         PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3206 #endif /* defined(CONFIG_440SP) || ... */
3207         PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3208         PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3209         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3210 #endif /* defined(DEBUG) */
3211 }
3212
3213 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */