2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
12 #include "sequencer_auto.h"
13 #include "sequencer_auto_ac_init.h"
14 #include "sequencer_auto_inst_init.h"
15 #include "sequencer_defines.h"
17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
18 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
21 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
23 static struct socfpga_sdr_reg_file *sdr_reg_file =
24 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
27 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
30 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
33 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
35 static struct socfpga_data_mgr *data_mgr =
36 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
38 static struct socfpga_sdr_ctrl *sdr_ctrl =
39 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
44 * In order to reduce ROM size, most of the selectable calibration steps are
45 * decided at compile time based on the user's calibration mode selection,
46 * as captured by the STATIC_CALIB_STEPS selection below.
48 * However, to support simulation-time selection of fast simulation mode, where
49 * we skip everything except the bare minimum, we need a few of the steps to
50 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
51 * check, which is based on the rtl-supplied value, or we dynamically compute
52 * the value to use based on the dynamically-chosen calibration mode
56 #define STATIC_IN_RTL_SIM 0
57 #define STATIC_SKIP_DELAY_LOOPS 0
59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
60 STATIC_SKIP_DELAY_LOOPS)
62 /* calibration steps requested by the rtl */
63 uint16_t dyn_calib_steps;
66 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
67 * instead of static, we use boolean logic to select between
68 * non-skip and skip values
70 * The mask is set to include all bits when not-skipping, but is
74 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
77 ((non_skip_value) & skip_delay_mask)
80 struct param_type *param;
81 uint32_t curr_shadow_reg;
83 static void set_failing_group_stage(uint32_t group, uint32_t stage,
87 * Only set the global stage if there was not been any other
90 if (gbl->error_stage == CAL_STAGE_NIL) {
91 gbl->error_substage = substage;
92 gbl->error_stage = stage;
93 gbl->error_group = group;
97 static void reg_file_set_group(u16 set_group)
99 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
102 static void reg_file_set_stage(u8 set_stage)
104 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
107 static void reg_file_set_sub_stage(u8 set_sub_stage)
109 set_sub_stage &= 0xff;
110 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
114 * phy_mgr_initialize() - Initialize PHY Manager
116 * Initialize PHY Manager.
118 static void phy_mgr_initialize(void)
122 debug("%s:%d\n", __func__, __LINE__);
123 /* Calibration has control over path to memory */
125 * In Hard PHY this is a 2-bit control:
129 writel(0x3, &phy_mgr_cfg->mux_sel);
131 /* USER memory clock is not stable we begin initialization */
132 writel(0, &phy_mgr_cfg->reset_mem_stbl);
134 /* USER calibration status all set to zero */
135 writel(0, &phy_mgr_cfg->cal_status);
137 writel(0, &phy_mgr_cfg->cal_debug_info);
139 /* Init params only if we do NOT skip calibration. */
140 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
143 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
144 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
145 param->read_correct_mask_vg = (1 << ratio) - 1;
146 param->write_correct_mask_vg = (1 << ratio) - 1;
147 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
148 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
149 ratio = RW_MGR_MEM_DATA_WIDTH /
150 RW_MGR_MEM_DATA_MASK_WIDTH;
151 param->dm_correct_mask = (1 << ratio) - 1;
155 * set_rank_and_odt_mask() - Set Rank and ODT mask
157 * @odt_mode: ODT mode, OFF or READ_WRITE
159 * Set Rank and ODT mask (On-Die Termination).
161 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
167 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
170 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
171 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
173 /* Read: ODT = 0 ; Write: ODT = 1 */
177 case 2: /* 2 Ranks */
178 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
180 * - Dual-Slot , Single-Rank (1 CS per DIMM)
182 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
184 * Since MEM_NUMBER_OF_RANKS is 2, they
185 * are both single rank with 2 CS each
186 * (special for RDIMM).
188 * Read: Turn on ODT on the opposite rank
189 * Write: Turn on ODT on all ranks
191 odt_mask_0 = 0x3 & ~(1 << rank);
195 * - Single-Slot , Dual-Rank (2 CS per DIMM)
197 * Read: Turn on ODT off on all ranks
198 * Write: Turn on ODT on active rank
201 odt_mask_1 = 0x3 & (1 << rank);
204 case 4: /* 4 Ranks */
206 * ----------+-----------------------+
208 * Read From +-----------------------+
209 * Rank | 3 | 2 | 1 | 0 |
210 * ----------+-----+-----+-----+-----+
211 * 0 | 0 | 1 | 0 | 0 |
212 * 1 | 1 | 0 | 0 | 0 |
213 * 2 | 0 | 0 | 0 | 1 |
214 * 3 | 0 | 0 | 1 | 0 |
215 * ----------+-----+-----+-----+-----+
218 * ----------+-----------------------+
220 * Write To +-----------------------+
221 * Rank | 3 | 2 | 1 | 0 |
222 * ----------+-----+-----+-----+-----+
223 * 0 | 0 | 1 | 0 | 1 |
224 * 1 | 1 | 0 | 1 | 0 |
225 * 2 | 0 | 1 | 0 | 1 |
226 * 3 | 1 | 0 | 1 | 0 |
227 * ----------+-----+-----+-----+-----+
251 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
252 ((0xFF & odt_mask_0) << 8) |
253 ((0xFF & odt_mask_1) << 16);
254 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
255 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
259 * scc_mgr_set() - Set SCC Manager register
260 * @off: Base offset in SCC Manager space
261 * @grp: Read/Write group
262 * @val: Value to be set
264 * This function sets the SCC Manager (Scan Chain Control Manager) register.
266 static void scc_mgr_set(u32 off, u32 grp, u32 val)
268 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
272 * scc_mgr_initialize() - Initialize SCC Manager registers
274 * Initialize SCC Manager registers.
276 static void scc_mgr_initialize(void)
279 * Clear register file for HPS. 16 (2^4) is the size of the
280 * full register file in the scc mgr:
281 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
282 * MEM_IF_READ_DQS_WIDTH - 1);
286 for (i = 0; i < 16; i++) {
287 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
288 __func__, __LINE__, i);
289 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
293 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
295 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
298 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
300 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
303 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
305 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
308 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
310 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
313 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
315 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
319 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
321 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
324 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
326 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
329 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
331 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
335 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
337 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
338 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
342 /* load up dqs config settings */
343 static void scc_mgr_load_dqs(uint32_t dqs)
345 writel(dqs, &sdr_scc_mgr->dqs_ena);
348 /* load up dqs io config settings */
349 static void scc_mgr_load_dqs_io(void)
351 writel(0, &sdr_scc_mgr->dqs_io_ena);
354 /* load up dq config settings */
355 static void scc_mgr_load_dq(uint32_t dq_in_group)
357 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
360 /* load up dm config settings */
361 static void scc_mgr_load_dm(uint32_t dm)
363 writel(dm, &sdr_scc_mgr->dm_ena);
367 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
368 * @off: Base offset in SCC Manager space
369 * @grp: Read/Write group
370 * @val: Value to be set
371 * @update: If non-zero, trigger SCC Manager update for all ranks
373 * This function sets the SCC Manager (Scan Chain Control Manager) register
374 * and optionally triggers the SCC update for all ranks.
376 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
381 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
382 r += NUM_RANKS_PER_SHADOW_REG) {
383 scc_mgr_set(off, grp, val);
385 if (update || (r == 0)) {
386 writel(grp, &sdr_scc_mgr->dqs_ena);
387 writel(0, &sdr_scc_mgr->update);
392 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
395 * USER although the h/w doesn't support different phases per
396 * shadow register, for simplicity our scc manager modeling
397 * keeps different phase settings per shadow reg, and it's
398 * important for us to keep them in sync to match h/w.
399 * for efficiency, the scan chain update should occur only
402 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
403 read_group, phase, 0);
406 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
410 * USER although the h/w doesn't support different phases per
411 * shadow register, for simplicity our scc manager modeling
412 * keeps different phase settings per shadow reg, and it's
413 * important for us to keep them in sync to match h/w.
414 * for efficiency, the scan chain update should occur only
417 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
418 write_group, phase, 0);
421 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
425 * In shadow register mode, the T11 settings are stored in
426 * registers in the core, which are updated by the DQS_ENA
427 * signals. Not issuing the SCC_MGR_UPD command allows us to
428 * save lots of rank switching overhead, by calling
429 * select_shadow_regs_for_update with update_scan_chains
432 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
433 read_group, delay, 1);
434 writel(0, &sdr_scc_mgr->update);
438 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
439 * @write_group: Write group
440 * @delay: Delay value
442 * This function sets the OCT output delay in SCC manager.
444 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
446 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
447 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
448 const int base = write_group * ratio;
451 * Load the setting in the SCC manager
452 * Although OCT affects only write data, the OCT delay is controlled
453 * by the DQS logic block which is instantiated once per read group.
454 * For protocols where a write group consists of multiple read groups,
455 * the setting must be set multiple times.
457 for (i = 0; i < ratio; i++)
458 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
462 * scc_mgr_set_hhp_extras() - Set HHP extras.
464 * Load the fixed setting in the SCC manager HHP extras.
466 static void scc_mgr_set_hhp_extras(void)
469 * Load the fixed setting in the SCC manager
470 * bits: 0:0 = 1'b1 - DQS bypass
471 * bits: 1:1 = 1'b1 - DQ bypass
472 * bits: 4:2 = 3'b001 - rfifo_mode
473 * bits: 6:5 = 2'b01 - rfifo clock_select
474 * bits: 7:7 = 1'b0 - separate gating from ungating setting
475 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
477 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
478 (1 << 2) | (1 << 1) | (1 << 0);
479 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
480 SCC_MGR_HHP_GLOBALS_OFFSET |
481 SCC_MGR_HHP_EXTRAS_OFFSET;
483 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
486 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
491 * scc_mgr_zero_all() - Zero all DQS config
493 * Zero all DQS config.
495 static void scc_mgr_zero_all(void)
500 * USER Zero all DQS config settings, across all groups and all
503 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
504 r += NUM_RANKS_PER_SHADOW_REG) {
505 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
507 * The phases actually don't exist on a per-rank basis,
508 * but there's no harm updating them several times, so
509 * let's keep the code simple.
511 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
512 scc_mgr_set_dqs_en_phase(i, 0);
513 scc_mgr_set_dqs_en_delay(i, 0);
516 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
517 scc_mgr_set_dqdqs_output_phase(i, 0);
518 /* Arria V/Cyclone V don't have out2. */
519 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
523 /* Multicast to all DQS group enables. */
524 writel(0xff, &sdr_scc_mgr->dqs_ena);
525 writel(0, &sdr_scc_mgr->update);
529 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
530 * @write_group: Write group
532 * Set bypass mode and trigger SCC update.
534 static void scc_set_bypass_mode(const u32 write_group)
536 /* Multicast to all DQ enables. */
537 writel(0xff, &sdr_scc_mgr->dq_ena);
538 writel(0xff, &sdr_scc_mgr->dm_ena);
540 /* Update current DQS IO enable. */
541 writel(0, &sdr_scc_mgr->dqs_io_ena);
543 /* Update the DQS logic. */
544 writel(write_group, &sdr_scc_mgr->dqs_ena);
547 writel(0, &sdr_scc_mgr->update);
551 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
552 * @write_group: Write group
554 * Load DQS settings for Write Group, do not trigger SCC update.
556 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
558 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
559 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
560 const int base = write_group * ratio;
563 * Load the setting in the SCC manager
564 * Although OCT affects only write data, the OCT delay is controlled
565 * by the DQS logic block which is instantiated once per read group.
566 * For protocols where a write group consists of multiple read groups,
567 * the setting must be set multiple times.
569 for (i = 0; i < ratio; i++)
570 writel(base + i, &sdr_scc_mgr->dqs_ena);
574 * scc_mgr_zero_group() - Zero all configs for a group
576 * Zero DQ, DM, DQS and OCT configs for a group.
578 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
582 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
583 r += NUM_RANKS_PER_SHADOW_REG) {
584 /* Zero all DQ config settings. */
585 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
586 scc_mgr_set_dq_out1_delay(i, 0);
588 scc_mgr_set_dq_in_delay(i, 0);
591 /* Multicast to all DQ enables. */
592 writel(0xff, &sdr_scc_mgr->dq_ena);
594 /* Zero all DM config settings. */
595 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
596 scc_mgr_set_dm_out1_delay(i, 0);
598 /* Multicast to all DM enables. */
599 writel(0xff, &sdr_scc_mgr->dm_ena);
601 /* Zero all DQS IO settings. */
603 scc_mgr_set_dqs_io_in_delay(0);
605 /* Arria V/Cyclone V don't have out2. */
606 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
607 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
608 scc_mgr_load_dqs_for_write_group(write_group);
610 /* Multicast to all DQS IO enables (only 1 in total). */
611 writel(0, &sdr_scc_mgr->dqs_io_ena);
613 /* Hit update to zero everything. */
614 writel(0, &sdr_scc_mgr->update);
619 * apply and load a particular input delay for the DQ pins in a group
620 * group_bgn is the index of the first dq pin (in the write group)
622 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
626 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
627 scc_mgr_set_dq_in_delay(p, delay);
633 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
634 * @delay: Delay value
636 * Apply and load a particular output delay for the DQ pins in a group.
638 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
642 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
643 scc_mgr_set_dq_out1_delay(i, delay);
648 /* apply and load a particular output delay for the DM pins in a group */
649 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
653 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
654 scc_mgr_set_dm_out1_delay(i, delay1);
660 /* apply and load delay on both DQS and OCT out1 */
661 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
664 scc_mgr_set_dqs_out1_delay(delay);
665 scc_mgr_load_dqs_io();
667 scc_mgr_set_oct_out1_delay(write_group, delay);
668 scc_mgr_load_dqs_for_write_group(write_group);
672 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
673 * @write_group: Write group
674 * @delay: Delay value
676 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
678 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
684 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
688 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
692 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
693 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
694 debug_cond(DLEVEL == 1,
695 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
696 __func__, __LINE__, write_group, delay, new_delay,
697 IO_IO_OUT2_DELAY_MAX,
698 new_delay - IO_IO_OUT2_DELAY_MAX);
699 new_delay -= IO_IO_OUT2_DELAY_MAX;
700 scc_mgr_set_dqs_out1_delay(new_delay);
703 scc_mgr_load_dqs_io();
706 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
707 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
708 debug_cond(DLEVEL == 1,
709 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
710 __func__, __LINE__, write_group, delay,
711 new_delay, IO_IO_OUT2_DELAY_MAX,
712 new_delay - IO_IO_OUT2_DELAY_MAX);
713 new_delay -= IO_IO_OUT2_DELAY_MAX;
714 scc_mgr_set_oct_out1_delay(write_group, new_delay);
717 scc_mgr_load_dqs_for_write_group(write_group);
721 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
722 * @write_group: Write group
723 * @delay: Delay value
725 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
728 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
733 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
734 r += NUM_RANKS_PER_SHADOW_REG) {
735 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
736 writel(0, &sdr_scc_mgr->update);
741 * set_jump_as_return() - Return instruction optimization
743 * Optimization used to recover some slots in ddr3 inst_rom could be
744 * applied to other protocols if we wanted to
746 static void set_jump_as_return(void)
749 * To save space, we replace return with jump to special shared
750 * RETURN instruction so we set the counter to large value so that
753 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
754 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
758 * should always use constants as argument to ensure all computations are
759 * performed at compile time
761 static void delay_for_n_mem_clocks(const u32 clocks)
768 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
770 /* Scale (rounding up) to get afi clocks. */
771 afi_clocks = DIV_ROUND_UP(clocks, AFI_RATE_RATIO);
772 if (afi_clocks) /* Temporary underflow protection */
776 * Note, we don't bother accounting for being off a little
777 * bit because of a few extra instructions in outer loops.
778 * Note, the loops have a test at the end, and do the test
779 * before the decrement, and so always perform the loop
780 * 1 time more than the counter value
782 c_loop = afi_clocks >> 16;
783 outer = c_loop ? 0xff : (afi_clocks >> 8);
784 inner = outer ? 0xff : afi_clocks;
787 * rom instructions are structured as follows:
789 * IDLE_LOOP2: jnz cntr0, TARGET_A
790 * IDLE_LOOP1: jnz cntr1, TARGET_B
793 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
794 * TARGET_B is set to IDLE_LOOP2 as well
796 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
797 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
799 * a little confusing, but it helps save precious space in the inst_rom
800 * and sequencer rom and keeps the delays more accurate and reduces
803 if (afi_clocks < 0x100) {
804 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
805 &sdr_rw_load_mgr_regs->load_cntr1);
807 writel(RW_MGR_IDLE_LOOP1,
808 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
810 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
811 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
813 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
814 &sdr_rw_load_mgr_regs->load_cntr0);
816 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
817 &sdr_rw_load_mgr_regs->load_cntr1);
819 writel(RW_MGR_IDLE_LOOP2,
820 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
822 writel(RW_MGR_IDLE_LOOP2,
823 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
826 writel(RW_MGR_IDLE_LOOP2,
827 SDR_PHYGRP_RWMGRGRP_ADDRESS |
828 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
829 } while (c_loop-- != 0);
831 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
835 * rw_mgr_mem_init_load_regs() - Load instruction registers
836 * @cntr0: Counter 0 value
837 * @cntr1: Counter 1 value
838 * @cntr2: Counter 2 value
839 * @jump: Jump instruction value
841 * Load instruction registers.
843 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
845 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
846 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
849 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
850 &sdr_rw_load_mgr_regs->load_cntr0);
851 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
852 &sdr_rw_load_mgr_regs->load_cntr1);
853 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
854 &sdr_rw_load_mgr_regs->load_cntr2);
856 /* Load jump address */
857 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
858 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
859 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
861 /* Execute count instruction */
862 writel(jump, grpaddr);
866 * rw_mgr_mem_load_user() - Load user calibration values
867 * @fin1: Final instruction 1
868 * @fin2: Final instruction 2
869 * @precharge: If 1, precharge the banks at the end
871 * Load user calibration values and optionally precharge the banks.
873 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
876 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
877 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
880 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
881 if (param->skip_ranks[r]) {
882 /* request to skip the rank */
887 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
889 /* precharge all banks ... */
891 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
894 * USER Use Mirror-ed commands for odd ranks if address
897 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
898 set_jump_as_return();
899 writel(RW_MGR_MRS2_MIRR, grpaddr);
900 delay_for_n_mem_clocks(4);
901 set_jump_as_return();
902 writel(RW_MGR_MRS3_MIRR, grpaddr);
903 delay_for_n_mem_clocks(4);
904 set_jump_as_return();
905 writel(RW_MGR_MRS1_MIRR, grpaddr);
906 delay_for_n_mem_clocks(4);
907 set_jump_as_return();
908 writel(fin1, grpaddr);
910 set_jump_as_return();
911 writel(RW_MGR_MRS2, grpaddr);
912 delay_for_n_mem_clocks(4);
913 set_jump_as_return();
914 writel(RW_MGR_MRS3, grpaddr);
915 delay_for_n_mem_clocks(4);
916 set_jump_as_return();
917 writel(RW_MGR_MRS1, grpaddr);
918 set_jump_as_return();
919 writel(fin2, grpaddr);
925 set_jump_as_return();
926 writel(RW_MGR_ZQCL, grpaddr);
928 /* tZQinit = tDLLK = 512 ck cycles */
929 delay_for_n_mem_clocks(512);
934 * rw_mgr_mem_initialize() - Initialize RW Manager
936 * Initialize RW Manager.
938 static void rw_mgr_mem_initialize(void)
940 debug("%s:%d\n", __func__, __LINE__);
942 /* The reset / cke part of initialization is broadcasted to all ranks */
943 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
944 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
947 * Here's how you load register for a loop
948 * Counters are located @ 0x800
949 * Jump address are located @ 0xC00
950 * For both, registers 0 to 3 are selected using bits 3 and 2, like
951 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
952 * I know this ain't pretty, but Avalon bus throws away the 2 least
956 /* Start with memory RESET activated */
961 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
962 * If a and b are the number of iteration in 2 nested loops
963 * it takes the following number of cycles to complete the operation:
964 * number_of_cycles = ((2 + n) * a + 2) * b
965 * where n is the number of instruction in the inner loop
966 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
969 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
971 RW_MGR_INIT_RESET_0_CKE_0);
973 /* Indicate that memory is stable. */
974 writel(1, &phy_mgr_cfg->reset_mem_stbl);
977 * transition the RESET to high
982 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
983 * If a and b are the number of iteration in 2 nested loops
984 * it takes the following number of cycles to complete the operation
985 * number_of_cycles = ((2 + n) * a + 2) * b
986 * where n is the number of instruction in the inner loop
987 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
990 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
991 SEQ_TRESET_CNTR2_VAL,
992 RW_MGR_INIT_RESET_1_CKE_0);
994 /* Bring up clock enable. */
996 /* tXRP < 250 ck cycles */
997 delay_for_n_mem_clocks(250);
999 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1004 * rw_mgr_mem_handoff() - Hand off the memory to user
1006 * At the end of calibration we have to program the user settings in
1007 * and hand off the memory to the user.
1009 static void rw_mgr_mem_handoff(void)
1011 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1013 * Need to wait tMOD (12CK or 15ns) time before issuing other
1014 * commands, but we will have plenty of NIOS cycles before actual
1015 * handoff so its okay.
1020 * rw_mgr_mem_calibrate_write_test_issue() - Issue write test command
1021 * @group: Write Group
1024 * Issue write test command. Two variants are provided, one that just tests
1025 * a write pattern and another that tests datamask functionality.
1027 static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
1030 const u32 quick_write_mode =
1031 (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) &&
1032 ENABLE_SUPER_QUICK_CALIBRATION;
1033 u32 mcc_instruction;
1034 u32 rw_wl_nop_cycles;
1037 * Set counter and jump addresses for the right
1038 * number of NOP cycles.
1039 * The number of supported NOP cycles can range from -1 to infinity
1040 * Three different cases are handled:
1042 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
1043 * mechanism will be used to insert the right number of NOPs
1045 * 2. For a number of NOP cycles equals to 0, the micro-instruction
1046 * issuing the write command will jump straight to the
1047 * micro-instruction that turns on DQS (for DDRx), or outputs write
1048 * data (for RLD), skipping
1049 * the NOP micro-instruction all together
1051 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
1052 * turned on in the same micro-instruction that issues the write
1053 * command. Then we need
1054 * to directly jump to the micro-instruction that sends out the data
1056 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
1057 * (2 and 3). One jump-counter (0) is used to perform multiple
1058 * write-read operations.
1059 * one counter left to issue this command in "multiple-group" mode
1062 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
1064 if (rw_wl_nop_cycles == -1) {
1066 * CNTR 2 - We want to execute the special write operation that
1067 * turns on DQS right away and then skip directly to the
1068 * instruction that sends out the data. We set the counter to a
1069 * large number so that the jump is always taken.
1071 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1073 /* CNTR 3 - Not used */
1075 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
1076 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
1077 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1078 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
1079 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1081 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
1082 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
1083 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1084 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
1085 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1087 } else if (rw_wl_nop_cycles == 0) {
1089 * CNTR 2 - We want to skip the NOP operation and go straight
1090 * to the DQS enable instruction. We set the counter to a large
1091 * number so that the jump is always taken.
1093 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1095 /* CNTR 3 - Not used */
1097 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
1098 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
1099 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1101 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
1102 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
1103 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1107 * CNTR 2 - In this case we want to execute the next instruction
1108 * and NOT take the jump. So we set the counter to 0. The jump
1109 * address doesn't count.
1111 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
1112 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1115 * CNTR 3 - Set the nop counter to the number of cycles we
1116 * need to loop for, minus 1.
1118 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
1120 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
1121 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
1122 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1124 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
1125 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
1126 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1130 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1131 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1133 if (quick_write_mode)
1134 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
1136 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
1138 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1141 * CNTR 1 - This is used to ensure enough time elapses
1142 * for read data to come back.
1144 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
1147 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
1148 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1150 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
1151 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1154 writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS |
1155 RW_MGR_RUN_SINGLE_GROUP_OFFSET) +
1160 * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple pass
1161 * @rank_bgn: Rank number
1162 * @write_group: Write Group
1164 * @all_correct: All bits must be correct in the mask
1165 * @bit_chk: Resulting bit mask after the test
1166 * @all_ranks: Test all ranks
1168 * Test writes, can check for a single bit pass or multiple bit pass.
1171 rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
1172 const u32 use_dm, const u32 all_correct,
1173 u32 *bit_chk, const u32 all_ranks)
1175 const u32 rank_end = all_ranks ?
1176 RW_MGR_MEM_NUMBER_OF_RANKS :
1177 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1178 const u32 shift_ratio = RW_MGR_MEM_DQ_PER_WRITE_DQS /
1179 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS;
1180 const u32 correct_mask_vg = param->write_correct_mask_vg;
1182 u32 tmp_bit_chk, base_rw_mgr;
1185 *bit_chk = param->write_correct_mask;
1187 for (r = rank_bgn; r < rank_end; r++) {
1188 /* Request to skip the rank */
1189 if (param->skip_ranks[r])
1193 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1196 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS - 1;
1198 /* Reset the FIFOs to get pointers to known state. */
1199 writel(0, &phy_mgr_cmd->fifo_reset);
1201 rw_mgr_mem_calibrate_write_test_issue(
1203 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS + vg,
1206 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1207 tmp_bit_chk <<= shift_ratio;
1208 tmp_bit_chk |= (correct_mask_vg & ~(base_rw_mgr));
1211 *bit_chk &= tmp_bit_chk;
1214 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1216 debug_cond(DLEVEL == 2,
1217 "write_test(%u,%u,ALL) : %u == %u => %i\n",
1218 write_group, use_dm, *bit_chk,
1219 param->write_correct_mask,
1220 *bit_chk == param->write_correct_mask);
1221 return *bit_chk == param->write_correct_mask;
1223 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1224 debug_cond(DLEVEL == 2,
1225 "write_test(%u,%u,ONE) : %u != %i => %i\n",
1226 write_group, use_dm, *bit_chk, 0, *bit_chk != 0);
1227 return *bit_chk != 0x00;
1232 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1233 * @rank_bgn: Rank number
1234 * @group: Read/Write Group
1235 * @all_ranks: Test all ranks
1237 * Performs a guaranteed read on the patterns we are going to use during a
1238 * read test to ensure memory works.
1241 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1242 const u32 all_ranks)
1244 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1245 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1246 const u32 addr_offset =
1247 (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1248 const u32 rank_end = all_ranks ?
1249 RW_MGR_MEM_NUMBER_OF_RANKS :
1250 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1251 const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1252 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1253 const u32 correct_mask_vg = param->read_correct_mask_vg;
1255 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1259 bit_chk = param->read_correct_mask;
1261 for (r = rank_bgn; r < rank_end; r++) {
1262 /* Request to skip the rank */
1263 if (param->skip_ranks[r])
1267 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1269 /* Load up a constant bursts of read commands */
1270 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1271 writel(RW_MGR_GUARANTEED_READ,
1272 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1274 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1275 writel(RW_MGR_GUARANTEED_READ_CONT,
1276 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1279 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1281 /* Reset the FIFOs to get pointers to known state. */
1282 writel(0, &phy_mgr_cmd->fifo_reset);
1283 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1284 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1285 writel(RW_MGR_GUARANTEED_READ,
1286 addr + addr_offset + (vg << 2));
1288 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1289 tmp_bit_chk <<= shift_ratio;
1290 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1293 bit_chk &= tmp_bit_chk;
1296 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1298 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1300 if (bit_chk != param->read_correct_mask)
1303 debug_cond(DLEVEL == 1,
1304 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1305 __func__, __LINE__, group, bit_chk,
1306 param->read_correct_mask, ret);
1312 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1313 * @rank_bgn: Rank number
1314 * @all_ranks: Test all ranks
1316 * Load up the patterns we are going to use during a read test.
1318 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1319 const int all_ranks)
1321 const u32 rank_end = all_ranks ?
1322 RW_MGR_MEM_NUMBER_OF_RANKS :
1323 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1326 debug("%s:%d\n", __func__, __LINE__);
1328 for (r = rank_bgn; r < rank_end; r++) {
1329 if (param->skip_ranks[r])
1330 /* request to skip the rank */
1334 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1336 /* Load up a constant bursts */
1337 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1339 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1340 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1342 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1344 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1345 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1347 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1349 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1350 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1352 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1354 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1355 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1357 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1358 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1361 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1365 * rw_mgr_mem_calibrate_read_test() - Perform READ test on single rank
1366 * @rank_bgn: Rank number
1367 * @group: Read/Write group
1368 * @num_tries: Number of retries of the test
1369 * @all_correct: All bits must be correct in the mask
1370 * @bit_chk: Resulting bit mask after the test
1371 * @all_groups: Test all R/W groups
1372 * @all_ranks: Test all ranks
1374 * Try a read and see if it returns correct data back. Test has dummy reads
1375 * inserted into the mix used to align DQS enable. Test has more thorough
1376 * checks than the regular read test.
1379 rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
1380 const u32 num_tries, const u32 all_correct,
1382 const u32 all_groups, const u32 all_ranks)
1384 const u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1385 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1386 const u32 quick_read_mode =
1387 ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
1388 ENABLE_SUPER_QUICK_CALIBRATION);
1389 u32 correct_mask_vg = param->read_correct_mask_vg;
1396 *bit_chk = param->read_correct_mask;
1398 for (r = rank_bgn; r < rank_end; r++) {
1399 if (param->skip_ranks[r])
1400 /* request to skip the rank */
1404 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1406 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1408 writel(RW_MGR_READ_B2B_WAIT1,
1409 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1411 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1412 writel(RW_MGR_READ_B2B_WAIT2,
1413 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1415 if (quick_read_mode)
1416 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1417 /* need at least two (1+1) reads to capture failures */
1418 else if (all_groups)
1419 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1421 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1423 writel(RW_MGR_READ_B2B,
1424 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1426 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1427 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1428 &sdr_rw_load_mgr_regs->load_cntr3);
1430 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1432 writel(RW_MGR_READ_B2B,
1433 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1436 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1; vg >= 0;
1438 /* Reset the FIFOs to get pointers to known state. */
1439 writel(0, &phy_mgr_cmd->fifo_reset);
1440 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1441 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1444 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1445 RW_MGR_RUN_ALL_GROUPS_OFFSET;
1447 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1448 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1451 writel(RW_MGR_READ_B2B, addr +
1452 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1455 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1456 tmp_bit_chk <<= RW_MGR_MEM_DQ_PER_READ_DQS /
1457 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1458 tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
1461 *bit_chk &= tmp_bit_chk;
1464 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1465 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1467 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1470 ret = (*bit_chk == param->read_correct_mask);
1471 debug_cond(DLEVEL == 2,
1472 "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1473 __func__, __LINE__, group, all_groups, *bit_chk,
1474 param->read_correct_mask, ret);
1476 ret = (*bit_chk != 0x00);
1477 debug_cond(DLEVEL == 2,
1478 "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1479 __func__, __LINE__, group, all_groups, *bit_chk,
1487 * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1488 * @grp: Read/Write group
1489 * @num_tries: Number of retries of the test
1490 * @all_correct: All bits must be correct in the mask
1491 * @all_groups: Test all R/W groups
1493 * Perform a READ test across all memory ranks.
1496 rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries,
1497 const u32 all_correct,
1498 const u32 all_groups)
1501 return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct,
1502 &bit_chk, all_groups, 1);
1506 * rw_mgr_incr_vfifo() - Increase VFIFO value
1507 * @grp: Read/Write group
1509 * Increase VFIFO value.
1511 static void rw_mgr_incr_vfifo(const u32 grp)
1513 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1517 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1518 * @grp: Read/Write group
1520 * Decrease VFIFO value.
1522 static void rw_mgr_decr_vfifo(const u32 grp)
1526 for (i = 0; i < VFIFO_SIZE - 1; i++)
1527 rw_mgr_incr_vfifo(grp);
1531 * find_vfifo_failing_read() - Push VFIFO to get a failing read
1532 * @grp: Read/Write group
1534 * Push VFIFO until a failing read happens.
1536 static int find_vfifo_failing_read(const u32 grp)
1538 u32 v, ret, fail_cnt = 0;
1540 for (v = 0; v < VFIFO_SIZE; v++) {
1541 debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
1542 __func__, __LINE__, v);
1543 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1552 /* Fiddle with FIFO. */
1553 rw_mgr_incr_vfifo(grp);
1556 /* No failing read found! Something must have gone wrong. */
1557 debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1562 * sdr_find_phase_delay() - Find DQS enable phase or delay
1563 * @working: If 1, look for working phase/delay, if 0, look for non-working
1564 * @delay: If 1, look for delay, if 0, look for phase
1565 * @grp: Read/Write group
1566 * @work: Working window position
1567 * @work_inc: Working window increment
1568 * @pd: DQS Phase/Delay Iterator
1570 * Find working or non-working DQS enable phase setting.
1572 static int sdr_find_phase_delay(int working, int delay, const u32 grp,
1573 u32 *work, const u32 work_inc, u32 *pd)
1575 const u32 max = delay ? IO_DQS_EN_DELAY_MAX : IO_DQS_EN_PHASE_MAX;
1578 for (; *pd <= max; (*pd)++) {
1580 scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd);
1582 scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
1584 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1599 * sdr_find_phase() - Find DQS enable phase
1600 * @working: If 1, look for working phase, if 0, look for non-working phase
1601 * @grp: Read/Write group
1602 * @work: Working window position
1604 * @p: DQS Phase Iterator
1606 * Find working or non-working DQS enable phase setting.
1608 static int sdr_find_phase(int working, const u32 grp, u32 *work,
1611 const u32 end = VFIFO_SIZE + (working ? 0 : 1);
1614 for (; *i < end; (*i)++) {
1618 ret = sdr_find_phase_delay(working, 0, grp, work,
1619 IO_DELAY_PER_OPA_TAP, p);
1623 if (*p > IO_DQS_EN_PHASE_MAX) {
1624 /* Fiddle with FIFO. */
1625 rw_mgr_incr_vfifo(grp);
1635 * sdr_working_phase() - Find working DQS enable phase
1636 * @grp: Read/Write group
1637 * @work_bgn: Working window start position
1638 * @d: dtaps output value
1639 * @p: DQS Phase Iterator
1642 * Find working DQS enable phase setting.
1644 static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
1647 const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
1648 IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1653 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1655 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1656 ret = sdr_find_phase(1, grp, work_bgn, i, p);
1659 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1662 /* Cannot find working solution */
1663 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1664 __func__, __LINE__);
1669 * sdr_backup_phase() - Find DQS enable backup phase
1670 * @grp: Read/Write group
1671 * @work_bgn: Working window start position
1672 * @p: DQS Phase Iterator
1674 * Find DQS enable backup phase setting.
1676 static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
1681 /* Special case code for backing up a phase */
1683 *p = IO_DQS_EN_PHASE_MAX;
1684 rw_mgr_decr_vfifo(grp);
1688 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1689 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1691 for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
1692 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1694 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1697 *work_bgn = tmp_delay;
1701 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1704 /* Restore VFIFO to old state before we decremented it (if needed). */
1706 if (*p > IO_DQS_EN_PHASE_MAX) {
1708 rw_mgr_incr_vfifo(grp);
1711 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1715 * sdr_nonworking_phase() - Find non-working DQS enable phase
1716 * @grp: Read/Write group
1717 * @work_end: Working window end position
1718 * @p: DQS Phase Iterator
1721 * Find non-working DQS enable phase setting.
1723 static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
1728 *work_end += IO_DELAY_PER_OPA_TAP;
1729 if (*p > IO_DQS_EN_PHASE_MAX) {
1730 /* Fiddle with FIFO. */
1732 rw_mgr_incr_vfifo(grp);
1735 ret = sdr_find_phase(0, grp, work_end, i, p);
1737 /* Cannot see edge of failing read. */
1738 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1739 __func__, __LINE__);
1746 * sdr_find_window_center() - Find center of the working DQS window.
1747 * @grp: Read/Write group
1748 * @work_bgn: First working settings
1749 * @work_end: Last working settings
1751 * Find center of the working DQS enable window.
1753 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1760 work_mid = (work_bgn + work_end) / 2;
1762 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1763 work_bgn, work_end, work_mid);
1764 /* Get the middle delay to be less than a VFIFO delay */
1765 tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1767 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1768 work_mid %= tmp_delay;
1769 debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1771 tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1772 if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1773 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1774 p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1776 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1778 d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1779 if (d > IO_DQS_EN_DELAY_MAX)
1780 d = IO_DQS_EN_DELAY_MAX;
1781 tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1783 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1785 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1786 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1789 * push vfifo until we can successfully calibrate. We can do this
1790 * because the largest possible margin in 1 VFIFO cycle.
1792 for (i = 0; i < VFIFO_SIZE; i++) {
1793 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
1794 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1797 debug_cond(DLEVEL == 2,
1798 "%s:%d center: found: ptap=%u dtap=%u\n",
1799 __func__, __LINE__, p, d);
1803 /* Fiddle with FIFO. */
1804 rw_mgr_incr_vfifo(grp);
1807 debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1808 __func__, __LINE__);
1813 * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
1814 * @grp: Read/Write Group
1816 * Find a good DQS enable to use.
1818 static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
1822 u32 work_bgn, work_end;
1823 u32 found_passing_read, found_failing_read, initial_failing_dtap;
1826 debug("%s:%d %u\n", __func__, __LINE__, grp);
1828 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1830 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1831 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1833 /* Step 0: Determine number of delay taps for each phase tap. */
1834 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1836 /* Step 1: First push vfifo until we get a failing read. */
1837 find_vfifo_failing_read(grp);
1839 /* Step 2: Find first working phase, increment in ptaps. */
1841 ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i);
1845 work_end = work_bgn;
1848 * If d is 0 then the working window covers a phase tap and we can
1849 * follow the old procedure. Otherwise, we've found the beginning
1850 * and we need to increment the dtaps until we find the end.
1854 * Step 3a: If we have room, back off by one and
1855 * increment in dtaps.
1857 sdr_backup_phase(grp, &work_bgn, &p);
1860 * Step 4a: go forward from working phase to non working
1861 * phase, increment in ptaps.
1863 ret = sdr_nonworking_phase(grp, &work_end, &p, &i);
1867 /* Step 5a: Back off one from last, increment in dtaps. */
1869 /* Special case code for backing up a phase */
1871 p = IO_DQS_EN_PHASE_MAX;
1872 rw_mgr_decr_vfifo(grp);
1877 work_end -= IO_DELAY_PER_OPA_TAP;
1878 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1882 debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
1883 __func__, __LINE__, p);
1886 /* The dtap increment to find the failing edge is done here. */
1887 sdr_find_phase_delay(0, 1, grp, &work_end,
1888 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, &d);
1890 /* Go back to working dtap */
1892 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1894 debug_cond(DLEVEL == 2,
1895 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1896 __func__, __LINE__, p, d - 1, work_end);
1898 if (work_end < work_bgn) {
1900 debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
1901 __func__, __LINE__);
1905 debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
1906 __func__, __LINE__, work_bgn, work_end);
1909 * We need to calculate the number of dtaps that equal a ptap.
1910 * To do that we'll back up a ptap and re-find the edge of the
1911 * window using dtaps
1913 debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1914 __func__, __LINE__);
1916 /* Special case code for backing up a phase */
1918 p = IO_DQS_EN_PHASE_MAX;
1919 rw_mgr_decr_vfifo(grp);
1920 debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
1921 __func__, __LINE__, p);
1924 debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
1925 __func__, __LINE__, p);
1928 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1931 * Increase dtap until we first see a passing read (in case the
1932 * window is smaller than a ptap), and then a failing read to
1933 * mark the edge of the window again.
1936 /* Find a passing read. */
1937 debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
1938 __func__, __LINE__);
1940 initial_failing_dtap = d;
1942 found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
1943 if (found_passing_read) {
1944 /* Find a failing read. */
1945 debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
1946 __func__, __LINE__);
1948 found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
1951 debug_cond(DLEVEL == 1,
1952 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1953 __func__, __LINE__);
1957 * The dynamically calculated dtaps_per_ptap is only valid if we
1958 * found a passing/failing read. If we didn't, it means d hit the max
1959 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1960 * statically calculated value.
1962 if (found_passing_read && found_failing_read)
1963 dtaps_per_ptap = d - initial_failing_dtap;
1965 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1966 debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1967 __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
1969 /* Step 6: Find the centre of the window. */
1970 ret = sdr_find_window_center(grp, work_bgn, work_end);
1976 * search_stop_check() - Check if the detected edge is valid
1977 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1979 * @rank_bgn: Rank number
1980 * @write_group: Write Group
1981 * @read_group: Read Group
1982 * @bit_chk: Resulting bit mask after the test
1983 * @sticky_bit_chk: Resulting sticky bit mask after the test
1984 * @use_read_test: Perform read test
1986 * Test if the found edge is valid.
1988 static u32 search_stop_check(const int write, const int d, const int rank_bgn,
1989 const u32 write_group, const u32 read_group,
1990 u32 *bit_chk, u32 *sticky_bit_chk,
1991 const u32 use_read_test)
1993 const u32 ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
1994 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
1995 const u32 correct_mask = write ? param->write_correct_mask :
1996 param->read_correct_mask;
1997 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
1998 RW_MGR_MEM_DQ_PER_READ_DQS;
2001 * Stop searching when the read test doesn't pass AND when
2002 * we've seen a passing read on every bit.
2004 if (write) { /* WRITE-ONLY */
2005 ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2008 } else if (use_read_test) { /* READ-ONLY */
2009 ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group,
2011 PASS_ONE_BIT, bit_chk,
2013 } else { /* READ-ONLY */
2014 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0,
2015 PASS_ONE_BIT, bit_chk, 0);
2016 *bit_chk = *bit_chk >> (per_dqs *
2017 (read_group - (write_group * ratio)));
2018 ret = (*bit_chk == 0);
2020 *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
2021 ret = ret && (*sticky_bit_chk == correct_mask);
2022 debug_cond(DLEVEL == 2,
2023 "%s:%d center(left): dtap=%u => %u == %u && %u",
2024 __func__, __LINE__, d,
2025 *sticky_bit_chk, correct_mask, ret);
2030 * search_left_edge() - Find left edge of DQ/DQS working phase
2031 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2032 * @rank_bgn: Rank number
2033 * @write_group: Write Group
2034 * @read_group: Read Group
2035 * @test_bgn: Rank number to begin the test
2036 * @sticky_bit_chk: Resulting sticky bit mask after the test
2037 * @left_edge: Left edge of the DQ/DQS phase
2038 * @right_edge: Right edge of the DQ/DQS phase
2039 * @use_read_test: Perform read test
2041 * Find left edge of DQ/DQS working phase.
2043 static void search_left_edge(const int write, const int rank_bgn,
2044 const u32 write_group, const u32 read_group, const u32 test_bgn,
2045 u32 *sticky_bit_chk,
2046 int *left_edge, int *right_edge, const u32 use_read_test)
2048 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
2049 const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
2050 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2051 RW_MGR_MEM_DQ_PER_READ_DQS;
2055 for (d = 0; d <= dqs_max; d++) {
2057 scc_mgr_apply_group_dq_out1_delay(d);
2059 scc_mgr_apply_group_dq_in_delay(test_bgn, d);
2061 writel(0, &sdr_scc_mgr->update);
2063 stop = search_stop_check(write, d, rank_bgn, write_group,
2064 read_group, &bit_chk, sticky_bit_chk,
2070 for (i = 0; i < per_dqs; i++) {
2073 * Remember a passing test as
2079 * If a left edge has not been seen
2080 * yet, then a future passing test
2081 * will mark this edge as the right
2084 if (left_edge[i] == delay_max + 1)
2085 right_edge[i] = -(d + 1);
2091 /* Reset DQ delay chains to 0 */
2093 scc_mgr_apply_group_dq_out1_delay(0);
2095 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2097 *sticky_bit_chk = 0;
2098 for (i = per_dqs - 1; i >= 0; i--) {
2099 debug_cond(DLEVEL == 2,
2100 "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
2101 __func__, __LINE__, i, left_edge[i],
2105 * Check for cases where we haven't found the left edge,
2106 * which makes our assignment of the the right edge invalid.
2107 * Reset it to the illegal value.
2109 if ((left_edge[i] == delay_max + 1) &&
2110 (right_edge[i] != delay_max + 1)) {
2111 right_edge[i] = delay_max + 1;
2112 debug_cond(DLEVEL == 2,
2113 "%s:%d vfifo_center: reset right_edge[%u]: %d\n",
2114 __func__, __LINE__, i, right_edge[i]);
2119 * READ: except for bits where we have seen both
2120 * the left and right edge.
2121 * WRITE: except for bits where we have seen the
2124 *sticky_bit_chk <<= 1;
2126 if (left_edge[i] != delay_max + 1)
2127 *sticky_bit_chk |= 1;
2129 if ((left_edge[i] != delay_max + 1) &&
2130 (right_edge[i] != delay_max + 1))
2131 *sticky_bit_chk |= 1;
2139 * search_right_edge() - Find right edge of DQ/DQS working phase
2140 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2141 * @rank_bgn: Rank number
2142 * @write_group: Write Group
2143 * @read_group: Read Group
2144 * @start_dqs: DQS start phase
2145 * @start_dqs_en: DQS enable start phase
2146 * @sticky_bit_chk: Resulting sticky bit mask after the test
2147 * @left_edge: Left edge of the DQ/DQS phase
2148 * @right_edge: Right edge of the DQ/DQS phase
2149 * @use_read_test: Perform read test
2151 * Find right edge of DQ/DQS working phase.
2153 static int search_right_edge(const int write, const int rank_bgn,
2154 const u32 write_group, const u32 read_group,
2155 const int start_dqs, const int start_dqs_en,
2156 u32 *sticky_bit_chk,
2157 int *left_edge, int *right_edge, const u32 use_read_test)
2159 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
2160 const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
2161 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2162 RW_MGR_MEM_DQ_PER_READ_DQS;
2166 for (d = 0; d <= dqs_max - start_dqs; d++) {
2167 if (write) { /* WRITE-ONLY */
2168 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2170 } else { /* READ-ONLY */
2171 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
2172 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2173 uint32_t delay = d + start_dqs_en;
2174 if (delay > IO_DQS_EN_DELAY_MAX)
2175 delay = IO_DQS_EN_DELAY_MAX;
2176 scc_mgr_set_dqs_en_delay(read_group, delay);
2178 scc_mgr_load_dqs(read_group);
2181 writel(0, &sdr_scc_mgr->update);
2183 stop = search_stop_check(write, d, rank_bgn, write_group,
2184 read_group, &bit_chk, sticky_bit_chk,
2187 if (write && (d == 0)) { /* WRITE-ONLY */
2188 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2190 * d = 0 failed, but it passed when
2191 * testing the left edge, so it must be
2192 * marginal, set it to -1
2194 if (right_edge[i] == delay_max + 1 &&
2195 left_edge[i] != delay_max + 1)
2203 for (i = 0; i < per_dqs; i++) {
2206 * Remember a passing test as
2213 * If a right edge has not
2214 * been seen yet, then a future
2215 * passing test will mark this
2216 * edge as the left edge.
2218 if (right_edge[i] == delay_max + 1)
2219 left_edge[i] = -(d + 1);
2222 * d = 0 failed, but it passed
2223 * when testing the left edge,
2224 * so it must be marginal, set
2227 if (right_edge[i] == delay_max + 1 &&
2228 left_edge[i] != delay_max + 1)
2231 * If a right edge has not been
2232 * seen yet, then a future
2233 * passing test will mark this
2234 * edge as the left edge.
2236 else if (right_edge[i] == delay_max + 1)
2237 left_edge[i] = -(d + 1);
2241 debug_cond(DLEVEL == 2, "%s:%d center[r,d=%u]: ",
2242 __func__, __LINE__, d);
2243 debug_cond(DLEVEL == 2,
2244 "bit_chk_test=%i left_edge[%u]: %d ",
2245 bit_chk & 1, i, left_edge[i]);
2246 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2252 /* Check that all bits have a window */
2253 for (i = 0; i < per_dqs; i++) {
2254 debug_cond(DLEVEL == 2,
2255 "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
2256 __func__, __LINE__, i, left_edge[i],
2258 if ((left_edge[i] == dqs_max + 1) ||
2259 (right_edge[i] == dqs_max + 1))
2260 return i + 1; /* FIXME: If we fail, retval > 0 */
2267 * get_window_mid_index() - Find the best middle setting of DQ/DQS phase
2268 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2269 * @left_edge: Left edge of the DQ/DQS phase
2270 * @right_edge: Right edge of the DQ/DQS phase
2271 * @mid_min: Best DQ/DQS phase middle setting
2273 * Find index and value of the middle of the DQ/DQS working phase.
2275 static int get_window_mid_index(const int write, int *left_edge,
2276 int *right_edge, int *mid_min)
2278 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2279 RW_MGR_MEM_DQ_PER_READ_DQS;
2280 int i, mid, min_index;
2282 /* Find middle of window for each DQ bit */
2283 *mid_min = left_edge[0] - right_edge[0];
2285 for (i = 1; i < per_dqs; i++) {
2286 mid = left_edge[i] - right_edge[i];
2287 if (mid < *mid_min) {
2294 * -mid_min/2 represents the amount that we need to move DQS.
2295 * If mid_min is odd and positive we'll need to add one to make
2296 * sure the rounding in further calculations is correct (always
2297 * bias to the right), so just add 1 for all positive values.
2301 *mid_min = *mid_min / 2;
2303 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
2304 __func__, __LINE__, *mid_min, min_index);
2309 * center_dq_windows() - Center the DQ/DQS windows
2310 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2311 * @left_edge: Left edge of the DQ/DQS phase
2312 * @right_edge: Right edge of the DQ/DQS phase
2313 * @mid_min: Adjusted DQ/DQS phase middle setting
2314 * @orig_mid_min: Original DQ/DQS phase middle setting
2315 * @min_index: DQ/DQS phase middle setting index
2316 * @test_bgn: Rank number to begin the test
2317 * @dq_margin: Amount of shift for the DQ
2318 * @dqs_margin: Amount of shift for the DQS
2320 * Align the DQ/DQS windows in each group.
2322 static void center_dq_windows(const int write, int *left_edge, int *right_edge,
2323 const int mid_min, const int orig_mid_min,
2324 const int min_index, const int test_bgn,
2325 int *dq_margin, int *dqs_margin)
2327 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
2328 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2329 RW_MGR_MEM_DQ_PER_READ_DQS;
2330 const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
2331 SCC_MGR_IO_IN_DELAY_OFFSET;
2332 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
2334 u32 temp_dq_io_delay1, temp_dq_io_delay2;
2337 /* Initialize data for export structures */
2338 *dqs_margin = delay_max + 1;
2339 *dq_margin = delay_max + 1;
2341 /* add delay to bring centre of all DQ windows to the same "level" */
2342 for (i = 0, p = test_bgn; i < per_dqs; i++, p++) {
2343 /* Use values before divide by 2 to reduce round off error */
2344 shift_dq = (left_edge[i] - right_edge[i] -
2345 (left_edge[min_index] - right_edge[min_index]))/2 +
2346 (orig_mid_min - mid_min);
2348 debug_cond(DLEVEL == 2,
2349 "vfifo_center: before: shift_dq[%u]=%d\n",
2352 temp_dq_io_delay1 = readl(addr + (p << 2));
2353 temp_dq_io_delay2 = readl(addr + (i << 2));
2355 if (shift_dq + temp_dq_io_delay1 > delay_max)
2356 shift_dq = delay_max - temp_dq_io_delay2;
2357 else if (shift_dq + temp_dq_io_delay1 < 0)
2358 shift_dq = -temp_dq_io_delay1;
2360 debug_cond(DLEVEL == 2,
2361 "vfifo_center: after: shift_dq[%u]=%d\n",
2365 scc_mgr_set_dq_out1_delay(i, temp_dq_io_delay1 + shift_dq);
2367 scc_mgr_set_dq_in_delay(p, temp_dq_io_delay1 + shift_dq);
2371 debug_cond(DLEVEL == 2,
2372 "vfifo_center: margin[%u]=[%d,%d]\n", i,
2373 left_edge[i] - shift_dq + (-mid_min),
2374 right_edge[i] + shift_dq - (-mid_min));
2376 /* To determine values for export structures */
2377 if (left_edge[i] - shift_dq + (-mid_min) < *dq_margin)
2378 *dq_margin = left_edge[i] - shift_dq + (-mid_min);
2380 if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin)
2381 *dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2387 * rw_mgr_mem_calibrate_vfifo_center() - Per-bit deskew DQ and centering
2388 * @rank_bgn: Rank number
2389 * @rw_group: Read/Write Group
2390 * @test_bgn: Rank at which the test begins
2391 * @use_read_test: Perform a read test
2392 * @update_fom: Update FOM
2394 * Per-bit deskew DQ and centering.
2396 static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
2397 const u32 rw_group, const u32 test_bgn,
2398 const int use_read_test, const int update_fom)
2401 SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET +
2404 * Store these as signed since there are comparisons with
2407 uint32_t sticky_bit_chk;
2408 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
2409 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
2410 int32_t orig_mid_min, mid_min;
2411 int32_t new_dqs, start_dqs, start_dqs_en, final_dqs_en;
2412 int32_t dq_margin, dqs_margin;
2416 debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn);
2418 start_dqs = readl(addr);
2419 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2420 start_dqs_en = readl(addr - IO_DQS_EN_DELAY_OFFSET);
2422 /* set the left and right edge of each bit to an illegal value */
2423 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
2425 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2426 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
2427 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
2430 /* Search for the left edge of the window for each bit */
2431 search_left_edge(0, rank_bgn, rw_group, rw_group, test_bgn,
2433 left_edge, right_edge, use_read_test);
2436 /* Search for the right edge of the window for each bit */
2437 ret = search_right_edge(0, rank_bgn, rw_group, rw_group,
2438 start_dqs, start_dqs_en,
2440 left_edge, right_edge, use_read_test);
2443 * Restore delay chain settings before letting the loop
2444 * in rw_mgr_mem_calibrate_vfifo to retry different
2445 * dqs/ck relationships.
2447 scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs);
2448 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2449 scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en);
2451 scc_mgr_load_dqs(rw_group);
2452 writel(0, &sdr_scc_mgr->update);
2454 debug_cond(DLEVEL == 1,
2455 "%s:%d vfifo_center: failed to find edge [%u]: %d %d",
2456 __func__, __LINE__, i, left_edge[i], right_edge[i]);
2457 if (use_read_test) {
2458 set_failing_group_stage(rw_group *
2459 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2461 CAL_SUBSTAGE_VFIFO_CENTER);
2463 set_failing_group_stage(rw_group *
2464 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2465 CAL_STAGE_VFIFO_AFTER_WRITES,
2466 CAL_SUBSTAGE_VFIFO_CENTER);
2471 min_index = get_window_mid_index(0, left_edge, right_edge, &mid_min);
2473 /* Determine the amount we can change DQS (which is -mid_min) */
2474 orig_mid_min = mid_min;
2475 new_dqs = start_dqs - mid_min;
2476 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2477 new_dqs = IO_DQS_IN_DELAY_MAX;
2478 else if (new_dqs < 0)
2481 mid_min = start_dqs - new_dqs;
2482 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2485 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2486 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2487 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2488 else if (start_dqs_en - mid_min < 0)
2489 mid_min += start_dqs_en - mid_min;
2491 new_dqs = start_dqs - mid_min;
2493 debug_cond(DLEVEL == 1,
2494 "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
2496 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2499 /* Add delay to bring centre of all DQ windows to the same "level". */
2500 center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min,
2501 min_index, test_bgn, &dq_margin, &dqs_margin);
2504 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2505 final_dqs_en = start_dqs_en - mid_min;
2506 scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en);
2507 scc_mgr_load_dqs(rw_group);
2511 scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs);
2512 scc_mgr_load_dqs(rw_group);
2513 debug_cond(DLEVEL == 2,
2514 "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
2515 __func__, __LINE__, dq_margin, dqs_margin);
2518 * Do not remove this line as it makes sure all of our decisions
2519 * have been applied. Apply the update bit.
2521 writel(0, &sdr_scc_mgr->update);
2523 if ((dq_margin < 0) || (dqs_margin < 0))
2530 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2531 * @rw_group: Read/Write Group
2532 * @phase: DQ/DQS phase
2534 * Because initially no communication ca be reliably performed with the memory
2535 * device, the sequencer uses a guaranteed write mechanism to write data into
2536 * the memory device.
2538 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2543 /* Set a particular DQ/DQS phase. */
2544 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2546 debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2547 __func__, __LINE__, rw_group, phase);
2550 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2551 * Load up the patterns used by read calibration using the
2552 * current DQDQS phase.
2554 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2556 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2560 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2561 * Back-to-Back reads of the patterns used for calibration.
2563 ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2565 debug_cond(DLEVEL == 1,
2566 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2567 __func__, __LINE__, rw_group, phase);
2572 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2573 * @rw_group: Read/Write Group
2574 * @test_bgn: Rank at which the test begins
2576 * DQS enable calibration ensures reliable capture of the DQ signal without
2577 * glitches on the DQS line.
2579 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2583 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2584 * DQS and DQS Eanble Signal Relationships.
2587 /* We start at zero, so have one less dq to devide among */
2588 const u32 delay_step = IO_IO_IN_DELAY_MAX /
2589 (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2593 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2595 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2596 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2597 r += NUM_RANKS_PER_SHADOW_REG) {
2598 for (i = 0, p = test_bgn, d = 0;
2599 i < RW_MGR_MEM_DQ_PER_READ_DQS;
2600 i++, p++, d += delay_step) {
2601 debug_cond(DLEVEL == 1,
2602 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2603 __func__, __LINE__, rw_group, r, i, p, d);
2605 scc_mgr_set_dq_in_delay(p, d);
2609 writel(0, &sdr_scc_mgr->update);
2613 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2614 * dq_in_delay values
2616 ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2618 debug_cond(DLEVEL == 1,
2619 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2620 __func__, __LINE__, rw_group, !ret);
2622 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2623 r += NUM_RANKS_PER_SHADOW_REG) {
2624 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2625 writel(0, &sdr_scc_mgr->update);
2632 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2633 * @rw_group: Read/Write Group
2634 * @test_bgn: Rank at which the test begins
2635 * @use_read_test: Perform a read test
2636 * @update_fom: Update FOM
2638 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2642 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2643 const int use_read_test,
2644 const int update_fom)
2647 int ret, grp_calibrated;
2651 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2652 * Read per-bit deskew can be done on a per shadow register basis.
2655 for (rank_bgn = 0, sr = 0;
2656 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2657 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2658 /* Check if this set of ranks should be skipped entirely. */
2659 if (param->skip_shadow_regs[sr])
2662 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2672 if (!grp_calibrated)
2679 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2680 * @rw_group: Read/Write Group
2681 * @test_bgn: Rank at which the test begins
2683 * Stage 1: Calibrate the read valid prediction FIFO.
2685 * This function implements UniPHY calibration Stage 1, as explained in
2686 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2688 * - read valid prediction will consist of finding:
2689 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2690 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2691 * - we also do a per-bit deskew on the DQ lines.
2693 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2696 uint32_t dtaps_per_ptap;
2697 uint32_t failed_substage;
2701 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2703 /* Update info for sims */
2704 reg_file_set_group(rw_group);
2705 reg_file_set_stage(CAL_STAGE_VFIFO);
2706 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2708 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2710 /* USER Determine number of delay taps for each phase tap. */
2711 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2712 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2714 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2716 * In RLDRAMX we may be messing the delay of pins in
2717 * the same write rw_group but outside of the current read
2718 * the rw_group, but that's ok because we haven't calibrated
2722 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2726 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2727 /* 1) Guaranteed Write */
2728 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2732 /* 2) DQS Enable Calibration */
2733 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2736 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2740 /* 3) Centering DQ/DQS */
2742 * If doing read after write calibration, do not update
2743 * FOM now. Do it then.
2745 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2748 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2757 /* Calibration Stage 1 failed. */
2758 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2761 /* Calibration Stage 1 completed OK. */
2764 * Reset the delay chains back to zero if they have moved > 1
2765 * (check for > 1 because loop will increase d even when pass in
2769 scc_mgr_zero_group(rw_group, 1);
2775 * rw_mgr_mem_calibrate_vfifo_end() - DQ/DQS Centering.
2776 * @rw_group: Read/Write Group
2777 * @test_bgn: Rank at which the test begins
2779 * Stage 3: DQ/DQS Centering.
2781 * This function implements UniPHY calibration Stage 3, as explained in
2782 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2784 static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group,
2789 debug("%s:%d %u %u", __func__, __LINE__, rw_group, test_bgn);
2791 /* Update info for sims. */
2792 reg_file_set_group(rw_group);
2793 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2794 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2796 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, test_bgn, 0, 1);
2798 set_failing_group_stage(rw_group,
2799 CAL_STAGE_VFIFO_AFTER_WRITES,
2800 CAL_SUBSTAGE_VFIFO_CENTER);
2805 * rw_mgr_mem_calibrate_lfifo() - Minimize latency
2807 * Stage 4: Minimize latency.
2809 * This function implements UniPHY calibration Stage 4, as explained in
2810 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2811 * Calibrate LFIFO to find smallest read latency.
2813 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2817 debug("%s:%d\n", __func__, __LINE__);
2819 /* Update info for sims. */
2820 reg_file_set_stage(CAL_STAGE_LFIFO);
2821 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2823 /* Load up the patterns used by read calibration for all ranks */
2824 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2827 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2828 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2829 __func__, __LINE__, gbl->curr_read_lat);
2831 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS,
2837 * Reduce read latency and see if things are
2838 * working correctly.
2840 gbl->curr_read_lat--;
2841 } while (gbl->curr_read_lat > 0);
2843 /* Reset the fifos to get pointers to known state. */
2844 writel(0, &phy_mgr_cmd->fifo_reset);
2847 /* Add a fudge factor to the read latency that was determined */
2848 gbl->curr_read_lat += 2;
2849 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2850 debug_cond(DLEVEL == 2,
2851 "%s:%d lfifo: success: using read_lat=%u\n",
2852 __func__, __LINE__, gbl->curr_read_lat);
2854 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2855 CAL_SUBSTAGE_READ_LATENCY);
2857 debug_cond(DLEVEL == 2,
2858 "%s:%d lfifo: failed at initial read_lat=%u\n",
2859 __func__, __LINE__, gbl->curr_read_lat);
2866 * search_window() - Search for the/part of the window with DM/DQS shift
2867 * @search_dm: If 1, search for the DM shift, if 0, search for DQS shift
2868 * @rank_bgn: Rank number
2869 * @write_group: Write Group
2870 * @bgn_curr: Current window begin
2871 * @end_curr: Current window end
2872 * @bgn_best: Current best window begin
2873 * @end_best: Current best window end
2874 * @win_best: Size of the best window
2875 * @new_dqs: New DQS value (only applicable if search_dm = 0).
2877 * Search for the/part of the window with DM/DQS shift.
2879 static void search_window(const int search_dm,
2880 const u32 rank_bgn, const u32 write_group,
2881 int *bgn_curr, int *end_curr, int *bgn_best,
2882 int *end_best, int *win_best, int new_dqs)
2885 const int max = IO_IO_OUT1_DELAY_MAX - new_dqs;
2888 /* Search for the/part of the window with DM/DQS shift. */
2889 for (di = max; di >= 0; di -= DELTA_D) {
2892 scc_mgr_apply_group_dm_out1_delay(d);
2894 /* For DQS, we go from 0...max */
2897 * Note: This only shifts DQS, so are we limiting ourselve to
2898 * width of DQ unnecessarily.
2900 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2904 writel(0, &sdr_scc_mgr->update);
2906 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2907 PASS_ALL_BITS, &bit_chk,
2909 /* Set current end of the window. */
2910 *end_curr = search_dm ? -d : d;
2913 * If a starting edge of our window has not been seen
2914 * this is our current start of the DM window.
2916 if (*bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
2917 *bgn_curr = search_dm ? -d : d;
2920 * If current window is bigger than best seen.
2921 * Set best seen to be current window.
2923 if ((*end_curr - *bgn_curr + 1) > *win_best) {
2924 *win_best = *end_curr - *bgn_curr + 1;
2925 *bgn_best = *bgn_curr;
2926 *end_best = *end_curr;
2929 /* We just saw a failing test. Reset temp edge. */
2930 *bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2931 *end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2933 /* Early exit is only applicable to DQS. */
2938 * Early exit optimization: if the remaining delay
2939 * chain space is less than already seen largest
2940 * window we can exit.
2942 if (*win_best - 1 > IO_IO_OUT1_DELAY_MAX - new_dqs - d)
2949 * rw_mgr_mem_calibrate_writes_center() - Center all windows
2950 * @rank_bgn: Rank number
2951 * @write_group: Write group
2952 * @test_bgn: Rank at which the test begins
2954 * Center all windows. Do per-bit-deskew to possibly increase size of
2958 rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
2964 int left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2965 int right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2967 int mid_min, orig_mid_min;
2968 int new_dqs, start_dqs;
2969 int dq_margin, dqs_margin, dm_margin;
2970 int bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2971 int end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2972 int bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2973 int end_best = IO_IO_OUT1_DELAY_MAX + 1;
2978 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2982 start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
2983 SCC_MGR_IO_OUT1_DELAY_OFFSET) +
2984 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2986 /* Per-bit deskew. */
2989 * Set the left and right edge of each bit to an illegal value.
2990 * Use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2993 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2994 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2995 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2998 /* Search for the left edge of the window for each bit. */
2999 search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
3001 left_edge, right_edge, 0);
3003 /* Search for the right edge of the window for each bit. */
3004 ret = search_right_edge(1, rank_bgn, write_group, 0,
3007 left_edge, right_edge, 0);
3009 set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
3010 CAL_SUBSTAGE_WRITES_CENTER);
3014 min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min);
3016 /* Determine the amount we can change DQS (which is -mid_min). */
3017 orig_mid_min = mid_min;
3018 new_dqs = start_dqs;
3020 debug_cond(DLEVEL == 1,
3021 "%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
3022 __func__, __LINE__, start_dqs, new_dqs, mid_min);
3024 /* Add delay to bring centre of all DQ windows to the same "level". */
3025 center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min,
3026 min_index, 0, &dq_margin, &dqs_margin);
3029 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3030 writel(0, &sdr_scc_mgr->update);
3033 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3036 * Set the left and right edge of each bit to an illegal value.
3037 * Use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
3039 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3040 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3042 /* Search for the/part of the window with DM shift. */
3043 search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr,
3044 &bgn_best, &end_best, &win_best, 0);
3046 /* Reset DM delay chains to 0. */
3047 scc_mgr_apply_group_dm_out1_delay(0);
3050 * Check to see if the current window nudges up aganist 0 delay.
3051 * If so we need to continue the search by shifting DQS otherwise DQS
3052 * search begins as a new search.
3054 if (end_curr != 0) {
3055 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3056 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3059 /* Search for the/part of the window with DQS shifts. */
3060 search_window(0, rank_bgn, write_group, &bgn_curr, &end_curr,
3061 &bgn_best, &end_best, &win_best, new_dqs);
3063 /* Assign left and right edge for cal and reporting. */
3064 left_edge[0] = -1 * bgn_best;
3065 right_edge[0] = end_best;
3067 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n",
3068 __func__, __LINE__, left_edge[0], right_edge[0]);
3070 /* Move DQS (back to orig). */
3071 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3075 /* Find middle of window for the DM bit. */
3076 mid = (left_edge[0] - right_edge[0]) / 2;
3078 /* Only move right, since we are not moving DQS/DQ. */
3082 /* dm_marign should fail if we never find a window. */
3086 dm_margin = left_edge[0] - mid;
3088 scc_mgr_apply_group_dm_out1_delay(mid);
3089 writel(0, &sdr_scc_mgr->update);
3091 debug_cond(DLEVEL == 2,
3092 "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
3093 __func__, __LINE__, left_edge[0], right_edge[0],
3095 /* Export values. */
3096 gbl->fom_out += dq_margin + dqs_margin;
3098 debug_cond(DLEVEL == 2,
3099 "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
3100 __func__, __LINE__, dq_margin, dqs_margin, dm_margin);
3103 * Do not remove this line as it makes sure all of our
3104 * decisions have been applied.
3106 writel(0, &sdr_scc_mgr->update);
3108 if ((dq_margin < 0) || (dqs_margin < 0) || (dm_margin < 0))
3115 * rw_mgr_mem_calibrate_writes() - Write Calibration Part One
3116 * @rank_bgn: Rank number
3117 * @group: Read/Write Group
3118 * @test_bgn: Rank at which the test begins
3120 * Stage 2: Write Calibration Part One.
3122 * This function implements UniPHY calibration Stage 2, as explained in
3123 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
3125 static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group,
3130 /* Update info for sims */
3131 debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn);
3133 reg_file_set_group(group);
3134 reg_file_set_stage(CAL_STAGE_WRITES);
3135 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3137 ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
3139 set_failing_group_stage(group, CAL_STAGE_WRITES,
3140 CAL_SUBSTAGE_WRITES_CENTER);
3146 * mem_precharge_and_activate() - Precharge all banks and activate
3148 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3150 static void mem_precharge_and_activate(void)
3154 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3155 /* Test if the rank should be skipped. */
3156 if (param->skip_ranks[r])
3160 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3162 /* Precharge all banks. */
3163 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3164 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3166 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3167 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3168 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3170 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3171 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3172 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3174 /* Activate rows. */
3175 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3176 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3181 * mem_init_latency() - Configure memory RLAT and WLAT settings
3183 * Configure memory RLAT and WLAT parameters.
3185 static void mem_init_latency(void)
3188 * For AV/CV, LFIFO is hardened and always runs at full rate
3189 * so max latency in AFI clocks, used here, is correspondingly
3192 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3195 debug("%s:%d\n", __func__, __LINE__);
3198 * Read in write latency.
3199 * WL for Hard PHY does not include additive latency.
3201 wlat = readl(&data_mgr->t_wl_add);
3202 wlat += readl(&data_mgr->mem_t_add);
3204 gbl->rw_wl_nop_cycles = wlat - 1;
3206 /* Read in readl latency. */
3207 rlat = readl(&data_mgr->t_rl_add);
3209 /* Set a pretty high read latency initially. */
3210 gbl->curr_read_lat = rlat + 16;
3211 if (gbl->curr_read_lat > max_latency)
3212 gbl->curr_read_lat = max_latency;
3214 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3216 /* Advertise write latency. */
3217 writel(wlat, &phy_mgr_cfg->afi_wlat);
3221 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3223 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3225 static void mem_skip_calibrate(void)
3227 uint32_t vfifo_offset;
3230 debug("%s:%d\n", __func__, __LINE__);
3231 /* Need to update every shadow register set used by the interface */
3232 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3233 r += NUM_RANKS_PER_SHADOW_REG) {
3235 * Set output phase alignment settings appropriate for
3238 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3239 scc_mgr_set_dqs_en_phase(i, 0);
3240 #if IO_DLL_CHAIN_LENGTH == 6
3241 scc_mgr_set_dqdqs_output_phase(i, 6);
3243 scc_mgr_set_dqdqs_output_phase(i, 7);
3248 * Write data arrives to the I/O two cycles before write
3249 * latency is reached (720 deg).
3250 * -> due to bit-slip in a/c bus
3251 * -> to allow board skew where dqs is longer than ck
3252 * -> how often can this happen!?
3253 * -> can claim back some ptaps for high freq
3254 * support if we can relax this, but i digress...
3256 * The write_clk leads mem_ck by 90 deg
3257 * The minimum ptap of the OPA is 180 deg
3258 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3259 * The write_clk is always delayed by 2 ptaps
3261 * Hence, to make DQS aligned to CK, we need to delay
3263 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3265 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3266 * gives us the number of ptaps, which simplies to:
3268 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3270 scc_mgr_set_dqdqs_output_phase(i,
3271 1.25 * IO_DLL_CHAIN_LENGTH - 2);
3273 writel(0xff, &sdr_scc_mgr->dqs_ena);
3274 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3276 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3277 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3278 SCC_MGR_GROUP_COUNTER_OFFSET);
3280 writel(0xff, &sdr_scc_mgr->dq_ena);
3281 writel(0xff, &sdr_scc_mgr->dm_ena);
3282 writel(0, &sdr_scc_mgr->update);
3285 /* Compensate for simulation model behaviour */
3286 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3287 scc_mgr_set_dqs_bus_in_delay(i, 10);
3288 scc_mgr_load_dqs(i);
3290 writel(0, &sdr_scc_mgr->update);
3293 * ArriaV has hard FIFOs that can only be initialized by incrementing
3296 vfifo_offset = CALIB_VFIFO_OFFSET;
3297 for (j = 0; j < vfifo_offset; j++)
3298 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3299 writel(0, &phy_mgr_cmd->fifo_reset);
3302 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3303 * setting from generation-time constant.
3305 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3306 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3310 * mem_calibrate() - Memory calibration entry point.
3312 * Perform memory calibration.
3314 static uint32_t mem_calibrate(void)
3317 uint32_t rank_bgn, sr;
3318 uint32_t write_group, write_test_bgn;
3319 uint32_t read_group, read_test_bgn;
3320 uint32_t run_groups, current_run;
3321 uint32_t failing_groups = 0;
3322 uint32_t group_failed = 0;
3324 const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3325 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3327 debug("%s:%d\n", __func__, __LINE__);
3329 /* Initialize the data settings */
3330 gbl->error_substage = CAL_SUBSTAGE_NIL;
3331 gbl->error_stage = CAL_STAGE_NIL;
3332 gbl->error_group = 0xff;
3336 /* Initialize WLAT and RLAT. */
3339 /* Initialize bit slips. */
3340 mem_precharge_and_activate();
3342 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3343 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3344 SCC_MGR_GROUP_COUNTER_OFFSET);
3345 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3347 scc_mgr_set_hhp_extras();
3349 scc_set_bypass_mode(i);
3352 /* Calibration is skipped. */
3353 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3355 * Set VFIFO and LFIFO to instant-on settings in skip
3358 mem_skip_calibrate();
3361 * Do not remove this line as it makes sure all of our
3362 * decisions have been applied.
3364 writel(0, &sdr_scc_mgr->update);
3368 /* Calibration is not skipped. */
3369 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3371 * Zero all delay chain/phase settings for all
3372 * groups and all shadow register sets.
3376 run_groups = ~param->skip_groups;
3378 for (write_group = 0, write_test_bgn = 0; write_group
3379 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3380 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3382 /* Initialize the group failure */
3385 current_run = run_groups & ((1 <<
3386 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3387 run_groups = run_groups >>
3388 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3390 if (current_run == 0)
3393 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3394 SCC_MGR_GROUP_COUNTER_OFFSET);
3395 scc_mgr_zero_group(write_group, 0);
3397 for (read_group = write_group * rwdqs_ratio,
3399 read_group < (write_group + 1) * rwdqs_ratio;
3401 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3402 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3405 /* Calibrate the VFIFO */
3406 if (rw_mgr_mem_calibrate_vfifo(read_group,
3410 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3413 /* The group failed, we're done. */
3417 /* Calibrate the output side */
3418 for (rank_bgn = 0, sr = 0;
3419 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3420 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3421 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3424 /* Not needed in quick mode! */
3425 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3429 * Determine if this set of ranks
3430 * should be skipped entirely.
3432 if (param->skip_shadow_regs[sr])
3435 /* Calibrate WRITEs */
3436 if (!rw_mgr_mem_calibrate_writes(rank_bgn,
3437 write_group, write_test_bgn))
3441 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3445 /* Some group failed, we're done. */
3449 for (read_group = write_group * rwdqs_ratio,
3451 read_group < (write_group + 1) * rwdqs_ratio;
3453 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3454 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3457 if (!rw_mgr_mem_calibrate_vfifo_end(read_group,
3461 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3464 /* The group failed, we're done. */
3468 /* No group failed, continue as usual. */
3471 grp_failed: /* A group failed, increment the counter. */
3476 * USER If there are any failing groups then report
3479 if (failing_groups != 0)
3482 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3486 * If we're skipping groups as part of debug,
3487 * don't calibrate LFIFO.
3489 if (param->skip_groups != 0)
3492 /* Calibrate the LFIFO */
3493 if (!rw_mgr_mem_calibrate_lfifo())
3498 * Do not remove this line as it makes sure all of our decisions
3499 * have been applied.
3501 writel(0, &sdr_scc_mgr->update);
3506 * run_mem_calibrate() - Perform memory calibration
3508 * This function triggers the entire memory calibration procedure.
3510 static int run_mem_calibrate(void)
3514 debug("%s:%d\n", __func__, __LINE__);
3516 /* Reset pass/fail status shown on afi_cal_success/fail */
3517 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3519 /* Stop tracking manager. */
3520 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3522 phy_mgr_initialize();
3523 rw_mgr_mem_initialize();
3525 /* Perform the actual memory calibration. */
3526 pass = mem_calibrate();
3528 mem_precharge_and_activate();
3529 writel(0, &phy_mgr_cmd->fifo_reset);
3532 rw_mgr_mem_handoff();
3534 * In Hard PHY this is a 2-bit control:
3536 * 1: DDIO Mux Select
3538 writel(0x2, &phy_mgr_cfg->mux_sel);
3540 /* Start tracking manager. */
3541 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3547 * debug_mem_calibrate() - Report result of memory calibration
3548 * @pass: Value indicating whether calibration passed or failed
3550 * This function reports the results of the memory calibration
3551 * and writes debug information into the register file.
3553 static void debug_mem_calibrate(int pass)
3555 uint32_t debug_info;
3558 printf("%s: CALIBRATION PASSED\n", __FILE__);
3563 if (gbl->fom_in > 0xff)
3566 if (gbl->fom_out > 0xff)
3567 gbl->fom_out = 0xff;
3569 /* Update the FOM in the register file */
3570 debug_info = gbl->fom_in;
3571 debug_info |= gbl->fom_out << 8;
3572 writel(debug_info, &sdr_reg_file->fom);
3574 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3575 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3577 printf("%s: CALIBRATION FAILED\n", __FILE__);
3579 debug_info = gbl->error_stage;
3580 debug_info |= gbl->error_substage << 8;
3581 debug_info |= gbl->error_group << 16;
3583 writel(debug_info, &sdr_reg_file->failing_stage);
3584 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3585 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3587 /* Update the failing group/stage in the register file */
3588 debug_info = gbl->error_stage;
3589 debug_info |= gbl->error_substage << 8;
3590 debug_info |= gbl->error_group << 16;
3591 writel(debug_info, &sdr_reg_file->failing_stage);
3594 printf("%s: Calibration complete\n", __FILE__);
3598 * hc_initialize_rom_data() - Initialize ROM data
3600 * Initialize ROM data.
3602 static void hc_initialize_rom_data(void)
3606 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3607 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3608 writel(inst_rom_init[i], addr + (i << 2));
3610 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3611 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3612 writel(ac_rom_init[i], addr + (i << 2));
3616 * initialize_reg_file() - Initialize SDR register file
3618 * Initialize SDR register file.
3620 static void initialize_reg_file(void)
3622 /* Initialize the register file with the correct data */
3623 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3624 writel(0, &sdr_reg_file->debug_data_addr);
3625 writel(0, &sdr_reg_file->cur_stage);
3626 writel(0, &sdr_reg_file->fom);
3627 writel(0, &sdr_reg_file->failing_stage);
3628 writel(0, &sdr_reg_file->debug1);
3629 writel(0, &sdr_reg_file->debug2);
3633 * initialize_hps_phy() - Initialize HPS PHY
3635 * Initialize HPS PHY.
3637 static void initialize_hps_phy(void)
3641 * Tracking also gets configured here because it's in the
3644 uint32_t trk_sample_count = 7500;
3645 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3647 * Format is number of outer loops in the 16 MSB, sample
3652 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3653 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3654 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3655 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3656 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3657 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3659 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3660 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3662 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3663 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3665 writel(reg, &sdr_ctrl->phy_ctrl0);
3668 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3670 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3671 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3672 trk_long_idle_sample_count);
3673 writel(reg, &sdr_ctrl->phy_ctrl1);
3676 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3677 trk_long_idle_sample_count >>
3678 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3679 writel(reg, &sdr_ctrl->phy_ctrl2);
3683 * initialize_tracking() - Initialize tracking
3685 * Initialize the register file with usable initial data.
3687 static void initialize_tracking(void)
3690 * Initialize the register file with the correct data.
3691 * Compute usable version of value in case we skip full
3692 * computation later.
3694 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3695 &sdr_reg_file->dtaps_per_ptap);
3697 /* trk_sample_count */
3698 writel(7500, &sdr_reg_file->trk_sample_count);
3700 /* longidle outer loop [15:0] */
3701 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3704 * longidle sample count [31:24]
3705 * trfc, worst case of 933Mhz 4Gb [23:16]
3706 * trcd, worst case [15:8]
3709 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3710 &sdr_reg_file->delays);
3713 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3714 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3715 &sdr_reg_file->trk_rw_mgr_addr);
3717 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3718 &sdr_reg_file->trk_read_dqs_width);
3721 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3722 &sdr_reg_file->trk_rfsh);
3725 int sdram_calibration_full(void)
3727 struct param_type my_param;
3728 struct gbl_type my_gbl;
3731 memset(&my_param, 0, sizeof(my_param));
3732 memset(&my_gbl, 0, sizeof(my_gbl));
3737 /* Set the calibration enabled by default */
3738 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3740 * Only sweep all groups (regardless of fail state) by default
3741 * Set enabled read test by default.
3743 #if DISABLE_GUARANTEED_READ
3744 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3746 /* Initialize the register file */
3747 initialize_reg_file();
3749 /* Initialize any PHY CSR */
3750 initialize_hps_phy();
3752 scc_mgr_initialize();
3754 initialize_tracking();
3756 printf("%s: Preparing to start memory calibration\n", __FILE__);
3758 debug("%s:%d\n", __func__, __LINE__);
3759 debug_cond(DLEVEL == 1,
3760 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3761 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3762 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3763 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3764 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3765 debug_cond(DLEVEL == 1,
3766 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3767 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3768 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3769 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3770 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3771 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3772 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3773 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3774 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3775 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3776 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3777 IO_IO_OUT2_DELAY_MAX);
3778 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3779 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3781 hc_initialize_rom_data();
3783 /* update info for sims */
3784 reg_file_set_stage(CAL_STAGE_NIL);
3785 reg_file_set_group(0);
3788 * Load global needed for those actions that require
3789 * some dynamic calibration support.
3791 dyn_calib_steps = STATIC_CALIB_STEPS;
3793 * Load global to allow dynamic selection of delay loop settings
3794 * based on calibration mode.
3796 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3797 skip_delay_mask = 0xff;
3799 skip_delay_mask = 0x0;
3801 pass = run_mem_calibrate();
3802 debug_mem_calibrate(pass);