2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
12 #include "sequencer_auto.h"
13 #include "sequencer_auto_ac_init.h"
14 #include "sequencer_auto_inst_init.h"
15 #include "sequencer_defines.h"
17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
18 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
21 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
23 static struct socfpga_sdr_reg_file *sdr_reg_file =
24 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
27 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
30 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
33 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
35 static struct socfpga_data_mgr *data_mgr =
36 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
38 static struct socfpga_sdr_ctrl *sdr_ctrl =
39 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
44 * In order to reduce ROM size, most of the selectable calibration steps are
45 * decided at compile time based on the user's calibration mode selection,
46 * as captured by the STATIC_CALIB_STEPS selection below.
48 * However, to support simulation-time selection of fast simulation mode, where
49 * we skip everything except the bare minimum, we need a few of the steps to
50 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
51 * check, which is based on the rtl-supplied value, or we dynamically compute
52 * the value to use based on the dynamically-chosen calibration mode
56 #define STATIC_IN_RTL_SIM 0
57 #define STATIC_SKIP_DELAY_LOOPS 0
59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
60 STATIC_SKIP_DELAY_LOOPS)
62 /* calibration steps requested by the rtl */
63 uint16_t dyn_calib_steps;
66 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
67 * instead of static, we use boolean logic to select between
68 * non-skip and skip values
70 * The mask is set to include all bits when not-skipping, but is
74 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
77 ((non_skip_value) & skip_delay_mask)
80 struct param_type *param;
81 uint32_t curr_shadow_reg;
83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
84 uint32_t write_group, uint32_t use_dm,
85 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
91 * Only set the global stage if there was not been any other
94 if (gbl->error_stage == CAL_STAGE_NIL) {
95 gbl->error_substage = substage;
96 gbl->error_stage = stage;
97 gbl->error_group = group;
101 static void reg_file_set_group(u16 set_group)
103 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
106 static void reg_file_set_stage(u8 set_stage)
108 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
111 static void reg_file_set_sub_stage(u8 set_sub_stage)
113 set_sub_stage &= 0xff;
114 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
118 * phy_mgr_initialize() - Initialize PHY Manager
120 * Initialize PHY Manager.
122 static void phy_mgr_initialize(void)
126 debug("%s:%d\n", __func__, __LINE__);
127 /* Calibration has control over path to memory */
129 * In Hard PHY this is a 2-bit control:
133 writel(0x3, &phy_mgr_cfg->mux_sel);
135 /* USER memory clock is not stable we begin initialization */
136 writel(0, &phy_mgr_cfg->reset_mem_stbl);
138 /* USER calibration status all set to zero */
139 writel(0, &phy_mgr_cfg->cal_status);
141 writel(0, &phy_mgr_cfg->cal_debug_info);
143 /* Init params only if we do NOT skip calibration. */
144 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
147 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
148 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
149 param->read_correct_mask_vg = (1 << ratio) - 1;
150 param->write_correct_mask_vg = (1 << ratio) - 1;
151 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
152 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
153 ratio = RW_MGR_MEM_DATA_WIDTH /
154 RW_MGR_MEM_DATA_MASK_WIDTH;
155 param->dm_correct_mask = (1 << ratio) - 1;
159 * set_rank_and_odt_mask() - Set Rank and ODT mask
161 * @odt_mode: ODT mode, OFF or READ_WRITE
163 * Set Rank and ODT mask (On-Die Termination).
165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
171 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
174 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
175 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
177 /* Read: ODT = 0 ; Write: ODT = 1 */
181 case 2: /* 2 Ranks */
182 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
184 * - Dual-Slot , Single-Rank (1 CS per DIMM)
186 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
188 * Since MEM_NUMBER_OF_RANKS is 2, they
189 * are both single rank with 2 CS each
190 * (special for RDIMM).
192 * Read: Turn on ODT on the opposite rank
193 * Write: Turn on ODT on all ranks
195 odt_mask_0 = 0x3 & ~(1 << rank);
199 * - Single-Slot , Dual-Rank (2 CS per DIMM)
201 * Read: Turn on ODT off on all ranks
202 * Write: Turn on ODT on active rank
205 odt_mask_1 = 0x3 & (1 << rank);
208 case 4: /* 4 Ranks */
210 * ----------+-----------------------+
212 * Read From +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 0 |
216 * 1 | 1 | 0 | 0 | 0 |
217 * 2 | 0 | 0 | 0 | 1 |
218 * 3 | 0 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
222 * ----------+-----------------------+
224 * Write To +-----------------------+
225 * Rank | 3 | 2 | 1 | 0 |
226 * ----------+-----+-----+-----+-----+
227 * 0 | 0 | 1 | 0 | 1 |
228 * 1 | 1 | 0 | 1 | 0 |
229 * 2 | 0 | 1 | 0 | 1 |
230 * 3 | 1 | 0 | 1 | 0 |
231 * ----------+-----+-----+-----+-----+
255 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
256 ((0xFF & odt_mask_0) << 8) |
257 ((0xFF & odt_mask_1) << 16);
258 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
259 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
263 * scc_mgr_set() - Set SCC Manager register
264 * @off: Base offset in SCC Manager space
265 * @grp: Read/Write group
266 * @val: Value to be set
268 * This function sets the SCC Manager (Scan Chain Control Manager) register.
270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
272 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
276 * scc_mgr_initialize() - Initialize SCC Manager registers
278 * Initialize SCC Manager registers.
280 static void scc_mgr_initialize(void)
283 * Clear register file for HPS. 16 (2^4) is the size of the
284 * full register file in the scc mgr:
285 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
286 * MEM_IF_READ_DQS_WIDTH - 1);
290 for (i = 0; i < 16; i++) {
291 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
292 __func__, __LINE__, i);
293 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
299 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
304 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
309 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
314 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
319 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
325 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
330 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
335 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
341 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
342 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
346 /* load up dqs config settings */
347 static void scc_mgr_load_dqs(uint32_t dqs)
349 writel(dqs, &sdr_scc_mgr->dqs_ena);
352 /* load up dqs io config settings */
353 static void scc_mgr_load_dqs_io(void)
355 writel(0, &sdr_scc_mgr->dqs_io_ena);
358 /* load up dq config settings */
359 static void scc_mgr_load_dq(uint32_t dq_in_group)
361 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
364 /* load up dm config settings */
365 static void scc_mgr_load_dm(uint32_t dm)
367 writel(dm, &sdr_scc_mgr->dm_ena);
371 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
372 * @off: Base offset in SCC Manager space
373 * @grp: Read/Write group
374 * @val: Value to be set
375 * @update: If non-zero, trigger SCC Manager update for all ranks
377 * This function sets the SCC Manager (Scan Chain Control Manager) register
378 * and optionally triggers the SCC update for all ranks.
380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
385 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
386 r += NUM_RANKS_PER_SHADOW_REG) {
387 scc_mgr_set(off, grp, val);
389 if (update || (r == 0)) {
390 writel(grp, &sdr_scc_mgr->dqs_ena);
391 writel(0, &sdr_scc_mgr->update);
396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
399 * USER although the h/w doesn't support different phases per
400 * shadow register, for simplicity our scc manager modeling
401 * keeps different phase settings per shadow reg, and it's
402 * important for us to keep them in sync to match h/w.
403 * for efficiency, the scan chain update should occur only
406 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
407 read_group, phase, 0);
410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
414 * USER although the h/w doesn't support different phases per
415 * shadow register, for simplicity our scc manager modeling
416 * keeps different phase settings per shadow reg, and it's
417 * important for us to keep them in sync to match h/w.
418 * for efficiency, the scan chain update should occur only
421 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
422 write_group, phase, 0);
425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
429 * In shadow register mode, the T11 settings are stored in
430 * registers in the core, which are updated by the DQS_ENA
431 * signals. Not issuing the SCC_MGR_UPD command allows us to
432 * save lots of rank switching overhead, by calling
433 * select_shadow_regs_for_update with update_scan_chains
436 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
437 read_group, delay, 1);
438 writel(0, &sdr_scc_mgr->update);
442 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
443 * @write_group: Write group
444 * @delay: Delay value
446 * This function sets the OCT output delay in SCC manager.
448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
450 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
451 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
452 const int base = write_group * ratio;
455 * Load the setting in the SCC manager
456 * Although OCT affects only write data, the OCT delay is controlled
457 * by the DQS logic block which is instantiated once per read group.
458 * For protocols where a write group consists of multiple read groups,
459 * the setting must be set multiple times.
461 for (i = 0; i < ratio; i++)
462 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
466 * scc_mgr_set_hhp_extras() - Set HHP extras.
468 * Load the fixed setting in the SCC manager HHP extras.
470 static void scc_mgr_set_hhp_extras(void)
473 * Load the fixed setting in the SCC manager
474 * bits: 0:0 = 1'b1 - DQS bypass
475 * bits: 1:1 = 1'b1 - DQ bypass
476 * bits: 4:2 = 3'b001 - rfifo_mode
477 * bits: 6:5 = 2'b01 - rfifo clock_select
478 * bits: 7:7 = 1'b0 - separate gating from ungating setting
479 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
481 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
482 (1 << 2) | (1 << 1) | (1 << 0);
483 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
484 SCC_MGR_HHP_GLOBALS_OFFSET |
485 SCC_MGR_HHP_EXTRAS_OFFSET;
487 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
490 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
495 * scc_mgr_zero_all() - Zero all DQS config
497 * Zero all DQS config.
499 static void scc_mgr_zero_all(void)
504 * USER Zero all DQS config settings, across all groups and all
507 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
508 r += NUM_RANKS_PER_SHADOW_REG) {
509 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
511 * The phases actually don't exist on a per-rank basis,
512 * but there's no harm updating them several times, so
513 * let's keep the code simple.
515 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
516 scc_mgr_set_dqs_en_phase(i, 0);
517 scc_mgr_set_dqs_en_delay(i, 0);
520 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
521 scc_mgr_set_dqdqs_output_phase(i, 0);
522 /* Arria V/Cyclone V don't have out2. */
523 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
527 /* Multicast to all DQS group enables. */
528 writel(0xff, &sdr_scc_mgr->dqs_ena);
529 writel(0, &sdr_scc_mgr->update);
533 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
534 * @write_group: Write group
536 * Set bypass mode and trigger SCC update.
538 static void scc_set_bypass_mode(const u32 write_group)
540 /* Multicast to all DQ enables. */
541 writel(0xff, &sdr_scc_mgr->dq_ena);
542 writel(0xff, &sdr_scc_mgr->dm_ena);
544 /* Update current DQS IO enable. */
545 writel(0, &sdr_scc_mgr->dqs_io_ena);
547 /* Update the DQS logic. */
548 writel(write_group, &sdr_scc_mgr->dqs_ena);
551 writel(0, &sdr_scc_mgr->update);
555 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
556 * @write_group: Write group
558 * Load DQS settings for Write Group, do not trigger SCC update.
560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
562 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
563 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
564 const int base = write_group * ratio;
567 * Load the setting in the SCC manager
568 * Although OCT affects only write data, the OCT delay is controlled
569 * by the DQS logic block which is instantiated once per read group.
570 * For protocols where a write group consists of multiple read groups,
571 * the setting must be set multiple times.
573 for (i = 0; i < ratio; i++)
574 writel(base + i, &sdr_scc_mgr->dqs_ena);
578 * scc_mgr_zero_group() - Zero all configs for a group
580 * Zero DQ, DM, DQS and OCT configs for a group.
582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
586 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
587 r += NUM_RANKS_PER_SHADOW_REG) {
588 /* Zero all DQ config settings. */
589 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
590 scc_mgr_set_dq_out1_delay(i, 0);
592 scc_mgr_set_dq_in_delay(i, 0);
595 /* Multicast to all DQ enables. */
596 writel(0xff, &sdr_scc_mgr->dq_ena);
598 /* Zero all DM config settings. */
599 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
600 scc_mgr_set_dm_out1_delay(i, 0);
602 /* Multicast to all DM enables. */
603 writel(0xff, &sdr_scc_mgr->dm_ena);
605 /* Zero all DQS IO settings. */
607 scc_mgr_set_dqs_io_in_delay(0);
609 /* Arria V/Cyclone V don't have out2. */
610 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
611 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
612 scc_mgr_load_dqs_for_write_group(write_group);
614 /* Multicast to all DQS IO enables (only 1 in total). */
615 writel(0, &sdr_scc_mgr->dqs_io_ena);
617 /* Hit update to zero everything. */
618 writel(0, &sdr_scc_mgr->update);
623 * apply and load a particular input delay for the DQ pins in a group
624 * group_bgn is the index of the first dq pin (in the write group)
626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
630 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
631 scc_mgr_set_dq_in_delay(p, delay);
637 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
638 * @delay: Delay value
640 * Apply and load a particular output delay for the DQ pins in a group.
642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
646 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
647 scc_mgr_set_dq_out1_delay(i, delay);
652 /* apply and load a particular output delay for the DM pins in a group */
653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
657 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
658 scc_mgr_set_dm_out1_delay(i, delay1);
664 /* apply and load delay on both DQS and OCT out1 */
665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
668 scc_mgr_set_dqs_out1_delay(delay);
669 scc_mgr_load_dqs_io();
671 scc_mgr_set_oct_out1_delay(write_group, delay);
672 scc_mgr_load_dqs_for_write_group(write_group);
676 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
677 * @write_group: Write group
678 * @delay: Delay value
680 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
688 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
692 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
696 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
697 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
698 debug_cond(DLEVEL == 1,
699 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
700 __func__, __LINE__, write_group, delay, new_delay,
701 IO_IO_OUT2_DELAY_MAX,
702 new_delay - IO_IO_OUT2_DELAY_MAX);
703 new_delay -= IO_IO_OUT2_DELAY_MAX;
704 scc_mgr_set_dqs_out1_delay(new_delay);
707 scc_mgr_load_dqs_io();
710 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
711 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
712 debug_cond(DLEVEL == 1,
713 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
714 __func__, __LINE__, write_group, delay,
715 new_delay, IO_IO_OUT2_DELAY_MAX,
716 new_delay - IO_IO_OUT2_DELAY_MAX);
717 new_delay -= IO_IO_OUT2_DELAY_MAX;
718 scc_mgr_set_oct_out1_delay(write_group, new_delay);
721 scc_mgr_load_dqs_for_write_group(write_group);
725 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
726 * @write_group: Write group
727 * @delay: Delay value
729 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
737 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
738 r += NUM_RANKS_PER_SHADOW_REG) {
739 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
740 writel(0, &sdr_scc_mgr->update);
745 * set_jump_as_return() - Return instruction optimization
747 * Optimization used to recover some slots in ddr3 inst_rom could be
748 * applied to other protocols if we wanted to
750 static void set_jump_as_return(void)
753 * To save space, we replace return with jump to special shared
754 * RETURN instruction so we set the counter to large value so that
757 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
758 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
762 * should always use constants as argument to ensure all computations are
763 * performed at compile time
765 static void delay_for_n_mem_clocks(const uint32_t clocks)
772 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
775 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
776 /* scale (rounding up) to get afi clocks */
779 * Note, we don't bother accounting for being off a little bit
780 * because of a few extra instructions in outer loops
781 * Note, the loops have a test at the end, and do the test before
782 * the decrement, and so always perform the loop
783 * 1 time more than the counter value
785 if (afi_clocks == 0) {
787 } else if (afi_clocks <= 0x100) {
788 inner = afi_clocks-1;
791 } else if (afi_clocks <= 0x10000) {
793 outer = (afi_clocks-1) >> 8;
798 c_loop = (afi_clocks-1) >> 16;
802 * rom instructions are structured as follows:
804 * IDLE_LOOP2: jnz cntr0, TARGET_A
805 * IDLE_LOOP1: jnz cntr1, TARGET_B
808 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
809 * TARGET_B is set to IDLE_LOOP2 as well
811 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
812 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
814 * a little confusing, but it helps save precious space in the inst_rom
815 * and sequencer rom and keeps the delays more accurate and reduces
818 if (afi_clocks <= 0x100) {
819 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
820 &sdr_rw_load_mgr_regs->load_cntr1);
822 writel(RW_MGR_IDLE_LOOP1,
823 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
825 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
826 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
828 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
829 &sdr_rw_load_mgr_regs->load_cntr0);
831 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
832 &sdr_rw_load_mgr_regs->load_cntr1);
834 writel(RW_MGR_IDLE_LOOP2,
835 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
837 writel(RW_MGR_IDLE_LOOP2,
838 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
840 /* hack to get around compiler not being smart enough */
841 if (afi_clocks <= 0x10000) {
842 /* only need to run once */
843 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
844 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
847 writel(RW_MGR_IDLE_LOOP2,
848 SDR_PHYGRP_RWMGRGRP_ADDRESS |
849 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
850 } while (c_loop-- != 0);
853 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
857 * rw_mgr_mem_init_load_regs() - Load instruction registers
858 * @cntr0: Counter 0 value
859 * @cntr1: Counter 1 value
860 * @cntr2: Counter 2 value
861 * @jump: Jump instruction value
863 * Load instruction registers.
865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
867 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
868 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
871 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
872 &sdr_rw_load_mgr_regs->load_cntr0);
873 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
874 &sdr_rw_load_mgr_regs->load_cntr1);
875 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
876 &sdr_rw_load_mgr_regs->load_cntr2);
878 /* Load jump address */
879 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
880 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
881 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
883 /* Execute count instruction */
884 writel(jump, grpaddr);
888 * rw_mgr_mem_load_user() - Load user calibration values
889 * @fin1: Final instruction 1
890 * @fin2: Final instruction 2
891 * @precharge: If 1, precharge the banks at the end
893 * Load user calibration values and optionally precharge the banks.
895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
898 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
899 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
902 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
903 if (param->skip_ranks[r]) {
904 /* request to skip the rank */
909 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
911 /* precharge all banks ... */
913 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
916 * USER Use Mirror-ed commands for odd ranks if address
919 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
920 set_jump_as_return();
921 writel(RW_MGR_MRS2_MIRR, grpaddr);
922 delay_for_n_mem_clocks(4);
923 set_jump_as_return();
924 writel(RW_MGR_MRS3_MIRR, grpaddr);
925 delay_for_n_mem_clocks(4);
926 set_jump_as_return();
927 writel(RW_MGR_MRS1_MIRR, grpaddr);
928 delay_for_n_mem_clocks(4);
929 set_jump_as_return();
930 writel(fin1, grpaddr);
932 set_jump_as_return();
933 writel(RW_MGR_MRS2, grpaddr);
934 delay_for_n_mem_clocks(4);
935 set_jump_as_return();
936 writel(RW_MGR_MRS3, grpaddr);
937 delay_for_n_mem_clocks(4);
938 set_jump_as_return();
939 writel(RW_MGR_MRS1, grpaddr);
940 set_jump_as_return();
941 writel(fin2, grpaddr);
947 set_jump_as_return();
948 writel(RW_MGR_ZQCL, grpaddr);
950 /* tZQinit = tDLLK = 512 ck cycles */
951 delay_for_n_mem_clocks(512);
956 * rw_mgr_mem_initialize() - Initialize RW Manager
958 * Initialize RW Manager.
960 static void rw_mgr_mem_initialize(void)
962 debug("%s:%d\n", __func__, __LINE__);
964 /* The reset / cke part of initialization is broadcasted to all ranks */
965 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
966 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
969 * Here's how you load register for a loop
970 * Counters are located @ 0x800
971 * Jump address are located @ 0xC00
972 * For both, registers 0 to 3 are selected using bits 3 and 2, like
973 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
974 * I know this ain't pretty, but Avalon bus throws away the 2 least
978 /* Start with memory RESET activated */
983 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
984 * If a and b are the number of iteration in 2 nested loops
985 * it takes the following number of cycles to complete the operation:
986 * number_of_cycles = ((2 + n) * a + 2) * b
987 * where n is the number of instruction in the inner loop
988 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
991 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
993 RW_MGR_INIT_RESET_0_CKE_0);
995 /* Indicate that memory is stable. */
996 writel(1, &phy_mgr_cfg->reset_mem_stbl);
999 * transition the RESET to high
1004 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005 * If a and b are the number of iteration in 2 nested loops
1006 * it takes the following number of cycles to complete the operation
1007 * number_of_cycles = ((2 + n) * a + 2) * b
1008 * where n is the number of instruction in the inner loop
1009 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1012 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013 SEQ_TRESET_CNTR2_VAL,
1014 RW_MGR_INIT_RESET_1_CKE_0);
1016 /* Bring up clock enable. */
1018 /* tXRP < 250 ck cycles */
1019 delay_for_n_mem_clocks(250);
1021 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1026 * At the end of calibration we have to program the user settings in, and
1027 * USER hand off the memory to the user.
1029 static void rw_mgr_mem_handoff(void)
1031 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1033 * USER need to wait tMOD (12CK or 15ns) time before issuing
1034 * other commands, but we will have plenty of NIOS cycles before
1035 * actual handoff so its okay.
1040 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041 * @rank_bgn: Rank number
1042 * @group: Read/Write Group
1043 * @all_ranks: Test all ranks
1045 * Performs a guaranteed read on the patterns we are going to use during a
1046 * read test to ensure memory works.
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050 const u32 all_ranks)
1052 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054 const u32 addr_offset =
1055 (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056 const u32 rank_end = all_ranks ?
1057 RW_MGR_MEM_NUMBER_OF_RANKS :
1058 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059 const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061 const u32 correct_mask_vg = param->read_correct_mask_vg;
1063 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1067 bit_chk = param->read_correct_mask;
1069 for (r = rank_bgn; r < rank_end; r++) {
1070 /* Request to skip the rank */
1071 if (param->skip_ranks[r])
1075 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1077 /* Load up a constant bursts of read commands */
1078 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079 writel(RW_MGR_GUARANTEED_READ,
1080 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1082 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083 writel(RW_MGR_GUARANTEED_READ_CONT,
1084 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1087 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1089 /* Reset the FIFOs to get pointers to known state. */
1090 writel(0, &phy_mgr_cmd->fifo_reset);
1091 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1093 writel(RW_MGR_GUARANTEED_READ,
1094 addr + addr_offset + (vg << 2));
1096 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1097 tmp_bit_chk <<= shift_ratio;
1098 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1101 bit_chk &= tmp_bit_chk;
1104 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1106 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1108 if (bit_chk != param->read_correct_mask)
1111 debug_cond(DLEVEL == 1,
1112 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113 __func__, __LINE__, group, bit_chk,
1114 param->read_correct_mask, ret);
1120 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121 * @rank_bgn: Rank number
1122 * @all_ranks: Test all ranks
1124 * Load up the patterns we are going to use during a read test.
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127 const int all_ranks)
1129 const u32 rank_end = all_ranks ?
1130 RW_MGR_MEM_NUMBER_OF_RANKS :
1131 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1134 debug("%s:%d\n", __func__, __LINE__);
1136 for (r = rank_bgn; r < rank_end; r++) {
1137 if (param->skip_ranks[r])
1138 /* request to skip the rank */
1142 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1144 /* Load up a constant bursts */
1145 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1147 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1150 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1152 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1155 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1157 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1160 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1162 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1165 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1169 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1173 * rw_mgr_mem_calibrate_read_test() - Perform READ test on single rank
1174 * @rank_bgn: Rank number
1175 * @group: Read/Write group
1176 * @num_tries: Number of retries of the test
1177 * @all_correct: All bits must be correct in the mask
1178 * @bit_chk: Resulting bit mask after the test
1179 * @all_groups: Test all R/W groups
1180 * @all_ranks: Test all ranks
1182 * Try a read and see if it returns correct data back. Test has dummy reads
1183 * inserted into the mix used to align DQS enable. Test has more thorough
1184 * checks than the regular read test.
1187 rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
1188 const u32 num_tries, const u32 all_correct,
1190 const u32 all_groups, const u32 all_ranks)
1192 const u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1193 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1194 const u32 quick_read_mode =
1195 ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
1196 ENABLE_SUPER_QUICK_CALIBRATION);
1197 u32 correct_mask_vg = param->read_correct_mask_vg;
1204 *bit_chk = param->read_correct_mask;
1206 for (r = rank_bgn; r < rank_end; r++) {
1207 if (param->skip_ranks[r])
1208 /* request to skip the rank */
1212 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1214 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1216 writel(RW_MGR_READ_B2B_WAIT1,
1217 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1219 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1220 writel(RW_MGR_READ_B2B_WAIT2,
1221 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1223 if (quick_read_mode)
1224 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1225 /* need at least two (1+1) reads to capture failures */
1226 else if (all_groups)
1227 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1229 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1231 writel(RW_MGR_READ_B2B,
1232 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1234 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1235 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1236 &sdr_rw_load_mgr_regs->load_cntr3);
1238 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1240 writel(RW_MGR_READ_B2B,
1241 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1244 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1; vg >= 0;
1246 /* Reset the FIFOs to get pointers to known state. */
1247 writel(0, &phy_mgr_cmd->fifo_reset);
1248 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1249 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1252 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1253 RW_MGR_RUN_ALL_GROUPS_OFFSET;
1255 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1256 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1259 writel(RW_MGR_READ_B2B, addr +
1260 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1263 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1264 tmp_bit_chk <<= RW_MGR_MEM_DQ_PER_READ_DQS /
1265 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1266 tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
1269 *bit_chk &= tmp_bit_chk;
1272 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1273 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1275 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1278 ret = (*bit_chk == param->read_correct_mask);
1279 debug_cond(DLEVEL == 2,
1280 "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1281 __func__, __LINE__, group, all_groups, *bit_chk,
1282 param->read_correct_mask, ret);
1284 ret = (*bit_chk != 0x00);
1285 debug_cond(DLEVEL == 2,
1286 "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1287 __func__, __LINE__, group, all_groups, *bit_chk,
1295 * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1296 * @grp: Read/Write group
1297 * @num_tries: Number of retries of the test
1298 * @all_correct: All bits must be correct in the mask
1299 * @all_groups: Test all R/W groups
1301 * Perform a READ test across all memory ranks.
1304 rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries,
1305 const u32 all_correct,
1306 const u32 all_groups)
1309 return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct,
1310 &bit_chk, all_groups, 1);
1314 * rw_mgr_incr_vfifo() - Increase VFIFO value
1315 * @grp: Read/Write group
1317 * Increase VFIFO value.
1319 static void rw_mgr_incr_vfifo(const u32 grp)
1321 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1325 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1326 * @grp: Read/Write group
1328 * Decrease VFIFO value.
1330 static void rw_mgr_decr_vfifo(const u32 grp)
1334 for (i = 0; i < VFIFO_SIZE - 1; i++)
1335 rw_mgr_incr_vfifo(grp);
1339 * find_vfifo_failing_read() - Push VFIFO to get a failing read
1340 * @grp: Read/Write group
1342 * Push VFIFO until a failing read happens.
1344 static int find_vfifo_failing_read(const u32 grp)
1346 u32 v, ret, fail_cnt = 0;
1348 for (v = 0; v < VFIFO_SIZE; v++) {
1349 debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
1350 __func__, __LINE__, v);
1351 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1360 /* Fiddle with FIFO. */
1361 rw_mgr_incr_vfifo(grp);
1364 /* No failing read found! Something must have gone wrong. */
1365 debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1370 * sdr_find_phase_delay() - Find DQS enable phase or delay
1371 * @working: If 1, look for working phase/delay, if 0, look for non-working
1372 * @delay: If 1, look for delay, if 0, look for phase
1373 * @grp: Read/Write group
1374 * @work: Working window position
1375 * @work_inc: Working window increment
1376 * @pd: DQS Phase/Delay Iterator
1378 * Find working or non-working DQS enable phase setting.
1380 static int sdr_find_phase_delay(int working, int delay, const u32 grp,
1381 u32 *work, const u32 work_inc, u32 *pd)
1383 const u32 max = delay ? IO_DQS_EN_DELAY_MAX : IO_DQS_EN_PHASE_MAX;
1386 for (; *pd <= max; (*pd)++) {
1388 scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd);
1390 scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
1392 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1407 * sdr_find_phase() - Find DQS enable phase
1408 * @working: If 1, look for working phase, if 0, look for non-working phase
1409 * @grp: Read/Write group
1410 * @work: Working window position
1412 * @p: DQS Phase Iterator
1414 * Find working or non-working DQS enable phase setting.
1416 static int sdr_find_phase(int working, const u32 grp, u32 *work,
1419 const u32 end = VFIFO_SIZE + (working ? 0 : 1);
1422 for (; *i < end; (*i)++) {
1426 ret = sdr_find_phase_delay(working, 0, grp, work,
1427 IO_DELAY_PER_OPA_TAP, p);
1431 if (*p > IO_DQS_EN_PHASE_MAX) {
1432 /* Fiddle with FIFO. */
1433 rw_mgr_incr_vfifo(grp);
1443 * sdr_working_phase() - Find working DQS enable phase
1444 * @grp: Read/Write group
1445 * @work_bgn: Working window start position
1446 * @d: dtaps output value
1447 * @p: DQS Phase Iterator
1450 * Find working DQS enable phase setting.
1452 static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
1455 const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
1456 IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1461 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1463 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1464 ret = sdr_find_phase(1, grp, work_bgn, i, p);
1467 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1470 /* Cannot find working solution */
1471 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1472 __func__, __LINE__);
1477 * sdr_backup_phase() - Find DQS enable backup phase
1478 * @grp: Read/Write group
1479 * @work_bgn: Working window start position
1480 * @p: DQS Phase Iterator
1482 * Find DQS enable backup phase setting.
1484 static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
1489 /* Special case code for backing up a phase */
1491 *p = IO_DQS_EN_PHASE_MAX;
1492 rw_mgr_decr_vfifo(grp);
1496 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1497 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1499 for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
1500 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1502 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1505 *work_bgn = tmp_delay;
1509 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1512 /* Restore VFIFO to old state before we decremented it (if needed). */
1514 if (*p > IO_DQS_EN_PHASE_MAX) {
1516 rw_mgr_incr_vfifo(grp);
1519 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1523 * sdr_nonworking_phase() - Find non-working DQS enable phase
1524 * @grp: Read/Write group
1525 * @work_end: Working window end position
1526 * @p: DQS Phase Iterator
1529 * Find non-working DQS enable phase setting.
1531 static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
1536 *work_end += IO_DELAY_PER_OPA_TAP;
1537 if (*p > IO_DQS_EN_PHASE_MAX) {
1538 /* Fiddle with FIFO. */
1540 rw_mgr_incr_vfifo(grp);
1543 ret = sdr_find_phase(0, grp, work_end, i, p);
1545 /* Cannot see edge of failing read. */
1546 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1547 __func__, __LINE__);
1554 * sdr_find_window_center() - Find center of the working DQS window.
1555 * @grp: Read/Write group
1556 * @work_bgn: First working settings
1557 * @work_end: Last working settings
1559 * Find center of the working DQS enable window.
1561 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1568 work_mid = (work_bgn + work_end) / 2;
1570 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1571 work_bgn, work_end, work_mid);
1572 /* Get the middle delay to be less than a VFIFO delay */
1573 tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1575 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1576 work_mid %= tmp_delay;
1577 debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1579 tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1580 if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1581 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1582 p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1584 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1586 d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1587 if (d > IO_DQS_EN_DELAY_MAX)
1588 d = IO_DQS_EN_DELAY_MAX;
1589 tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1591 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1593 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1594 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1597 * push vfifo until we can successfully calibrate. We can do this
1598 * because the largest possible margin in 1 VFIFO cycle.
1600 for (i = 0; i < VFIFO_SIZE; i++) {
1601 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
1602 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1605 debug_cond(DLEVEL == 2,
1606 "%s:%d center: found: ptap=%u dtap=%u\n",
1607 __func__, __LINE__, p, d);
1611 /* Fiddle with FIFO. */
1612 rw_mgr_incr_vfifo(grp);
1615 debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1616 __func__, __LINE__);
1621 * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
1622 * @grp: Read/Write Group
1624 * Find a good DQS enable to use.
1626 static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
1630 u32 work_bgn, work_end;
1631 u32 found_passing_read, found_failing_read, initial_failing_dtap;
1634 debug("%s:%d %u\n", __func__, __LINE__, grp);
1636 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1638 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1639 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1641 /* Step 0: Determine number of delay taps for each phase tap. */
1642 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1644 /* Step 1: First push vfifo until we get a failing read. */
1645 find_vfifo_failing_read(grp);
1647 /* Step 2: Find first working phase, increment in ptaps. */
1649 ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i);
1653 work_end = work_bgn;
1656 * If d is 0 then the working window covers a phase tap and we can
1657 * follow the old procedure. Otherwise, we've found the beginning
1658 * and we need to increment the dtaps until we find the end.
1662 * Step 3a: If we have room, back off by one and
1663 * increment in dtaps.
1665 sdr_backup_phase(grp, &work_bgn, &p);
1668 * Step 4a: go forward from working phase to non working
1669 * phase, increment in ptaps.
1671 ret = sdr_nonworking_phase(grp, &work_end, &p, &i);
1675 /* Step 5a: Back off one from last, increment in dtaps. */
1677 /* Special case code for backing up a phase */
1679 p = IO_DQS_EN_PHASE_MAX;
1680 rw_mgr_decr_vfifo(grp);
1685 work_end -= IO_DELAY_PER_OPA_TAP;
1686 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1690 debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
1691 __func__, __LINE__, p);
1694 /* The dtap increment to find the failing edge is done here. */
1695 sdr_find_phase_delay(0, 1, grp, &work_end,
1696 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, &d);
1698 /* Go back to working dtap */
1700 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1702 debug_cond(DLEVEL == 2,
1703 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1704 __func__, __LINE__, p, d - 1, work_end);
1706 if (work_end < work_bgn) {
1708 debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
1709 __func__, __LINE__);
1713 debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
1714 __func__, __LINE__, work_bgn, work_end);
1717 * We need to calculate the number of dtaps that equal a ptap.
1718 * To do that we'll back up a ptap and re-find the edge of the
1719 * window using dtaps
1721 debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1722 __func__, __LINE__);
1724 /* Special case code for backing up a phase */
1726 p = IO_DQS_EN_PHASE_MAX;
1727 rw_mgr_decr_vfifo(grp);
1728 debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
1729 __func__, __LINE__, p);
1732 debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
1733 __func__, __LINE__, p);
1736 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1739 * Increase dtap until we first see a passing read (in case the
1740 * window is smaller than a ptap), and then a failing read to
1741 * mark the edge of the window again.
1744 /* Find a passing read. */
1745 debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
1746 __func__, __LINE__);
1748 initial_failing_dtap = d;
1750 found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
1751 if (found_passing_read) {
1752 /* Find a failing read. */
1753 debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
1754 __func__, __LINE__);
1756 found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
1759 debug_cond(DLEVEL == 1,
1760 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1761 __func__, __LINE__);
1765 * The dynamically calculated dtaps_per_ptap is only valid if we
1766 * found a passing/failing read. If we didn't, it means d hit the max
1767 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1768 * statically calculated value.
1770 if (found_passing_read && found_failing_read)
1771 dtaps_per_ptap = d - initial_failing_dtap;
1773 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1774 debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1775 __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
1777 /* Step 6: Find the centre of the window. */
1778 ret = sdr_find_window_center(grp, work_bgn, work_end);
1784 * search_stop_check() - Check if the detected edge is valid
1785 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1787 * @rank_bgn: Rank number
1788 * @write_group: Write Group
1789 * @read_group: Read Group
1790 * @bit_chk: Resulting bit mask after the test
1791 * @sticky_bit_chk: Resulting sticky bit mask after the test
1792 * @use_read_test: Perform read test
1794 * Test if the found edge is valid.
1796 static u32 search_stop_check(const int write, const int d, const int rank_bgn,
1797 const u32 write_group, const u32 read_group,
1798 u32 *bit_chk, u32 *sticky_bit_chk,
1799 const u32 use_read_test)
1801 const u32 ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
1802 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
1803 const u32 correct_mask = write ? param->write_correct_mask :
1804 param->read_correct_mask;
1805 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
1806 RW_MGR_MEM_DQ_PER_READ_DQS;
1809 * Stop searching when the read test doesn't pass AND when
1810 * we've seen a passing read on every bit.
1812 if (write) { /* WRITE-ONLY */
1813 ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1816 } else if (use_read_test) { /* READ-ONLY */
1817 ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group,
1819 PASS_ONE_BIT, bit_chk,
1821 } else { /* READ-ONLY */
1822 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0,
1823 PASS_ONE_BIT, bit_chk, 0);
1824 *bit_chk = *bit_chk >> (per_dqs *
1825 (read_group - (write_group * ratio)));
1826 ret = (*bit_chk == 0);
1828 *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
1829 ret = ret && (*sticky_bit_chk == correct_mask);
1830 debug_cond(DLEVEL == 2,
1831 "%s:%d center(left): dtap=%u => %u == %u && %u",
1832 __func__, __LINE__, d,
1833 *sticky_bit_chk, correct_mask, ret);
1838 * search_left_edge() - Find left edge of DQ/DQS working phase
1839 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1840 * @rank_bgn: Rank number
1841 * @write_group: Write Group
1842 * @read_group: Read Group
1843 * @test_bgn: Rank number to begin the test
1844 * @bit_chk: Resulting bit mask after the test
1845 * @sticky_bit_chk: Resulting sticky bit mask after the test
1846 * @left_edge: Left edge of the DQ/DQS phase
1847 * @right_edge: Right edge of the DQ/DQS phase
1848 * @use_read_test: Perform read test
1850 * Find left edge of DQ/DQS working phase.
1852 static void search_left_edge(const int write, const int rank_bgn,
1853 const u32 write_group, const u32 read_group, const u32 test_bgn,
1854 u32 *bit_chk, u32 *sticky_bit_chk,
1855 int *left_edge, int *right_edge, const u32 use_read_test)
1857 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
1858 const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
1859 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
1860 RW_MGR_MEM_DQ_PER_READ_DQS;
1864 for (d = 0; d <= dqs_max; d++) {
1866 scc_mgr_apply_group_dq_out1_delay(d);
1868 scc_mgr_apply_group_dq_in_delay(test_bgn, d);
1870 writel(0, &sdr_scc_mgr->update);
1872 stop = search_stop_check(write, d, rank_bgn, write_group,
1873 read_group, bit_chk, sticky_bit_chk,
1879 for (i = 0; i < per_dqs; i++) {
1882 * Remember a passing test as
1888 * If a left edge has not been seen
1889 * yet, then a future passing test
1890 * will mark this edge as the right
1893 if (left_edge[i] == delay_max + 1)
1894 right_edge[i] = -(d + 1);
1896 *bit_chk = *bit_chk >> 1;
1900 /* Reset DQ delay chains to 0 */
1902 scc_mgr_apply_group_dq_out1_delay(0);
1904 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1906 *sticky_bit_chk = 0;
1907 for (i = per_dqs - 1; i >= 0; i--) {
1908 debug_cond(DLEVEL == 2,
1909 "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
1910 __func__, __LINE__, i, left_edge[i],
1914 * Check for cases where we haven't found the left edge,
1915 * which makes our assignment of the the right edge invalid.
1916 * Reset it to the illegal value.
1918 if ((left_edge[i] == delay_max + 1) &&
1919 (right_edge[i] != delay_max + 1)) {
1920 right_edge[i] = delay_max + 1;
1921 debug_cond(DLEVEL == 2,
1922 "%s:%d vfifo_center: reset right_edge[%u]: %d\n",
1923 __func__, __LINE__, i, right_edge[i]);
1928 * READ: except for bits where we have seen both
1929 * the left and right edge.
1930 * WRITE: except for bits where we have seen the
1933 *sticky_bit_chk <<= 1;
1935 if (left_edge[i] != delay_max + 1)
1936 *sticky_bit_chk |= 1;
1938 if ((left_edge[i] != delay_max + 1) &&
1939 (right_edge[i] != delay_max + 1))
1940 *sticky_bit_chk |= 1;
1948 * search_right_edge() - Find right edge of DQ/DQS working phase
1949 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1950 * @rank_bgn: Rank number
1951 * @write_group: Write Group
1952 * @read_group: Read Group
1953 * @start_dqs: DQS start phase
1954 * @start_dqs_en: DQS enable start phase
1955 * @bit_chk: Resulting bit mask after the test
1956 * @sticky_bit_chk: Resulting sticky bit mask after the test
1957 * @left_edge: Left edge of the DQ/DQS phase
1958 * @right_edge: Right edge of the DQ/DQS phase
1959 * @use_read_test: Perform read test
1961 * Find right edge of DQ/DQS working phase.
1963 static int search_right_edge(const int write, const int rank_bgn,
1964 const u32 write_group, const u32 read_group,
1965 const int start_dqs, const int start_dqs_en,
1966 u32 *bit_chk, u32 *sticky_bit_chk,
1967 int *left_edge, int *right_edge, const u32 use_read_test)
1969 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
1970 const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
1971 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
1972 RW_MGR_MEM_DQ_PER_READ_DQS;
1976 for (d = 0; d <= dqs_max - start_dqs; d++) {
1977 if (write) { /* WRITE-ONLY */
1978 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
1980 } else { /* READ-ONLY */
1981 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1982 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1983 uint32_t delay = d + start_dqs_en;
1984 if (delay > IO_DQS_EN_DELAY_MAX)
1985 delay = IO_DQS_EN_DELAY_MAX;
1986 scc_mgr_set_dqs_en_delay(read_group, delay);
1988 scc_mgr_load_dqs(read_group);
1991 writel(0, &sdr_scc_mgr->update);
1993 stop = search_stop_check(write, d, rank_bgn, write_group,
1994 read_group, bit_chk, sticky_bit_chk,
1997 if (write && (d == 0)) { /* WRITE-ONLY */
1998 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2000 * d = 0 failed, but it passed when
2001 * testing the left edge, so it must be
2002 * marginal, set it to -1
2004 if (right_edge[i] == delay_max + 1 &&
2005 left_edge[i] != delay_max + 1)
2013 for (i = 0; i < per_dqs; i++) {
2016 * Remember a passing test as
2023 * If a right edge has not
2024 * been seen yet, then a future
2025 * passing test will mark this
2026 * edge as the left edge.
2028 if (right_edge[i] == delay_max + 1)
2029 left_edge[i] = -(d + 1);
2032 * d = 0 failed, but it passed
2033 * when testing the left edge,
2034 * so it must be marginal, set
2037 if (right_edge[i] == delay_max + 1 &&
2038 left_edge[i] != delay_max + 1)
2041 * If a right edge has not been
2042 * seen yet, then a future
2043 * passing test will mark this
2044 * edge as the left edge.
2046 else if (right_edge[i] == delay_max + 1)
2047 left_edge[i] = -(d + 1);
2051 debug_cond(DLEVEL == 2, "%s:%d center[r,d=%u]: ",
2052 __func__, __LINE__, d);
2053 debug_cond(DLEVEL == 2,
2054 "bit_chk_test=%i left_edge[%u]: %d ",
2055 *bit_chk & 1, i, left_edge[i]);
2056 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2058 *bit_chk = *bit_chk >> 1;
2062 /* Check that all bits have a window */
2063 for (i = 0; i < per_dqs; i++) {
2064 debug_cond(DLEVEL == 2,
2065 "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
2066 __func__, __LINE__, i, left_edge[i],
2068 if ((left_edge[i] == dqs_max + 1) ||
2069 (right_edge[i] == dqs_max + 1))
2070 return i + 1; /* FIXME: If we fail, retval > 0 */
2076 /* per-bit deskew DQ and center */
2077 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
2078 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
2079 uint32_t use_read_test, uint32_t update_fom)
2081 uint32_t i, p, min_index;
2083 * Store these as signed since there are comparisons with
2087 uint32_t sticky_bit_chk;
2088 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
2089 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
2090 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
2092 int32_t orig_mid_min, mid_min;
2093 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
2095 int32_t dq_margin, dqs_margin;
2096 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
2100 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
2102 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
2103 start_dqs = readl(addr + (read_group << 2));
2104 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2105 start_dqs_en = readl(addr + ((read_group << 2)
2106 - IO_DQS_EN_DELAY_OFFSET));
2108 /* set the left and right edge of each bit to an illegal value */
2109 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
2111 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2112 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
2113 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
2116 /* Search for the left edge of the window for each bit */
2117 search_left_edge(0, rank_bgn, write_group, read_group, test_bgn,
2118 &bit_chk, &sticky_bit_chk,
2119 left_edge, right_edge, use_read_test);
2121 /* Search for the right edge of the window for each bit */
2122 ret = search_right_edge(0, rank_bgn, write_group, read_group,
2123 start_dqs, start_dqs_en,
2124 &bit_chk, &sticky_bit_chk,
2125 left_edge, right_edge, use_read_test);
2128 * Restore delay chain settings before letting the loop
2129 * in rw_mgr_mem_calibrate_vfifo to retry different
2130 * dqs/ck relationships.
2132 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2133 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2134 scc_mgr_set_dqs_en_delay(read_group, start_dqs_en);
2136 scc_mgr_load_dqs(read_group);
2137 writel(0, &sdr_scc_mgr->update);
2139 debug_cond(DLEVEL == 1,
2140 "%s:%d vfifo_center: failed to find edge [%u]: %d %d",
2141 __func__, __LINE__, i, left_edge[i], right_edge[i]);
2142 if (use_read_test) {
2143 set_failing_group_stage(read_group *
2144 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2146 CAL_SUBSTAGE_VFIFO_CENTER);
2148 set_failing_group_stage(read_group *
2149 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2150 CAL_STAGE_VFIFO_AFTER_WRITES,
2151 CAL_SUBSTAGE_VFIFO_CENTER);
2156 /* Find middle of window for each DQ bit */
2157 mid_min = left_edge[0] - right_edge[0];
2159 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2160 mid = left_edge[i] - right_edge[i];
2161 if (mid < mid_min) {
2168 * -mid_min/2 represents the amount that we need to move DQS.
2169 * If mid_min is odd and positive we'll need to add one to
2170 * make sure the rounding in further calculations is correct
2171 * (always bias to the right), so just add 1 for all positive values.
2176 mid_min = mid_min / 2;
2178 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2179 __func__, __LINE__, mid_min, min_index);
2181 /* Determine the amount we can change DQS (which is -mid_min) */
2182 orig_mid_min = mid_min;
2183 new_dqs = start_dqs - mid_min;
2184 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2185 new_dqs = IO_DQS_IN_DELAY_MAX;
2186 else if (new_dqs < 0)
2189 mid_min = start_dqs - new_dqs;
2190 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2193 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2194 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2195 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2196 else if (start_dqs_en - mid_min < 0)
2197 mid_min += start_dqs_en - mid_min;
2199 new_dqs = start_dqs - mid_min;
2201 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2202 new_dqs=%d mid_min=%d\n", start_dqs,
2203 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2206 /* Initialize data for export structures */
2207 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2208 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2210 /* add delay to bring centre of all DQ windows to the same "level" */
2211 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2212 /* Use values before divide by 2 to reduce round off error */
2213 shift_dq = (left_edge[i] - right_edge[i] -
2214 (left_edge[min_index] - right_edge[min_index]))/2 +
2215 (orig_mid_min - mid_min);
2217 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2218 shift_dq[%u]=%d\n", i, shift_dq);
2220 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2221 temp_dq_in_delay1 = readl(addr + (p << 2));
2222 temp_dq_in_delay2 = readl(addr + (i << 2));
2224 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2225 (int32_t)IO_IO_IN_DELAY_MAX) {
2226 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2227 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2228 shift_dq = -(int32_t)temp_dq_in_delay1;
2230 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2231 shift_dq[%u]=%d\n", i, shift_dq);
2232 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2233 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2236 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2237 left_edge[i] - shift_dq + (-mid_min),
2238 right_edge[i] + shift_dq - (-mid_min));
2239 /* To determine values for export structures */
2240 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2241 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2243 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2244 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2247 final_dqs = new_dqs;
2248 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2249 final_dqs_en = start_dqs_en - mid_min;
2252 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2253 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2254 scc_mgr_load_dqs(read_group);
2258 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2259 scc_mgr_load_dqs(read_group);
2260 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2261 dqs_margin=%d", __func__, __LINE__,
2262 dq_margin, dqs_margin);
2265 * Do not remove this line as it makes sure all of our decisions
2266 * have been applied. Apply the update bit.
2268 writel(0, &sdr_scc_mgr->update);
2270 return (dq_margin >= 0) && (dqs_margin >= 0);
2274 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2275 * @rw_group: Read/Write Group
2276 * @phase: DQ/DQS phase
2278 * Because initially no communication ca be reliably performed with the memory
2279 * device, the sequencer uses a guaranteed write mechanism to write data into
2280 * the memory device.
2282 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2287 /* Set a particular DQ/DQS phase. */
2288 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2290 debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2291 __func__, __LINE__, rw_group, phase);
2294 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2295 * Load up the patterns used by read calibration using the
2296 * current DQDQS phase.
2298 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2300 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2304 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2305 * Back-to-Back reads of the patterns used for calibration.
2307 ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2309 debug_cond(DLEVEL == 1,
2310 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2311 __func__, __LINE__, rw_group, phase);
2316 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2317 * @rw_group: Read/Write Group
2318 * @test_bgn: Rank at which the test begins
2320 * DQS enable calibration ensures reliable capture of the DQ signal without
2321 * glitches on the DQS line.
2323 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2327 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2328 * DQS and DQS Eanble Signal Relationships.
2331 /* We start at zero, so have one less dq to devide among */
2332 const u32 delay_step = IO_IO_IN_DELAY_MAX /
2333 (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2337 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2339 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2340 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2341 r += NUM_RANKS_PER_SHADOW_REG) {
2342 for (i = 0, p = test_bgn, d = 0;
2343 i < RW_MGR_MEM_DQ_PER_READ_DQS;
2344 i++, p++, d += delay_step) {
2345 debug_cond(DLEVEL == 1,
2346 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2347 __func__, __LINE__, rw_group, r, i, p, d);
2349 scc_mgr_set_dq_in_delay(p, d);
2353 writel(0, &sdr_scc_mgr->update);
2357 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2358 * dq_in_delay values
2360 ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2362 debug_cond(DLEVEL == 1,
2363 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2364 __func__, __LINE__, rw_group, !ret);
2366 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2367 r += NUM_RANKS_PER_SHADOW_REG) {
2368 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2369 writel(0, &sdr_scc_mgr->update);
2376 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2377 * @rw_group: Read/Write Group
2378 * @test_bgn: Rank at which the test begins
2379 * @use_read_test: Perform a read test
2380 * @update_fom: Update FOM
2382 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2386 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2387 const int use_read_test,
2388 const int update_fom)
2391 int ret, grp_calibrated;
2395 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2396 * Read per-bit deskew can be done on a per shadow register basis.
2399 for (rank_bgn = 0, sr = 0;
2400 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2401 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2402 /* Check if this set of ranks should be skipped entirely. */
2403 if (param->skip_shadow_regs[sr])
2406 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2416 if (!grp_calibrated)
2423 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2424 * @rw_group: Read/Write Group
2425 * @test_bgn: Rank at which the test begins
2427 * Stage 1: Calibrate the read valid prediction FIFO.
2429 * This function implements UniPHY calibration Stage 1, as explained in
2430 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2432 * - read valid prediction will consist of finding:
2433 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2434 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2435 * - we also do a per-bit deskew on the DQ lines.
2437 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2440 uint32_t dtaps_per_ptap;
2441 uint32_t failed_substage;
2445 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2447 /* Update info for sims */
2448 reg_file_set_group(rw_group);
2449 reg_file_set_stage(CAL_STAGE_VFIFO);
2450 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2452 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2454 /* USER Determine number of delay taps for each phase tap. */
2455 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2456 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2458 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2460 * In RLDRAMX we may be messing the delay of pins in
2461 * the same write rw_group but outside of the current read
2462 * the rw_group, but that's ok because we haven't calibrated
2466 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2470 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2471 /* 1) Guaranteed Write */
2472 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2476 /* 2) DQS Enable Calibration */
2477 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2480 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2484 /* 3) Centering DQ/DQS */
2486 * If doing read after write calibration, do not update
2487 * FOM now. Do it then.
2489 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2492 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2501 /* Calibration Stage 1 failed. */
2502 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2505 /* Calibration Stage 1 completed OK. */
2508 * Reset the delay chains back to zero if they have moved > 1
2509 * (check for > 1 because loop will increase d even when pass in
2513 scc_mgr_zero_group(rw_group, 1);
2518 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2519 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2522 uint32_t rank_bgn, sr;
2523 uint32_t grp_calibrated;
2524 uint32_t write_group;
2526 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2528 /* update info for sims */
2530 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2531 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2533 write_group = read_group;
2535 /* update info for sims */
2536 reg_file_set_group(read_group);
2539 /* Read per-bit deskew can be done on a per shadow register basis */
2540 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2541 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2542 /* Determine if this set of ranks should be skipped entirely */
2543 if (!param->skip_shadow_regs[sr]) {
2544 /* This is the last calibration round, update FOM here */
2545 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2556 if (grp_calibrated == 0) {
2557 set_failing_group_stage(write_group,
2558 CAL_STAGE_VFIFO_AFTER_WRITES,
2559 CAL_SUBSTAGE_VFIFO_CENTER);
2566 /* Calibrate LFIFO to find smallest read latency */
2567 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2571 debug("%s:%d\n", __func__, __LINE__);
2573 /* update info for sims */
2574 reg_file_set_stage(CAL_STAGE_LFIFO);
2575 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2577 /* Load up the patterns used by read calibration for all ranks */
2578 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2582 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2583 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2584 __func__, __LINE__, gbl->curr_read_lat);
2586 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2594 /* reduce read latency and see if things are working */
2596 gbl->curr_read_lat--;
2597 } while (gbl->curr_read_lat > 0);
2599 /* reset the fifos to get pointers to known state */
2601 writel(0, &phy_mgr_cmd->fifo_reset);
2604 /* add a fudge factor to the read latency that was determined */
2605 gbl->curr_read_lat += 2;
2606 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2607 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2608 read_lat=%u\n", __func__, __LINE__,
2609 gbl->curr_read_lat);
2612 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2613 CAL_SUBSTAGE_READ_LATENCY);
2615 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2616 read_lat=%u\n", __func__, __LINE__,
2617 gbl->curr_read_lat);
2623 * issue write test command.
2624 * two variants are provided. one that just tests a write pattern and
2625 * another that tests datamask functionality.
2627 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2630 uint32_t mcc_instruction;
2631 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2632 ENABLE_SUPER_QUICK_CALIBRATION);
2633 uint32_t rw_wl_nop_cycles;
2637 * Set counter and jump addresses for the right
2638 * number of NOP cycles.
2639 * The number of supported NOP cycles can range from -1 to infinity
2640 * Three different cases are handled:
2642 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2643 * mechanism will be used to insert the right number of NOPs
2645 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2646 * issuing the write command will jump straight to the
2647 * micro-instruction that turns on DQS (for DDRx), or outputs write
2648 * data (for RLD), skipping
2649 * the NOP micro-instruction all together
2651 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2652 * turned on in the same micro-instruction that issues the write
2653 * command. Then we need
2654 * to directly jump to the micro-instruction that sends out the data
2656 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2657 * (2 and 3). One jump-counter (0) is used to perform multiple
2658 * write-read operations.
2659 * one counter left to issue this command in "multiple-group" mode
2662 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2664 if (rw_wl_nop_cycles == -1) {
2666 * CNTR 2 - We want to execute the special write operation that
2667 * turns on DQS right away and then skip directly to the
2668 * instruction that sends out the data. We set the counter to a
2669 * large number so that the jump is always taken.
2671 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2673 /* CNTR 3 - Not used */
2675 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2676 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2677 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2678 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2679 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2681 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2682 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2683 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2684 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2685 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2687 } else if (rw_wl_nop_cycles == 0) {
2689 * CNTR 2 - We want to skip the NOP operation and go straight
2690 * to the DQS enable instruction. We set the counter to a large
2691 * number so that the jump is always taken.
2693 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2695 /* CNTR 3 - Not used */
2697 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2698 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2699 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2701 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2702 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2703 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2707 * CNTR 2 - In this case we want to execute the next instruction
2708 * and NOT take the jump. So we set the counter to 0. The jump
2709 * address doesn't count.
2711 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2712 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2715 * CNTR 3 - Set the nop counter to the number of cycles we
2716 * need to loop for, minus 1.
2718 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2720 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2721 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2722 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2724 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2725 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2726 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2730 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2731 RW_MGR_RESET_READ_DATAPATH_OFFSET);
2733 if (quick_write_mode)
2734 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2736 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2738 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2741 * CNTR 1 - This is used to ensure enough time elapses
2742 * for read data to come back.
2744 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2747 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2748 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2750 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2751 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2754 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2755 writel(mcc_instruction, addr + (group << 2));
2758 /* Test writes, can check for a single bit pass or multiple bit pass */
2759 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2760 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2761 uint32_t *bit_chk, uint32_t all_ranks)
2764 uint32_t correct_mask_vg;
2765 uint32_t tmp_bit_chk;
2767 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2768 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2769 uint32_t addr_rw_mgr;
2770 uint32_t base_rw_mgr;
2772 *bit_chk = param->write_correct_mask;
2773 correct_mask_vg = param->write_correct_mask_vg;
2775 for (r = rank_bgn; r < rank_end; r++) {
2776 if (param->skip_ranks[r]) {
2777 /* request to skip the rank */
2782 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2785 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2786 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2787 /* reset the fifos to get pointers to known state */
2788 writel(0, &phy_mgr_cmd->fifo_reset);
2790 tmp_bit_chk = tmp_bit_chk <<
2791 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2792 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2793 rw_mgr_mem_calibrate_write_test_issue(write_group *
2794 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2797 base_rw_mgr = readl(addr_rw_mgr);
2798 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2802 *bit_chk &= tmp_bit_chk;
2806 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2807 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2808 %u => %lu", write_group, use_dm,
2809 *bit_chk, param->write_correct_mask,
2810 (long unsigned int)(*bit_chk ==
2811 param->write_correct_mask));
2812 return *bit_chk == param->write_correct_mask;
2814 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2815 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2816 write_group, use_dm, *bit_chk);
2817 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2818 (long unsigned int)(*bit_chk != 0));
2819 return *bit_chk != 0x00;
2824 * center all windows. do per-bit-deskew to possibly increase size of
2827 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2828 uint32_t write_group, uint32_t test_bgn)
2830 uint32_t i, p, min_index;
2833 * Store these as signed since there are comparisons with
2837 uint32_t sticky_bit_chk;
2838 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2839 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2841 int32_t mid_min, orig_mid_min;
2842 int32_t new_dqs, start_dqs, shift_dq;
2843 int32_t dq_margin, dqs_margin, dm_margin;
2844 uint32_t temp_dq_out1_delay;
2849 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2853 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2854 start_dqs = readl(addr +
2855 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2857 /* per-bit deskew */
2860 * set the left and right edge of each bit to an illegal value
2861 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2864 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2865 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2866 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2869 /* Search for the left edge of the window for each bit */
2870 search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
2871 &bit_chk, &sticky_bit_chk,
2872 left_edge, right_edge, 0);
2874 /* Search for the right edge of the window for each bit */
2875 ret = search_right_edge(1, rank_bgn, write_group, 0,
2877 &bit_chk, &sticky_bit_chk,
2878 left_edge, right_edge, 0);
2880 set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
2881 CAL_SUBSTAGE_WRITES_CENTER);
2885 /* Find middle of window for each DQ bit */
2886 mid_min = left_edge[0] - right_edge[0];
2888 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2889 mid = left_edge[i] - right_edge[i];
2890 if (mid < mid_min) {
2897 * -mid_min/2 represents the amount that we need to move DQS.
2898 * If mid_min is odd and positive we'll need to add one to
2899 * make sure the rounding in further calculations is correct
2900 * (always bias to the right), so just add 1 for all positive values.
2904 mid_min = mid_min / 2;
2905 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2908 /* Determine the amount we can change DQS (which is -mid_min) */
2909 orig_mid_min = mid_min;
2910 new_dqs = start_dqs;
2912 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2913 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2914 /* Initialize data for export structures */
2915 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2916 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2918 /* add delay to bring centre of all DQ windows to the same "level" */
2919 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2920 /* Use values before divide by 2 to reduce round off error */
2921 shift_dq = (left_edge[i] - right_edge[i] -
2922 (left_edge[min_index] - right_edge[min_index]))/2 +
2923 (orig_mid_min - mid_min);
2925 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2926 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2928 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2929 temp_dq_out1_delay = readl(addr + (i << 2));
2930 if (shift_dq + (int32_t)temp_dq_out1_delay >
2931 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2932 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2933 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2934 shift_dq = -(int32_t)temp_dq_out1_delay;
2936 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2938 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2941 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2942 left_edge[i] - shift_dq + (-mid_min),
2943 right_edge[i] + shift_dq - (-mid_min));
2944 /* To determine values for export structures */
2945 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2946 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2948 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2949 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2953 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2954 writel(0, &sdr_scc_mgr->update);
2957 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2960 * set the left and right edge of each bit to an illegal value,
2961 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2963 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2964 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2965 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2966 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2967 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2968 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2969 int32_t win_best = 0;
2971 /* Search for the/part of the window with DM shift */
2972 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
2973 scc_mgr_apply_group_dm_out1_delay(d);
2974 writel(0, &sdr_scc_mgr->update);
2976 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2977 PASS_ALL_BITS, &bit_chk,
2979 /* USE Set current end of the window */
2982 * If a starting edge of our window has not been seen
2983 * this is our current start of the DM window.
2985 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
2989 * If current window is bigger than best seen.
2990 * Set best seen to be current window.
2992 if ((end_curr-bgn_curr+1) > win_best) {
2993 win_best = end_curr-bgn_curr+1;
2994 bgn_best = bgn_curr;
2995 end_best = end_curr;
2998 /* We just saw a failing test. Reset temp edge */
2999 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3000 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3005 /* Reset DM delay chains to 0 */
3006 scc_mgr_apply_group_dm_out1_delay(0);
3009 * Check to see if the current window nudges up aganist 0 delay.
3010 * If so we need to continue the search by shifting DQS otherwise DQS
3011 * search begins as a new search. */
3012 if (end_curr != 0) {
3013 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3014 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3017 /* Search for the/part of the window with DQS shifts */
3018 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3020 * Note: This only shifts DQS, so are we limiting ourselve to
3021 * width of DQ unnecessarily.
3023 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3026 writel(0, &sdr_scc_mgr->update);
3027 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3028 PASS_ALL_BITS, &bit_chk,
3030 /* USE Set current end of the window */
3033 * If a beginning edge of our window has not been seen
3034 * this is our current begin of the DM window.
3036 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3040 * If current window is bigger than best seen. Set best
3041 * seen to be current window.
3043 if ((end_curr-bgn_curr+1) > win_best) {
3044 win_best = end_curr-bgn_curr+1;
3045 bgn_best = bgn_curr;
3046 end_best = end_curr;
3049 /* We just saw a failing test. Reset temp edge */
3050 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3051 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3053 /* Early exit optimization: if ther remaining delay
3054 chain space is less than already seen largest window
3057 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3063 /* assign left and right edge for cal and reporting; */
3064 left_edge[0] = -1*bgn_best;
3065 right_edge[0] = end_best;
3067 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3068 __LINE__, left_edge[0], right_edge[0]);
3070 /* Move DQS (back to orig) */
3071 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3075 /* Find middle of window for the DM bit */
3076 mid = (left_edge[0] - right_edge[0]) / 2;
3078 /* only move right, since we are not moving DQS/DQ */
3082 /* dm_marign should fail if we never find a window */
3086 dm_margin = left_edge[0] - mid;
3088 scc_mgr_apply_group_dm_out1_delay(mid);
3089 writel(0, &sdr_scc_mgr->update);
3091 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3092 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3093 right_edge[0], mid, dm_margin);
3095 gbl->fom_out += dq_margin + dqs_margin;
3097 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3098 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3099 dq_margin, dqs_margin, dm_margin);
3102 * Do not remove this line as it makes sure all of our
3103 * decisions have been applied.
3105 writel(0, &sdr_scc_mgr->update);
3106 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3110 * rw_mgr_mem_calibrate_writes() - Write Calibration Part One
3111 * @rank_bgn: Rank number
3112 * @group: Read/Write Group
3113 * @test_bgn: Rank at which the test begins
3115 * Stage 2: Write Calibration Part One.
3117 * This function implements UniPHY calibration Stage 2, as explained in
3118 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
3120 static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group,
3125 /* Update info for sims */
3126 debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn);
3128 reg_file_set_group(group);
3129 reg_file_set_stage(CAL_STAGE_WRITES);
3130 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3132 ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
3134 set_failing_group_stage(group, CAL_STAGE_WRITES,
3135 CAL_SUBSTAGE_WRITES_CENTER);
3143 * mem_precharge_and_activate() - Precharge all banks and activate
3145 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3147 static void mem_precharge_and_activate(void)
3151 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3152 /* Test if the rank should be skipped. */
3153 if (param->skip_ranks[r])
3157 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3159 /* Precharge all banks. */
3160 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3161 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3163 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3164 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3165 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3167 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3168 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3169 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3171 /* Activate rows. */
3172 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3173 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3178 * mem_init_latency() - Configure memory RLAT and WLAT settings
3180 * Configure memory RLAT and WLAT parameters.
3182 static void mem_init_latency(void)
3185 * For AV/CV, LFIFO is hardened and always runs at full rate
3186 * so max latency in AFI clocks, used here, is correspondingly
3189 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3192 debug("%s:%d\n", __func__, __LINE__);
3195 * Read in write latency.
3196 * WL for Hard PHY does not include additive latency.
3198 wlat = readl(&data_mgr->t_wl_add);
3199 wlat += readl(&data_mgr->mem_t_add);
3201 gbl->rw_wl_nop_cycles = wlat - 1;
3203 /* Read in readl latency. */
3204 rlat = readl(&data_mgr->t_rl_add);
3206 /* Set a pretty high read latency initially. */
3207 gbl->curr_read_lat = rlat + 16;
3208 if (gbl->curr_read_lat > max_latency)
3209 gbl->curr_read_lat = max_latency;
3211 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3213 /* Advertise write latency. */
3214 writel(wlat, &phy_mgr_cfg->afi_wlat);
3218 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3220 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3222 static void mem_skip_calibrate(void)
3224 uint32_t vfifo_offset;
3227 debug("%s:%d\n", __func__, __LINE__);
3228 /* Need to update every shadow register set used by the interface */
3229 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3230 r += NUM_RANKS_PER_SHADOW_REG) {
3232 * Set output phase alignment settings appropriate for
3235 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3236 scc_mgr_set_dqs_en_phase(i, 0);
3237 #if IO_DLL_CHAIN_LENGTH == 6
3238 scc_mgr_set_dqdqs_output_phase(i, 6);
3240 scc_mgr_set_dqdqs_output_phase(i, 7);
3245 * Write data arrives to the I/O two cycles before write
3246 * latency is reached (720 deg).
3247 * -> due to bit-slip in a/c bus
3248 * -> to allow board skew where dqs is longer than ck
3249 * -> how often can this happen!?
3250 * -> can claim back some ptaps for high freq
3251 * support if we can relax this, but i digress...
3253 * The write_clk leads mem_ck by 90 deg
3254 * The minimum ptap of the OPA is 180 deg
3255 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3256 * The write_clk is always delayed by 2 ptaps
3258 * Hence, to make DQS aligned to CK, we need to delay
3260 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3262 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3263 * gives us the number of ptaps, which simplies to:
3265 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3267 scc_mgr_set_dqdqs_output_phase(i,
3268 1.25 * IO_DLL_CHAIN_LENGTH - 2);
3270 writel(0xff, &sdr_scc_mgr->dqs_ena);
3271 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3273 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3274 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3275 SCC_MGR_GROUP_COUNTER_OFFSET);
3277 writel(0xff, &sdr_scc_mgr->dq_ena);
3278 writel(0xff, &sdr_scc_mgr->dm_ena);
3279 writel(0, &sdr_scc_mgr->update);
3282 /* Compensate for simulation model behaviour */
3283 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3284 scc_mgr_set_dqs_bus_in_delay(i, 10);
3285 scc_mgr_load_dqs(i);
3287 writel(0, &sdr_scc_mgr->update);
3290 * ArriaV has hard FIFOs that can only be initialized by incrementing
3293 vfifo_offset = CALIB_VFIFO_OFFSET;
3294 for (j = 0; j < vfifo_offset; j++)
3295 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3296 writel(0, &phy_mgr_cmd->fifo_reset);
3299 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3300 * setting from generation-time constant.
3302 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3303 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3307 * mem_calibrate() - Memory calibration entry point.
3309 * Perform memory calibration.
3311 static uint32_t mem_calibrate(void)
3314 uint32_t rank_bgn, sr;
3315 uint32_t write_group, write_test_bgn;
3316 uint32_t read_group, read_test_bgn;
3317 uint32_t run_groups, current_run;
3318 uint32_t failing_groups = 0;
3319 uint32_t group_failed = 0;
3321 const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3322 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3324 debug("%s:%d\n", __func__, __LINE__);
3326 /* Initialize the data settings */
3327 gbl->error_substage = CAL_SUBSTAGE_NIL;
3328 gbl->error_stage = CAL_STAGE_NIL;
3329 gbl->error_group = 0xff;
3333 /* Initialize WLAT and RLAT. */
3336 /* Initialize bit slips. */
3337 mem_precharge_and_activate();
3339 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3340 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3341 SCC_MGR_GROUP_COUNTER_OFFSET);
3342 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3344 scc_mgr_set_hhp_extras();
3346 scc_set_bypass_mode(i);
3349 /* Calibration is skipped. */
3350 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3352 * Set VFIFO and LFIFO to instant-on settings in skip
3355 mem_skip_calibrate();
3358 * Do not remove this line as it makes sure all of our
3359 * decisions have been applied.
3361 writel(0, &sdr_scc_mgr->update);
3365 /* Calibration is not skipped. */
3366 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3368 * Zero all delay chain/phase settings for all
3369 * groups and all shadow register sets.
3373 run_groups = ~param->skip_groups;
3375 for (write_group = 0, write_test_bgn = 0; write_group
3376 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3377 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3379 /* Initialize the group failure */
3382 current_run = run_groups & ((1 <<
3383 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3384 run_groups = run_groups >>
3385 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3387 if (current_run == 0)
3390 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3391 SCC_MGR_GROUP_COUNTER_OFFSET);
3392 scc_mgr_zero_group(write_group, 0);
3394 for (read_group = write_group * rwdqs_ratio,
3396 read_group < (write_group + 1) * rwdqs_ratio;
3398 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3399 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3402 /* Calibrate the VFIFO */
3403 if (rw_mgr_mem_calibrate_vfifo(read_group,
3407 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3410 /* The group failed, we're done. */
3414 /* Calibrate the output side */
3415 for (rank_bgn = 0, sr = 0;
3416 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3417 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3418 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3421 /* Not needed in quick mode! */
3422 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3426 * Determine if this set of ranks
3427 * should be skipped entirely.
3429 if (param->skip_shadow_regs[sr])
3432 /* Calibrate WRITEs */
3433 if (!rw_mgr_mem_calibrate_writes(rank_bgn,
3434 write_group, write_test_bgn))
3438 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3442 /* Some group failed, we're done. */
3446 for (read_group = write_group * rwdqs_ratio,
3448 read_group < (write_group + 1) * rwdqs_ratio;
3450 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3451 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3454 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3458 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3461 /* The group failed, we're done. */
3465 /* No group failed, continue as usual. */
3468 grp_failed: /* A group failed, increment the counter. */
3473 * USER If there are any failing groups then report
3476 if (failing_groups != 0)
3479 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3483 * If we're skipping groups as part of debug,
3484 * don't calibrate LFIFO.
3486 if (param->skip_groups != 0)
3489 /* Calibrate the LFIFO */
3490 if (!rw_mgr_mem_calibrate_lfifo())
3495 * Do not remove this line as it makes sure all of our decisions
3496 * have been applied.
3498 writel(0, &sdr_scc_mgr->update);
3503 * run_mem_calibrate() - Perform memory calibration
3505 * This function triggers the entire memory calibration procedure.
3507 static int run_mem_calibrate(void)
3511 debug("%s:%d\n", __func__, __LINE__);
3513 /* Reset pass/fail status shown on afi_cal_success/fail */
3514 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3516 /* Stop tracking manager. */
3517 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3519 phy_mgr_initialize();
3520 rw_mgr_mem_initialize();
3522 /* Perform the actual memory calibration. */
3523 pass = mem_calibrate();
3525 mem_precharge_and_activate();
3526 writel(0, &phy_mgr_cmd->fifo_reset);
3529 rw_mgr_mem_handoff();
3531 * In Hard PHY this is a 2-bit control:
3533 * 1: DDIO Mux Select
3535 writel(0x2, &phy_mgr_cfg->mux_sel);
3537 /* Start tracking manager. */
3538 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3544 * debug_mem_calibrate() - Report result of memory calibration
3545 * @pass: Value indicating whether calibration passed or failed
3547 * This function reports the results of the memory calibration
3548 * and writes debug information into the register file.
3550 static void debug_mem_calibrate(int pass)
3552 uint32_t debug_info;
3555 printf("%s: CALIBRATION PASSED\n", __FILE__);
3560 if (gbl->fom_in > 0xff)
3563 if (gbl->fom_out > 0xff)
3564 gbl->fom_out = 0xff;
3566 /* Update the FOM in the register file */
3567 debug_info = gbl->fom_in;
3568 debug_info |= gbl->fom_out << 8;
3569 writel(debug_info, &sdr_reg_file->fom);
3571 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3572 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3574 printf("%s: CALIBRATION FAILED\n", __FILE__);
3576 debug_info = gbl->error_stage;
3577 debug_info |= gbl->error_substage << 8;
3578 debug_info |= gbl->error_group << 16;
3580 writel(debug_info, &sdr_reg_file->failing_stage);
3581 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3582 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3584 /* Update the failing group/stage in the register file */
3585 debug_info = gbl->error_stage;
3586 debug_info |= gbl->error_substage << 8;
3587 debug_info |= gbl->error_group << 16;
3588 writel(debug_info, &sdr_reg_file->failing_stage);
3591 printf("%s: Calibration complete\n", __FILE__);
3595 * hc_initialize_rom_data() - Initialize ROM data
3597 * Initialize ROM data.
3599 static void hc_initialize_rom_data(void)
3603 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3604 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3605 writel(inst_rom_init[i], addr + (i << 2));
3607 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3608 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3609 writel(ac_rom_init[i], addr + (i << 2));
3613 * initialize_reg_file() - Initialize SDR register file
3615 * Initialize SDR register file.
3617 static void initialize_reg_file(void)
3619 /* Initialize the register file with the correct data */
3620 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3621 writel(0, &sdr_reg_file->debug_data_addr);
3622 writel(0, &sdr_reg_file->cur_stage);
3623 writel(0, &sdr_reg_file->fom);
3624 writel(0, &sdr_reg_file->failing_stage);
3625 writel(0, &sdr_reg_file->debug1);
3626 writel(0, &sdr_reg_file->debug2);
3630 * initialize_hps_phy() - Initialize HPS PHY
3632 * Initialize HPS PHY.
3634 static void initialize_hps_phy(void)
3638 * Tracking also gets configured here because it's in the
3641 uint32_t trk_sample_count = 7500;
3642 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3644 * Format is number of outer loops in the 16 MSB, sample
3649 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3650 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3651 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3652 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3653 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3654 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3656 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3657 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3659 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3660 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3662 writel(reg, &sdr_ctrl->phy_ctrl0);
3665 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3667 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3668 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3669 trk_long_idle_sample_count);
3670 writel(reg, &sdr_ctrl->phy_ctrl1);
3673 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3674 trk_long_idle_sample_count >>
3675 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3676 writel(reg, &sdr_ctrl->phy_ctrl2);
3680 * initialize_tracking() - Initialize tracking
3682 * Initialize the register file with usable initial data.
3684 static void initialize_tracking(void)
3687 * Initialize the register file with the correct data.
3688 * Compute usable version of value in case we skip full
3689 * computation later.
3691 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3692 &sdr_reg_file->dtaps_per_ptap);
3694 /* trk_sample_count */
3695 writel(7500, &sdr_reg_file->trk_sample_count);
3697 /* longidle outer loop [15:0] */
3698 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3701 * longidle sample count [31:24]
3702 * trfc, worst case of 933Mhz 4Gb [23:16]
3703 * trcd, worst case [15:8]
3706 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3707 &sdr_reg_file->delays);
3710 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3711 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3712 &sdr_reg_file->trk_rw_mgr_addr);
3714 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3715 &sdr_reg_file->trk_read_dqs_width);
3718 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3719 &sdr_reg_file->trk_rfsh);
3722 int sdram_calibration_full(void)
3724 struct param_type my_param;
3725 struct gbl_type my_gbl;
3728 memset(&my_param, 0, sizeof(my_param));
3729 memset(&my_gbl, 0, sizeof(my_gbl));
3734 /* Set the calibration enabled by default */
3735 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3737 * Only sweep all groups (regardless of fail state) by default
3738 * Set enabled read test by default.
3740 #if DISABLE_GUARANTEED_READ
3741 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3743 /* Initialize the register file */
3744 initialize_reg_file();
3746 /* Initialize any PHY CSR */
3747 initialize_hps_phy();
3749 scc_mgr_initialize();
3751 initialize_tracking();
3753 printf("%s: Preparing to start memory calibration\n", __FILE__);
3755 debug("%s:%d\n", __func__, __LINE__);
3756 debug_cond(DLEVEL == 1,
3757 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3758 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3759 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3760 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3761 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3762 debug_cond(DLEVEL == 1,
3763 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3764 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3765 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3766 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3767 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3768 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3769 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3770 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3771 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3772 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3773 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3774 IO_IO_OUT2_DELAY_MAX);
3775 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3776 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3778 hc_initialize_rom_data();
3780 /* update info for sims */
3781 reg_file_set_stage(CAL_STAGE_NIL);
3782 reg_file_set_group(0);
3785 * Load global needed for those actions that require
3786 * some dynamic calibration support.
3788 dyn_calib_steps = STATIC_CALIB_STEPS;
3790 * Load global to allow dynamic selection of delay loop settings
3791 * based on calibration mode.
3793 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3794 skip_delay_mask = 0xff;
3796 skip_delay_mask = 0x0;
3798 pass = run_mem_calibrate();
3799 debug_mem_calibrate(pass);