drivers/ddr/altera/sequencer.c

   1 /*
   2  * Copyright Altera Corporation (C) 2012-2015
   3  *
   4  * SPDX-License-Identifier:    BSD-3-Clause
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/sdram.h>
  10 #include <errno.h>
  11 #include "sequencer.h"
  12 #include "sequencer_auto.h"
  13 #include "sequencer_auto_ac_init.h"
  14 #include "sequencer_auto_inst_init.h"
  15 #include "sequencer_defines.h"
  16
  17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
  18         (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
  19
  20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
  21         (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
  22
  23 static struct socfpga_sdr_reg_file *sdr_reg_file =
  24         (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
  25
  26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
  27         (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
  28
  29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
  30         (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
  31
  32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
  33         (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
  34
  35 static struct socfpga_data_mgr *data_mgr =
  36         (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
  37
  38 static struct socfpga_sdr_ctrl *sdr_ctrl =
  39         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  40
  41 #define DELTA_D         1
  42
  43 /*
  44  * In order to reduce ROM size, most of the selectable calibration steps are
  45  * decided at compile time based on the user's calibration mode selection,
  46  * as captured by the STATIC_CALIB_STEPS selection below.
  47  *
  48  * However, to support simulation-time selection of fast simulation mode, where
  49  * we skip everything except the bare minimum, we need a few of the steps to
  50  * be dynamic.  In those cases, we either use the DYNAMIC_CALIB_STEPS for the
  51  * check, which is based on the rtl-supplied value, or we dynamically compute
  52  * the value to use based on the dynamically-chosen calibration mode
  53  */
  54
  55 #define DLEVEL 0
  56 #define STATIC_IN_RTL_SIM 0
  57 #define STATIC_SKIP_DELAY_LOOPS 0
  58
  59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
  60         STATIC_SKIP_DELAY_LOOPS)
  61
  62 /* calibration steps requested by the rtl */
  63 uint16_t dyn_calib_steps;
  64
  65 /*
  66  * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
  67  * instead of static, we use boolean logic to select between
  68  * non-skip and skip values
  69  *
  70  * The mask is set to include all bits when not-skipping, but is
  71  * zero when skipping
  72  */
  73
  74 uint16_t skip_delay_mask;       /* mask off bits when skipping/not-skipping */
  75
  76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
  77         ((non_skip_value) & skip_delay_mask)
  78
  79 struct gbl_type *gbl;
  80 struct param_type *param;
  81 uint32_t curr_shadow_reg;
  82
  83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
  84         uint32_t write_group, uint32_t use_dm,
  85         uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
  86
  87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
  88         uint32_t substage)
  89 {
  90         /*
  91          * Only set the global stage if there was not been any other
  92          * failing group
  93          */
  94         if (gbl->error_stage == CAL_STAGE_NIL)  {
  95                 gbl->error_substage = substage;
  96                 gbl->error_stage = stage;
  97                 gbl->error_group = group;
  98         }
  99 }
 100
 101 static void reg_file_set_group(u16 set_group)
 102 {
 103         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
 104 }
 105
 106 static void reg_file_set_stage(u8 set_stage)
 107 {
 108         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
 109 }
 110
 111 static void reg_file_set_sub_stage(u8 set_sub_stage)
 112 {
 113         set_sub_stage &= 0xff;
 114         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
 115 }
 116
 117 /**
 118  * phy_mgr_initialize() - Initialize PHY Manager
 119  *
 120  * Initialize PHY Manager.
 121  */
 122 static void phy_mgr_initialize(void)
 123 {
 124         u32 ratio;
 125
 126         debug("%s:%d\n", __func__, __LINE__);
 127         /* Calibration has control over path to memory */
 128         /*
 129          * In Hard PHY this is a 2-bit control:
 130          * 0: AFI Mux Select
 131          * 1: DDIO Mux Select
 132          */
 133         writel(0x3, &phy_mgr_cfg->mux_sel);
 134
 135         /* USER memory clock is not stable we begin initialization  */
 136         writel(0, &phy_mgr_cfg->reset_mem_stbl);
 137
 138         /* USER calibration status all set to zero */
 139         writel(0, &phy_mgr_cfg->cal_status);
 140
 141         writel(0, &phy_mgr_cfg->cal_debug_info);
 142
 143         /* Init params only if we do NOT skip calibration. */
 144         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
 145                 return;
 146
 147         ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
 148                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
 149         param->read_correct_mask_vg = (1 << ratio) - 1;
 150         param->write_correct_mask_vg = (1 << ratio) - 1;
 151         param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
 152         param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
 153         ratio = RW_MGR_MEM_DATA_WIDTH /
 154                 RW_MGR_MEM_DATA_MASK_WIDTH;
 155         param->dm_correct_mask = (1 << ratio) - 1;
 156 }
 157
 158 /**
 159  * set_rank_and_odt_mask() - Set Rank and ODT mask
 160  * @rank:       Rank mask
 161  * @odt_mode:   ODT mode, OFF or READ_WRITE
 162  *
 163  * Set Rank and ODT mask (On-Die Termination).
 164  */
 165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
 166 {
 167         u32 odt_mask_0 = 0;
 168         u32 odt_mask_1 = 0;
 169         u32 cs_and_odt_mask;
 170
 171         if (odt_mode == RW_MGR_ODT_MODE_OFF) {
 172                 odt_mask_0 = 0x0;
 173                 odt_mask_1 = 0x0;
 174         } else {        /* RW_MGR_ODT_MODE_READ_WRITE */
 175                 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
 176                 case 1: /* 1 Rank */
 177                         /* Read: ODT = 0 ; Write: ODT = 1 */
 178                         odt_mask_0 = 0x0;
 179                         odt_mask_1 = 0x1;
 180                         break;
 181                 case 2: /* 2 Ranks */
 182                         if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
 183                                 /*
 184                                  * - Dual-Slot , Single-Rank (1 CS per DIMM)
 185                                  *   OR
 186                                  * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
 187                                  *
 188                                  * Since MEM_NUMBER_OF_RANKS is 2, they
 189                                  * are both single rank with 2 CS each
 190                                  * (special for RDIMM).
 191                                  *
 192                                  * Read: Turn on ODT on the opposite rank
 193                                  * Write: Turn on ODT on all ranks
 194                                  */
 195                                 odt_mask_0 = 0x3 & ~(1 << rank);
 196                                 odt_mask_1 = 0x3;
 197                         } else {
 198                                 /*
 199                                  * - Single-Slot , Dual-Rank (2 CS per DIMM)
 200                                  *
 201                                  * Read: Turn on ODT off on all ranks
 202                                  * Write: Turn on ODT on active rank
 203                                  */
 204                                 odt_mask_0 = 0x0;
 205                                 odt_mask_1 = 0x3 & (1 << rank);
 206                         }
 207                         break;
 208                 case 4: /* 4 Ranks */
 209                         /* Read:
 210                          * ----------+-----------------------+
 211                          *           |         ODT           |
 212                          * Read From +-----------------------+
 213                          *   Rank    |  3  |  2  |  1  |  0  |
 214                          * ----------+-----+-----+-----+-----+
 215                          *     0     |  0  |  1  |  0  |  0  |
 216                          *     1     |  1  |  0  |  0  |  0  |
 217                          *     2     |  0  |  0  |  0  |  1  |
 218                          *     3     |  0  |  0  |  1  |  0  |
 219                          * ----------+-----+-----+-----+-----+
 220                          *
 221                          * Write:
 222                          * ----------+-----------------------+
 223                          *           |         ODT           |
 224                          * Write To  +-----------------------+
 225                          *   Rank    |  3  |  2  |  1  |  0  |
 226                          * ----------+-----+-----+-----+-----+
 227                          *     0     |  0  |  1  |  0  |  1  |
 228                          *     1     |  1  |  0  |  1  |  0  |
 229                          *     2     |  0  |  1  |  0  |  1  |
 230                          *     3     |  1  |  0  |  1  |  0  |
 231                          * ----------+-----+-----+-----+-----+
 232                          */
 233                         switch (rank) {
 234                         case 0:
 235                                 odt_mask_0 = 0x4;
 236                                 odt_mask_1 = 0x5;
 237                                 break;
 238                         case 1:
 239                                 odt_mask_0 = 0x8;
 240                                 odt_mask_1 = 0xA;
 241                                 break;
 242                         case 2:
 243                                 odt_mask_0 = 0x1;
 244                                 odt_mask_1 = 0x5;
 245                                 break;
 246                         case 3:
 247                                 odt_mask_0 = 0x2;
 248                                 odt_mask_1 = 0xA;
 249                                 break;
 250                         }
 251                         break;
 252                 }
 253         }
 254
 255         cs_and_odt_mask = (0xFF & ~(1 << rank)) |
 256                           ((0xFF & odt_mask_0) << 8) |
 257                           ((0xFF & odt_mask_1) << 16);
 258         writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 259                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 260 }
 261
 262 /**
 263  * scc_mgr_set() - Set SCC Manager register
 264  * @off:        Base offset in SCC Manager space
 265  * @grp:        Read/Write group
 266  * @val:        Value to be set
 267  *
 268  * This function sets the SCC Manager (Scan Chain Control Manager) register.
 269  */
 270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
 271 {
 272         writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
 273 }
 274
 275 /**
 276  * scc_mgr_initialize() - Initialize SCC Manager registers
 277  *
 278  * Initialize SCC Manager registers.
 279  */
 280 static void scc_mgr_initialize(void)
 281 {
 282         /*
 283          * Clear register file for HPS. 16 (2^4) is the size of the
 284          * full register file in the scc mgr:
 285          *      RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
 286          *                             MEM_IF_READ_DQS_WIDTH - 1);
 287          */
 288         int i;
 289
 290         for (i = 0; i < 16; i++) {
 291                 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
 292                            __func__, __LINE__, i);
 293                 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
 294         }
 295 }
 296
 297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
 298 {
 299         scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
 300 }
 301
 302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
 303 {
 304         scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
 305 }
 306
 307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
 308 {
 309         scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
 310 }
 311
 312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
 313 {
 314         scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
 315 }
 316
 317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
 318 {
 319         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 320                     delay);
 321 }
 322
 323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
 324 {
 325         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
 326 }
 327
 328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
 329 {
 330         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
 331 }
 332
 333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
 334 {
 335         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 336                     delay);
 337 }
 338
 339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
 340 {
 341         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
 342                     RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
 343                     delay);
 344 }
 345
 346 /* load up dqs config settings */
 347 static void scc_mgr_load_dqs(uint32_t dqs)
 348 {
 349         writel(dqs, &sdr_scc_mgr->dqs_ena);
 350 }
 351
 352 /* load up dqs io config settings */
 353 static void scc_mgr_load_dqs_io(void)
 354 {
 355         writel(0, &sdr_scc_mgr->dqs_io_ena);
 356 }
 357
 358 /* load up dq config settings */
 359 static void scc_mgr_load_dq(uint32_t dq_in_group)
 360 {
 361         writel(dq_in_group, &sdr_scc_mgr->dq_ena);
 362 }
 363
 364 /* load up dm config settings */
 365 static void scc_mgr_load_dm(uint32_t dm)
 366 {
 367         writel(dm, &sdr_scc_mgr->dm_ena);
 368 }
 369
 370 /**
 371  * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
 372  * @off:        Base offset in SCC Manager space
 373  * @grp:        Read/Write group
 374  * @val:        Value to be set
 375  * @update:     If non-zero, trigger SCC Manager update for all ranks
 376  *
 377  * This function sets the SCC Manager (Scan Chain Control Manager) register
 378  * and optionally triggers the SCC update for all ranks.
 379  */
 380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
 381                                   const int update)
 382 {
 383         u32 r;
 384
 385         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 386              r += NUM_RANKS_PER_SHADOW_REG) {
 387                 scc_mgr_set(off, grp, val);
 388
 389                 if (update || (r == 0)) {
 390                         writel(grp, &sdr_scc_mgr->dqs_ena);
 391                         writel(0, &sdr_scc_mgr->update);
 392                 }
 393         }
 394 }
 395
 396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
 397 {
 398         /*
 399          * USER although the h/w doesn't support different phases per
 400          * shadow register, for simplicity our scc manager modeling
 401          * keeps different phase settings per shadow reg, and it's
 402          * important for us to keep them in sync to match h/w.
 403          * for efficiency, the scan chain update should occur only
 404          * once to sr0.
 405          */
 406         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
 407                               read_group, phase, 0);
 408 }
 409
 410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
 411                                                      uint32_t phase)
 412 {
 413         /*
 414          * USER although the h/w doesn't support different phases per
 415          * shadow register, for simplicity our scc manager modeling
 416          * keeps different phase settings per shadow reg, and it's
 417          * important for us to keep them in sync to match h/w.
 418          * for efficiency, the scan chain update should occur only
 419          * once to sr0.
 420          */
 421         scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
 422                               write_group, phase, 0);
 423 }
 424
 425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
 426                                                uint32_t delay)
 427 {
 428         /*
 429          * In shadow register mode, the T11 settings are stored in
 430          * registers in the core, which are updated by the DQS_ENA
 431          * signals. Not issuing the SCC_MGR_UPD command allows us to
 432          * save lots of rank switching overhead, by calling
 433          * select_shadow_regs_for_update with update_scan_chains
 434          * set to 0.
 435          */
 436         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
 437                               read_group, delay, 1);
 438         writel(0, &sdr_scc_mgr->update);
 439 }
 440
 441 /**
 442  * scc_mgr_set_oct_out1_delay() - Set OCT output delay
 443  * @write_group:        Write group
 444  * @delay:              Delay value
 445  *
 446  * This function sets the OCT output delay in SCC manager.
 447  */
 448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
 449 {
 450         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 451                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 452         const int base = write_group * ratio;
 453         int i;
 454         /*
 455          * Load the setting in the SCC manager
 456          * Although OCT affects only write data, the OCT delay is controlled
 457          * by the DQS logic block which is instantiated once per read group.
 458          * For protocols where a write group consists of multiple read groups,
 459          * the setting must be set multiple times.
 460          */
 461         for (i = 0; i < ratio; i++)
 462                 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
 463 }
 464
 465 /**
 466  * scc_mgr_set_hhp_extras() - Set HHP extras.
 467  *
 468  * Load the fixed setting in the SCC manager HHP extras.
 469  */
 470 static void scc_mgr_set_hhp_extras(void)
 471 {
 472         /*
 473          * Load the fixed setting in the SCC manager
 474          * bits: 0:0 = 1'b1     - DQS bypass
 475          * bits: 1:1 = 1'b1     - DQ bypass
 476          * bits: 4:2 = 3'b001   - rfifo_mode
 477          * bits: 6:5 = 2'b01    - rfifo clock_select
 478          * bits: 7:7 = 1'b0     - separate gating from ungating setting
 479          * bits: 8:8 = 1'b0     - separate OE from Output delay setting
 480          */
 481         const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
 482                           (1 << 2) | (1 << 1) | (1 << 0);
 483         const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
 484                          SCC_MGR_HHP_GLOBALS_OFFSET |
 485                          SCC_MGR_HHP_EXTRAS_OFFSET;
 486
 487         debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
 488                    __func__, __LINE__);
 489         writel(value, addr);
 490         debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
 491                    __func__, __LINE__);
 492 }
 493
 494 /**
 495  * scc_mgr_zero_all() - Zero all DQS config
 496  *
 497  * Zero all DQS config.
 498  */
 499 static void scc_mgr_zero_all(void)
 500 {
 501         int i, r;
 502
 503         /*
 504          * USER Zero all DQS config settings, across all groups and all
 505          * shadow registers
 506          */
 507         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 508              r += NUM_RANKS_PER_SHADOW_REG) {
 509                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
 510                         /*
 511                          * The phases actually don't exist on a per-rank basis,
 512                          * but there's no harm updating them several times, so
 513                          * let's keep the code simple.
 514                          */
 515                         scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
 516                         scc_mgr_set_dqs_en_phase(i, 0);
 517                         scc_mgr_set_dqs_en_delay(i, 0);
 518                 }
 519
 520                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
 521                         scc_mgr_set_dqdqs_output_phase(i, 0);
 522                         /* Arria V/Cyclone V don't have out2. */
 523                         scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
 524                 }
 525         }
 526
 527         /* Multicast to all DQS group enables. */
 528         writel(0xff, &sdr_scc_mgr->dqs_ena);
 529         writel(0, &sdr_scc_mgr->update);
 530 }
 531
 532 /**
 533  * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
 534  * @write_group:        Write group
 535  *
 536  * Set bypass mode and trigger SCC update.
 537  */
 538 static void scc_set_bypass_mode(const u32 write_group)
 539 {
 540         /* Multicast to all DQ enables. */
 541         writel(0xff, &sdr_scc_mgr->dq_ena);
 542         writel(0xff, &sdr_scc_mgr->dm_ena);
 543
 544         /* Update current DQS IO enable. */
 545         writel(0, &sdr_scc_mgr->dqs_io_ena);
 546
 547         /* Update the DQS logic. */
 548         writel(write_group, &sdr_scc_mgr->dqs_ena);
 549
 550         /* Hit update. */
 551         writel(0, &sdr_scc_mgr->update);
 552 }
 553
 554 /**
 555  * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
 556  * @write_group:        Write group
 557  *
 558  * Load DQS settings for Write Group, do not trigger SCC update.
 559  */
 560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
 561 {
 562         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 563                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 564         const int base = write_group * ratio;
 565         int i;
 566         /*
 567          * Load the setting in the SCC manager
 568          * Although OCT affects only write data, the OCT delay is controlled
 569          * by the DQS logic block which is instantiated once per read group.
 570          * For protocols where a write group consists of multiple read groups,
 571          * the setting must be set multiple times.
 572          */
 573         for (i = 0; i < ratio; i++)
 574                 writel(base + i, &sdr_scc_mgr->dqs_ena);
 575 }
 576
 577 /**
 578  * scc_mgr_zero_group() - Zero all configs for a group
 579  *
 580  * Zero DQ, DM, DQS and OCT configs for a group.
 581  */
 582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
 583 {
 584         int i, r;
 585
 586         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 587              r += NUM_RANKS_PER_SHADOW_REG) {
 588                 /* Zero all DQ config settings. */
 589                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 590                         scc_mgr_set_dq_out1_delay(i, 0);
 591                         if (!out_only)
 592                                 scc_mgr_set_dq_in_delay(i, 0);
 593                 }
 594
 595                 /* Multicast to all DQ enables. */
 596                 writel(0xff, &sdr_scc_mgr->dq_ena);
 597
 598                 /* Zero all DM config settings. */
 599                 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 600                         scc_mgr_set_dm_out1_delay(i, 0);
 601
 602                 /* Multicast to all DM enables. */
 603                 writel(0xff, &sdr_scc_mgr->dm_ena);
 604
 605                 /* Zero all DQS IO settings. */
 606                 if (!out_only)
 607                         scc_mgr_set_dqs_io_in_delay(0);
 608
 609                 /* Arria V/Cyclone V don't have out2. */
 610                 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
 611                 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
 612                 scc_mgr_load_dqs_for_write_group(write_group);
 613
 614                 /* Multicast to all DQS IO enables (only 1 in total). */
 615                 writel(0, &sdr_scc_mgr->dqs_io_ena);
 616
 617                 /* Hit update to zero everything. */
 618                 writel(0, &sdr_scc_mgr->update);
 619         }
 620 }
 621
 622 /*
 623  * apply and load a particular input delay for the DQ pins in a group
 624  * group_bgn is the index of the first dq pin (in the write group)
 625  */
 626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
 627 {
 628         uint32_t i, p;
 629
 630         for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
 631                 scc_mgr_set_dq_in_delay(p, delay);
 632                 scc_mgr_load_dq(p);
 633         }
 634 }
 635
 636 /**
 637  * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
 638  * @delay:              Delay value
 639  *
 640  * Apply and load a particular output delay for the DQ pins in a group.
 641  */
 642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
 643 {
 644         int i;
 645
 646         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 647                 scc_mgr_set_dq_out1_delay(i, delay);
 648                 scc_mgr_load_dq(i);
 649         }
 650 }
 651
 652 /* apply and load a particular output delay for the DM pins in a group */
 653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
 654 {
 655         uint32_t i;
 656
 657         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
 658                 scc_mgr_set_dm_out1_delay(i, delay1);
 659                 scc_mgr_load_dm(i);
 660         }
 661 }
 662
 663
 664 /* apply and load delay on both DQS and OCT out1 */
 665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
 666                                                     uint32_t delay)
 667 {
 668         scc_mgr_set_dqs_out1_delay(delay);
 669         scc_mgr_load_dqs_io();
 670
 671         scc_mgr_set_oct_out1_delay(write_group, delay);
 672         scc_mgr_load_dqs_for_write_group(write_group);
 673 }
 674
 675 /**
 676  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
 677  * @write_group:        Write group
 678  * @delay:              Delay value
 679  *
 680  * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
 681  */
 682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
 683                                                   const u32 delay)
 684 {
 685         u32 i, new_delay;
 686
 687         /* DQ shift */
 688         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
 689                 scc_mgr_load_dq(i);
 690
 691         /* DM shift */
 692         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 693                 scc_mgr_load_dm(i);
 694
 695         /* DQS shift */
 696         new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
 697         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 698                 debug_cond(DLEVEL == 1,
 699                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 700                            __func__, __LINE__, write_group, delay, new_delay,
 701                            IO_IO_OUT2_DELAY_MAX,
 702                            new_delay - IO_IO_OUT2_DELAY_MAX);
 703                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 704                 scc_mgr_set_dqs_out1_delay(new_delay);
 705         }
 706
 707         scc_mgr_load_dqs_io();
 708
 709         /* OCT shift */
 710         new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
 711         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 712                 debug_cond(DLEVEL == 1,
 713                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 714                            __func__, __LINE__, write_group, delay,
 715                            new_delay, IO_IO_OUT2_DELAY_MAX,
 716                            new_delay - IO_IO_OUT2_DELAY_MAX);
 717                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 718                 scc_mgr_set_oct_out1_delay(write_group, new_delay);
 719         }
 720
 721         scc_mgr_load_dqs_for_write_group(write_group);
 722 }
 723
 724 /**
 725  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
 726  * @write_group:        Write group
 727  * @delay:              Delay value
 728  *
 729  * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
 730  */
 731 static void
 732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
 733                                                 const u32 delay)
 734 {
 735         int r;
 736
 737         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 738              r += NUM_RANKS_PER_SHADOW_REG) {
 739                 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
 740                 writel(0, &sdr_scc_mgr->update);
 741         }
 742 }
 743
 744 /**
 745  * set_jump_as_return() - Return instruction optimization
 746  *
 747  * Optimization used to recover some slots in ddr3 inst_rom could be
 748  * applied to other protocols if we wanted to
 749  */
 750 static void set_jump_as_return(void)
 751 {
 752         /*
 753          * To save space, we replace return with jump to special shared
 754          * RETURN instruction so we set the counter to large value so that
 755          * we always jump.
 756          */
 757         writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
 758         writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 759 }
 760
 761 /*
 762  * should always use constants as argument to ensure all computations are
 763  * performed at compile time
 764  */
 765 static void delay_for_n_mem_clocks(const uint32_t clocks)
 766 {
 767         uint32_t afi_clocks;
 768         uint8_t inner = 0;
 769         uint8_t outer = 0;
 770         uint16_t c_loop = 0;
 771
 772         debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
 773
 774
 775         afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
 776         /* scale (rounding up) to get afi clocks */
 777
 778         /*
 779          * Note, we don't bother accounting for being off a little bit
 780          * because of a few extra instructions in outer loops
 781          * Note, the loops have a test at the end, and do the test before
 782          * the decrement, and so always perform the loop
 783          * 1 time more than the counter value
 784          */
 785         if (afi_clocks == 0) {
 786                 ;
 787         } else if (afi_clocks <= 0x100) {
 788                 inner = afi_clocks-1;
 789                 outer = 0;
 790                 c_loop = 0;
 791         } else if (afi_clocks <= 0x10000) {
 792                 inner = 0xff;
 793                 outer = (afi_clocks-1) >> 8;
 794                 c_loop = 0;
 795         } else {
 796                 inner = 0xff;
 797                 outer = 0xff;
 798                 c_loop = (afi_clocks-1) >> 16;
 799         }
 800
 801         /*
 802          * rom instructions are structured as follows:
 803          *
 804          *    IDLE_LOOP2: jnz cntr0, TARGET_A
 805          *    IDLE_LOOP1: jnz cntr1, TARGET_B
 806          *                return
 807          *
 808          * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
 809          * TARGET_B is set to IDLE_LOOP2 as well
 810          *
 811          * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
 812          * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
 813          *
 814          * a little confusing, but it helps save precious space in the inst_rom
 815          * and sequencer rom and keeps the delays more accurate and reduces
 816          * overhead
 817          */
 818         if (afi_clocks <= 0x100) {
 819                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 820                         &sdr_rw_load_mgr_regs->load_cntr1);
 821
 822                 writel(RW_MGR_IDLE_LOOP1,
 823                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 824
 825                 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 826                                           RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 827         } else {
 828                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 829                         &sdr_rw_load_mgr_regs->load_cntr0);
 830
 831                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
 832                         &sdr_rw_load_mgr_regs->load_cntr1);
 833
 834                 writel(RW_MGR_IDLE_LOOP2,
 835                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 836
 837                 writel(RW_MGR_IDLE_LOOP2,
 838                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 839
 840                 /* hack to get around compiler not being smart enough */
 841                 if (afi_clocks <= 0x10000) {
 842                         /* only need to run once */
 843                         writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 844                                                   RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 845                 } else {
 846                         do {
 847                                 writel(RW_MGR_IDLE_LOOP2,
 848                                         SDR_PHYGRP_RWMGRGRP_ADDRESS |
 849                                         RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 850                         } while (c_loop-- != 0);
 851                 }
 852         }
 853         debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
 854 }
 855
 856 /**
 857  * rw_mgr_mem_init_load_regs() - Load instruction registers
 858  * @cntr0:      Counter 0 value
 859  * @cntr1:      Counter 1 value
 860  * @cntr2:      Counter 2 value
 861  * @jump:       Jump instruction value
 862  *
 863  * Load instruction registers.
 864  */
 865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
 866 {
 867         uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 868                            RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 869
 870         /* Load counters */
 871         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
 872                &sdr_rw_load_mgr_regs->load_cntr0);
 873         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
 874                &sdr_rw_load_mgr_regs->load_cntr1);
 875         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
 876                &sdr_rw_load_mgr_regs->load_cntr2);
 877
 878         /* Load jump address */
 879         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 880         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 881         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
 882
 883         /* Execute count instruction */
 884         writel(jump, grpaddr);
 885 }
 886
 887 /**
 888  * rw_mgr_mem_load_user() - Load user calibration values
 889  * @fin1:       Final instruction 1
 890  * @fin2:       Final instruction 2
 891  * @precharge:  If 1, precharge the banks at the end
 892  *
 893  * Load user calibration values and optionally precharge the banks.
 894  */
 895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
 896                                  const int precharge)
 897 {
 898         u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 899                       RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 900         u32 r;
 901
 902         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
 903                 if (param->skip_ranks[r]) {
 904                         /* request to skip the rank */
 905                         continue;
 906                 }
 907
 908                 /* set rank */
 909                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
 910
 911                 /* precharge all banks ... */
 912                 if (precharge)
 913                         writel(RW_MGR_PRECHARGE_ALL, grpaddr);
 914
 915                 /*
 916                  * USER Use Mirror-ed commands for odd ranks if address
 917                  * mirrorring is on
 918                  */
 919                 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
 920                         set_jump_as_return();
 921                         writel(RW_MGR_MRS2_MIRR, grpaddr);
 922                         delay_for_n_mem_clocks(4);
 923                         set_jump_as_return();
 924                         writel(RW_MGR_MRS3_MIRR, grpaddr);
 925                         delay_for_n_mem_clocks(4);
 926                         set_jump_as_return();
 927                         writel(RW_MGR_MRS1_MIRR, grpaddr);
 928                         delay_for_n_mem_clocks(4);
 929                         set_jump_as_return();
 930                         writel(fin1, grpaddr);
 931                 } else {
 932                         set_jump_as_return();
 933                         writel(RW_MGR_MRS2, grpaddr);
 934                         delay_for_n_mem_clocks(4);
 935                         set_jump_as_return();
 936                         writel(RW_MGR_MRS3, grpaddr);
 937                         delay_for_n_mem_clocks(4);
 938                         set_jump_as_return();
 939                         writel(RW_MGR_MRS1, grpaddr);
 940                         set_jump_as_return();
 941                         writel(fin2, grpaddr);
 942                 }
 943
 944                 if (precharge)
 945                         continue;
 946
 947                 set_jump_as_return();
 948                 writel(RW_MGR_ZQCL, grpaddr);
 949
 950                 /* tZQinit = tDLLK = 512 ck cycles */
 951                 delay_for_n_mem_clocks(512);
 952         }
 953 }
 954
 955 /**
 956  * rw_mgr_mem_initialize() - Initialize RW Manager
 957  *
 958  * Initialize RW Manager.
 959  */
 960 static void rw_mgr_mem_initialize(void)
 961 {
 962         debug("%s:%d\n", __func__, __LINE__);
 963
 964         /* The reset / cke part of initialization is broadcasted to all ranks */
 965         writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 966                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 967
 968         /*
 969          * Here's how you load register for a loop
 970          * Counters are located @ 0x800
 971          * Jump address are located @ 0xC00
 972          * For both, registers 0 to 3 are selected using bits 3 and 2, like
 973          * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
 974          * I know this ain't pretty, but Avalon bus throws away the 2 least
 975          * significant bits
 976          */
 977
 978         /* Start with memory RESET activated */
 979
 980         /* tINIT = 200us */
 981
 982         /*
 983          * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
 984          * If a and b are the number of iteration in 2 nested loops
 985          * it takes the following number of cycles to complete the operation:
 986          * number_of_cycles = ((2 + n) * a + 2) * b
 987          * where n is the number of instruction in the inner loop
 988          * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
 989          * b = 6A
 990          */
 991         rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
 992                                   SEQ_TINIT_CNTR2_VAL,
 993                                   RW_MGR_INIT_RESET_0_CKE_0);
 994
 995         /* Indicate that memory is stable. */
 996         writel(1, &phy_mgr_cfg->reset_mem_stbl);
 997
 998         /*
 999          * transition the RESET to high
1000          * Wait for 500us
1001          */
1002
1003         /*
1004          * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005          * If a and b are the number of iteration in 2 nested loops
1006          * it takes the following number of cycles to complete the operation
1007          * number_of_cycles = ((2 + n) * a + 2) * b
1008          * where n is the number of instruction in the inner loop
1009          * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1010          * b = FF
1011          */
1012         rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013                                   SEQ_TRESET_CNTR2_VAL,
1014                                   RW_MGR_INIT_RESET_1_CKE_0);
1015
1016         /* Bring up clock enable. */
1017
1018         /* tXRP < 250 ck cycles */
1019         delay_for_n_mem_clocks(250);
1020
1021         rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1022                              0);
1023 }
1024
1025 /*
1026  * At the end of calibration we have to program the user settings in, and
1027  * USER  hand off the memory to the user.
1028  */
1029 static void rw_mgr_mem_handoff(void)
1030 {
1031         rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1032         /*
1033          * USER  need to wait tMOD (12CK or 15ns) time before issuing
1034          * other commands, but we will have plenty of NIOS cycles before
1035          * actual handoff so its okay.
1036          */
1037 }
1038
1039 /*
1040  * performs a guaranteed read on the patterns we are going to use during a
1041  * read test to ensure memory works
1042  */
1043 static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
1044         uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
1045         uint32_t all_ranks)
1046 {
1047         uint32_t r, vg;
1048         uint32_t correct_mask_vg;
1049         uint32_t tmp_bit_chk;
1050         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1051                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1052         uint32_t addr;
1053         uint32_t base_rw_mgr;
1054
1055         *bit_chk = param->read_correct_mask;
1056         correct_mask_vg = param->read_correct_mask_vg;
1057
1058         for (r = rank_bgn; r < rank_end; r++) {
1059                 if (param->skip_ranks[r])
1060                         /* request to skip the rank */
1061                         continue;
1062
1063                 /* set rank */
1064                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1065
1066                 /* Load up a constant bursts of read commands */
1067                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1068                 writel(RW_MGR_GUARANTEED_READ,
1069                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1070
1071                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1072                 writel(RW_MGR_GUARANTEED_READ_CONT,
1073                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1074
1075                 tmp_bit_chk = 0;
1076                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1077                         /* reset the fifos to get pointers to known state */
1078
1079                         writel(0, &phy_mgr_cmd->fifo_reset);
1080                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1081                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1082
1083                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1084                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1085
1086                         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1087                         writel(RW_MGR_GUARANTEED_READ, addr +
1088                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1089                                 vg) << 2));
1090
1091                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1092                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
1093
1094                         if (vg == 0)
1095                                 break;
1096                 }
1097                 *bit_chk &= tmp_bit_chk;
1098         }
1099
1100         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1101         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1102
1103         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1104         debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
1105                    %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
1106                    (long unsigned int)(*bit_chk == param->read_correct_mask));
1107         return *bit_chk == param->read_correct_mask;
1108 }
1109
1110 static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
1111         (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
1112 {
1113         return rw_mgr_mem_calibrate_read_test_patterns(0, group,
1114                 num_tries, bit_chk, 1);
1115 }
1116
1117 /* load up the patterns we are going to use during a read test */
1118 static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
1119         uint32_t all_ranks)
1120 {
1121         uint32_t r;
1122         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1123                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1124
1125         debug("%s:%d\n", __func__, __LINE__);
1126         for (r = rank_bgn; r < rank_end; r++) {
1127                 if (param->skip_ranks[r])
1128                         /* request to skip the rank */
1129                         continue;
1130
1131                 /* set rank */
1132                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1133
1134                 /* Load up a constant bursts */
1135                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1136
1137                 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1138                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1139
1140                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1141
1142                 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1143                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1144
1145                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1146
1147                 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1148                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1149
1150                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1151
1152                 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1153                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1154
1155                 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1156                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1157         }
1158
1159         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1160 }
1161
1162 /*
1163  * try a read and see if it returns correct data back. has dummy reads
1164  * inserted into the mix used to align dqs enable. has more thorough checks
1165  * than the regular read test.
1166  */
1167 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1168         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1169         uint32_t all_groups, uint32_t all_ranks)
1170 {
1171         uint32_t r, vg;
1172         uint32_t correct_mask_vg;
1173         uint32_t tmp_bit_chk;
1174         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1175                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1176         uint32_t addr;
1177         uint32_t base_rw_mgr;
1178
1179         *bit_chk = param->read_correct_mask;
1180         correct_mask_vg = param->read_correct_mask_vg;
1181
1182         uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1183                 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1184
1185         for (r = rank_bgn; r < rank_end; r++) {
1186                 if (param->skip_ranks[r])
1187                         /* request to skip the rank */
1188                         continue;
1189
1190                 /* set rank */
1191                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1192
1193                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1194
1195                 writel(RW_MGR_READ_B2B_WAIT1,
1196                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1197
1198                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1199                 writel(RW_MGR_READ_B2B_WAIT2,
1200                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1201
1202                 if (quick_read_mode)
1203                         writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1204                         /* need at least two (1+1) reads to capture failures */
1205                 else if (all_groups)
1206                         writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1207                 else
1208                         writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1209
1210                 writel(RW_MGR_READ_B2B,
1211                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1212                 if (all_groups)
1213                         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1214                                RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1215                                &sdr_rw_load_mgr_regs->load_cntr3);
1216                 else
1217                         writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1218
1219                 writel(RW_MGR_READ_B2B,
1220                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1221
1222                 tmp_bit_chk = 0;
1223                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1224                         /* reset the fifos to get pointers to known state */
1225                         writel(0, &phy_mgr_cmd->fifo_reset);
1226                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1227                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1228
1229                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1230                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1231
1232                         if (all_groups)
1233                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1234                         else
1235                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1236
1237                         writel(RW_MGR_READ_B2B, addr +
1238                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1239                                vg) << 2));
1240
1241                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1242                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1243
1244                         if (vg == 0)
1245                                 break;
1246                 }
1247                 *bit_chk &= tmp_bit_chk;
1248         }
1249
1250         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1251         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1252
1253         if (all_correct) {
1254                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1255                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1256                            (%u == %u) => %lu", __func__, __LINE__, group,
1257                            all_groups, *bit_chk, param->read_correct_mask,
1258                            (long unsigned int)(*bit_chk ==
1259                            param->read_correct_mask));
1260                 return *bit_chk == param->read_correct_mask;
1261         } else  {
1262                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1263                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1264                            (%u != %lu) => %lu\n", __func__, __LINE__,
1265                            group, all_groups, *bit_chk, (long unsigned int)0,
1266                            (long unsigned int)(*bit_chk != 0x00));
1267                 return *bit_chk != 0x00;
1268         }
1269 }
1270
1271 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1272         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1273         uint32_t all_groups)
1274 {
1275         return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1276                                               bit_chk, all_groups, 1);
1277 }
1278
1279 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1280 {
1281         writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1282         (*v)++;
1283 }
1284
1285 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1286 {
1287         uint32_t i;
1288
1289         for (i = 0; i < VFIFO_SIZE-1; i++)
1290                 rw_mgr_incr_vfifo(grp, v);
1291 }
1292
1293 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1294 {
1295         uint32_t  v;
1296         uint32_t fail_cnt = 0;
1297         uint32_t test_status;
1298
1299         for (v = 0; v < VFIFO_SIZE; ) {
1300                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1301                            __func__, __LINE__, v);
1302                 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1303                         (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1304                 if (!test_status) {
1305                         fail_cnt++;
1306
1307                         if (fail_cnt == 2)
1308                                 break;
1309                 }
1310
1311                 /* fiddle with FIFO */
1312                 rw_mgr_incr_vfifo(grp, &v);
1313         }
1314
1315         if (v >= VFIFO_SIZE) {
1316                 /* no failing read found!! Something must have gone wrong */
1317                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1318                            __func__, __LINE__);
1319                 return 0;
1320         } else {
1321                 return v;
1322         }
1323 }
1324
1325 static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1326                               uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1327                               uint32_t *v, uint32_t *d, uint32_t *p,
1328                               uint32_t *i, uint32_t *max_working_cnt)
1329 {
1330         uint32_t found_begin = 0;
1331         uint32_t tmp_delay = 0;
1332         uint32_t test_status;
1333
1334         for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1335                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1336                 *work_bgn = tmp_delay;
1337                 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1338
1339                 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1340                         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1341                                 IO_DELAY_PER_OPA_TAP) {
1342                                 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1343
1344                                 test_status =
1345                                 rw_mgr_mem_calibrate_read_test_all_ranks
1346                                 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1347
1348                                 if (test_status) {
1349                                         *max_working_cnt = 1;
1350                                         found_begin = 1;
1351                                         break;
1352                                 }
1353                         }
1354
1355                         if (found_begin)
1356                                 break;
1357
1358                         if (*p > IO_DQS_EN_PHASE_MAX)
1359                                 /* fiddle with FIFO */
1360                                 rw_mgr_incr_vfifo(*grp, v);
1361                 }
1362
1363                 if (found_begin)
1364                         break;
1365         }
1366
1367         if (*i >= VFIFO_SIZE) {
1368                 /* cannot find working solution */
1369                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1370                            ptap/dtap\n", __func__, __LINE__);
1371                 return 0;
1372         } else {
1373                 return 1;
1374         }
1375 }
1376
1377 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1378                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1379                              uint32_t *p, uint32_t *max_working_cnt)
1380 {
1381         uint32_t found_begin = 0;
1382         uint32_t tmp_delay;
1383
1384         /* Special case code for backing up a phase */
1385         if (*p == 0) {
1386                 *p = IO_DQS_EN_PHASE_MAX;
1387                 rw_mgr_decr_vfifo(*grp, v);
1388         } else {
1389                 (*p)--;
1390         }
1391         tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1392         scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1393
1394         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1395                 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1396                 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1397
1398                 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1399                                                              PASS_ONE_BIT,
1400                                                              bit_chk, 0)) {
1401                         found_begin = 1;
1402                         *work_bgn = tmp_delay;
1403                         break;
1404                 }
1405         }
1406
1407         /* We have found a working dtap before the ptap found above */
1408         if (found_begin == 1)
1409                 (*max_working_cnt)++;
1410
1411         /*
1412          * Restore VFIFO to old state before we decremented it
1413          * (if needed).
1414          */
1415         (*p)++;
1416         if (*p > IO_DQS_EN_PHASE_MAX) {
1417                 *p = 0;
1418                 rw_mgr_incr_vfifo(*grp, v);
1419         }
1420
1421         scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1422 }
1423
1424 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1425                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1426                              uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1427                              uint32_t *work_end)
1428 {
1429         uint32_t found_end = 0;
1430
1431         (*p)++;
1432         *work_end += IO_DELAY_PER_OPA_TAP;
1433         if (*p > IO_DQS_EN_PHASE_MAX) {
1434                 /* fiddle with FIFO */
1435                 *p = 0;
1436                 rw_mgr_incr_vfifo(*grp, v);
1437         }
1438
1439         for (; *i < VFIFO_SIZE + 1; (*i)++) {
1440                 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1441                         += IO_DELAY_PER_OPA_TAP) {
1442                         scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1443
1444                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1445                                 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1446                                 found_end = 1;
1447                                 break;
1448                         } else {
1449                                 (*max_working_cnt)++;
1450                         }
1451                 }
1452
1453                 if (found_end)
1454                         break;
1455
1456                 if (*p > IO_DQS_EN_PHASE_MAX) {
1457                         /* fiddle with FIFO */
1458                         rw_mgr_incr_vfifo(*grp, v);
1459                         *p = 0;
1460                 }
1461         }
1462
1463         if (*i >= VFIFO_SIZE + 1) {
1464                 /* cannot see edge of failing read */
1465                 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1466                            failed\n", __func__, __LINE__);
1467                 return 0;
1468         } else {
1469                 return 1;
1470         }
1471 }
1472
1473 static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1474                                   uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1475                                   uint32_t *p, uint32_t *work_mid,
1476                                   uint32_t *work_end)
1477 {
1478         int i;
1479         int tmp_delay = 0;
1480
1481         *work_mid = (*work_bgn + *work_end) / 2;
1482
1483         debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1484                    *work_bgn, *work_end, *work_mid);
1485         /* Get the middle delay to be less than a VFIFO delay */
1486         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1487                 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1488                 ;
1489         debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1490         while (*work_mid > tmp_delay)
1491                 *work_mid -= tmp_delay;
1492         debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1493
1494         tmp_delay = 0;
1495         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1496                 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1497                 ;
1498         tmp_delay -= IO_DELAY_PER_OPA_TAP;
1499         debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1500         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1501                 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1502                 ;
1503         debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1504
1505         scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1506         scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1507
1508         /*
1509          * push vfifo until we can successfully calibrate. We can do this
1510          * because the largest possible margin in 1 VFIFO cycle.
1511          */
1512         for (i = 0; i < VFIFO_SIZE; i++) {
1513                 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1514                            *v);
1515                 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1516                                                              PASS_ONE_BIT,
1517                                                              bit_chk, 0)) {
1518                         break;
1519                 }
1520
1521                 /* fiddle with FIFO */
1522                 rw_mgr_incr_vfifo(*grp, v);
1523         }
1524
1525         if (i >= VFIFO_SIZE) {
1526                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1527                            failed\n", __func__, __LINE__);
1528                 return 0;
1529         } else {
1530                 return 1;
1531         }
1532 }
1533
1534 /* find a good dqs enable to use */
1535 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1536 {
1537         uint32_t v, d, p, i;
1538         uint32_t max_working_cnt;
1539         uint32_t bit_chk;
1540         uint32_t dtaps_per_ptap;
1541         uint32_t work_bgn, work_mid, work_end;
1542         uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1543
1544         debug("%s:%d %u\n", __func__, __LINE__, grp);
1545
1546         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1547
1548         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1549         scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1550
1551         /* ************************************************************** */
1552         /* * Step 0 : Determine number of delay taps for each phase tap * */
1553         dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1554
1555         /* ********************************************************* */
1556         /* * Step 1 : First push vfifo until we get a failing read * */
1557         v = find_vfifo_read(grp, &bit_chk);
1558
1559         max_working_cnt = 0;
1560
1561         /* ******************************************************** */
1562         /* * step 2: find first working phase, increment in ptaps * */
1563         work_bgn = 0;
1564         if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1565                                 &p, &i, &max_working_cnt) == 0)
1566                 return 0;
1567
1568         work_end = work_bgn;
1569
1570         /*
1571          * If d is 0 then the working window covers a phase tap and
1572          * we can follow the old procedure otherwise, we've found the beginning,
1573          * and we need to increment the dtaps until we find the end.
1574          */
1575         if (d == 0) {
1576                 /* ********************************************************* */
1577                 /* * step 3a: if we have room, back off by one and
1578                 increment in dtaps * */
1579
1580                 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1581                                  &max_working_cnt);
1582
1583                 /* ********************************************************* */
1584                 /* * step 4a: go forward from working phase to non working
1585                 phase, increment in ptaps * */
1586                 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1587                                          &i, &max_working_cnt, &work_end) == 0)
1588                         return 0;
1589
1590                 /* ********************************************************* */
1591                 /* * step 5a:  back off one from last, increment in dtaps  * */
1592
1593                 /* Special case code for backing up a phase */
1594                 if (p == 0) {
1595                         p = IO_DQS_EN_PHASE_MAX;
1596                         rw_mgr_decr_vfifo(grp, &v);
1597                 } else {
1598                         p = p - 1;
1599                 }
1600
1601                 work_end -= IO_DELAY_PER_OPA_TAP;
1602                 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1603
1604                 /* * The actual increment of dtaps is done outside of
1605                 the if/else loop to share code */
1606                 d = 0;
1607
1608                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1609                            vfifo=%u ptap=%u\n", __func__, __LINE__,
1610                            v, p);
1611         } else {
1612                 /* ******************************************************* */
1613                 /* * step 3-5b:  Find the right edge of the window using
1614                 delay taps   * */
1615                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1616                            ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1617                            v, p, d, work_bgn);
1618
1619                 work_end = work_bgn;
1620
1621                 /* * The actual increment of dtaps is done outside of the
1622                 if/else loop to share code */
1623
1624                 /* Only here to counterbalance a subtract later on which is
1625                 not needed if this branch of the algorithm is taken */
1626                 max_working_cnt++;
1627         }
1628
1629         /* The dtap increment to find the failing edge is done here */
1630         for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1631                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1632                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1633                                    end-2: dtap=%u\n", __func__, __LINE__, d);
1634                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1635
1636                         if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1637                                                                       PASS_ONE_BIT,
1638                                                                       &bit_chk, 0)) {
1639                                 break;
1640                         }
1641         }
1642
1643         /* Go back to working dtap */
1644         if (d != 0)
1645                 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1646
1647         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1648                    ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1649                    v, p, d-1, work_end);
1650
1651         if (work_end < work_bgn) {
1652                 /* nil range */
1653                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1654                            failed\n", __func__, __LINE__);
1655                 return 0;
1656         }
1657
1658         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1659                    __func__, __LINE__, work_bgn, work_end);
1660
1661         /* *************************************************************** */
1662         /*
1663          * * We need to calculate the number of dtaps that equal a ptap
1664          * * To do that we'll back up a ptap and re-find the edge of the
1665          * * window using dtaps
1666          */
1667
1668         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1669                    for tracking\n", __func__, __LINE__);
1670
1671         /* Special case code for backing up a phase */
1672         if (p == 0) {
1673                 p = IO_DQS_EN_PHASE_MAX;
1674                 rw_mgr_decr_vfifo(grp, &v);
1675                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1676                            cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1677                            v, p);
1678         } else {
1679                 p = p - 1;
1680                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1681                            phase only: v=%u p=%u", __func__, __LINE__,
1682                            v, p);
1683         }
1684
1685         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1686
1687         /*
1688          * Increase dtap until we first see a passing read (in case the
1689          * window is smaller than a ptap),
1690          * and then a failing read to mark the edge of the window again
1691          */
1692
1693         /* Find a passing read */
1694         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1695                    __func__, __LINE__);
1696         found_passing_read = 0;
1697         found_failing_read = 0;
1698         initial_failing_dtap = d;
1699         for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1700                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1701                            read d=%u\n", __func__, __LINE__, d);
1702                 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1703
1704                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1705                                                              PASS_ONE_BIT,
1706                                                              &bit_chk, 0)) {
1707                         found_passing_read = 1;
1708                         break;
1709                 }
1710         }
1711
1712         if (found_passing_read) {
1713                 /* Find a failing read */
1714                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1715                            read\n", __func__, __LINE__);
1716                 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1717                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1718                                    testing read d=%u\n", __func__, __LINE__, d);
1719                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1720
1721                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1722                                 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1723                                 found_failing_read = 1;
1724                                 break;
1725                         }
1726                 }
1727         } else {
1728                 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1729                            calculate dtaps", __func__, __LINE__);
1730                 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1731         }
1732
1733         /*
1734          * The dynamically calculated dtaps_per_ptap is only valid if we
1735          * found a passing/failing read. If we didn't, it means d hit the max
1736          * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1737          * statically calculated value.
1738          */
1739         if (found_passing_read && found_failing_read)
1740                 dtaps_per_ptap = d - initial_failing_dtap;
1741
1742         writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1743         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1744                    - %u = %u",  __func__, __LINE__, d,
1745                    initial_failing_dtap, dtaps_per_ptap);
1746
1747         /* ******************************************** */
1748         /* * step 6:  Find the centre of the window   * */
1749         if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1750                                    &work_mid, &work_end) == 0)
1751                 return 0;
1752
1753         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1754                    vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1755                    v, p-1, d);
1756         return 1;
1757 }
1758
1759 /*
1760  * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1761  * dq_in_delay values
1762  */
1763 static uint32_t
1764 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1765 (uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
1766 {
1767         uint32_t found;
1768         uint32_t i;
1769         uint32_t p;
1770         uint32_t d;
1771         uint32_t r;
1772
1773         const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
1774                 (RW_MGR_MEM_DQ_PER_READ_DQS-1);
1775                 /* we start at zero, so have one less dq to devide among */
1776
1777         debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
1778               test_bgn);
1779
1780         /* try different dq_in_delays since the dq path is shorter than dqs */
1781
1782         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1783              r += NUM_RANKS_PER_SHADOW_REG) {
1784                 for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) {
1785                         debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
1786                                    vfifo_find_dqs_", __func__, __LINE__);
1787                         debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
1788                                write_group, read_group);
1789                         debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
1790                         scc_mgr_set_dq_in_delay(p, d);
1791                         scc_mgr_load_dq(p);
1792                 }
1793                 writel(0, &sdr_scc_mgr->update);
1794         }
1795
1796         found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
1797
1798         debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
1799                    en_phase_sweep_dq", __func__, __LINE__);
1800         debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
1801                    chain to zero\n", write_group, read_group, found);
1802
1803         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1804              r += NUM_RANKS_PER_SHADOW_REG) {
1805                 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1806                         i++, p++) {
1807                         scc_mgr_set_dq_in_delay(p, 0);
1808                         scc_mgr_load_dq(p);
1809                 }
1810                 writel(0, &sdr_scc_mgr->update);
1811         }
1812
1813         return found;
1814 }
1815
1816 /* per-bit deskew DQ and center */
1817 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1818         uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1819         uint32_t use_read_test, uint32_t update_fom)
1820 {
1821         uint32_t i, p, d, min_index;
1822         /*
1823          * Store these as signed since there are comparisons with
1824          * signed numbers.
1825          */
1826         uint32_t bit_chk;
1827         uint32_t sticky_bit_chk;
1828         int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1829         int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1830         int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1831         int32_t mid;
1832         int32_t orig_mid_min, mid_min;
1833         int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1834                 final_dqs_en;
1835         int32_t dq_margin, dqs_margin;
1836         uint32_t stop;
1837         uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1838         uint32_t addr;
1839
1840         debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1841
1842         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1843         start_dqs = readl(addr + (read_group << 2));
1844         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1845                 start_dqs_en = readl(addr + ((read_group << 2)
1846                                      - IO_DQS_EN_DELAY_OFFSET));
1847
1848         /* set the left and right edge of each bit to an illegal value */
1849         /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1850         sticky_bit_chk = 0;
1851         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1852                 left_edge[i]  = IO_IO_IN_DELAY_MAX + 1;
1853                 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1854         }
1855
1856         /* Search for the left edge of the window for each bit */
1857         for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1858                 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1859
1860                 writel(0, &sdr_scc_mgr->update);
1861
1862                 /*
1863                  * Stop searching when the read test doesn't pass AND when
1864                  * we've seen a passing read on every bit.
1865                  */
1866                 if (use_read_test) {
1867                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1868                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1869                                 &bit_chk, 0, 0);
1870                 } else {
1871                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1872                                                         0, PASS_ONE_BIT,
1873                                                         &bit_chk, 0);
1874                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1875                                 (read_group - (write_group *
1876                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1877                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1878                         stop = (bit_chk == 0);
1879                 }
1880                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1881                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1882                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1883                            && %u", __func__, __LINE__, d,
1884                            sticky_bit_chk,
1885                         param->read_correct_mask, stop);
1886
1887                 if (stop == 1) {
1888                         break;
1889                 } else {
1890                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1891                                 if (bit_chk & 1) {
1892                                         /* Remember a passing test as the
1893                                         left_edge */
1894                                         left_edge[i] = d;
1895                                 } else {
1896                                         /* If a left edge has not been seen yet,
1897                                         then a future passing test will mark
1898                                         this edge as the right edge */
1899                                         if (left_edge[i] ==
1900                                                 IO_IO_IN_DELAY_MAX + 1) {
1901                                                 right_edge[i] = -(d + 1);
1902                                         }
1903                                 }
1904                                 bit_chk = bit_chk >> 1;
1905                         }
1906                 }
1907         }
1908
1909         /* Reset DQ delay chains to 0 */
1910         scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1911         sticky_bit_chk = 0;
1912         for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1913                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1914                            %d right_edge[%u]: %d\n", __func__, __LINE__,
1915                            i, left_edge[i], i, right_edge[i]);
1916
1917                 /*
1918                  * Check for cases where we haven't found the left edge,
1919                  * which makes our assignment of the the right edge invalid.
1920                  * Reset it to the illegal value.
1921                  */
1922                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1923                         right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1924                         right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1925                         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1926                                    right_edge[%u]: %d\n", __func__, __LINE__,
1927                                    i, right_edge[i]);
1928                 }
1929
1930                 /*
1931                  * Reset sticky bit (except for bits where we have seen
1932                  * both the left and right edge).
1933                  */
1934                 sticky_bit_chk = sticky_bit_chk << 1;
1935                 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1936                     (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1937                         sticky_bit_chk = sticky_bit_chk | 1;
1938                 }
1939
1940                 if (i == 0)
1941                         break;
1942         }
1943
1944         /* Search for the right edge of the window for each bit */
1945         for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1946                 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1947                 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1948                         uint32_t delay = d + start_dqs_en;
1949                         if (delay > IO_DQS_EN_DELAY_MAX)
1950                                 delay = IO_DQS_EN_DELAY_MAX;
1951                         scc_mgr_set_dqs_en_delay(read_group, delay);
1952                 }
1953                 scc_mgr_load_dqs(read_group);
1954
1955                 writel(0, &sdr_scc_mgr->update);
1956
1957                 /*
1958                  * Stop searching when the read test doesn't pass AND when
1959                  * we've seen a passing read on every bit.
1960                  */
1961                 if (use_read_test) {
1962                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1963                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1964                                 &bit_chk, 0, 0);
1965                 } else {
1966                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1967                                                         0, PASS_ONE_BIT,
1968                                                         &bit_chk, 0);
1969                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1970                                 (read_group - (write_group *
1971                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1972                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1973                         stop = (bit_chk == 0);
1974                 }
1975                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1976                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1977
1978                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1979                            %u && %u", __func__, __LINE__, d,
1980                            sticky_bit_chk, param->read_correct_mask, stop);
1981
1982                 if (stop == 1) {
1983                         break;
1984                 } else {
1985                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1986                                 if (bit_chk & 1) {
1987                                         /* Remember a passing test as
1988                                         the right_edge */
1989                                         right_edge[i] = d;
1990                                 } else {
1991                                         if (d != 0) {
1992                                                 /* If a right edge has not been
1993                                                 seen yet, then a future passing
1994                                                 test will mark this edge as the
1995                                                 left edge */
1996                                                 if (right_edge[i] ==
1997                                                 IO_IO_IN_DELAY_MAX + 1) {
1998                                                         left_edge[i] = -(d + 1);
1999                                                 }
2000                                         } else {
2001                                                 /* d = 0 failed, but it passed
2002                                                 when testing the left edge,
2003                                                 so it must be marginal,
2004                                                 set it to -1 */
2005                                                 if (right_edge[i] ==
2006                                                         IO_IO_IN_DELAY_MAX + 1 &&
2007                                                         left_edge[i] !=
2008                                                         IO_IO_IN_DELAY_MAX
2009                                                         + 1) {
2010                                                         right_edge[i] = -1;
2011                                                 }
2012                                                 /* If a right edge has not been
2013                                                 seen yet, then a future passing
2014                                                 test will mark this edge as the
2015                                                 left edge */
2016                                                 else if (right_edge[i] ==
2017                                                         IO_IO_IN_DELAY_MAX +
2018                                                         1) {
2019                                                         left_edge[i] = -(d + 1);
2020                                                 }
2021                                         }
2022                                 }
2023
2024                                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2025                                            d=%u]: ", __func__, __LINE__, d);
2026                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2027                                            (int)(bit_chk & 1), i, left_edge[i]);
2028                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2029                                            right_edge[i]);
2030                                 bit_chk = bit_chk >> 1;
2031                         }
2032                 }
2033         }
2034
2035         /* Check that all bits have a window */
2036         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2037                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2038                            %d right_edge[%u]: %d", __func__, __LINE__,
2039                            i, left_edge[i], i, right_edge[i]);
2040                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2041                         == IO_IO_IN_DELAY_MAX + 1)) {
2042                         /*
2043                          * Restore delay chain settings before letting the loop
2044                          * in rw_mgr_mem_calibrate_vfifo to retry different
2045                          * dqs/ck relationships.
2046                          */
2047                         scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2048                         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2049                                 scc_mgr_set_dqs_en_delay(read_group,
2050                                                          start_dqs_en);
2051                         }
2052                         scc_mgr_load_dqs(read_group);
2053                         writel(0, &sdr_scc_mgr->update);
2054
2055                         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2056                                    find edge [%u]: %d %d", __func__, __LINE__,
2057                                    i, left_edge[i], right_edge[i]);
2058                         if (use_read_test) {
2059                                 set_failing_group_stage(read_group *
2060                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2061                                         CAL_STAGE_VFIFO,
2062                                         CAL_SUBSTAGE_VFIFO_CENTER);
2063                         } else {
2064                                 set_failing_group_stage(read_group *
2065                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2066                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2067                                         CAL_SUBSTAGE_VFIFO_CENTER);
2068                         }
2069                         return 0;
2070                 }
2071         }
2072
2073         /* Find middle of window for each DQ bit */
2074         mid_min = left_edge[0] - right_edge[0];
2075         min_index = 0;
2076         for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2077                 mid = left_edge[i] - right_edge[i];
2078                 if (mid < mid_min) {
2079                         mid_min = mid;
2080                         min_index = i;
2081                 }
2082         }
2083
2084         /*
2085          * -mid_min/2 represents the amount that we need to move DQS.
2086          * If mid_min is odd and positive we'll need to add one to
2087          * make sure the rounding in further calculations is correct
2088          * (always bias to the right), so just add 1 for all positive values.
2089          */
2090         if (mid_min > 0)
2091                 mid_min++;
2092
2093         mid_min = mid_min / 2;
2094
2095         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2096                    __func__, __LINE__, mid_min, min_index);
2097
2098         /* Determine the amount we can change DQS (which is -mid_min) */
2099         orig_mid_min = mid_min;
2100         new_dqs = start_dqs - mid_min;
2101         if (new_dqs > IO_DQS_IN_DELAY_MAX)
2102                 new_dqs = IO_DQS_IN_DELAY_MAX;
2103         else if (new_dqs < 0)
2104                 new_dqs = 0;
2105
2106         mid_min = start_dqs - new_dqs;
2107         debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2108                    mid_min, new_dqs);
2109
2110         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2111                 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2112                         mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2113                 else if (start_dqs_en - mid_min < 0)
2114                         mid_min += start_dqs_en - mid_min;
2115         }
2116         new_dqs = start_dqs - mid_min;
2117
2118         debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2119                    new_dqs=%d mid_min=%d\n", start_dqs,
2120                    IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2121                    new_dqs, mid_min);
2122
2123         /* Initialize data for export structures */
2124         dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2125         dq_margin  = IO_IO_IN_DELAY_MAX + 1;
2126
2127         /* add delay to bring centre of all DQ windows to the same "level" */
2128         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2129                 /* Use values before divide by 2 to reduce round off error */
2130                 shift_dq = (left_edge[i] - right_edge[i] -
2131                         (left_edge[min_index] - right_edge[min_index]))/2  +
2132                         (orig_mid_min - mid_min);
2133
2134                 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2135                            shift_dq[%u]=%d\n", i, shift_dq);
2136
2137                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2138                 temp_dq_in_delay1 = readl(addr + (p << 2));
2139                 temp_dq_in_delay2 = readl(addr + (i << 2));
2140
2141                 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2142                         (int32_t)IO_IO_IN_DELAY_MAX) {
2143                         shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2144                 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2145                         shift_dq = -(int32_t)temp_dq_in_delay1;
2146                 }
2147                 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2148                            shift_dq[%u]=%d\n", i, shift_dq);
2149                 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2150                 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2151                 scc_mgr_load_dq(p);
2152
2153                 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2154                            left_edge[i] - shift_dq + (-mid_min),
2155                            right_edge[i] + shift_dq - (-mid_min));
2156                 /* To determine values for export structures */
2157                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2158                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2159
2160                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2161                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2162         }
2163
2164         final_dqs = new_dqs;
2165         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2166                 final_dqs_en = start_dqs_en - mid_min;
2167
2168         /* Move DQS-en */
2169         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2170                 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2171                 scc_mgr_load_dqs(read_group);
2172         }
2173
2174         /* Move DQS */
2175         scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2176         scc_mgr_load_dqs(read_group);
2177         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2178                    dqs_margin=%d", __func__, __LINE__,
2179                    dq_margin, dqs_margin);
2180
2181         /*
2182          * Do not remove this line as it makes sure all of our decisions
2183          * have been applied. Apply the update bit.
2184          */
2185         writel(0, &sdr_scc_mgr->update);
2186
2187         return (dq_margin >= 0) && (dqs_margin >= 0);
2188 }
2189
2190 /**
2191  * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2192  * @rw_group:   Read/Write Group
2193  * @phase:      DQ/DQS phase
2194  *
2195  * Because initially no communication ca be reliably performed with the memory
2196  * device, the sequencer uses a guaranteed write mechanism to write data into
2197  * the memory device.
2198  */
2199 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2200                                                  const u32 phase)
2201 {
2202         u32 bit_chk;
2203         int ret;
2204
2205         /* Set a particular DQ/DQS phase. */
2206         scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2207
2208         debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2209                    __func__, __LINE__, rw_group, phase);
2210
2211         /*
2212          * Altera EMI_RM 2015.05.04 :: Figure 1-25
2213          * Load up the patterns used by read calibration using the
2214          * current DQDQS phase.
2215          */
2216         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2217
2218         if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2219                 return 0;
2220
2221         /*
2222          * Altera EMI_RM 2015.05.04 :: Figure 1-26
2223          * Back-to-Back reads of the patterns used for calibration.
2224          */
2225         ret = rw_mgr_mem_calibrate_read_test_patterns_all_ranks(rw_group, 1,
2226                                                                 &bit_chk);
2227         if (!ret) {     /* FIXME: 0 means failure in this old code :-( */
2228                 debug_cond(DLEVEL == 1,
2229                            "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2230                            __func__, __LINE__, rw_group, phase);
2231                 return -EIO;
2232         }
2233
2234         return 0;
2235 }
2236
2237 /**
2238  * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2239  * @rw_group:   Read/Write Group
2240  * @test_bgn:   Rank at which the test begins
2241  *
2242  * DQS enable calibration ensures reliable capture of the DQ signal without
2243  * glitches on the DQS line.
2244  */
2245 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2246                                                        const u32 test_bgn)
2247 {
2248         int ret;
2249
2250         /*
2251          * Altera EMI_RM 2015.05.04 :: Figure 1-27
2252          * DQS and DQS Eanble Signal Relationships.
2253          */
2254         ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(
2255                                                 rw_group, rw_group, test_bgn);
2256         if (!ret)       /* FIXME: 0 means failure in this old code :-( */
2257                 return -EIO;
2258
2259         return 0;
2260 }
2261
2262 /**
2263  * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2264  * @rw_group:           Read/Write Group
2265  * @test_bgn:           Rank at which the test begins
2266  *
2267  * Stage 1: Calibrate the read valid prediction FIFO.
2268  *
2269  * This function implements UniPHY calibration Stage 1, as explained in
2270  * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2271  *
2272  * - read valid prediction will consist of finding:
2273  *   - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2274  *   - DQS input phase  and DQS input delay (DQ/DQS Centering)
2275  *  - we also do a per-bit deskew on the DQ lines.
2276  */
2277 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2278 {
2279         uint32_t p, d, rank_bgn, sr;
2280         uint32_t dtaps_per_ptap;
2281         uint32_t grp_calibrated;
2282         uint32_t failed_substage;
2283
2284         int ret;
2285
2286         debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2287
2288         /* Update info for sims */
2289         reg_file_set_group(rw_group);
2290         reg_file_set_stage(CAL_STAGE_VFIFO);
2291         reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2292
2293         failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2294
2295         /* USER Determine number of delay taps for each phase tap. */
2296         dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2297                                       IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2298
2299         for (d = 0; d <= dtaps_per_ptap; d += 2) {
2300                 /*
2301                  * In RLDRAMX we may be messing the delay of pins in
2302                  * the same write rw_group but outside of the current read
2303                  * the rw_group, but that's ok because we haven't calibrated
2304                  * output side yet.
2305                  */
2306                 if (d > 0) {
2307                         scc_mgr_apply_group_all_out_delay_add_all_ranks(
2308                                                                 rw_group, d);
2309                 }
2310
2311                 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2312                         /* 1) Guaranteed Write */
2313                         ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2314                         if (ret)
2315                                 break;
2316
2317                         /* 2) DQS Enable Calibration */
2318                         ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2319                                                                           test_bgn);
2320                         if (ret) {
2321                                 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2322                                 continue;
2323                         }
2324
2325                         /*
2326                          * USER Read per-bit deskew can be done on a
2327                          * per shadow register basis.
2328                          */
2329                         grp_calibrated = 1;
2330                         for (rank_bgn = 0, sr = 0;
2331                              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2332                              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2333                                 /*
2334                                  * Determine if this set of ranks
2335                                  * should be skipped entirely.
2336                                  */
2337                                 if (param->skip_shadow_regs[sr])
2338                                         continue;
2339                                 /*
2340                                  * If doing read after write
2341                                  * calibration, do not update
2342                                  * FOM, now - do it then.
2343                                  */
2344                                 if (rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2345                                                         rw_group, rw_group,
2346                                                         test_bgn, 1, 0))
2347                                         continue;
2348
2349                                 grp_calibrated = 0;
2350                                 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2351                         }
2352
2353                         if (grp_calibrated)
2354                                 goto cal_done_ok;
2355                 }
2356         }
2357
2358         /* Calibration Stage 1 failed. */
2359         set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2360         return 0;
2361
2362         /* Calibration Stage 1 completed OK. */
2363 cal_done_ok:
2364         /*
2365          * Reset the delay chains back to zero if they have moved > 1
2366          * (check for > 1 because loop will increase d even when pass in
2367          * first case).
2368          */
2369         if (d > 2)
2370                 scc_mgr_zero_group(rw_group, 1);
2371
2372         return 1;
2373 }
2374
2375 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2376 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2377                                                uint32_t test_bgn)
2378 {
2379         uint32_t rank_bgn, sr;
2380         uint32_t grp_calibrated;
2381         uint32_t write_group;
2382
2383         debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2384
2385         /* update info for sims */
2386
2387         reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2388         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2389
2390         write_group = read_group;
2391
2392         /* update info for sims */
2393         reg_file_set_group(read_group);
2394
2395         grp_calibrated = 1;
2396         /* Read per-bit deskew can be done on a per shadow register basis */
2397         for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2398                 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2399                 /* Determine if this set of ranks should be skipped entirely */
2400                 if (!param->skip_shadow_regs[sr]) {
2401                 /* This is the last calibration round, update FOM here */
2402                         if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2403                                                                 write_group,
2404                                                                 read_group,
2405                                                                 test_bgn, 0,
2406                                                                 1)) {
2407                                 grp_calibrated = 0;
2408                         }
2409                 }
2410         }
2411
2412
2413         if (grp_calibrated == 0) {
2414                 set_failing_group_stage(write_group,
2415                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2416                                         CAL_SUBSTAGE_VFIFO_CENTER);
2417                 return 0;
2418         }
2419
2420         return 1;
2421 }
2422
2423 /* Calibrate LFIFO to find smallest read latency */
2424 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2425 {
2426         uint32_t found_one;
2427         uint32_t bit_chk;
2428
2429         debug("%s:%d\n", __func__, __LINE__);
2430
2431         /* update info for sims */
2432         reg_file_set_stage(CAL_STAGE_LFIFO);
2433         reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2434
2435         /* Load up the patterns used by read calibration for all ranks */
2436         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2437         found_one = 0;
2438
2439         do {
2440                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2441                 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2442                            __func__, __LINE__, gbl->curr_read_lat);
2443
2444                 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2445                                                               NUM_READ_TESTS,
2446                                                               PASS_ALL_BITS,
2447                                                               &bit_chk, 1)) {
2448                         break;
2449                 }
2450
2451                 found_one = 1;
2452                 /* reduce read latency and see if things are working */
2453                 /* correctly */
2454                 gbl->curr_read_lat--;
2455         } while (gbl->curr_read_lat > 0);
2456
2457         /* reset the fifos to get pointers to known state */
2458
2459         writel(0, &phy_mgr_cmd->fifo_reset);
2460
2461         if (found_one) {
2462                 /* add a fudge factor to the read latency that was determined */
2463                 gbl->curr_read_lat += 2;
2464                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2465                 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2466                            read_lat=%u\n", __func__, __LINE__,
2467                            gbl->curr_read_lat);
2468                 return 1;
2469         } else {
2470                 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2471                                         CAL_SUBSTAGE_READ_LATENCY);
2472
2473                 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2474                            read_lat=%u\n", __func__, __LINE__,
2475                            gbl->curr_read_lat);
2476                 return 0;
2477         }
2478 }
2479
2480 /*
2481  * issue write test command.
2482  * two variants are provided. one that just tests a write pattern and
2483  * another that tests datamask functionality.
2484  */
2485 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2486                                                   uint32_t test_dm)
2487 {
2488         uint32_t mcc_instruction;
2489         uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2490                 ENABLE_SUPER_QUICK_CALIBRATION);
2491         uint32_t rw_wl_nop_cycles;
2492         uint32_t addr;
2493
2494         /*
2495          * Set counter and jump addresses for the right
2496          * number of NOP cycles.
2497          * The number of supported NOP cycles can range from -1 to infinity
2498          * Three different cases are handled:
2499          *
2500          * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2501          *    mechanism will be used to insert the right number of NOPs
2502          *
2503          * 2. For a number of NOP cycles equals to 0, the micro-instruction
2504          *    issuing the write command will jump straight to the
2505          *    micro-instruction that turns on DQS (for DDRx), or outputs write
2506          *    data (for RLD), skipping
2507          *    the NOP micro-instruction all together
2508          *
2509          * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2510          *    turned on in the same micro-instruction that issues the write
2511          *    command. Then we need
2512          *    to directly jump to the micro-instruction that sends out the data
2513          *
2514          * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2515          *       (2 and 3). One jump-counter (0) is used to perform multiple
2516          *       write-read operations.
2517          *       one counter left to issue this command in "multiple-group" mode
2518          */
2519
2520         rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2521
2522         if (rw_wl_nop_cycles == -1) {
2523                 /*
2524                  * CNTR 2 - We want to execute the special write operation that
2525                  * turns on DQS right away and then skip directly to the
2526                  * instruction that sends out the data. We set the counter to a
2527                  * large number so that the jump is always taken.
2528                  */
2529                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2530
2531                 /* CNTR 3 - Not used */
2532                 if (test_dm) {
2533                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2534                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2535                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2536                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2537                                &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2538                 } else {
2539                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2540                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2541                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2542                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2543                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2544                 }
2545         } else if (rw_wl_nop_cycles == 0) {
2546                 /*
2547                  * CNTR 2 - We want to skip the NOP operation and go straight
2548                  * to the DQS enable instruction. We set the counter to a large
2549                  * number so that the jump is always taken.
2550                  */
2551                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2552
2553                 /* CNTR 3 - Not used */
2554                 if (test_dm) {
2555                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2556                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2557                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2558                 } else {
2559                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2560                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2561                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2562                 }
2563         } else {
2564                 /*
2565                  * CNTR 2 - In this case we want to execute the next instruction
2566                  * and NOT take the jump. So we set the counter to 0. The jump
2567                  * address doesn't count.
2568                  */
2569                 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2570                 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2571
2572                 /*
2573                  * CNTR 3 - Set the nop counter to the number of cycles we
2574                  * need to loop for, minus 1.
2575                  */
2576                 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2577                 if (test_dm) {
2578                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2579                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2580                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2581                 } else {
2582                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2583                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2584                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2585                 }
2586         }
2587
2588         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2589                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
2590
2591         if (quick_write_mode)
2592                 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2593         else
2594                 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2595
2596         writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2597
2598         /*
2599          * CNTR 1 - This is used to ensure enough time elapses
2600          * for read data to come back.
2601          */
2602         writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2603
2604         if (test_dm) {
2605                 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2606                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2607         } else {
2608                 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2609                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2610         }
2611
2612         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2613         writel(mcc_instruction, addr + (group << 2));
2614 }
2615
2616 /* Test writes, can check for a single bit pass or multiple bit pass */
2617 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2618         uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2619         uint32_t *bit_chk, uint32_t all_ranks)
2620 {
2621         uint32_t r;
2622         uint32_t correct_mask_vg;
2623         uint32_t tmp_bit_chk;
2624         uint32_t vg;
2625         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2626                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2627         uint32_t addr_rw_mgr;
2628         uint32_t base_rw_mgr;
2629
2630         *bit_chk = param->write_correct_mask;
2631         correct_mask_vg = param->write_correct_mask_vg;
2632
2633         for (r = rank_bgn; r < rank_end; r++) {
2634                 if (param->skip_ranks[r]) {
2635                         /* request to skip the rank */
2636                         continue;
2637                 }
2638
2639                 /* set rank */
2640                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2641
2642                 tmp_bit_chk = 0;
2643                 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2644                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2645                         /* reset the fifos to get pointers to known state */
2646                         writel(0, &phy_mgr_cmd->fifo_reset);
2647
2648                         tmp_bit_chk = tmp_bit_chk <<
2649                                 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2650                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2651                         rw_mgr_mem_calibrate_write_test_issue(write_group *
2652                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2653                                 use_dm);
2654
2655                         base_rw_mgr = readl(addr_rw_mgr);
2656                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2657                         if (vg == 0)
2658                                 break;
2659                 }
2660                 *bit_chk &= tmp_bit_chk;
2661         }
2662
2663         if (all_correct) {
2664                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2665                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2666                            %u => %lu", write_group, use_dm,
2667                            *bit_chk, param->write_correct_mask,
2668                            (long unsigned int)(*bit_chk ==
2669                            param->write_correct_mask));
2670                 return *bit_chk == param->write_correct_mask;
2671         } else {
2672                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2673                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2674                        write_group, use_dm, *bit_chk);
2675                 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2676                         (long unsigned int)(*bit_chk != 0));
2677                 return *bit_chk != 0x00;
2678         }
2679 }
2680
2681 /*
2682  * center all windows. do per-bit-deskew to possibly increase size of
2683  * certain windows.
2684  */
2685 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2686         uint32_t write_group, uint32_t test_bgn)
2687 {
2688         uint32_t i, p, min_index;
2689         int32_t d;
2690         /*
2691          * Store these as signed since there are comparisons with
2692          * signed numbers.
2693          */
2694         uint32_t bit_chk;
2695         uint32_t sticky_bit_chk;
2696         int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2697         int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2698         int32_t mid;
2699         int32_t mid_min, orig_mid_min;
2700         int32_t new_dqs, start_dqs, shift_dq;
2701         int32_t dq_margin, dqs_margin, dm_margin;
2702         uint32_t stop;
2703         uint32_t temp_dq_out1_delay;
2704         uint32_t addr;
2705
2706         debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2707
2708         dm_margin = 0;
2709
2710         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2711         start_dqs = readl(addr +
2712                           (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2713
2714         /* per-bit deskew */
2715
2716         /*
2717          * set the left and right edge of each bit to an illegal value
2718          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2719          */
2720         sticky_bit_chk = 0;
2721         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2722                 left_edge[i]  = IO_IO_OUT1_DELAY_MAX + 1;
2723                 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2724         }
2725
2726         /* Search for the left edge of the window for each bit */
2727         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2728                 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2729
2730                 writel(0, &sdr_scc_mgr->update);
2731
2732                 /*
2733                  * Stop searching when the read test doesn't pass AND when
2734                  * we've seen a passing read on every bit.
2735                  */
2736                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2737                         0, PASS_ONE_BIT, &bit_chk, 0);
2738                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2739                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2740                 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2741                            == %u && %u [bit_chk= %u ]\n",
2742                         d, sticky_bit_chk, param->write_correct_mask,
2743                         stop, bit_chk);
2744
2745                 if (stop == 1) {
2746                         break;
2747                 } else {
2748                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2749                                 if (bit_chk & 1) {
2750                                         /*
2751                                          * Remember a passing test as the
2752                                          * left_edge.
2753                                          */
2754                                         left_edge[i] = d;
2755                                 } else {
2756                                         /*
2757                                          * If a left edge has not been seen
2758                                          * yet, then a future passing test will
2759                                          * mark this edge as the right edge.
2760                                          */
2761                                         if (left_edge[i] ==
2762                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2763                                                 right_edge[i] = -(d + 1);
2764                                         }
2765                                 }
2766                                 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2767                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2768                                            (int)(bit_chk & 1), i, left_edge[i]);
2769                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2770                                        right_edge[i]);
2771                                 bit_chk = bit_chk >> 1;
2772                         }
2773                 }
2774         }
2775
2776         /* Reset DQ delay chains to 0 */
2777         scc_mgr_apply_group_dq_out1_delay(0);
2778         sticky_bit_chk = 0;
2779         for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2780                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2781                            %d right_edge[%u]: %d\n", __func__, __LINE__,
2782                            i, left_edge[i], i, right_edge[i]);
2783
2784                 /*
2785                  * Check for cases where we haven't found the left edge,
2786                  * which makes our assignment of the the right edge invalid.
2787                  * Reset it to the illegal value.
2788                  */
2789                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2790                     (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2791                         right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2792                         debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2793                                    right_edge[%u]: %d\n", __func__, __LINE__,
2794                                    i, right_edge[i]);
2795                 }
2796
2797                 /*
2798                  * Reset sticky bit (except for bits where we have
2799                  * seen the left edge).
2800                  */
2801                 sticky_bit_chk = sticky_bit_chk << 1;
2802                 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2803                         sticky_bit_chk = sticky_bit_chk | 1;
2804
2805                 if (i == 0)
2806                         break;
2807         }
2808
2809         /* Search for the right edge of the window for each bit */
2810         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2811                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2812                                                         d + start_dqs);
2813
2814                 writel(0, &sdr_scc_mgr->update);
2815
2816                 /*
2817                  * Stop searching when the read test doesn't pass AND when
2818                  * we've seen a passing read on every bit.
2819                  */
2820                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2821                         0, PASS_ONE_BIT, &bit_chk, 0);
2822
2823                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2824                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2825
2826                 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2827                            %u && %u\n", d, sticky_bit_chk,
2828                            param->write_correct_mask, stop);
2829
2830                 if (stop == 1) {
2831                         if (d == 0) {
2832                                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2833                                         i++) {
2834                                         /* d = 0 failed, but it passed when
2835                                         testing the left edge, so it must be
2836                                         marginal, set it to -1 */
2837                                         if (right_edge[i] ==
2838                                                 IO_IO_OUT1_DELAY_MAX + 1 &&
2839                                                 left_edge[i] !=
2840                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2841                                                 right_edge[i] = -1;
2842                                         }
2843                                 }
2844                         }
2845                         break;
2846                 } else {
2847                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2848                                 if (bit_chk & 1) {
2849                                         /*
2850                                          * Remember a passing test as
2851                                          * the right_edge.
2852                                          */
2853                                         right_edge[i] = d;
2854                                 } else {
2855                                         if (d != 0) {
2856                                                 /*
2857                                                  * If a right edge has not
2858                                                  * been seen yet, then a future
2859                                                  * passing test will mark this
2860                                                  * edge as the left edge.
2861                                                  */
2862                                                 if (right_edge[i] ==
2863                                                     IO_IO_OUT1_DELAY_MAX + 1)
2864                                                         left_edge[i] = -(d + 1);
2865                                         } else {
2866                                                 /*
2867                                                  * d = 0 failed, but it passed
2868                                                  * when testing the left edge,
2869                                                  * so it must be marginal, set
2870                                                  * it to -1.
2871                                                  */
2872                                                 if (right_edge[i] ==
2873                                                     IO_IO_OUT1_DELAY_MAX + 1 &&
2874                                                     left_edge[i] !=
2875                                                     IO_IO_OUT1_DELAY_MAX + 1)
2876                                                         right_edge[i] = -1;
2877                                                 /*
2878                                                  * If a right edge has not been
2879                                                  * seen yet, then a future
2880                                                  * passing test will mark this
2881                                                  * edge as the left edge.
2882                                                  */
2883                                                 else if (right_edge[i] ==
2884                                                         IO_IO_OUT1_DELAY_MAX +
2885                                                         1)
2886                                                         left_edge[i] = -(d + 1);
2887                                         }
2888                                 }
2889                                 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2890                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2891                                            (int)(bit_chk & 1), i, left_edge[i]);
2892                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2893                                            right_edge[i]);
2894                                 bit_chk = bit_chk >> 1;
2895                         }
2896                 }
2897         }
2898
2899         /* Check that all bits have a window */
2900         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2901                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2902                            %d right_edge[%u]: %d", __func__, __LINE__,
2903                            i, left_edge[i], i, right_edge[i]);
2904                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2905                     (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2906                         set_failing_group_stage(test_bgn + i,
2907                                                 CAL_STAGE_WRITES,
2908                                                 CAL_SUBSTAGE_WRITES_CENTER);
2909                         return 0;
2910                 }
2911         }
2912
2913         /* Find middle of window for each DQ bit */
2914         mid_min = left_edge[0] - right_edge[0];
2915         min_index = 0;
2916         for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2917                 mid = left_edge[i] - right_edge[i];
2918                 if (mid < mid_min) {
2919                         mid_min = mid;
2920                         min_index = i;
2921                 }
2922         }
2923
2924         /*
2925          * -mid_min/2 represents the amount that we need to move DQS.
2926          * If mid_min is odd and positive we'll need to add one to
2927          * make sure the rounding in further calculations is correct
2928          * (always bias to the right), so just add 1 for all positive values.
2929          */
2930         if (mid_min > 0)
2931                 mid_min++;
2932         mid_min = mid_min / 2;
2933         debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2934                    __LINE__, mid_min);
2935
2936         /* Determine the amount we can change DQS (which is -mid_min) */
2937         orig_mid_min = mid_min;
2938         new_dqs = start_dqs;
2939         mid_min = 0;
2940         debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2941                    mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2942         /* Initialize data for export structures */
2943         dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2944         dq_margin  = IO_IO_OUT1_DELAY_MAX + 1;
2945
2946         /* add delay to bring centre of all DQ windows to the same "level" */
2947         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2948                 /* Use values before divide by 2 to reduce round off error */
2949                 shift_dq = (left_edge[i] - right_edge[i] -
2950                         (left_edge[min_index] - right_edge[min_index]))/2  +
2951                 (orig_mid_min - mid_min);
2952
2953                 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2954                            [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2955
2956                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2957                 temp_dq_out1_delay = readl(addr + (i << 2));
2958                 if (shift_dq + (int32_t)temp_dq_out1_delay >
2959                         (int32_t)IO_IO_OUT1_DELAY_MAX) {
2960                         shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2961                 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2962                         shift_dq = -(int32_t)temp_dq_out1_delay;
2963                 }
2964                 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2965                            i, shift_dq);
2966                 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2967                 scc_mgr_load_dq(i);
2968
2969                 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2970                            left_edge[i] - shift_dq + (-mid_min),
2971                            right_edge[i] + shift_dq - (-mid_min));
2972                 /* To determine values for export structures */
2973                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2974                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2975
2976                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2977                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2978         }
2979
2980         /* Move DQS */
2981         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2982         writel(0, &sdr_scc_mgr->update);
2983
2984         /* Centre DM */
2985         debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2986
2987         /*
2988          * set the left and right edge of each bit to an illegal value,
2989          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2990          */
2991         left_edge[0]  = IO_IO_OUT1_DELAY_MAX + 1;
2992         right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2993         int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2994         int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2995         int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2996         int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2997         int32_t win_best = 0;
2998
2999         /* Search for the/part of the window with DM shift */
3000         for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
3001                 scc_mgr_apply_group_dm_out1_delay(d);
3002                 writel(0, &sdr_scc_mgr->update);
3003
3004                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3005                                                     PASS_ALL_BITS, &bit_chk,
3006                                                     0)) {
3007                         /* USE Set current end of the window */
3008                         end_curr = -d;
3009                         /*
3010                          * If a starting edge of our window has not been seen
3011                          * this is our current start of the DM window.
3012                          */
3013                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3014                                 bgn_curr = -d;
3015
3016                         /*
3017                          * If current window is bigger than best seen.
3018                          * Set best seen to be current window.
3019                          */
3020                         if ((end_curr-bgn_curr+1) > win_best) {
3021                                 win_best = end_curr-bgn_curr+1;
3022                                 bgn_best = bgn_curr;
3023                                 end_best = end_curr;
3024                         }
3025                 } else {
3026                         /* We just saw a failing test. Reset temp edge */
3027                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3028                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3029                         }
3030                 }
3031
3032
3033         /* Reset DM delay chains to 0 */
3034         scc_mgr_apply_group_dm_out1_delay(0);
3035
3036         /*
3037          * Check to see if the current window nudges up aganist 0 delay.
3038          * If so we need to continue the search by shifting DQS otherwise DQS
3039          * search begins as a new search. */
3040         if (end_curr != 0) {
3041                 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3042                 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3043         }
3044
3045         /* Search for the/part of the window with DQS shifts */
3046         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3047                 /*
3048                  * Note: This only shifts DQS, so are we limiting ourselve to
3049                  * width of DQ unnecessarily.
3050                  */
3051                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3052                                                         d + new_dqs);
3053
3054                 writel(0, &sdr_scc_mgr->update);
3055                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3056                                                     PASS_ALL_BITS, &bit_chk,
3057                                                     0)) {
3058                         /* USE Set current end of the window */
3059                         end_curr = d;
3060                         /*
3061                          * If a beginning edge of our window has not been seen
3062                          * this is our current begin of the DM window.
3063                          */
3064                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3065                                 bgn_curr = d;
3066
3067                         /*
3068                          * If current window is bigger than best seen. Set best
3069                          * seen to be current window.
3070                          */
3071                         if ((end_curr-bgn_curr+1) > win_best) {
3072                                 win_best = end_curr-bgn_curr+1;
3073                                 bgn_best = bgn_curr;
3074                                 end_best = end_curr;
3075                         }
3076                 } else {
3077                         /* We just saw a failing test. Reset temp edge */
3078                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3079                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3080
3081                         /* Early exit optimization: if ther remaining delay
3082                         chain space is less than already seen largest window
3083                         we can exit */
3084                         if ((win_best-1) >
3085                                 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3086                                         break;
3087                                 }
3088                         }
3089                 }
3090
3091         /* assign left and right edge for cal and reporting; */
3092         left_edge[0] = -1*bgn_best;
3093         right_edge[0] = end_best;
3094
3095         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3096                    __LINE__, left_edge[0], right_edge[0]);
3097
3098         /* Move DQS (back to orig) */
3099         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3100
3101         /* Move DM */
3102
3103         /* Find middle of window for the DM bit */
3104         mid = (left_edge[0] - right_edge[0]) / 2;
3105
3106         /* only move right, since we are not moving DQS/DQ */
3107         if (mid < 0)
3108                 mid = 0;
3109
3110         /* dm_marign should fail if we never find a window */
3111         if (win_best == 0)
3112                 dm_margin = -1;
3113         else
3114                 dm_margin = left_edge[0] - mid;
3115
3116         scc_mgr_apply_group_dm_out1_delay(mid);
3117         writel(0, &sdr_scc_mgr->update);
3118
3119         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3120                    dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3121                    right_edge[0], mid, dm_margin);
3122         /* Export values */
3123         gbl->fom_out += dq_margin + dqs_margin;
3124
3125         debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3126                    dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3127                    dq_margin, dqs_margin, dm_margin);
3128
3129         /*
3130          * Do not remove this line as it makes sure all of our
3131          * decisions have been applied.
3132          */
3133         writel(0, &sdr_scc_mgr->update);
3134         return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3135 }
3136
3137 /* calibrate the write operations */
3138 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3139         uint32_t test_bgn)
3140 {
3141         /* update info for sims */
3142         debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3143
3144         reg_file_set_stage(CAL_STAGE_WRITES);
3145         reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3146
3147         reg_file_set_group(g);
3148
3149         if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3150                 set_failing_group_stage(g, CAL_STAGE_WRITES,
3151                                         CAL_SUBSTAGE_WRITES_CENTER);
3152                 return 0;
3153         }
3154
3155         return 1;
3156 }
3157
3158 /**
3159  * mem_precharge_and_activate() - Precharge all banks and activate
3160  *
3161  * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3162  */
3163 static void mem_precharge_and_activate(void)
3164 {
3165         int r;
3166
3167         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3168                 /* Test if the rank should be skipped. */
3169                 if (param->skip_ranks[r])
3170                         continue;
3171
3172                 /* Set rank. */
3173                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3174
3175                 /* Precharge all banks. */
3176                 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3177                                              RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3178
3179                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3180                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3181                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3182
3183                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3184                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3185                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3186
3187                 /* Activate rows. */
3188                 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3189                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3190         }
3191 }
3192
3193 /**
3194  * mem_init_latency() - Configure memory RLAT and WLAT settings
3195  *
3196  * Configure memory RLAT and WLAT parameters.
3197  */
3198 static void mem_init_latency(void)
3199 {
3200         /*
3201          * For AV/CV, LFIFO is hardened and always runs at full rate
3202          * so max latency in AFI clocks, used here, is correspondingly
3203          * smaller.
3204          */
3205         const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3206         u32 rlat, wlat;
3207
3208         debug("%s:%d\n", __func__, __LINE__);
3209
3210         /*
3211          * Read in write latency.
3212          * WL for Hard PHY does not include additive latency.
3213          */
3214         wlat = readl(&data_mgr->t_wl_add);
3215         wlat += readl(&data_mgr->mem_t_add);
3216
3217         gbl->rw_wl_nop_cycles = wlat - 1;
3218
3219         /* Read in readl latency. */
3220         rlat = readl(&data_mgr->t_rl_add);
3221
3222         /* Set a pretty high read latency initially. */
3223         gbl->curr_read_lat = rlat + 16;
3224         if (gbl->curr_read_lat > max_latency)
3225                 gbl->curr_read_lat = max_latency;
3226
3227         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3228
3229         /* Advertise write latency. */
3230         writel(wlat, &phy_mgr_cfg->afi_wlat);
3231 }
3232
3233 /**
3234  * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3235  *
3236  * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3237  */
3238 static void mem_skip_calibrate(void)
3239 {
3240         uint32_t vfifo_offset;
3241         uint32_t i, j, r;
3242
3243         debug("%s:%d\n", __func__, __LINE__);
3244         /* Need to update every shadow register set used by the interface */
3245         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3246              r += NUM_RANKS_PER_SHADOW_REG) {
3247                 /*
3248                  * Set output phase alignment settings appropriate for
3249                  * skip calibration.
3250                  */
3251                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3252                         scc_mgr_set_dqs_en_phase(i, 0);
3253 #if IO_DLL_CHAIN_LENGTH == 6
3254                         scc_mgr_set_dqdqs_output_phase(i, 6);
3255 #else
3256                         scc_mgr_set_dqdqs_output_phase(i, 7);
3257 #endif
3258                         /*
3259                          * Case:33398
3260                          *
3261                          * Write data arrives to the I/O two cycles before write
3262                          * latency is reached (720 deg).
3263                          *   -> due to bit-slip in a/c bus
3264                          *   -> to allow board skew where dqs is longer than ck
3265                          *      -> how often can this happen!?
3266                          *      -> can claim back some ptaps for high freq
3267                          *       support if we can relax this, but i digress...
3268                          *
3269                          * The write_clk leads mem_ck by 90 deg
3270                          * The minimum ptap of the OPA is 180 deg
3271                          * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3272                          * The write_clk is always delayed by 2 ptaps
3273                          *
3274                          * Hence, to make DQS aligned to CK, we need to delay
3275                          * DQS by:
3276                          *    (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3277                          *
3278                          * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3279                          * gives us the number of ptaps, which simplies to:
3280                          *
3281                          *    (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3282                          */
3283                         scc_mgr_set_dqdqs_output_phase(i,
3284                                         1.25 * IO_DLL_CHAIN_LENGTH - 2);
3285                 }
3286                 writel(0xff, &sdr_scc_mgr->dqs_ena);
3287                 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3288
3289                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3290                         writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3291                                   SCC_MGR_GROUP_COUNTER_OFFSET);
3292                 }
3293                 writel(0xff, &sdr_scc_mgr->dq_ena);
3294                 writel(0xff, &sdr_scc_mgr->dm_ena);
3295                 writel(0, &sdr_scc_mgr->update);
3296         }
3297
3298         /* Compensate for simulation model behaviour */
3299         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3300                 scc_mgr_set_dqs_bus_in_delay(i, 10);
3301                 scc_mgr_load_dqs(i);
3302         }
3303         writel(0, &sdr_scc_mgr->update);
3304
3305         /*
3306          * ArriaV has hard FIFOs that can only be initialized by incrementing
3307          * in sequencer.
3308          */
3309         vfifo_offset = CALIB_VFIFO_OFFSET;
3310         for (j = 0; j < vfifo_offset; j++)
3311                 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3312         writel(0, &phy_mgr_cmd->fifo_reset);
3313
3314         /*
3315          * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3316          * setting from generation-time constant.
3317          */
3318         gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3319         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3320 }
3321
3322 /**
3323  * mem_calibrate() - Memory calibration entry point.
3324  *
3325  * Perform memory calibration.
3326  */
3327 static uint32_t mem_calibrate(void)
3328 {
3329         uint32_t i;
3330         uint32_t rank_bgn, sr;
3331         uint32_t write_group, write_test_bgn;
3332         uint32_t read_group, read_test_bgn;
3333         uint32_t run_groups, current_run;
3334         uint32_t failing_groups = 0;
3335         uint32_t group_failed = 0;
3336
3337         const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3338                                 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3339
3340         debug("%s:%d\n", __func__, __LINE__);
3341
3342         /* Initialize the data settings */
3343         gbl->error_substage = CAL_SUBSTAGE_NIL;
3344         gbl->error_stage = CAL_STAGE_NIL;
3345         gbl->error_group = 0xff;
3346         gbl->fom_in = 0;
3347         gbl->fom_out = 0;
3348
3349         /* Initialize WLAT and RLAT. */
3350         mem_init_latency();
3351
3352         /* Initialize bit slips. */
3353         mem_precharge_and_activate();
3354
3355         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3356                 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3357                           SCC_MGR_GROUP_COUNTER_OFFSET);
3358                 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3359                 if (i == 0)
3360                         scc_mgr_set_hhp_extras();
3361
3362                 scc_set_bypass_mode(i);
3363         }
3364
3365         /* Calibration is skipped. */
3366         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3367                 /*
3368                  * Set VFIFO and LFIFO to instant-on settings in skip
3369                  * calibration mode.
3370                  */
3371                 mem_skip_calibrate();
3372
3373                 /*
3374                  * Do not remove this line as it makes sure all of our
3375                  * decisions have been applied.
3376                  */
3377                 writel(0, &sdr_scc_mgr->update);
3378                 return 1;
3379         }
3380
3381         /* Calibration is not skipped. */
3382         for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3383                 /*
3384                  * Zero all delay chain/phase settings for all
3385                  * groups and all shadow register sets.
3386                  */
3387                 scc_mgr_zero_all();
3388
3389                 run_groups = ~param->skip_groups;
3390
3391                 for (write_group = 0, write_test_bgn = 0; write_group
3392                         < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3393                         write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3394
3395                         /* Initialize the group failure */
3396                         group_failed = 0;
3397
3398                         current_run = run_groups & ((1 <<
3399                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3400                         run_groups = run_groups >>
3401                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3402
3403                         if (current_run == 0)
3404                                 continue;
3405
3406                         writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3407                                             SCC_MGR_GROUP_COUNTER_OFFSET);
3408                         scc_mgr_zero_group(write_group, 0);
3409
3410                         for (read_group = write_group * rwdqs_ratio,
3411                              read_test_bgn = 0;
3412                              read_group < (write_group + 1) * rwdqs_ratio;
3413                              read_group++,
3414                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3415                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3416                                         continue;
3417
3418                                 /* Calibrate the VFIFO */
3419                                 if (rw_mgr_mem_calibrate_vfifo(read_group,
3420                                                                read_test_bgn))
3421                                         continue;
3422
3423                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3424                                         return 0;
3425
3426                                 /* The group failed, we're done. */
3427                                 goto grp_failed;
3428                         }
3429
3430                         /* Calibrate the output side */
3431                         for (rank_bgn = 0, sr = 0;
3432                              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3433                              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3434                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3435                                         continue;
3436
3437                                 /* Not needed in quick mode! */
3438                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3439                                         continue;
3440
3441                                 /*
3442                                  * Determine if this set of ranks
3443                                  * should be skipped entirely.
3444                                  */
3445                                 if (param->skip_shadow_regs[sr])
3446                                         continue;
3447
3448                                 /* Calibrate WRITEs */
3449                                 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3450                                                 write_group, write_test_bgn))
3451                                         continue;
3452
3453                                 group_failed = 1;
3454                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3455                                         return 0;
3456                         }
3457
3458                         /* Some group failed, we're done. */
3459                         if (group_failed)
3460                                 goto grp_failed;
3461
3462                         for (read_group = write_group * rwdqs_ratio,
3463                              read_test_bgn = 0;
3464                              read_group < (write_group + 1) * rwdqs_ratio;
3465                              read_group++,
3466                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3467                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3468                                         continue;
3469
3470                                 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3471                                                                 read_test_bgn))
3472                                         continue;
3473
3474                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3475                                         return 0;
3476
3477                                 /* The group failed, we're done. */
3478                                 goto grp_failed;
3479                         }
3480
3481                         /* No group failed, continue as usual. */
3482                         continue;
3483
3484 grp_failed:             /* A group failed, increment the counter. */
3485                         failing_groups++;
3486                 }
3487
3488                 /*
3489                  * USER If there are any failing groups then report
3490                  * the failure.
3491                  */
3492                 if (failing_groups != 0)
3493                         return 0;
3494
3495                 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3496                         continue;
3497
3498                 /*
3499                  * If we're skipping groups as part of debug,
3500                  * don't calibrate LFIFO.
3501                  */
3502                 if (param->skip_groups != 0)
3503                         continue;
3504
3505                 /* Calibrate the LFIFO */
3506                 if (!rw_mgr_mem_calibrate_lfifo())
3507                         return 0;
3508         }
3509
3510         /*
3511          * Do not remove this line as it makes sure all of our decisions
3512          * have been applied.
3513          */
3514         writel(0, &sdr_scc_mgr->update);
3515         return 1;
3516 }
3517
3518 /**
3519  * run_mem_calibrate() - Perform memory calibration
3520  *
3521  * This function triggers the entire memory calibration procedure.
3522  */
3523 static int run_mem_calibrate(void)
3524 {
3525         int pass;
3526
3527         debug("%s:%d\n", __func__, __LINE__);
3528
3529         /* Reset pass/fail status shown on afi_cal_success/fail */
3530         writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3531
3532         /* Stop tracking manager. */
3533         clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3534
3535         phy_mgr_initialize();
3536         rw_mgr_mem_initialize();
3537
3538         /* Perform the actual memory calibration. */
3539         pass = mem_calibrate();
3540
3541         mem_precharge_and_activate();
3542         writel(0, &phy_mgr_cmd->fifo_reset);
3543
3544         /* Handoff. */
3545         rw_mgr_mem_handoff();
3546         /*
3547          * In Hard PHY this is a 2-bit control:
3548          * 0: AFI Mux Select
3549          * 1: DDIO Mux Select
3550          */
3551         writel(0x2, &phy_mgr_cfg->mux_sel);
3552
3553         /* Start tracking manager. */
3554         setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3555
3556         return pass;
3557 }
3558
3559 /**
3560  * debug_mem_calibrate() - Report result of memory calibration
3561  * @pass:       Value indicating whether calibration passed or failed
3562  *
3563  * This function reports the results of the memory calibration
3564  * and writes debug information into the register file.
3565  */
3566 static void debug_mem_calibrate(int pass)
3567 {
3568         uint32_t debug_info;
3569
3570         if (pass) {
3571                 printf("%s: CALIBRATION PASSED\n", __FILE__);
3572
3573                 gbl->fom_in /= 2;
3574                 gbl->fom_out /= 2;
3575
3576                 if (gbl->fom_in > 0xff)
3577                         gbl->fom_in = 0xff;
3578
3579                 if (gbl->fom_out > 0xff)
3580                         gbl->fom_out = 0xff;
3581
3582                 /* Update the FOM in the register file */
3583                 debug_info = gbl->fom_in;
3584                 debug_info |= gbl->fom_out << 8;
3585                 writel(debug_info, &sdr_reg_file->fom);
3586
3587                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3588                 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3589         } else {
3590                 printf("%s: CALIBRATION FAILED\n", __FILE__);
3591
3592                 debug_info = gbl->error_stage;
3593                 debug_info |= gbl->error_substage << 8;
3594                 debug_info |= gbl->error_group << 16;
3595
3596                 writel(debug_info, &sdr_reg_file->failing_stage);
3597                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3598                 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3599
3600                 /* Update the failing group/stage in the register file */
3601                 debug_info = gbl->error_stage;
3602                 debug_info |= gbl->error_substage << 8;
3603                 debug_info |= gbl->error_group << 16;
3604                 writel(debug_info, &sdr_reg_file->failing_stage);
3605         }
3606
3607         printf("%s: Calibration complete\n", __FILE__);
3608 }
3609
3610 /**
3611  * hc_initialize_rom_data() - Initialize ROM data
3612  *
3613  * Initialize ROM data.
3614  */
3615 static void hc_initialize_rom_data(void)
3616 {
3617         u32 i, addr;
3618
3619         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3620         for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3621                 writel(inst_rom_init[i], addr + (i << 2));
3622
3623         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3624         for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3625                 writel(ac_rom_init[i], addr + (i << 2));
3626 }
3627
3628 /**
3629  * initialize_reg_file() - Initialize SDR register file
3630  *
3631  * Initialize SDR register file.
3632  */
3633 static void initialize_reg_file(void)
3634 {
3635         /* Initialize the register file with the correct data */
3636         writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3637         writel(0, &sdr_reg_file->debug_data_addr);
3638         writel(0, &sdr_reg_file->cur_stage);
3639         writel(0, &sdr_reg_file->fom);
3640         writel(0, &sdr_reg_file->failing_stage);
3641         writel(0, &sdr_reg_file->debug1);
3642         writel(0, &sdr_reg_file->debug2);
3643 }
3644
3645 /**
3646  * initialize_hps_phy() - Initialize HPS PHY
3647  *
3648  * Initialize HPS PHY.
3649  */
3650 static void initialize_hps_phy(void)
3651 {
3652         uint32_t reg;
3653         /*
3654          * Tracking also gets configured here because it's in the
3655          * same register.
3656          */
3657         uint32_t trk_sample_count = 7500;
3658         uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3659         /*
3660          * Format is number of outer loops in the 16 MSB, sample
3661          * count in 16 LSB.
3662          */
3663
3664         reg = 0;
3665         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3666         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3667         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3668         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3669         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3670         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3671         /*
3672          * This field selects the intrinsic latency to RDATA_EN/FULL path.
3673          * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3674          */
3675         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3676         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3677                 trk_sample_count);
3678         writel(reg, &sdr_ctrl->phy_ctrl0);
3679
3680         reg = 0;
3681         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3682                 trk_sample_count >>
3683                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3684         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3685                 trk_long_idle_sample_count);
3686         writel(reg, &sdr_ctrl->phy_ctrl1);
3687
3688         reg = 0;
3689         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3690                 trk_long_idle_sample_count >>
3691                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3692         writel(reg, &sdr_ctrl->phy_ctrl2);
3693 }
3694
3695 /**
3696  * initialize_tracking() - Initialize tracking
3697  *
3698  * Initialize the register file with usable initial data.
3699  */
3700 static void initialize_tracking(void)
3701 {
3702         /*
3703          * Initialize the register file with the correct data.
3704          * Compute usable version of value in case we skip full
3705          * computation later.
3706          */
3707         writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3708                &sdr_reg_file->dtaps_per_ptap);
3709
3710         /* trk_sample_count */
3711         writel(7500, &sdr_reg_file->trk_sample_count);
3712
3713         /* longidle outer loop [15:0] */
3714         writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3715
3716         /*
3717          * longidle sample count [31:24]
3718          * trfc, worst case of 933Mhz 4Gb [23:16]
3719          * trcd, worst case [15:8]
3720          * vfifo wait [7:0]
3721          */
3722         writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3723                &sdr_reg_file->delays);
3724
3725         /* mux delay */
3726         writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3727                (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3728                &sdr_reg_file->trk_rw_mgr_addr);
3729
3730         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3731                &sdr_reg_file->trk_read_dqs_width);
3732
3733         /* trefi [7:0] */
3734         writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3735                &sdr_reg_file->trk_rfsh);
3736 }
3737
3738 int sdram_calibration_full(void)
3739 {
3740         struct param_type my_param;
3741         struct gbl_type my_gbl;
3742         uint32_t pass;
3743
3744         memset(&my_param, 0, sizeof(my_param));
3745         memset(&my_gbl, 0, sizeof(my_gbl));
3746
3747         param = &my_param;
3748         gbl = &my_gbl;
3749
3750         /* Set the calibration enabled by default */
3751         gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3752         /*
3753          * Only sweep all groups (regardless of fail state) by default
3754          * Set enabled read test by default.
3755          */
3756 #if DISABLE_GUARANTEED_READ
3757         gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3758 #endif
3759         /* Initialize the register file */
3760         initialize_reg_file();
3761
3762         /* Initialize any PHY CSR */
3763         initialize_hps_phy();
3764
3765         scc_mgr_initialize();
3766
3767         initialize_tracking();
3768
3769         printf("%s: Preparing to start memory calibration\n", __FILE__);
3770
3771         debug("%s:%d\n", __func__, __LINE__);
3772         debug_cond(DLEVEL == 1,
3773                    "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3774                    RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3775                    RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3776                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3777                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3778         debug_cond(DLEVEL == 1,
3779                    "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3780                    RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3781                    RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3782                    IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3783         debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3784                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3785         debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3786                    IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3787                    IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3788         debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3789                    IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3790                    IO_IO_OUT2_DELAY_MAX);
3791         debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3792                    IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3793
3794         hc_initialize_rom_data();
3795
3796         /* update info for sims */
3797         reg_file_set_stage(CAL_STAGE_NIL);
3798         reg_file_set_group(0);
3799
3800         /*
3801          * Load global needed for those actions that require
3802          * some dynamic calibration support.
3803          */
3804         dyn_calib_steps = STATIC_CALIB_STEPS;
3805         /*
3806          * Load global to allow dynamic selection of delay loop settings
3807          * based on calibration mode.
3808          */
3809         if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3810                 skip_delay_mask = 0xff;
3811         else
3812                 skip_delay_mask = 0x0;
3813
3814         pass = run_mem_calibrate();
3815         debug_mem_calibrate(pass);
3816         return pass;
3817 }