drivers/ddr/altera/sequencer.c

   1 /*
   2  * Copyright Altera Corporation (C) 2012-2015
   3  *
   4  * SPDX-License-Identifier:    BSD-3-Clause
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/sdram.h>
  10 #include <errno.h>
  11 #include "sequencer.h"
  12 #include "sequencer_auto.h"
  13 #include "sequencer_auto_ac_init.h"
  14 #include "sequencer_auto_inst_init.h"
  15 #include "sequencer_defines.h"
  16
  17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
  18         (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
  19
  20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
  21         (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
  22
  23 static struct socfpga_sdr_reg_file *sdr_reg_file =
  24         (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
  25
  26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
  27         (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
  28
  29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
  30         (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
  31
  32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
  33         (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
  34
  35 static struct socfpga_data_mgr *data_mgr =
  36         (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
  37
  38 static struct socfpga_sdr_ctrl *sdr_ctrl =
  39         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  40
  41 #define DELTA_D         1
  42
  43 /*
  44  * In order to reduce ROM size, most of the selectable calibration steps are
  45  * decided at compile time based on the user's calibration mode selection,
  46  * as captured by the STATIC_CALIB_STEPS selection below.
  47  *
  48  * However, to support simulation-time selection of fast simulation mode, where
  49  * we skip everything except the bare minimum, we need a few of the steps to
  50  * be dynamic.  In those cases, we either use the DYNAMIC_CALIB_STEPS for the
  51  * check, which is based on the rtl-supplied value, or we dynamically compute
  52  * the value to use based on the dynamically-chosen calibration mode
  53  */
  54
  55 #define DLEVEL 0
  56 #define STATIC_IN_RTL_SIM 0
  57 #define STATIC_SKIP_DELAY_LOOPS 0
  58
  59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
  60         STATIC_SKIP_DELAY_LOOPS)
  61
  62 /* calibration steps requested by the rtl */
  63 uint16_t dyn_calib_steps;
  64
  65 /*
  66  * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
  67  * instead of static, we use boolean logic to select between
  68  * non-skip and skip values
  69  *
  70  * The mask is set to include all bits when not-skipping, but is
  71  * zero when skipping
  72  */
  73
  74 uint16_t skip_delay_mask;       /* mask off bits when skipping/not-skipping */
  75
  76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
  77         ((non_skip_value) & skip_delay_mask)
  78
  79 struct gbl_type *gbl;
  80 struct param_type *param;
  81 uint32_t curr_shadow_reg;
  82
  83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
  84         uint32_t write_group, uint32_t use_dm,
  85         uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
  86
  87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
  88         uint32_t substage)
  89 {
  90         /*
  91          * Only set the global stage if there was not been any other
  92          * failing group
  93          */
  94         if (gbl->error_stage == CAL_STAGE_NIL)  {
  95                 gbl->error_substage = substage;
  96                 gbl->error_stage = stage;
  97                 gbl->error_group = group;
  98         }
  99 }
 100
 101 static void reg_file_set_group(u16 set_group)
 102 {
 103         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
 104 }
 105
 106 static void reg_file_set_stage(u8 set_stage)
 107 {
 108         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
 109 }
 110
 111 static void reg_file_set_sub_stage(u8 set_sub_stage)
 112 {
 113         set_sub_stage &= 0xff;
 114         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
 115 }
 116
 117 /**
 118  * phy_mgr_initialize() - Initialize PHY Manager
 119  *
 120  * Initialize PHY Manager.
 121  */
 122 static void phy_mgr_initialize(void)
 123 {
 124         u32 ratio;
 125
 126         debug("%s:%d\n", __func__, __LINE__);
 127         /* Calibration has control over path to memory */
 128         /*
 129          * In Hard PHY this is a 2-bit control:
 130          * 0: AFI Mux Select
 131          * 1: DDIO Mux Select
 132          */
 133         writel(0x3, &phy_mgr_cfg->mux_sel);
 134
 135         /* USER memory clock is not stable we begin initialization  */
 136         writel(0, &phy_mgr_cfg->reset_mem_stbl);
 137
 138         /* USER calibration status all set to zero */
 139         writel(0, &phy_mgr_cfg->cal_status);
 140
 141         writel(0, &phy_mgr_cfg->cal_debug_info);
 142
 143         /* Init params only if we do NOT skip calibration. */
 144         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
 145                 return;
 146
 147         ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
 148                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
 149         param->read_correct_mask_vg = (1 << ratio) - 1;
 150         param->write_correct_mask_vg = (1 << ratio) - 1;
 151         param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
 152         param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
 153         ratio = RW_MGR_MEM_DATA_WIDTH /
 154                 RW_MGR_MEM_DATA_MASK_WIDTH;
 155         param->dm_correct_mask = (1 << ratio) - 1;
 156 }
 157
 158 /**
 159  * set_rank_and_odt_mask() - Set Rank and ODT mask
 160  * @rank:       Rank mask
 161  * @odt_mode:   ODT mode, OFF or READ_WRITE
 162  *
 163  * Set Rank and ODT mask (On-Die Termination).
 164  */
 165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
 166 {
 167         u32 odt_mask_0 = 0;
 168         u32 odt_mask_1 = 0;
 169         u32 cs_and_odt_mask;
 170
 171         if (odt_mode == RW_MGR_ODT_MODE_OFF) {
 172                 odt_mask_0 = 0x0;
 173                 odt_mask_1 = 0x0;
 174         } else {        /* RW_MGR_ODT_MODE_READ_WRITE */
 175                 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
 176                 case 1: /* 1 Rank */
 177                         /* Read: ODT = 0 ; Write: ODT = 1 */
 178                         odt_mask_0 = 0x0;
 179                         odt_mask_1 = 0x1;
 180                         break;
 181                 case 2: /* 2 Ranks */
 182                         if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
 183                                 /*
 184                                  * - Dual-Slot , Single-Rank (1 CS per DIMM)
 185                                  *   OR
 186                                  * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
 187                                  *
 188                                  * Since MEM_NUMBER_OF_RANKS is 2, they
 189                                  * are both single rank with 2 CS each
 190                                  * (special for RDIMM).
 191                                  *
 192                                  * Read: Turn on ODT on the opposite rank
 193                                  * Write: Turn on ODT on all ranks
 194                                  */
 195                                 odt_mask_0 = 0x3 & ~(1 << rank);
 196                                 odt_mask_1 = 0x3;
 197                         } else {
 198                                 /*
 199                                  * - Single-Slot , Dual-Rank (2 CS per DIMM)
 200                                  *
 201                                  * Read: Turn on ODT off on all ranks
 202                                  * Write: Turn on ODT on active rank
 203                                  */
 204                                 odt_mask_0 = 0x0;
 205                                 odt_mask_1 = 0x3 & (1 << rank);
 206                         }
 207                         break;
 208                 case 4: /* 4 Ranks */
 209                         /* Read:
 210                          * ----------+-----------------------+
 211                          *           |         ODT           |
 212                          * Read From +-----------------------+
 213                          *   Rank    |  3  |  2  |  1  |  0  |
 214                          * ----------+-----+-----+-----+-----+
 215                          *     0     |  0  |  1  |  0  |  0  |
 216                          *     1     |  1  |  0  |  0  |  0  |
 217                          *     2     |  0  |  0  |  0  |  1  |
 218                          *     3     |  0  |  0  |  1  |  0  |
 219                          * ----------+-----+-----+-----+-----+
 220                          *
 221                          * Write:
 222                          * ----------+-----------------------+
 223                          *           |         ODT           |
 224                          * Write To  +-----------------------+
 225                          *   Rank    |  3  |  2  |  1  |  0  |
 226                          * ----------+-----+-----+-----+-----+
 227                          *     0     |  0  |  1  |  0  |  1  |
 228                          *     1     |  1  |  0  |  1  |  0  |
 229                          *     2     |  0  |  1  |  0  |  1  |
 230                          *     3     |  1  |  0  |  1  |  0  |
 231                          * ----------+-----+-----+-----+-----+
 232                          */
 233                         switch (rank) {
 234                         case 0:
 235                                 odt_mask_0 = 0x4;
 236                                 odt_mask_1 = 0x5;
 237                                 break;
 238                         case 1:
 239                                 odt_mask_0 = 0x8;
 240                                 odt_mask_1 = 0xA;
 241                                 break;
 242                         case 2:
 243                                 odt_mask_0 = 0x1;
 244                                 odt_mask_1 = 0x5;
 245                                 break;
 246                         case 3:
 247                                 odt_mask_0 = 0x2;
 248                                 odt_mask_1 = 0xA;
 249                                 break;
 250                         }
 251                         break;
 252                 }
 253         }
 254
 255         cs_and_odt_mask = (0xFF & ~(1 << rank)) |
 256                           ((0xFF & odt_mask_0) << 8) |
 257                           ((0xFF & odt_mask_1) << 16);
 258         writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 259                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 260 }
 261
 262 /**
 263  * scc_mgr_set() - Set SCC Manager register
 264  * @off:        Base offset in SCC Manager space
 265  * @grp:        Read/Write group
 266  * @val:        Value to be set
 267  *
 268  * This function sets the SCC Manager (Scan Chain Control Manager) register.
 269  */
 270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
 271 {
 272         writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
 273 }
 274
 275 /**
 276  * scc_mgr_initialize() - Initialize SCC Manager registers
 277  *
 278  * Initialize SCC Manager registers.
 279  */
 280 static void scc_mgr_initialize(void)
 281 {
 282         /*
 283          * Clear register file for HPS. 16 (2^4) is the size of the
 284          * full register file in the scc mgr:
 285          *      RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
 286          *                             MEM_IF_READ_DQS_WIDTH - 1);
 287          */
 288         int i;
 289
 290         for (i = 0; i < 16; i++) {
 291                 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
 292                            __func__, __LINE__, i);
 293                 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
 294         }
 295 }
 296
 297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
 298 {
 299         scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
 300 }
 301
 302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
 303 {
 304         scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
 305 }
 306
 307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
 308 {
 309         scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
 310 }
 311
 312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
 313 {
 314         scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
 315 }
 316
 317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
 318 {
 319         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 320                     delay);
 321 }
 322
 323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
 324 {
 325         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
 326 }
 327
 328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
 329 {
 330         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
 331 }
 332
 333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
 334 {
 335         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 336                     delay);
 337 }
 338
 339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
 340 {
 341         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
 342                     RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
 343                     delay);
 344 }
 345
 346 /* load up dqs config settings */
 347 static void scc_mgr_load_dqs(uint32_t dqs)
 348 {
 349         writel(dqs, &sdr_scc_mgr->dqs_ena);
 350 }
 351
 352 /* load up dqs io config settings */
 353 static void scc_mgr_load_dqs_io(void)
 354 {
 355         writel(0, &sdr_scc_mgr->dqs_io_ena);
 356 }
 357
 358 /* load up dq config settings */
 359 static void scc_mgr_load_dq(uint32_t dq_in_group)
 360 {
 361         writel(dq_in_group, &sdr_scc_mgr->dq_ena);
 362 }
 363
 364 /* load up dm config settings */
 365 static void scc_mgr_load_dm(uint32_t dm)
 366 {
 367         writel(dm, &sdr_scc_mgr->dm_ena);
 368 }
 369
 370 /**
 371  * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
 372  * @off:        Base offset in SCC Manager space
 373  * @grp:        Read/Write group
 374  * @val:        Value to be set
 375  * @update:     If non-zero, trigger SCC Manager update for all ranks
 376  *
 377  * This function sets the SCC Manager (Scan Chain Control Manager) register
 378  * and optionally triggers the SCC update for all ranks.
 379  */
 380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
 381                                   const int update)
 382 {
 383         u32 r;
 384
 385         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 386              r += NUM_RANKS_PER_SHADOW_REG) {
 387                 scc_mgr_set(off, grp, val);
 388
 389                 if (update || (r == 0)) {
 390                         writel(grp, &sdr_scc_mgr->dqs_ena);
 391                         writel(0, &sdr_scc_mgr->update);
 392                 }
 393         }
 394 }
 395
 396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
 397 {
 398         /*
 399          * USER although the h/w doesn't support different phases per
 400          * shadow register, for simplicity our scc manager modeling
 401          * keeps different phase settings per shadow reg, and it's
 402          * important for us to keep them in sync to match h/w.
 403          * for efficiency, the scan chain update should occur only
 404          * once to sr0.
 405          */
 406         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
 407                               read_group, phase, 0);
 408 }
 409
 410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
 411                                                      uint32_t phase)
 412 {
 413         /*
 414          * USER although the h/w doesn't support different phases per
 415          * shadow register, for simplicity our scc manager modeling
 416          * keeps different phase settings per shadow reg, and it's
 417          * important for us to keep them in sync to match h/w.
 418          * for efficiency, the scan chain update should occur only
 419          * once to sr0.
 420          */
 421         scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
 422                               write_group, phase, 0);
 423 }
 424
 425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
 426                                                uint32_t delay)
 427 {
 428         /*
 429          * In shadow register mode, the T11 settings are stored in
 430          * registers in the core, which are updated by the DQS_ENA
 431          * signals. Not issuing the SCC_MGR_UPD command allows us to
 432          * save lots of rank switching overhead, by calling
 433          * select_shadow_regs_for_update with update_scan_chains
 434          * set to 0.
 435          */
 436         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
 437                               read_group, delay, 1);
 438         writel(0, &sdr_scc_mgr->update);
 439 }
 440
 441 /**
 442  * scc_mgr_set_oct_out1_delay() - Set OCT output delay
 443  * @write_group:        Write group
 444  * @delay:              Delay value
 445  *
 446  * This function sets the OCT output delay in SCC manager.
 447  */
 448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
 449 {
 450         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 451                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 452         const int base = write_group * ratio;
 453         int i;
 454         /*
 455          * Load the setting in the SCC manager
 456          * Although OCT affects only write data, the OCT delay is controlled
 457          * by the DQS logic block which is instantiated once per read group.
 458          * For protocols where a write group consists of multiple read groups,
 459          * the setting must be set multiple times.
 460          */
 461         for (i = 0; i < ratio; i++)
 462                 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
 463 }
 464
 465 /**
 466  * scc_mgr_set_hhp_extras() - Set HHP extras.
 467  *
 468  * Load the fixed setting in the SCC manager HHP extras.
 469  */
 470 static void scc_mgr_set_hhp_extras(void)
 471 {
 472         /*
 473          * Load the fixed setting in the SCC manager
 474          * bits: 0:0 = 1'b1     - DQS bypass
 475          * bits: 1:1 = 1'b1     - DQ bypass
 476          * bits: 4:2 = 3'b001   - rfifo_mode
 477          * bits: 6:5 = 2'b01    - rfifo clock_select
 478          * bits: 7:7 = 1'b0     - separate gating from ungating setting
 479          * bits: 8:8 = 1'b0     - separate OE from Output delay setting
 480          */
 481         const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
 482                           (1 << 2) | (1 << 1) | (1 << 0);
 483         const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
 484                          SCC_MGR_HHP_GLOBALS_OFFSET |
 485                          SCC_MGR_HHP_EXTRAS_OFFSET;
 486
 487         debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
 488                    __func__, __LINE__);
 489         writel(value, addr);
 490         debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
 491                    __func__, __LINE__);
 492 }
 493
 494 /**
 495  * scc_mgr_zero_all() - Zero all DQS config
 496  *
 497  * Zero all DQS config.
 498  */
 499 static void scc_mgr_zero_all(void)
 500 {
 501         int i, r;
 502
 503         /*
 504          * USER Zero all DQS config settings, across all groups and all
 505          * shadow registers
 506          */
 507         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 508              r += NUM_RANKS_PER_SHADOW_REG) {
 509                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
 510                         /*
 511                          * The phases actually don't exist on a per-rank basis,
 512                          * but there's no harm updating them several times, so
 513                          * let's keep the code simple.
 514                          */
 515                         scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
 516                         scc_mgr_set_dqs_en_phase(i, 0);
 517                         scc_mgr_set_dqs_en_delay(i, 0);
 518                 }
 519
 520                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
 521                         scc_mgr_set_dqdqs_output_phase(i, 0);
 522                         /* Arria V/Cyclone V don't have out2. */
 523                         scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
 524                 }
 525         }
 526
 527         /* Multicast to all DQS group enables. */
 528         writel(0xff, &sdr_scc_mgr->dqs_ena);
 529         writel(0, &sdr_scc_mgr->update);
 530 }
 531
 532 /**
 533  * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
 534  * @write_group:        Write group
 535  *
 536  * Set bypass mode and trigger SCC update.
 537  */
 538 static void scc_set_bypass_mode(const u32 write_group)
 539 {
 540         /* Multicast to all DQ enables. */
 541         writel(0xff, &sdr_scc_mgr->dq_ena);
 542         writel(0xff, &sdr_scc_mgr->dm_ena);
 543
 544         /* Update current DQS IO enable. */
 545         writel(0, &sdr_scc_mgr->dqs_io_ena);
 546
 547         /* Update the DQS logic. */
 548         writel(write_group, &sdr_scc_mgr->dqs_ena);
 549
 550         /* Hit update. */
 551         writel(0, &sdr_scc_mgr->update);
 552 }
 553
 554 /**
 555  * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
 556  * @write_group:        Write group
 557  *
 558  * Load DQS settings for Write Group, do not trigger SCC update.
 559  */
 560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
 561 {
 562         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 563                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 564         const int base = write_group * ratio;
 565         int i;
 566         /*
 567          * Load the setting in the SCC manager
 568          * Although OCT affects only write data, the OCT delay is controlled
 569          * by the DQS logic block which is instantiated once per read group.
 570          * For protocols where a write group consists of multiple read groups,
 571          * the setting must be set multiple times.
 572          */
 573         for (i = 0; i < ratio; i++)
 574                 writel(base + i, &sdr_scc_mgr->dqs_ena);
 575 }
 576
 577 /**
 578  * scc_mgr_zero_group() - Zero all configs for a group
 579  *
 580  * Zero DQ, DM, DQS and OCT configs for a group.
 581  */
 582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
 583 {
 584         int i, r;
 585
 586         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 587              r += NUM_RANKS_PER_SHADOW_REG) {
 588                 /* Zero all DQ config settings. */
 589                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 590                         scc_mgr_set_dq_out1_delay(i, 0);
 591                         if (!out_only)
 592                                 scc_mgr_set_dq_in_delay(i, 0);
 593                 }
 594
 595                 /* Multicast to all DQ enables. */
 596                 writel(0xff, &sdr_scc_mgr->dq_ena);
 597
 598                 /* Zero all DM config settings. */
 599                 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 600                         scc_mgr_set_dm_out1_delay(i, 0);
 601
 602                 /* Multicast to all DM enables. */
 603                 writel(0xff, &sdr_scc_mgr->dm_ena);
 604
 605                 /* Zero all DQS IO settings. */
 606                 if (!out_only)
 607                         scc_mgr_set_dqs_io_in_delay(0);
 608
 609                 /* Arria V/Cyclone V don't have out2. */
 610                 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
 611                 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
 612                 scc_mgr_load_dqs_for_write_group(write_group);
 613
 614                 /* Multicast to all DQS IO enables (only 1 in total). */
 615                 writel(0, &sdr_scc_mgr->dqs_io_ena);
 616
 617                 /* Hit update to zero everything. */
 618                 writel(0, &sdr_scc_mgr->update);
 619         }
 620 }
 621
 622 /*
 623  * apply and load a particular input delay for the DQ pins in a group
 624  * group_bgn is the index of the first dq pin (in the write group)
 625  */
 626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
 627 {
 628         uint32_t i, p;
 629
 630         for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
 631                 scc_mgr_set_dq_in_delay(p, delay);
 632                 scc_mgr_load_dq(p);
 633         }
 634 }
 635
 636 /**
 637  * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
 638  * @delay:              Delay value
 639  *
 640  * Apply and load a particular output delay for the DQ pins in a group.
 641  */
 642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
 643 {
 644         int i;
 645
 646         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 647                 scc_mgr_set_dq_out1_delay(i, delay);
 648                 scc_mgr_load_dq(i);
 649         }
 650 }
 651
 652 /* apply and load a particular output delay for the DM pins in a group */
 653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
 654 {
 655         uint32_t i;
 656
 657         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
 658                 scc_mgr_set_dm_out1_delay(i, delay1);
 659                 scc_mgr_load_dm(i);
 660         }
 661 }
 662
 663
 664 /* apply and load delay on both DQS and OCT out1 */
 665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
 666                                                     uint32_t delay)
 667 {
 668         scc_mgr_set_dqs_out1_delay(delay);
 669         scc_mgr_load_dqs_io();
 670
 671         scc_mgr_set_oct_out1_delay(write_group, delay);
 672         scc_mgr_load_dqs_for_write_group(write_group);
 673 }
 674
 675 /**
 676  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
 677  * @write_group:        Write group
 678  * @delay:              Delay value
 679  *
 680  * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
 681  */
 682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
 683                                                   const u32 delay)
 684 {
 685         u32 i, new_delay;
 686
 687         /* DQ shift */
 688         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
 689                 scc_mgr_load_dq(i);
 690
 691         /* DM shift */
 692         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 693                 scc_mgr_load_dm(i);
 694
 695         /* DQS shift */
 696         new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
 697         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 698                 debug_cond(DLEVEL == 1,
 699                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 700                            __func__, __LINE__, write_group, delay, new_delay,
 701                            IO_IO_OUT2_DELAY_MAX,
 702                            new_delay - IO_IO_OUT2_DELAY_MAX);
 703                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 704                 scc_mgr_set_dqs_out1_delay(new_delay);
 705         }
 706
 707         scc_mgr_load_dqs_io();
 708
 709         /* OCT shift */
 710         new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
 711         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 712                 debug_cond(DLEVEL == 1,
 713                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 714                            __func__, __LINE__, write_group, delay,
 715                            new_delay, IO_IO_OUT2_DELAY_MAX,
 716                            new_delay - IO_IO_OUT2_DELAY_MAX);
 717                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 718                 scc_mgr_set_oct_out1_delay(write_group, new_delay);
 719         }
 720
 721         scc_mgr_load_dqs_for_write_group(write_group);
 722 }
 723
 724 /**
 725  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
 726  * @write_group:        Write group
 727  * @delay:              Delay value
 728  *
 729  * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
 730  */
 731 static void
 732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
 733                                                 const u32 delay)
 734 {
 735         int r;
 736
 737         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 738              r += NUM_RANKS_PER_SHADOW_REG) {
 739                 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
 740                 writel(0, &sdr_scc_mgr->update);
 741         }
 742 }
 743
 744 /**
 745  * set_jump_as_return() - Return instruction optimization
 746  *
 747  * Optimization used to recover some slots in ddr3 inst_rom could be
 748  * applied to other protocols if we wanted to
 749  */
 750 static void set_jump_as_return(void)
 751 {
 752         /*
 753          * To save space, we replace return with jump to special shared
 754          * RETURN instruction so we set the counter to large value so that
 755          * we always jump.
 756          */
 757         writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
 758         writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 759 }
 760
 761 /*
 762  * should always use constants as argument to ensure all computations are
 763  * performed at compile time
 764  */
 765 static void delay_for_n_mem_clocks(const uint32_t clocks)
 766 {
 767         uint32_t afi_clocks;
 768         uint8_t inner = 0;
 769         uint8_t outer = 0;
 770         uint16_t c_loop = 0;
 771
 772         debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
 773
 774
 775         afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
 776         /* scale (rounding up) to get afi clocks */
 777
 778         /*
 779          * Note, we don't bother accounting for being off a little bit
 780          * because of a few extra instructions in outer loops
 781          * Note, the loops have a test at the end, and do the test before
 782          * the decrement, and so always perform the loop
 783          * 1 time more than the counter value
 784          */
 785         if (afi_clocks == 0) {
 786                 ;
 787         } else if (afi_clocks <= 0x100) {
 788                 inner = afi_clocks-1;
 789                 outer = 0;
 790                 c_loop = 0;
 791         } else if (afi_clocks <= 0x10000) {
 792                 inner = 0xff;
 793                 outer = (afi_clocks-1) >> 8;
 794                 c_loop = 0;
 795         } else {
 796                 inner = 0xff;
 797                 outer = 0xff;
 798                 c_loop = (afi_clocks-1) >> 16;
 799         }
 800
 801         /*
 802          * rom instructions are structured as follows:
 803          *
 804          *    IDLE_LOOP2: jnz cntr0, TARGET_A
 805          *    IDLE_LOOP1: jnz cntr1, TARGET_B
 806          *                return
 807          *
 808          * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
 809          * TARGET_B is set to IDLE_LOOP2 as well
 810          *
 811          * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
 812          * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
 813          *
 814          * a little confusing, but it helps save precious space in the inst_rom
 815          * and sequencer rom and keeps the delays more accurate and reduces
 816          * overhead
 817          */
 818         if (afi_clocks <= 0x100) {
 819                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 820                         &sdr_rw_load_mgr_regs->load_cntr1);
 821
 822                 writel(RW_MGR_IDLE_LOOP1,
 823                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 824
 825                 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 826                                           RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 827         } else {
 828                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 829                         &sdr_rw_load_mgr_regs->load_cntr0);
 830
 831                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
 832                         &sdr_rw_load_mgr_regs->load_cntr1);
 833
 834                 writel(RW_MGR_IDLE_LOOP2,
 835                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 836
 837                 writel(RW_MGR_IDLE_LOOP2,
 838                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 839
 840                 /* hack to get around compiler not being smart enough */
 841                 if (afi_clocks <= 0x10000) {
 842                         /* only need to run once */
 843                         writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 844                                                   RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 845                 } else {
 846                         do {
 847                                 writel(RW_MGR_IDLE_LOOP2,
 848                                         SDR_PHYGRP_RWMGRGRP_ADDRESS |
 849                                         RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 850                         } while (c_loop-- != 0);
 851                 }
 852         }
 853         debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
 854 }
 855
 856 /**
 857  * rw_mgr_mem_init_load_regs() - Load instruction registers
 858  * @cntr0:      Counter 0 value
 859  * @cntr1:      Counter 1 value
 860  * @cntr2:      Counter 2 value
 861  * @jump:       Jump instruction value
 862  *
 863  * Load instruction registers.
 864  */
 865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
 866 {
 867         uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 868                            RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 869
 870         /* Load counters */
 871         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
 872                &sdr_rw_load_mgr_regs->load_cntr0);
 873         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
 874                &sdr_rw_load_mgr_regs->load_cntr1);
 875         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
 876                &sdr_rw_load_mgr_regs->load_cntr2);
 877
 878         /* Load jump address */
 879         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 880         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 881         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
 882
 883         /* Execute count instruction */
 884         writel(jump, grpaddr);
 885 }
 886
 887 /**
 888  * rw_mgr_mem_load_user() - Load user calibration values
 889  * @fin1:       Final instruction 1
 890  * @fin2:       Final instruction 2
 891  * @precharge:  If 1, precharge the banks at the end
 892  *
 893  * Load user calibration values and optionally precharge the banks.
 894  */
 895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
 896                                  const int precharge)
 897 {
 898         u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 899                       RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 900         u32 r;
 901
 902         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
 903                 if (param->skip_ranks[r]) {
 904                         /* request to skip the rank */
 905                         continue;
 906                 }
 907
 908                 /* set rank */
 909                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
 910
 911                 /* precharge all banks ... */
 912                 if (precharge)
 913                         writel(RW_MGR_PRECHARGE_ALL, grpaddr);
 914
 915                 /*
 916                  * USER Use Mirror-ed commands for odd ranks if address
 917                  * mirrorring is on
 918                  */
 919                 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
 920                         set_jump_as_return();
 921                         writel(RW_MGR_MRS2_MIRR, grpaddr);
 922                         delay_for_n_mem_clocks(4);
 923                         set_jump_as_return();
 924                         writel(RW_MGR_MRS3_MIRR, grpaddr);
 925                         delay_for_n_mem_clocks(4);
 926                         set_jump_as_return();
 927                         writel(RW_MGR_MRS1_MIRR, grpaddr);
 928                         delay_for_n_mem_clocks(4);
 929                         set_jump_as_return();
 930                         writel(fin1, grpaddr);
 931                 } else {
 932                         set_jump_as_return();
 933                         writel(RW_MGR_MRS2, grpaddr);
 934                         delay_for_n_mem_clocks(4);
 935                         set_jump_as_return();
 936                         writel(RW_MGR_MRS3, grpaddr);
 937                         delay_for_n_mem_clocks(4);
 938                         set_jump_as_return();
 939                         writel(RW_MGR_MRS1, grpaddr);
 940                         set_jump_as_return();
 941                         writel(fin2, grpaddr);
 942                 }
 943
 944                 if (precharge)
 945                         continue;
 946
 947                 set_jump_as_return();
 948                 writel(RW_MGR_ZQCL, grpaddr);
 949
 950                 /* tZQinit = tDLLK = 512 ck cycles */
 951                 delay_for_n_mem_clocks(512);
 952         }
 953 }
 954
 955 /**
 956  * rw_mgr_mem_initialize() - Initialize RW Manager
 957  *
 958  * Initialize RW Manager.
 959  */
 960 static void rw_mgr_mem_initialize(void)
 961 {
 962         debug("%s:%d\n", __func__, __LINE__);
 963
 964         /* The reset / cke part of initialization is broadcasted to all ranks */
 965         writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 966                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 967
 968         /*
 969          * Here's how you load register for a loop
 970          * Counters are located @ 0x800
 971          * Jump address are located @ 0xC00
 972          * For both, registers 0 to 3 are selected using bits 3 and 2, like
 973          * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
 974          * I know this ain't pretty, but Avalon bus throws away the 2 least
 975          * significant bits
 976          */
 977
 978         /* Start with memory RESET activated */
 979
 980         /* tINIT = 200us */
 981
 982         /*
 983          * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
 984          * If a and b are the number of iteration in 2 nested loops
 985          * it takes the following number of cycles to complete the operation:
 986          * number_of_cycles = ((2 + n) * a + 2) * b
 987          * where n is the number of instruction in the inner loop
 988          * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
 989          * b = 6A
 990          */
 991         rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
 992                                   SEQ_TINIT_CNTR2_VAL,
 993                                   RW_MGR_INIT_RESET_0_CKE_0);
 994
 995         /* Indicate that memory is stable. */
 996         writel(1, &phy_mgr_cfg->reset_mem_stbl);
 997
 998         /*
 999          * transition the RESET to high
1000          * Wait for 500us
1001          */
1002
1003         /*
1004          * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005          * If a and b are the number of iteration in 2 nested loops
1006          * it takes the following number of cycles to complete the operation
1007          * number_of_cycles = ((2 + n) * a + 2) * b
1008          * where n is the number of instruction in the inner loop
1009          * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1010          * b = FF
1011          */
1012         rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013                                   SEQ_TRESET_CNTR2_VAL,
1014                                   RW_MGR_INIT_RESET_1_CKE_0);
1015
1016         /* Bring up clock enable. */
1017
1018         /* tXRP < 250 ck cycles */
1019         delay_for_n_mem_clocks(250);
1020
1021         rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1022                              0);
1023 }
1024
1025 /*
1026  * At the end of calibration we have to program the user settings in, and
1027  * USER  hand off the memory to the user.
1028  */
1029 static void rw_mgr_mem_handoff(void)
1030 {
1031         rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1032         /*
1033          * USER  need to wait tMOD (12CK or 15ns) time before issuing
1034          * other commands, but we will have plenty of NIOS cycles before
1035          * actual handoff so its okay.
1036          */
1037 }
1038
1039 /**
1040  * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041  * @rank_bgn:   Rank number
1042  * @group:      Read/Write Group
1043  * @all_ranks:  Test all ranks
1044  *
1045  * Performs a guaranteed read on the patterns we are going to use during a
1046  * read test to ensure memory works.
1047  */
1048 static int
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050                                         const u32 all_ranks)
1051 {
1052         const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053                          RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054         const u32 addr_offset =
1055                          (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056         const u32 rank_end = all_ranks ?
1057                                 RW_MGR_MEM_NUMBER_OF_RANKS :
1058                                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059         const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061         const u32 correct_mask_vg = param->read_correct_mask_vg;
1062
1063         u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1064         int vg, r;
1065         int ret = 0;
1066
1067         bit_chk = param->read_correct_mask;
1068
1069         for (r = rank_bgn; r < rank_end; r++) {
1070                 /* Request to skip the rank */
1071                 if (param->skip_ranks[r])
1072                         continue;
1073
1074                 /* Set rank */
1075                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1076
1077                 /* Load up a constant bursts of read commands */
1078                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079                 writel(RW_MGR_GUARANTEED_READ,
1080                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1081
1082                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083                 writel(RW_MGR_GUARANTEED_READ_CONT,
1084                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1085
1086                 tmp_bit_chk = 0;
1087                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1088                      vg >= 0; vg--) {
1089                         /* Reset the FIFOs to get pointers to known state. */
1090                         writel(0, &phy_mgr_cmd->fifo_reset);
1091                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1093                         writel(RW_MGR_GUARANTEED_READ,
1094                                addr + addr_offset + (vg << 2));
1095
1096                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1097                         tmp_bit_chk <<= shift_ratio;
1098                         tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1099                 }
1100
1101                 bit_chk &= tmp_bit_chk;
1102         }
1103
1104         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1105
1106         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1107
1108         if (bit_chk != param->read_correct_mask)
1109                 ret = -EIO;
1110
1111         debug_cond(DLEVEL == 1,
1112                    "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113                    __func__, __LINE__, group, bit_chk,
1114                    param->read_correct_mask, ret);
1115
1116         return ret;
1117 }
1118
1119 /**
1120  * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121  * @rank_bgn:   Rank number
1122  * @all_ranks:  Test all ranks
1123  *
1124  * Load up the patterns we are going to use during a read test.
1125  */
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127                                                     const int all_ranks)
1128 {
1129         const u32 rank_end = all_ranks ?
1130                         RW_MGR_MEM_NUMBER_OF_RANKS :
1131                         (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1132         u32 r;
1133
1134         debug("%s:%d\n", __func__, __LINE__);
1135
1136         for (r = rank_bgn; r < rank_end; r++) {
1137                 if (param->skip_ranks[r])
1138                         /* request to skip the rank */
1139                         continue;
1140
1141                 /* set rank */
1142                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1143
1144                 /* Load up a constant bursts */
1145                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1146
1147                 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1149
1150                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1151
1152                 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1154
1155                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1156
1157                 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1159
1160                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1161
1162                 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1164
1165                 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1167         }
1168
1169         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1170 }
1171
1172 /*
1173  * try a read and see if it returns correct data back. has dummy reads
1174  * inserted into the mix used to align dqs enable. has more thorough checks
1175  * than the regular read test.
1176  */
1177 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1178         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1179         uint32_t all_groups, uint32_t all_ranks)
1180 {
1181         uint32_t r, vg;
1182         uint32_t correct_mask_vg;
1183         uint32_t tmp_bit_chk;
1184         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1185                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1186         uint32_t addr;
1187         uint32_t base_rw_mgr;
1188
1189         *bit_chk = param->read_correct_mask;
1190         correct_mask_vg = param->read_correct_mask_vg;
1191
1192         uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1193                 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1194
1195         for (r = rank_bgn; r < rank_end; r++) {
1196                 if (param->skip_ranks[r])
1197                         /* request to skip the rank */
1198                         continue;
1199
1200                 /* set rank */
1201                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1202
1203                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1204
1205                 writel(RW_MGR_READ_B2B_WAIT1,
1206                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1207
1208                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1209                 writel(RW_MGR_READ_B2B_WAIT2,
1210                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1211
1212                 if (quick_read_mode)
1213                         writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1214                         /* need at least two (1+1) reads to capture failures */
1215                 else if (all_groups)
1216                         writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1217                 else
1218                         writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1219
1220                 writel(RW_MGR_READ_B2B,
1221                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1222                 if (all_groups)
1223                         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1224                                RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1225                                &sdr_rw_load_mgr_regs->load_cntr3);
1226                 else
1227                         writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1228
1229                 writel(RW_MGR_READ_B2B,
1230                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1231
1232                 tmp_bit_chk = 0;
1233                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1234                         /* reset the fifos to get pointers to known state */
1235                         writel(0, &phy_mgr_cmd->fifo_reset);
1236                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1237                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1238
1239                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1240                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1241
1242                         if (all_groups)
1243                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1244                         else
1245                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1246
1247                         writel(RW_MGR_READ_B2B, addr +
1248                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1249                                vg) << 2));
1250
1251                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1252                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1253
1254                         if (vg == 0)
1255                                 break;
1256                 }
1257                 *bit_chk &= tmp_bit_chk;
1258         }
1259
1260         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1261         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1262
1263         if (all_correct) {
1264                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1265                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1266                            (%u == %u) => %lu", __func__, __LINE__, group,
1267                            all_groups, *bit_chk, param->read_correct_mask,
1268                            (long unsigned int)(*bit_chk ==
1269                            param->read_correct_mask));
1270                 return *bit_chk == param->read_correct_mask;
1271         } else  {
1272                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1273                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1274                            (%u != %lu) => %lu\n", __func__, __LINE__,
1275                            group, all_groups, *bit_chk, (long unsigned int)0,
1276                            (long unsigned int)(*bit_chk != 0x00));
1277                 return *bit_chk != 0x00;
1278         }
1279 }
1280
1281 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1282         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1283         uint32_t all_groups)
1284 {
1285         return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1286                                               bit_chk, all_groups, 1);
1287 }
1288
1289 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1290 {
1291         writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1292         (*v)++;
1293 }
1294
1295 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1296 {
1297         uint32_t i;
1298
1299         for (i = 0; i < VFIFO_SIZE-1; i++)
1300                 rw_mgr_incr_vfifo(grp, v);
1301 }
1302
1303 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1304 {
1305         uint32_t  v;
1306         uint32_t fail_cnt = 0;
1307         uint32_t test_status;
1308
1309         for (v = 0; v < VFIFO_SIZE; ) {
1310                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1311                            __func__, __LINE__, v);
1312                 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1313                         (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1314                 if (!test_status) {
1315                         fail_cnt++;
1316
1317                         if (fail_cnt == 2)
1318                                 break;
1319                 }
1320
1321                 /* fiddle with FIFO */
1322                 rw_mgr_incr_vfifo(grp, &v);
1323         }
1324
1325         if (v >= VFIFO_SIZE) {
1326                 /* no failing read found!! Something must have gone wrong */
1327                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1328                            __func__, __LINE__);
1329                 return 0;
1330         } else {
1331                 return v;
1332         }
1333 }
1334
1335 static int sdr_working_phase(uint32_t *grp, uint32_t *bit_chk,
1336                               uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1337                               uint32_t *v, uint32_t *d, uint32_t *p,
1338                               uint32_t *i, uint32_t *max_working_cnt)
1339 {
1340         uint32_t found_begin = 0;
1341         uint32_t tmp_delay = 0;
1342         uint32_t test_status;
1343
1344         for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1345                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1346                 *work_bgn = tmp_delay;
1347                 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1348
1349                 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1350                         for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1351                                 IO_DELAY_PER_OPA_TAP) {
1352                                 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1353
1354                                 test_status =
1355                                 rw_mgr_mem_calibrate_read_test_all_ranks
1356                                 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1357
1358                                 if (test_status) {
1359                                         *max_working_cnt = 1;
1360                                         found_begin = 1;
1361                                         break;
1362                                 }
1363                         }
1364
1365                         if (found_begin)
1366                                 break;
1367
1368                         if (*p > IO_DQS_EN_PHASE_MAX)
1369                                 /* fiddle with FIFO */
1370                                 rw_mgr_incr_vfifo(*grp, v);
1371                 }
1372
1373                 if (found_begin)
1374                         break;
1375         }
1376
1377         if (*i >= VFIFO_SIZE) {
1378                 /* cannot find working solution */
1379                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1380                            ptap/dtap\n", __func__, __LINE__);
1381                 return 0;
1382         } else {
1383                 return 1;
1384         }
1385 }
1386
1387 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1388                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1389                              uint32_t *p, uint32_t *max_working_cnt)
1390 {
1391         uint32_t found_begin = 0;
1392         uint32_t tmp_delay;
1393
1394         /* Special case code for backing up a phase */
1395         if (*p == 0) {
1396                 *p = IO_DQS_EN_PHASE_MAX;
1397                 rw_mgr_decr_vfifo(*grp, v);
1398         } else {
1399                 (*p)--;
1400         }
1401         tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1402         scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1403
1404         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1405                 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1406                 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1407
1408                 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1409                                                              PASS_ONE_BIT,
1410                                                              bit_chk, 0)) {
1411                         found_begin = 1;
1412                         *work_bgn = tmp_delay;
1413                         break;
1414                 }
1415         }
1416
1417         /* We have found a working dtap before the ptap found above */
1418         if (found_begin == 1)
1419                 (*max_working_cnt)++;
1420
1421         /*
1422          * Restore VFIFO to old state before we decremented it
1423          * (if needed).
1424          */
1425         (*p)++;
1426         if (*p > IO_DQS_EN_PHASE_MAX) {
1427                 *p = 0;
1428                 rw_mgr_incr_vfifo(*grp, v);
1429         }
1430
1431         scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1432 }
1433
1434 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1435                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1436                              uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1437                              uint32_t *work_end)
1438 {
1439         uint32_t found_end = 0;
1440
1441         (*p)++;
1442         *work_end += IO_DELAY_PER_OPA_TAP;
1443         if (*p > IO_DQS_EN_PHASE_MAX) {
1444                 /* fiddle with FIFO */
1445                 *p = 0;
1446                 rw_mgr_incr_vfifo(*grp, v);
1447         }
1448
1449         for (; *i < VFIFO_SIZE + 1; (*i)++) {
1450                 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1451                         += IO_DELAY_PER_OPA_TAP) {
1452                         scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1453
1454                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1455                                 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1456                                 found_end = 1;
1457                                 break;
1458                         } else {
1459                                 (*max_working_cnt)++;
1460                         }
1461                 }
1462
1463                 if (found_end)
1464                         break;
1465
1466                 if (*p > IO_DQS_EN_PHASE_MAX) {
1467                         /* fiddle with FIFO */
1468                         rw_mgr_incr_vfifo(*grp, v);
1469                         *p = 0;
1470                 }
1471         }
1472
1473         if (*i >= VFIFO_SIZE + 1) {
1474                 /* cannot see edge of failing read */
1475                 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1476                            failed\n", __func__, __LINE__);
1477                 return 0;
1478         } else {
1479                 return 1;
1480         }
1481 }
1482
1483 /**
1484  * sdr_find_window_center() - Find center of the working DQS window.
1485  * @grp:        Read/Write group
1486  * @work_bgn:   First working settings
1487  * @work_end:   Last working settings
1488  * @val:        VFIFO value
1489  *
1490  * Find center of the working DQS enable window.
1491  */
1492 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1493                                   const u32 work_end, const u32 val)
1494 {
1495         u32 bit_chk, work_mid, v = val;
1496         int tmp_delay = 0;
1497         int i, p, d;
1498
1499         work_mid = (work_bgn + work_end) / 2;
1500
1501         debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1502                    work_bgn, work_end, work_mid);
1503         /* Get the middle delay to be less than a VFIFO delay */
1504         tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1505
1506         debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1507         work_mid %= tmp_delay;
1508         debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1509
1510         tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1511         if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1512                 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1513         p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1514
1515         debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1516
1517         d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1518         if (d > IO_DQS_EN_DELAY_MAX)
1519                 d = IO_DQS_EN_DELAY_MAX;
1520         tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1521
1522         debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1523
1524         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1525         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1526
1527         /*
1528          * push vfifo until we can successfully calibrate. We can do this
1529          * because the largest possible margin in 1 VFIFO cycle.
1530          */
1531         for (i = 0; i < VFIFO_SIZE; i++) {
1532                 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1533                            v);
1534                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1535                                                              PASS_ONE_BIT,
1536                                                              &bit_chk, 0)) {
1537                         debug_cond(DLEVEL == 2,
1538                                    "%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n",
1539                                    __func__, __LINE__, v, p, d);
1540                         return 0;
1541                 }
1542
1543                 /* Fiddle with FIFO. */
1544                 rw_mgr_incr_vfifo(grp, &v);
1545         }
1546
1547         debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1548                    __func__, __LINE__);
1549         return -EINVAL;
1550 }
1551
1552 /* find a good dqs enable to use */
1553 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1554 {
1555         uint32_t v, d, p, i;
1556         uint32_t max_working_cnt;
1557         uint32_t bit_chk;
1558         uint32_t dtaps_per_ptap;
1559         uint32_t work_bgn, work_end;
1560         uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1561
1562         debug("%s:%d %u\n", __func__, __LINE__, grp);
1563
1564         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1565
1566         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1567         scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1568
1569         /* ************************************************************** */
1570         /* * Step 0 : Determine number of delay taps for each phase tap * */
1571         dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1572
1573         /* ********************************************************* */
1574         /* * Step 1 : First push vfifo until we get a failing read * */
1575         v = find_vfifo_read(grp, &bit_chk);
1576
1577         max_working_cnt = 0;
1578
1579         /* ******************************************************** */
1580         /* * step 2: find first working phase, increment in ptaps * */
1581         work_bgn = 0;
1582         if (sdr_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1583                               &p, &i, &max_working_cnt) == 0)
1584                 return 0;
1585
1586         work_end = work_bgn;
1587
1588         /*
1589          * If d is 0 then the working window covers a phase tap and
1590          * we can follow the old procedure otherwise, we've found the beginning,
1591          * and we need to increment the dtaps until we find the end.
1592          */
1593         if (d == 0) {
1594                 /* ********************************************************* */
1595                 /* * step 3a: if we have room, back off by one and
1596                 increment in dtaps * */
1597
1598                 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1599                                  &max_working_cnt);
1600
1601                 /* ********************************************************* */
1602                 /* * step 4a: go forward from working phase to non working
1603                 phase, increment in ptaps * */
1604                 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1605                                          &i, &max_working_cnt, &work_end) == 0)
1606                         return 0;
1607
1608                 /* ********************************************************* */
1609                 /* * step 5a:  back off one from last, increment in dtaps  * */
1610
1611                 /* Special case code for backing up a phase */
1612                 if (p == 0) {
1613                         p = IO_DQS_EN_PHASE_MAX;
1614                         rw_mgr_decr_vfifo(grp, &v);
1615                 } else {
1616                         p = p - 1;
1617                 }
1618
1619                 work_end -= IO_DELAY_PER_OPA_TAP;
1620                 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1621
1622                 /* * The actual increment of dtaps is done outside of
1623                 the if/else loop to share code */
1624                 d = 0;
1625
1626                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1627                            vfifo=%u ptap=%u\n", __func__, __LINE__,
1628                            v, p);
1629         } else {
1630                 /* ******************************************************* */
1631                 /* * step 3-5b:  Find the right edge of the window using
1632                 delay taps   * */
1633                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1634                            ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1635                            v, p, d, work_bgn);
1636
1637                 work_end = work_bgn;
1638
1639                 /* * The actual increment of dtaps is done outside of the
1640                 if/else loop to share code */
1641
1642                 /* Only here to counterbalance a subtract later on which is
1643                 not needed if this branch of the algorithm is taken */
1644                 max_working_cnt++;
1645         }
1646
1647         /* The dtap increment to find the failing edge is done here */
1648         for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1649                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1650                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1651                                    end-2: dtap=%u\n", __func__, __LINE__, d);
1652                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1653
1654                         if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1655                                                                       PASS_ONE_BIT,
1656                                                                       &bit_chk, 0)) {
1657                                 break;
1658                         }
1659         }
1660
1661         /* Go back to working dtap */
1662         if (d != 0)
1663                 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1664
1665         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1666                    ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1667                    v, p, d-1, work_end);
1668
1669         if (work_end < work_bgn) {
1670                 /* nil range */
1671                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1672                            failed\n", __func__, __LINE__);
1673                 return 0;
1674         }
1675
1676         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1677                    __func__, __LINE__, work_bgn, work_end);
1678
1679         /* *************************************************************** */
1680         /*
1681          * * We need to calculate the number of dtaps that equal a ptap
1682          * * To do that we'll back up a ptap and re-find the edge of the
1683          * * window using dtaps
1684          */
1685
1686         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1687                    for tracking\n", __func__, __LINE__);
1688
1689         /* Special case code for backing up a phase */
1690         if (p == 0) {
1691                 p = IO_DQS_EN_PHASE_MAX;
1692                 rw_mgr_decr_vfifo(grp, &v);
1693                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1694                            cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1695                            v, p);
1696         } else {
1697                 p = p - 1;
1698                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1699                            phase only: v=%u p=%u", __func__, __LINE__,
1700                            v, p);
1701         }
1702
1703         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1704
1705         /*
1706          * Increase dtap until we first see a passing read (in case the
1707          * window is smaller than a ptap),
1708          * and then a failing read to mark the edge of the window again
1709          */
1710
1711         /* Find a passing read */
1712         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1713                    __func__, __LINE__);
1714         found_passing_read = 0;
1715         found_failing_read = 0;
1716         initial_failing_dtap = d;
1717         for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1718                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1719                            read d=%u\n", __func__, __LINE__, d);
1720                 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1721
1722                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1723                                                              PASS_ONE_BIT,
1724                                                              &bit_chk, 0)) {
1725                         found_passing_read = 1;
1726                         break;
1727                 }
1728         }
1729
1730         if (found_passing_read) {
1731                 /* Find a failing read */
1732                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1733                            read\n", __func__, __LINE__);
1734                 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1735                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1736                                    testing read d=%u\n", __func__, __LINE__, d);
1737                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1738
1739                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1740                                 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1741                                 found_failing_read = 1;
1742                                 break;
1743                         }
1744                 }
1745         } else {
1746                 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1747                            calculate dtaps", __func__, __LINE__);
1748                 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1749         }
1750
1751         /*
1752          * The dynamically calculated dtaps_per_ptap is only valid if we
1753          * found a passing/failing read. If we didn't, it means d hit the max
1754          * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1755          * statically calculated value.
1756          */
1757         if (found_passing_read && found_failing_read)
1758                 dtaps_per_ptap = d - initial_failing_dtap;
1759
1760         writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1761         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1762                    - %u = %u",  __func__, __LINE__, d,
1763                    initial_failing_dtap, dtaps_per_ptap);
1764
1765         /* ******************************************** */
1766         /* * step 6:  Find the centre of the window   * */
1767         if (sdr_find_window_centre(grp, work_bgn, work_end, v))
1768                 return 0; /* FIXME: Old code, return 0 means failure :-( */
1769
1770         return 1;
1771 }
1772
1773 /* per-bit deskew DQ and center */
1774 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1775         uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1776         uint32_t use_read_test, uint32_t update_fom)
1777 {
1778         uint32_t i, p, d, min_index;
1779         /*
1780          * Store these as signed since there are comparisons with
1781          * signed numbers.
1782          */
1783         uint32_t bit_chk;
1784         uint32_t sticky_bit_chk;
1785         int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1786         int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1787         int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1788         int32_t mid;
1789         int32_t orig_mid_min, mid_min;
1790         int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1791                 final_dqs_en;
1792         int32_t dq_margin, dqs_margin;
1793         uint32_t stop;
1794         uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1795         uint32_t addr;
1796
1797         debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1798
1799         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1800         start_dqs = readl(addr + (read_group << 2));
1801         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1802                 start_dqs_en = readl(addr + ((read_group << 2)
1803                                      - IO_DQS_EN_DELAY_OFFSET));
1804
1805         /* set the left and right edge of each bit to an illegal value */
1806         /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1807         sticky_bit_chk = 0;
1808         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1809                 left_edge[i]  = IO_IO_IN_DELAY_MAX + 1;
1810                 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1811         }
1812
1813         /* Search for the left edge of the window for each bit */
1814         for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1815                 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1816
1817                 writel(0, &sdr_scc_mgr->update);
1818
1819                 /*
1820                  * Stop searching when the read test doesn't pass AND when
1821                  * we've seen a passing read on every bit.
1822                  */
1823                 if (use_read_test) {
1824                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1825                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1826                                 &bit_chk, 0, 0);
1827                 } else {
1828                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1829                                                         0, PASS_ONE_BIT,
1830                                                         &bit_chk, 0);
1831                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1832                                 (read_group - (write_group *
1833                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1834                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1835                         stop = (bit_chk == 0);
1836                 }
1837                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1838                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1839                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1840                            && %u", __func__, __LINE__, d,
1841                            sticky_bit_chk,
1842                         param->read_correct_mask, stop);
1843
1844                 if (stop == 1) {
1845                         break;
1846                 } else {
1847                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1848                                 if (bit_chk & 1) {
1849                                         /* Remember a passing test as the
1850                                         left_edge */
1851                                         left_edge[i] = d;
1852                                 } else {
1853                                         /* If a left edge has not been seen yet,
1854                                         then a future passing test will mark
1855                                         this edge as the right edge */
1856                                         if (left_edge[i] ==
1857                                                 IO_IO_IN_DELAY_MAX + 1) {
1858                                                 right_edge[i] = -(d + 1);
1859                                         }
1860                                 }
1861                                 bit_chk = bit_chk >> 1;
1862                         }
1863                 }
1864         }
1865
1866         /* Reset DQ delay chains to 0 */
1867         scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1868         sticky_bit_chk = 0;
1869         for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1870                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1871                            %d right_edge[%u]: %d\n", __func__, __LINE__,
1872                            i, left_edge[i], i, right_edge[i]);
1873
1874                 /*
1875                  * Check for cases where we haven't found the left edge,
1876                  * which makes our assignment of the the right edge invalid.
1877                  * Reset it to the illegal value.
1878                  */
1879                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1880                         right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1881                         right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1882                         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1883                                    right_edge[%u]: %d\n", __func__, __LINE__,
1884                                    i, right_edge[i]);
1885                 }
1886
1887                 /*
1888                  * Reset sticky bit (except for bits where we have seen
1889                  * both the left and right edge).
1890                  */
1891                 sticky_bit_chk = sticky_bit_chk << 1;
1892                 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1893                     (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1894                         sticky_bit_chk = sticky_bit_chk | 1;
1895                 }
1896
1897                 if (i == 0)
1898                         break;
1899         }
1900
1901         /* Search for the right edge of the window for each bit */
1902         for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1903                 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1904                 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1905                         uint32_t delay = d + start_dqs_en;
1906                         if (delay > IO_DQS_EN_DELAY_MAX)
1907                                 delay = IO_DQS_EN_DELAY_MAX;
1908                         scc_mgr_set_dqs_en_delay(read_group, delay);
1909                 }
1910                 scc_mgr_load_dqs(read_group);
1911
1912                 writel(0, &sdr_scc_mgr->update);
1913
1914                 /*
1915                  * Stop searching when the read test doesn't pass AND when
1916                  * we've seen a passing read on every bit.
1917                  */
1918                 if (use_read_test) {
1919                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1920                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1921                                 &bit_chk, 0, 0);
1922                 } else {
1923                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1924                                                         0, PASS_ONE_BIT,
1925                                                         &bit_chk, 0);
1926                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1927                                 (read_group - (write_group *
1928                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1929                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1930                         stop = (bit_chk == 0);
1931                 }
1932                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1933                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1934
1935                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1936                            %u && %u", __func__, __LINE__, d,
1937                            sticky_bit_chk, param->read_correct_mask, stop);
1938
1939                 if (stop == 1) {
1940                         break;
1941                 } else {
1942                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1943                                 if (bit_chk & 1) {
1944                                         /* Remember a passing test as
1945                                         the right_edge */
1946                                         right_edge[i] = d;
1947                                 } else {
1948                                         if (d != 0) {
1949                                                 /* If a right edge has not been
1950                                                 seen yet, then a future passing
1951                                                 test will mark this edge as the
1952                                                 left edge */
1953                                                 if (right_edge[i] ==
1954                                                 IO_IO_IN_DELAY_MAX + 1) {
1955                                                         left_edge[i] = -(d + 1);
1956                                                 }
1957                                         } else {
1958                                                 /* d = 0 failed, but it passed
1959                                                 when testing the left edge,
1960                                                 so it must be marginal,
1961                                                 set it to -1 */
1962                                                 if (right_edge[i] ==
1963                                                         IO_IO_IN_DELAY_MAX + 1 &&
1964                                                         left_edge[i] !=
1965                                                         IO_IO_IN_DELAY_MAX
1966                                                         + 1) {
1967                                                         right_edge[i] = -1;
1968                                                 }
1969                                                 /* If a right edge has not been
1970                                                 seen yet, then a future passing
1971                                                 test will mark this edge as the
1972                                                 left edge */
1973                                                 else if (right_edge[i] ==
1974                                                         IO_IO_IN_DELAY_MAX +
1975                                                         1) {
1976                                                         left_edge[i] = -(d + 1);
1977                                                 }
1978                                         }
1979                                 }
1980
1981                                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
1982                                            d=%u]: ", __func__, __LINE__, d);
1983                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
1984                                            (int)(bit_chk & 1), i, left_edge[i]);
1985                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
1986                                            right_edge[i]);
1987                                 bit_chk = bit_chk >> 1;
1988                         }
1989                 }
1990         }
1991
1992         /* Check that all bits have a window */
1993         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1994                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1995                            %d right_edge[%u]: %d", __func__, __LINE__,
1996                            i, left_edge[i], i, right_edge[i]);
1997                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
1998                         == IO_IO_IN_DELAY_MAX + 1)) {
1999                         /*
2000                          * Restore delay chain settings before letting the loop
2001                          * in rw_mgr_mem_calibrate_vfifo to retry different
2002                          * dqs/ck relationships.
2003                          */
2004                         scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2005                         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2006                                 scc_mgr_set_dqs_en_delay(read_group,
2007                                                          start_dqs_en);
2008                         }
2009                         scc_mgr_load_dqs(read_group);
2010                         writel(0, &sdr_scc_mgr->update);
2011
2012                         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2013                                    find edge [%u]: %d %d", __func__, __LINE__,
2014                                    i, left_edge[i], right_edge[i]);
2015                         if (use_read_test) {
2016                                 set_failing_group_stage(read_group *
2017                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2018                                         CAL_STAGE_VFIFO,
2019                                         CAL_SUBSTAGE_VFIFO_CENTER);
2020                         } else {
2021                                 set_failing_group_stage(read_group *
2022                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2023                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2024                                         CAL_SUBSTAGE_VFIFO_CENTER);
2025                         }
2026                         return 0;
2027                 }
2028         }
2029
2030         /* Find middle of window for each DQ bit */
2031         mid_min = left_edge[0] - right_edge[0];
2032         min_index = 0;
2033         for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2034                 mid = left_edge[i] - right_edge[i];
2035                 if (mid < mid_min) {
2036                         mid_min = mid;
2037                         min_index = i;
2038                 }
2039         }
2040
2041         /*
2042          * -mid_min/2 represents the amount that we need to move DQS.
2043          * If mid_min is odd and positive we'll need to add one to
2044          * make sure the rounding in further calculations is correct
2045          * (always bias to the right), so just add 1 for all positive values.
2046          */
2047         if (mid_min > 0)
2048                 mid_min++;
2049
2050         mid_min = mid_min / 2;
2051
2052         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2053                    __func__, __LINE__, mid_min, min_index);
2054
2055         /* Determine the amount we can change DQS (which is -mid_min) */
2056         orig_mid_min = mid_min;
2057         new_dqs = start_dqs - mid_min;
2058         if (new_dqs > IO_DQS_IN_DELAY_MAX)
2059                 new_dqs = IO_DQS_IN_DELAY_MAX;
2060         else if (new_dqs < 0)
2061                 new_dqs = 0;
2062
2063         mid_min = start_dqs - new_dqs;
2064         debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2065                    mid_min, new_dqs);
2066
2067         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2068                 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2069                         mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2070                 else if (start_dqs_en - mid_min < 0)
2071                         mid_min += start_dqs_en - mid_min;
2072         }
2073         new_dqs = start_dqs - mid_min;
2074
2075         debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2076                    new_dqs=%d mid_min=%d\n", start_dqs,
2077                    IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2078                    new_dqs, mid_min);
2079
2080         /* Initialize data for export structures */
2081         dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2082         dq_margin  = IO_IO_IN_DELAY_MAX + 1;
2083
2084         /* add delay to bring centre of all DQ windows to the same "level" */
2085         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2086                 /* Use values before divide by 2 to reduce round off error */
2087                 shift_dq = (left_edge[i] - right_edge[i] -
2088                         (left_edge[min_index] - right_edge[min_index]))/2  +
2089                         (orig_mid_min - mid_min);
2090
2091                 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2092                            shift_dq[%u]=%d\n", i, shift_dq);
2093
2094                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2095                 temp_dq_in_delay1 = readl(addr + (p << 2));
2096                 temp_dq_in_delay2 = readl(addr + (i << 2));
2097
2098                 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2099                         (int32_t)IO_IO_IN_DELAY_MAX) {
2100                         shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2101                 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2102                         shift_dq = -(int32_t)temp_dq_in_delay1;
2103                 }
2104                 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2105                            shift_dq[%u]=%d\n", i, shift_dq);
2106                 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2107                 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2108                 scc_mgr_load_dq(p);
2109
2110                 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2111                            left_edge[i] - shift_dq + (-mid_min),
2112                            right_edge[i] + shift_dq - (-mid_min));
2113                 /* To determine values for export structures */
2114                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2115                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2116
2117                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2118                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2119         }
2120
2121         final_dqs = new_dqs;
2122         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2123                 final_dqs_en = start_dqs_en - mid_min;
2124
2125         /* Move DQS-en */
2126         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2127                 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2128                 scc_mgr_load_dqs(read_group);
2129         }
2130
2131         /* Move DQS */
2132         scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2133         scc_mgr_load_dqs(read_group);
2134         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2135                    dqs_margin=%d", __func__, __LINE__,
2136                    dq_margin, dqs_margin);
2137
2138         /*
2139          * Do not remove this line as it makes sure all of our decisions
2140          * have been applied. Apply the update bit.
2141          */
2142         writel(0, &sdr_scc_mgr->update);
2143
2144         return (dq_margin >= 0) && (dqs_margin >= 0);
2145 }
2146
2147 /**
2148  * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2149  * @rw_group:   Read/Write Group
2150  * @phase:      DQ/DQS phase
2151  *
2152  * Because initially no communication ca be reliably performed with the memory
2153  * device, the sequencer uses a guaranteed write mechanism to write data into
2154  * the memory device.
2155  */
2156 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2157                                                  const u32 phase)
2158 {
2159         int ret;
2160
2161         /* Set a particular DQ/DQS phase. */
2162         scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2163
2164         debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2165                    __func__, __LINE__, rw_group, phase);
2166
2167         /*
2168          * Altera EMI_RM 2015.05.04 :: Figure 1-25
2169          * Load up the patterns used by read calibration using the
2170          * current DQDQS phase.
2171          */
2172         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2173
2174         if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2175                 return 0;
2176
2177         /*
2178          * Altera EMI_RM 2015.05.04 :: Figure 1-26
2179          * Back-to-Back reads of the patterns used for calibration.
2180          */
2181         ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2182         if (ret)
2183                 debug_cond(DLEVEL == 1,
2184                            "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2185                            __func__, __LINE__, rw_group, phase);
2186         return ret;
2187 }
2188
2189 /**
2190  * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2191  * @rw_group:   Read/Write Group
2192  * @test_bgn:   Rank at which the test begins
2193  *
2194  * DQS enable calibration ensures reliable capture of the DQ signal without
2195  * glitches on the DQS line.
2196  */
2197 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2198                                                        const u32 test_bgn)
2199 {
2200         /*
2201          * Altera EMI_RM 2015.05.04 :: Figure 1-27
2202          * DQS and DQS Eanble Signal Relationships.
2203          */
2204
2205         /* We start at zero, so have one less dq to devide among */
2206         const u32 delay_step = IO_IO_IN_DELAY_MAX /
2207                                (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2208         int found;
2209         u32 i, p, d, r;
2210
2211         debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2212
2213         /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2214         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2215              r += NUM_RANKS_PER_SHADOW_REG) {
2216                 for (i = 0, p = test_bgn, d = 0;
2217                      i < RW_MGR_MEM_DQ_PER_READ_DQS;
2218                      i++, p++, d += delay_step) {
2219                         debug_cond(DLEVEL == 1,
2220                                    "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2221                                    __func__, __LINE__, rw_group, r, i, p, d);
2222
2223                         scc_mgr_set_dq_in_delay(p, d);
2224                         scc_mgr_load_dq(p);
2225                 }
2226
2227                 writel(0, &sdr_scc_mgr->update);
2228         }
2229
2230         /*
2231          * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2232          * dq_in_delay values
2233          */
2234         found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2235
2236         debug_cond(DLEVEL == 1,
2237                    "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2238                    __func__, __LINE__, rw_group, found);
2239
2240         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2241              r += NUM_RANKS_PER_SHADOW_REG) {
2242                 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2243                 writel(0, &sdr_scc_mgr->update);
2244         }
2245
2246         if (!found)
2247                 return -EINVAL;
2248
2249         return 0;
2250
2251 }
2252
2253 /**
2254  * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2255  * @rw_group:           Read/Write Group
2256  * @test_bgn:           Rank at which the test begins
2257  * @use_read_test:      Perform a read test
2258  * @update_fom:         Update FOM
2259  *
2260  * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2261  * within a group.
2262  */
2263 static int
2264 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2265                                       const int use_read_test,
2266                                       const int update_fom)
2267
2268 {
2269         int ret, grp_calibrated;
2270         u32 rank_bgn, sr;
2271
2272         /*
2273          * Altera EMI_RM 2015.05.04 :: Figure 1-28
2274          * Read per-bit deskew can be done on a per shadow register basis.
2275          */
2276         grp_calibrated = 1;
2277         for (rank_bgn = 0, sr = 0;
2278              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2279              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2280                 /* Check if this set of ranks should be skipped entirely. */
2281                 if (param->skip_shadow_regs[sr])
2282                         continue;
2283
2284                 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2285                                                         rw_group, test_bgn,
2286                                                         use_read_test,
2287                                                         update_fom);
2288                 if (ret)
2289                         continue;
2290
2291                 grp_calibrated = 0;
2292         }
2293
2294         if (!grp_calibrated)
2295                 return -EIO;
2296
2297         return 0;
2298 }
2299
2300 /**
2301  * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2302  * @rw_group:           Read/Write Group
2303  * @test_bgn:           Rank at which the test begins
2304  *
2305  * Stage 1: Calibrate the read valid prediction FIFO.
2306  *
2307  * This function implements UniPHY calibration Stage 1, as explained in
2308  * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2309  *
2310  * - read valid prediction will consist of finding:
2311  *   - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2312  *   - DQS input phase  and DQS input delay (DQ/DQS Centering)
2313  *  - we also do a per-bit deskew on the DQ lines.
2314  */
2315 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2316 {
2317         uint32_t p, d;
2318         uint32_t dtaps_per_ptap;
2319         uint32_t failed_substage;
2320
2321         int ret;
2322
2323         debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2324
2325         /* Update info for sims */
2326         reg_file_set_group(rw_group);
2327         reg_file_set_stage(CAL_STAGE_VFIFO);
2328         reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2329
2330         failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2331
2332         /* USER Determine number of delay taps for each phase tap. */
2333         dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2334                                       IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2335
2336         for (d = 0; d <= dtaps_per_ptap; d += 2) {
2337                 /*
2338                  * In RLDRAMX we may be messing the delay of pins in
2339                  * the same write rw_group but outside of the current read
2340                  * the rw_group, but that's ok because we haven't calibrated
2341                  * output side yet.
2342                  */
2343                 if (d > 0) {
2344                         scc_mgr_apply_group_all_out_delay_add_all_ranks(
2345                                                                 rw_group, d);
2346                 }
2347
2348                 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2349                         /* 1) Guaranteed Write */
2350                         ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2351                         if (ret)
2352                                 break;
2353
2354                         /* 2) DQS Enable Calibration */
2355                         ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2356                                                                           test_bgn);
2357                         if (ret) {
2358                                 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2359                                 continue;
2360                         }
2361
2362                         /* 3) Centering DQ/DQS */
2363                         /*
2364                          * If doing read after write calibration, do not update
2365                          * FOM now. Do it then.
2366                          */
2367                         ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2368                                                                 test_bgn, 1, 0);
2369                         if (ret) {
2370                                 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2371                                 continue;
2372                         }
2373
2374                         /* All done. */
2375                         goto cal_done_ok;
2376                 }
2377         }
2378
2379         /* Calibration Stage 1 failed. */
2380         set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2381         return 0;
2382
2383         /* Calibration Stage 1 completed OK. */
2384 cal_done_ok:
2385         /*
2386          * Reset the delay chains back to zero if they have moved > 1
2387          * (check for > 1 because loop will increase d even when pass in
2388          * first case).
2389          */
2390         if (d > 2)
2391                 scc_mgr_zero_group(rw_group, 1);
2392
2393         return 1;
2394 }
2395
2396 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2397 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2398                                                uint32_t test_bgn)
2399 {
2400         uint32_t rank_bgn, sr;
2401         uint32_t grp_calibrated;
2402         uint32_t write_group;
2403
2404         debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2405
2406         /* update info for sims */
2407
2408         reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2409         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2410
2411         write_group = read_group;
2412
2413         /* update info for sims */
2414         reg_file_set_group(read_group);
2415
2416         grp_calibrated = 1;
2417         /* Read per-bit deskew can be done on a per shadow register basis */
2418         for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2419                 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2420                 /* Determine if this set of ranks should be skipped entirely */
2421                 if (!param->skip_shadow_regs[sr]) {
2422                 /* This is the last calibration round, update FOM here */
2423                         if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2424                                                                 write_group,
2425                                                                 read_group,
2426                                                                 test_bgn, 0,
2427                                                                 1)) {
2428                                 grp_calibrated = 0;
2429                         }
2430                 }
2431         }
2432
2433
2434         if (grp_calibrated == 0) {
2435                 set_failing_group_stage(write_group,
2436                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2437                                         CAL_SUBSTAGE_VFIFO_CENTER);
2438                 return 0;
2439         }
2440
2441         return 1;
2442 }
2443
2444 /* Calibrate LFIFO to find smallest read latency */
2445 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2446 {
2447         uint32_t found_one;
2448         uint32_t bit_chk;
2449
2450         debug("%s:%d\n", __func__, __LINE__);
2451
2452         /* update info for sims */
2453         reg_file_set_stage(CAL_STAGE_LFIFO);
2454         reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2455
2456         /* Load up the patterns used by read calibration for all ranks */
2457         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2458         found_one = 0;
2459
2460         do {
2461                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2462                 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2463                            __func__, __LINE__, gbl->curr_read_lat);
2464
2465                 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2466                                                               NUM_READ_TESTS,
2467                                                               PASS_ALL_BITS,
2468                                                               &bit_chk, 1)) {
2469                         break;
2470                 }
2471
2472                 found_one = 1;
2473                 /* reduce read latency and see if things are working */
2474                 /* correctly */
2475                 gbl->curr_read_lat--;
2476         } while (gbl->curr_read_lat > 0);
2477
2478         /* reset the fifos to get pointers to known state */
2479
2480         writel(0, &phy_mgr_cmd->fifo_reset);
2481
2482         if (found_one) {
2483                 /* add a fudge factor to the read latency that was determined */
2484                 gbl->curr_read_lat += 2;
2485                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2486                 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2487                            read_lat=%u\n", __func__, __LINE__,
2488                            gbl->curr_read_lat);
2489                 return 1;
2490         } else {
2491                 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2492                                         CAL_SUBSTAGE_READ_LATENCY);
2493
2494                 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2495                            read_lat=%u\n", __func__, __LINE__,
2496                            gbl->curr_read_lat);
2497                 return 0;
2498         }
2499 }
2500
2501 /*
2502  * issue write test command.
2503  * two variants are provided. one that just tests a write pattern and
2504  * another that tests datamask functionality.
2505  */
2506 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2507                                                   uint32_t test_dm)
2508 {
2509         uint32_t mcc_instruction;
2510         uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2511                 ENABLE_SUPER_QUICK_CALIBRATION);
2512         uint32_t rw_wl_nop_cycles;
2513         uint32_t addr;
2514
2515         /*
2516          * Set counter and jump addresses for the right
2517          * number of NOP cycles.
2518          * The number of supported NOP cycles can range from -1 to infinity
2519          * Three different cases are handled:
2520          *
2521          * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2522          *    mechanism will be used to insert the right number of NOPs
2523          *
2524          * 2. For a number of NOP cycles equals to 0, the micro-instruction
2525          *    issuing the write command will jump straight to the
2526          *    micro-instruction that turns on DQS (for DDRx), or outputs write
2527          *    data (for RLD), skipping
2528          *    the NOP micro-instruction all together
2529          *
2530          * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2531          *    turned on in the same micro-instruction that issues the write
2532          *    command. Then we need
2533          *    to directly jump to the micro-instruction that sends out the data
2534          *
2535          * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2536          *       (2 and 3). One jump-counter (0) is used to perform multiple
2537          *       write-read operations.
2538          *       one counter left to issue this command in "multiple-group" mode
2539          */
2540
2541         rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2542
2543         if (rw_wl_nop_cycles == -1) {
2544                 /*
2545                  * CNTR 2 - We want to execute the special write operation that
2546                  * turns on DQS right away and then skip directly to the
2547                  * instruction that sends out the data. We set the counter to a
2548                  * large number so that the jump is always taken.
2549                  */
2550                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2551
2552                 /* CNTR 3 - Not used */
2553                 if (test_dm) {
2554                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2555                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2556                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2557                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2558                                &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2559                 } else {
2560                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2561                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2562                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2563                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2564                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2565                 }
2566         } else if (rw_wl_nop_cycles == 0) {
2567                 /*
2568                  * CNTR 2 - We want to skip the NOP operation and go straight
2569                  * to the DQS enable instruction. We set the counter to a large
2570                  * number so that the jump is always taken.
2571                  */
2572                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2573
2574                 /* CNTR 3 - Not used */
2575                 if (test_dm) {
2576                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2577                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2578                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2579                 } else {
2580                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2581                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2582                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2583                 }
2584         } else {
2585                 /*
2586                  * CNTR 2 - In this case we want to execute the next instruction
2587                  * and NOT take the jump. So we set the counter to 0. The jump
2588                  * address doesn't count.
2589                  */
2590                 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2591                 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2592
2593                 /*
2594                  * CNTR 3 - Set the nop counter to the number of cycles we
2595                  * need to loop for, minus 1.
2596                  */
2597                 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2598                 if (test_dm) {
2599                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2600                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2601                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2602                 } else {
2603                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2604                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2605                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2606                 }
2607         }
2608
2609         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2610                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
2611
2612         if (quick_write_mode)
2613                 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2614         else
2615                 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2616
2617         writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2618
2619         /*
2620          * CNTR 1 - This is used to ensure enough time elapses
2621          * for read data to come back.
2622          */
2623         writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2624
2625         if (test_dm) {
2626                 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2627                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2628         } else {
2629                 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2630                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2631         }
2632
2633         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2634         writel(mcc_instruction, addr + (group << 2));
2635 }
2636
2637 /* Test writes, can check for a single bit pass or multiple bit pass */
2638 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2639         uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2640         uint32_t *bit_chk, uint32_t all_ranks)
2641 {
2642         uint32_t r;
2643         uint32_t correct_mask_vg;
2644         uint32_t tmp_bit_chk;
2645         uint32_t vg;
2646         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2647                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2648         uint32_t addr_rw_mgr;
2649         uint32_t base_rw_mgr;
2650
2651         *bit_chk = param->write_correct_mask;
2652         correct_mask_vg = param->write_correct_mask_vg;
2653
2654         for (r = rank_bgn; r < rank_end; r++) {
2655                 if (param->skip_ranks[r]) {
2656                         /* request to skip the rank */
2657                         continue;
2658                 }
2659
2660                 /* set rank */
2661                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2662
2663                 tmp_bit_chk = 0;
2664                 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2665                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2666                         /* reset the fifos to get pointers to known state */
2667                         writel(0, &phy_mgr_cmd->fifo_reset);
2668
2669                         tmp_bit_chk = tmp_bit_chk <<
2670                                 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2671                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2672                         rw_mgr_mem_calibrate_write_test_issue(write_group *
2673                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2674                                 use_dm);
2675
2676                         base_rw_mgr = readl(addr_rw_mgr);
2677                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2678                         if (vg == 0)
2679                                 break;
2680                 }
2681                 *bit_chk &= tmp_bit_chk;
2682         }
2683
2684         if (all_correct) {
2685                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2686                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2687                            %u => %lu", write_group, use_dm,
2688                            *bit_chk, param->write_correct_mask,
2689                            (long unsigned int)(*bit_chk ==
2690                            param->write_correct_mask));
2691                 return *bit_chk == param->write_correct_mask;
2692         } else {
2693                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2694                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2695                        write_group, use_dm, *bit_chk);
2696                 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2697                         (long unsigned int)(*bit_chk != 0));
2698                 return *bit_chk != 0x00;
2699         }
2700 }
2701
2702 /*
2703  * center all windows. do per-bit-deskew to possibly increase size of
2704  * certain windows.
2705  */
2706 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2707         uint32_t write_group, uint32_t test_bgn)
2708 {
2709         uint32_t i, p, min_index;
2710         int32_t d;
2711         /*
2712          * Store these as signed since there are comparisons with
2713          * signed numbers.
2714          */
2715         uint32_t bit_chk;
2716         uint32_t sticky_bit_chk;
2717         int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2718         int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2719         int32_t mid;
2720         int32_t mid_min, orig_mid_min;
2721         int32_t new_dqs, start_dqs, shift_dq;
2722         int32_t dq_margin, dqs_margin, dm_margin;
2723         uint32_t stop;
2724         uint32_t temp_dq_out1_delay;
2725         uint32_t addr;
2726
2727         debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2728
2729         dm_margin = 0;
2730
2731         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2732         start_dqs = readl(addr +
2733                           (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2734
2735         /* per-bit deskew */
2736
2737         /*
2738          * set the left and right edge of each bit to an illegal value
2739          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2740          */
2741         sticky_bit_chk = 0;
2742         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2743                 left_edge[i]  = IO_IO_OUT1_DELAY_MAX + 1;
2744                 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2745         }
2746
2747         /* Search for the left edge of the window for each bit */
2748         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2749                 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2750
2751                 writel(0, &sdr_scc_mgr->update);
2752
2753                 /*
2754                  * Stop searching when the read test doesn't pass AND when
2755                  * we've seen a passing read on every bit.
2756                  */
2757                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2758                         0, PASS_ONE_BIT, &bit_chk, 0);
2759                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2760                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2761                 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2762                            == %u && %u [bit_chk= %u ]\n",
2763                         d, sticky_bit_chk, param->write_correct_mask,
2764                         stop, bit_chk);
2765
2766                 if (stop == 1) {
2767                         break;
2768                 } else {
2769                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2770                                 if (bit_chk & 1) {
2771                                         /*
2772                                          * Remember a passing test as the
2773                                          * left_edge.
2774                                          */
2775                                         left_edge[i] = d;
2776                                 } else {
2777                                         /*
2778                                          * If a left edge has not been seen
2779                                          * yet, then a future passing test will
2780                                          * mark this edge as the right edge.
2781                                          */
2782                                         if (left_edge[i] ==
2783                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2784                                                 right_edge[i] = -(d + 1);
2785                                         }
2786                                 }
2787                                 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2788                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2789                                            (int)(bit_chk & 1), i, left_edge[i]);
2790                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2791                                        right_edge[i]);
2792                                 bit_chk = bit_chk >> 1;
2793                         }
2794                 }
2795         }
2796
2797         /* Reset DQ delay chains to 0 */
2798         scc_mgr_apply_group_dq_out1_delay(0);
2799         sticky_bit_chk = 0;
2800         for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2801                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2802                            %d right_edge[%u]: %d\n", __func__, __LINE__,
2803                            i, left_edge[i], i, right_edge[i]);
2804
2805                 /*
2806                  * Check for cases where we haven't found the left edge,
2807                  * which makes our assignment of the the right edge invalid.
2808                  * Reset it to the illegal value.
2809                  */
2810                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2811                     (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2812                         right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2813                         debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2814                                    right_edge[%u]: %d\n", __func__, __LINE__,
2815                                    i, right_edge[i]);
2816                 }
2817
2818                 /*
2819                  * Reset sticky bit (except for bits where we have
2820                  * seen the left edge).
2821                  */
2822                 sticky_bit_chk = sticky_bit_chk << 1;
2823                 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2824                         sticky_bit_chk = sticky_bit_chk | 1;
2825
2826                 if (i == 0)
2827                         break;
2828         }
2829
2830         /* Search for the right edge of the window for each bit */
2831         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2832                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2833                                                         d + start_dqs);
2834
2835                 writel(0, &sdr_scc_mgr->update);
2836
2837                 /*
2838                  * Stop searching when the read test doesn't pass AND when
2839                  * we've seen a passing read on every bit.
2840                  */
2841                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2842                         0, PASS_ONE_BIT, &bit_chk, 0);
2843
2844                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2845                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2846
2847                 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2848                            %u && %u\n", d, sticky_bit_chk,
2849                            param->write_correct_mask, stop);
2850
2851                 if (stop == 1) {
2852                         if (d == 0) {
2853                                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2854                                         i++) {
2855                                         /* d = 0 failed, but it passed when
2856                                         testing the left edge, so it must be
2857                                         marginal, set it to -1 */
2858                                         if (right_edge[i] ==
2859                                                 IO_IO_OUT1_DELAY_MAX + 1 &&
2860                                                 left_edge[i] !=
2861                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2862                                                 right_edge[i] = -1;
2863                                         }
2864                                 }
2865                         }
2866                         break;
2867                 } else {
2868                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2869                                 if (bit_chk & 1) {
2870                                         /*
2871                                          * Remember a passing test as
2872                                          * the right_edge.
2873                                          */
2874                                         right_edge[i] = d;
2875                                 } else {
2876                                         if (d != 0) {
2877                                                 /*
2878                                                  * If a right edge has not
2879                                                  * been seen yet, then a future
2880                                                  * passing test will mark this
2881                                                  * edge as the left edge.
2882                                                  */
2883                                                 if (right_edge[i] ==
2884                                                     IO_IO_OUT1_DELAY_MAX + 1)
2885                                                         left_edge[i] = -(d + 1);
2886                                         } else {
2887                                                 /*
2888                                                  * d = 0 failed, but it passed
2889                                                  * when testing the left edge,
2890                                                  * so it must be marginal, set
2891                                                  * it to -1.
2892                                                  */
2893                                                 if (right_edge[i] ==
2894                                                     IO_IO_OUT1_DELAY_MAX + 1 &&
2895                                                     left_edge[i] !=
2896                                                     IO_IO_OUT1_DELAY_MAX + 1)
2897                                                         right_edge[i] = -1;
2898                                                 /*
2899                                                  * If a right edge has not been
2900                                                  * seen yet, then a future
2901                                                  * passing test will mark this
2902                                                  * edge as the left edge.
2903                                                  */
2904                                                 else if (right_edge[i] ==
2905                                                         IO_IO_OUT1_DELAY_MAX +
2906                                                         1)
2907                                                         left_edge[i] = -(d + 1);
2908                                         }
2909                                 }
2910                                 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2911                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2912                                            (int)(bit_chk & 1), i, left_edge[i]);
2913                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2914                                            right_edge[i]);
2915                                 bit_chk = bit_chk >> 1;
2916                         }
2917                 }
2918         }
2919
2920         /* Check that all bits have a window */
2921         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2922                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2923                            %d right_edge[%u]: %d", __func__, __LINE__,
2924                            i, left_edge[i], i, right_edge[i]);
2925                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2926                     (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2927                         set_failing_group_stage(test_bgn + i,
2928                                                 CAL_STAGE_WRITES,
2929                                                 CAL_SUBSTAGE_WRITES_CENTER);
2930                         return 0;
2931                 }
2932         }
2933
2934         /* Find middle of window for each DQ bit */
2935         mid_min = left_edge[0] - right_edge[0];
2936         min_index = 0;
2937         for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2938                 mid = left_edge[i] - right_edge[i];
2939                 if (mid < mid_min) {
2940                         mid_min = mid;
2941                         min_index = i;
2942                 }
2943         }
2944
2945         /*
2946          * -mid_min/2 represents the amount that we need to move DQS.
2947          * If mid_min is odd and positive we'll need to add one to
2948          * make sure the rounding in further calculations is correct
2949          * (always bias to the right), so just add 1 for all positive values.
2950          */
2951         if (mid_min > 0)
2952                 mid_min++;
2953         mid_min = mid_min / 2;
2954         debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2955                    __LINE__, mid_min);
2956
2957         /* Determine the amount we can change DQS (which is -mid_min) */
2958         orig_mid_min = mid_min;
2959         new_dqs = start_dqs;
2960         mid_min = 0;
2961         debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2962                    mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2963         /* Initialize data for export structures */
2964         dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2965         dq_margin  = IO_IO_OUT1_DELAY_MAX + 1;
2966
2967         /* add delay to bring centre of all DQ windows to the same "level" */
2968         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2969                 /* Use values before divide by 2 to reduce round off error */
2970                 shift_dq = (left_edge[i] - right_edge[i] -
2971                         (left_edge[min_index] - right_edge[min_index]))/2  +
2972                 (orig_mid_min - mid_min);
2973
2974                 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2975                            [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2976
2977                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2978                 temp_dq_out1_delay = readl(addr + (i << 2));
2979                 if (shift_dq + (int32_t)temp_dq_out1_delay >
2980                         (int32_t)IO_IO_OUT1_DELAY_MAX) {
2981                         shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2982                 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2983                         shift_dq = -(int32_t)temp_dq_out1_delay;
2984                 }
2985                 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2986                            i, shift_dq);
2987                 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2988                 scc_mgr_load_dq(i);
2989
2990                 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2991                            left_edge[i] - shift_dq + (-mid_min),
2992                            right_edge[i] + shift_dq - (-mid_min));
2993                 /* To determine values for export structures */
2994                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2995                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2996
2997                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2998                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2999         }
3000
3001         /* Move DQS */
3002         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3003         writel(0, &sdr_scc_mgr->update);
3004
3005         /* Centre DM */
3006         debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3007
3008         /*
3009          * set the left and right edge of each bit to an illegal value,
3010          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
3011          */
3012         left_edge[0]  = IO_IO_OUT1_DELAY_MAX + 1;
3013         right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3014         int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3015         int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3016         int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
3017         int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
3018         int32_t win_best = 0;
3019
3020         /* Search for the/part of the window with DM shift */
3021         for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
3022                 scc_mgr_apply_group_dm_out1_delay(d);
3023                 writel(0, &sdr_scc_mgr->update);
3024
3025                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3026                                                     PASS_ALL_BITS, &bit_chk,
3027                                                     0)) {
3028                         /* USE Set current end of the window */
3029                         end_curr = -d;
3030                         /*
3031                          * If a starting edge of our window has not been seen
3032                          * this is our current start of the DM window.
3033                          */
3034                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3035                                 bgn_curr = -d;
3036
3037                         /*
3038                          * If current window is bigger than best seen.
3039                          * Set best seen to be current window.
3040                          */
3041                         if ((end_curr-bgn_curr+1) > win_best) {
3042                                 win_best = end_curr-bgn_curr+1;
3043                                 bgn_best = bgn_curr;
3044                                 end_best = end_curr;
3045                         }
3046                 } else {
3047                         /* We just saw a failing test. Reset temp edge */
3048                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3049                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3050                         }
3051                 }
3052
3053
3054         /* Reset DM delay chains to 0 */
3055         scc_mgr_apply_group_dm_out1_delay(0);
3056
3057         /*
3058          * Check to see if the current window nudges up aganist 0 delay.
3059          * If so we need to continue the search by shifting DQS otherwise DQS
3060          * search begins as a new search. */
3061         if (end_curr != 0) {
3062                 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3063                 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3064         }
3065
3066         /* Search for the/part of the window with DQS shifts */
3067         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3068                 /*
3069                  * Note: This only shifts DQS, so are we limiting ourselve to
3070                  * width of DQ unnecessarily.
3071                  */
3072                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3073                                                         d + new_dqs);
3074
3075                 writel(0, &sdr_scc_mgr->update);
3076                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3077                                                     PASS_ALL_BITS, &bit_chk,
3078                                                     0)) {
3079                         /* USE Set current end of the window */
3080                         end_curr = d;
3081                         /*
3082                          * If a beginning edge of our window has not been seen
3083                          * this is our current begin of the DM window.
3084                          */
3085                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3086                                 bgn_curr = d;
3087
3088                         /*
3089                          * If current window is bigger than best seen. Set best
3090                          * seen to be current window.
3091                          */
3092                         if ((end_curr-bgn_curr+1) > win_best) {
3093                                 win_best = end_curr-bgn_curr+1;
3094                                 bgn_best = bgn_curr;
3095                                 end_best = end_curr;
3096                         }
3097                 } else {
3098                         /* We just saw a failing test. Reset temp edge */
3099                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3100                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3101
3102                         /* Early exit optimization: if ther remaining delay
3103                         chain space is less than already seen largest window
3104                         we can exit */
3105                         if ((win_best-1) >
3106                                 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3107                                         break;
3108                                 }
3109                         }
3110                 }
3111
3112         /* assign left and right edge for cal and reporting; */
3113         left_edge[0] = -1*bgn_best;
3114         right_edge[0] = end_best;
3115
3116         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3117                    __LINE__, left_edge[0], right_edge[0]);
3118
3119         /* Move DQS (back to orig) */
3120         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3121
3122         /* Move DM */
3123
3124         /* Find middle of window for the DM bit */
3125         mid = (left_edge[0] - right_edge[0]) / 2;
3126
3127         /* only move right, since we are not moving DQS/DQ */
3128         if (mid < 0)
3129                 mid = 0;
3130
3131         /* dm_marign should fail if we never find a window */
3132         if (win_best == 0)
3133                 dm_margin = -1;
3134         else
3135                 dm_margin = left_edge[0] - mid;
3136
3137         scc_mgr_apply_group_dm_out1_delay(mid);
3138         writel(0, &sdr_scc_mgr->update);
3139
3140         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3141                    dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3142                    right_edge[0], mid, dm_margin);
3143         /* Export values */
3144         gbl->fom_out += dq_margin + dqs_margin;
3145
3146         debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3147                    dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3148                    dq_margin, dqs_margin, dm_margin);
3149
3150         /*
3151          * Do not remove this line as it makes sure all of our
3152          * decisions have been applied.
3153          */
3154         writel(0, &sdr_scc_mgr->update);
3155         return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3156 }
3157
3158 /* calibrate the write operations */
3159 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3160         uint32_t test_bgn)
3161 {
3162         /* update info for sims */
3163         debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3164
3165         reg_file_set_stage(CAL_STAGE_WRITES);
3166         reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3167
3168         reg_file_set_group(g);
3169
3170         if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3171                 set_failing_group_stage(g, CAL_STAGE_WRITES,
3172                                         CAL_SUBSTAGE_WRITES_CENTER);
3173                 return 0;
3174         }
3175
3176         return 1;
3177 }
3178
3179 /**
3180  * mem_precharge_and_activate() - Precharge all banks and activate
3181  *
3182  * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3183  */
3184 static void mem_precharge_and_activate(void)
3185 {
3186         int r;
3187
3188         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3189                 /* Test if the rank should be skipped. */
3190                 if (param->skip_ranks[r])
3191                         continue;
3192
3193                 /* Set rank. */
3194                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3195
3196                 /* Precharge all banks. */
3197                 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3198                                              RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3199
3200                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3201                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3202                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3203
3204                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3205                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3206                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3207
3208                 /* Activate rows. */
3209                 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3210                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3211         }
3212 }
3213
3214 /**
3215  * mem_init_latency() - Configure memory RLAT and WLAT settings
3216  *
3217  * Configure memory RLAT and WLAT parameters.
3218  */
3219 static void mem_init_latency(void)
3220 {
3221         /*
3222          * For AV/CV, LFIFO is hardened and always runs at full rate
3223          * so max latency in AFI clocks, used here, is correspondingly
3224          * smaller.
3225          */
3226         const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3227         u32 rlat, wlat;
3228
3229         debug("%s:%d\n", __func__, __LINE__);
3230
3231         /*
3232          * Read in write latency.
3233          * WL for Hard PHY does not include additive latency.
3234          */
3235         wlat = readl(&data_mgr->t_wl_add);
3236         wlat += readl(&data_mgr->mem_t_add);
3237
3238         gbl->rw_wl_nop_cycles = wlat - 1;
3239
3240         /* Read in readl latency. */
3241         rlat = readl(&data_mgr->t_rl_add);
3242
3243         /* Set a pretty high read latency initially. */
3244         gbl->curr_read_lat = rlat + 16;
3245         if (gbl->curr_read_lat > max_latency)
3246                 gbl->curr_read_lat = max_latency;
3247
3248         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3249
3250         /* Advertise write latency. */
3251         writel(wlat, &phy_mgr_cfg->afi_wlat);
3252 }
3253
3254 /**
3255  * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3256  *
3257  * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3258  */
3259 static void mem_skip_calibrate(void)
3260 {
3261         uint32_t vfifo_offset;
3262         uint32_t i, j, r;
3263
3264         debug("%s:%d\n", __func__, __LINE__);
3265         /* Need to update every shadow register set used by the interface */
3266         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3267              r += NUM_RANKS_PER_SHADOW_REG) {
3268                 /*
3269                  * Set output phase alignment settings appropriate for
3270                  * skip calibration.
3271                  */
3272                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3273                         scc_mgr_set_dqs_en_phase(i, 0);
3274 #if IO_DLL_CHAIN_LENGTH == 6
3275                         scc_mgr_set_dqdqs_output_phase(i, 6);
3276 #else
3277                         scc_mgr_set_dqdqs_output_phase(i, 7);
3278 #endif
3279                         /*
3280                          * Case:33398
3281                          *
3282                          * Write data arrives to the I/O two cycles before write
3283                          * latency is reached (720 deg).
3284                          *   -> due to bit-slip in a/c bus
3285                          *   -> to allow board skew where dqs is longer than ck
3286                          *      -> how often can this happen!?
3287                          *      -> can claim back some ptaps for high freq
3288                          *       support if we can relax this, but i digress...
3289                          *
3290                          * The write_clk leads mem_ck by 90 deg
3291                          * The minimum ptap of the OPA is 180 deg
3292                          * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3293                          * The write_clk is always delayed by 2 ptaps
3294                          *
3295                          * Hence, to make DQS aligned to CK, we need to delay
3296                          * DQS by:
3297                          *    (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3298                          *
3299                          * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3300                          * gives us the number of ptaps, which simplies to:
3301                          *
3302                          *    (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3303                          */
3304                         scc_mgr_set_dqdqs_output_phase(i,
3305                                         1.25 * IO_DLL_CHAIN_LENGTH - 2);
3306                 }
3307                 writel(0xff, &sdr_scc_mgr->dqs_ena);
3308                 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3309
3310                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3311                         writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3312                                   SCC_MGR_GROUP_COUNTER_OFFSET);
3313                 }
3314                 writel(0xff, &sdr_scc_mgr->dq_ena);
3315                 writel(0xff, &sdr_scc_mgr->dm_ena);
3316                 writel(0, &sdr_scc_mgr->update);
3317         }
3318
3319         /* Compensate for simulation model behaviour */
3320         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3321                 scc_mgr_set_dqs_bus_in_delay(i, 10);
3322                 scc_mgr_load_dqs(i);
3323         }
3324         writel(0, &sdr_scc_mgr->update);
3325
3326         /*
3327          * ArriaV has hard FIFOs that can only be initialized by incrementing
3328          * in sequencer.
3329          */
3330         vfifo_offset = CALIB_VFIFO_OFFSET;
3331         for (j = 0; j < vfifo_offset; j++)
3332                 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3333         writel(0, &phy_mgr_cmd->fifo_reset);
3334
3335         /*
3336          * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3337          * setting from generation-time constant.
3338          */
3339         gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3340         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3341 }
3342
3343 /**
3344  * mem_calibrate() - Memory calibration entry point.
3345  *
3346  * Perform memory calibration.
3347  */
3348 static uint32_t mem_calibrate(void)
3349 {
3350         uint32_t i;
3351         uint32_t rank_bgn, sr;
3352         uint32_t write_group, write_test_bgn;
3353         uint32_t read_group, read_test_bgn;
3354         uint32_t run_groups, current_run;
3355         uint32_t failing_groups = 0;
3356         uint32_t group_failed = 0;
3357
3358         const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3359                                 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3360
3361         debug("%s:%d\n", __func__, __LINE__);
3362
3363         /* Initialize the data settings */
3364         gbl->error_substage = CAL_SUBSTAGE_NIL;
3365         gbl->error_stage = CAL_STAGE_NIL;
3366         gbl->error_group = 0xff;
3367         gbl->fom_in = 0;
3368         gbl->fom_out = 0;
3369
3370         /* Initialize WLAT and RLAT. */
3371         mem_init_latency();
3372
3373         /* Initialize bit slips. */
3374         mem_precharge_and_activate();
3375
3376         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3377                 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3378                           SCC_MGR_GROUP_COUNTER_OFFSET);
3379                 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3380                 if (i == 0)
3381                         scc_mgr_set_hhp_extras();
3382
3383                 scc_set_bypass_mode(i);
3384         }
3385
3386         /* Calibration is skipped. */
3387         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3388                 /*
3389                  * Set VFIFO and LFIFO to instant-on settings in skip
3390                  * calibration mode.
3391                  */
3392                 mem_skip_calibrate();
3393
3394                 /*
3395                  * Do not remove this line as it makes sure all of our
3396                  * decisions have been applied.
3397                  */
3398                 writel(0, &sdr_scc_mgr->update);
3399                 return 1;
3400         }
3401
3402         /* Calibration is not skipped. */
3403         for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3404                 /*
3405                  * Zero all delay chain/phase settings for all
3406                  * groups and all shadow register sets.
3407                  */
3408                 scc_mgr_zero_all();
3409
3410                 run_groups = ~param->skip_groups;
3411
3412                 for (write_group = 0, write_test_bgn = 0; write_group
3413                         < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3414                         write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3415
3416                         /* Initialize the group failure */
3417                         group_failed = 0;
3418
3419                         current_run = run_groups & ((1 <<
3420                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3421                         run_groups = run_groups >>
3422                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3423
3424                         if (current_run == 0)
3425                                 continue;
3426
3427                         writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3428                                             SCC_MGR_GROUP_COUNTER_OFFSET);
3429                         scc_mgr_zero_group(write_group, 0);
3430
3431                         for (read_group = write_group * rwdqs_ratio,
3432                              read_test_bgn = 0;
3433                              read_group < (write_group + 1) * rwdqs_ratio;
3434                              read_group++,
3435                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3436                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3437                                         continue;
3438
3439                                 /* Calibrate the VFIFO */
3440                                 if (rw_mgr_mem_calibrate_vfifo(read_group,
3441                                                                read_test_bgn))
3442                                         continue;
3443
3444                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3445                                         return 0;
3446
3447                                 /* The group failed, we're done. */
3448                                 goto grp_failed;
3449                         }
3450
3451                         /* Calibrate the output side */
3452                         for (rank_bgn = 0, sr = 0;
3453                              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3454                              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3455                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3456                                         continue;
3457
3458                                 /* Not needed in quick mode! */
3459                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3460                                         continue;
3461
3462                                 /*
3463                                  * Determine if this set of ranks
3464                                  * should be skipped entirely.
3465                                  */
3466                                 if (param->skip_shadow_regs[sr])
3467                                         continue;
3468
3469                                 /* Calibrate WRITEs */
3470                                 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3471                                                 write_group, write_test_bgn))
3472                                         continue;
3473
3474                                 group_failed = 1;
3475                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3476                                         return 0;
3477                         }
3478
3479                         /* Some group failed, we're done. */
3480                         if (group_failed)
3481                                 goto grp_failed;
3482
3483                         for (read_group = write_group * rwdqs_ratio,
3484                              read_test_bgn = 0;
3485                              read_group < (write_group + 1) * rwdqs_ratio;
3486                              read_group++,
3487                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3488                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3489                                         continue;
3490
3491                                 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3492                                                                 read_test_bgn))
3493                                         continue;
3494
3495                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3496                                         return 0;
3497
3498                                 /* The group failed, we're done. */
3499                                 goto grp_failed;
3500                         }
3501
3502                         /* No group failed, continue as usual. */
3503                         continue;
3504
3505 grp_failed:             /* A group failed, increment the counter. */
3506                         failing_groups++;
3507                 }
3508
3509                 /*
3510                  * USER If there are any failing groups then report
3511                  * the failure.
3512                  */
3513                 if (failing_groups != 0)
3514                         return 0;
3515
3516                 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3517                         continue;
3518
3519                 /*
3520                  * If we're skipping groups as part of debug,
3521                  * don't calibrate LFIFO.
3522                  */
3523                 if (param->skip_groups != 0)
3524                         continue;
3525
3526                 /* Calibrate the LFIFO */
3527                 if (!rw_mgr_mem_calibrate_lfifo())
3528                         return 0;
3529         }
3530
3531         /*
3532          * Do not remove this line as it makes sure all of our decisions
3533          * have been applied.
3534          */
3535         writel(0, &sdr_scc_mgr->update);
3536         return 1;
3537 }
3538
3539 /**
3540  * run_mem_calibrate() - Perform memory calibration
3541  *
3542  * This function triggers the entire memory calibration procedure.
3543  */
3544 static int run_mem_calibrate(void)
3545 {
3546         int pass;
3547
3548         debug("%s:%d\n", __func__, __LINE__);
3549
3550         /* Reset pass/fail status shown on afi_cal_success/fail */
3551         writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3552
3553         /* Stop tracking manager. */
3554         clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3555
3556         phy_mgr_initialize();
3557         rw_mgr_mem_initialize();
3558
3559         /* Perform the actual memory calibration. */
3560         pass = mem_calibrate();
3561
3562         mem_precharge_and_activate();
3563         writel(0, &phy_mgr_cmd->fifo_reset);
3564
3565         /* Handoff. */
3566         rw_mgr_mem_handoff();
3567         /*
3568          * In Hard PHY this is a 2-bit control:
3569          * 0: AFI Mux Select
3570          * 1: DDIO Mux Select
3571          */
3572         writel(0x2, &phy_mgr_cfg->mux_sel);
3573
3574         /* Start tracking manager. */
3575         setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3576
3577         return pass;
3578 }
3579
3580 /**
3581  * debug_mem_calibrate() - Report result of memory calibration
3582  * @pass:       Value indicating whether calibration passed or failed
3583  *
3584  * This function reports the results of the memory calibration
3585  * and writes debug information into the register file.
3586  */
3587 static void debug_mem_calibrate(int pass)
3588 {
3589         uint32_t debug_info;
3590
3591         if (pass) {
3592                 printf("%s: CALIBRATION PASSED\n", __FILE__);
3593
3594                 gbl->fom_in /= 2;
3595                 gbl->fom_out /= 2;
3596
3597                 if (gbl->fom_in > 0xff)
3598                         gbl->fom_in = 0xff;
3599
3600                 if (gbl->fom_out > 0xff)
3601                         gbl->fom_out = 0xff;
3602
3603                 /* Update the FOM in the register file */
3604                 debug_info = gbl->fom_in;
3605                 debug_info |= gbl->fom_out << 8;
3606                 writel(debug_info, &sdr_reg_file->fom);
3607
3608                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3609                 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3610         } else {
3611                 printf("%s: CALIBRATION FAILED\n", __FILE__);
3612
3613                 debug_info = gbl->error_stage;
3614                 debug_info |= gbl->error_substage << 8;
3615                 debug_info |= gbl->error_group << 16;
3616
3617                 writel(debug_info, &sdr_reg_file->failing_stage);
3618                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3619                 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3620
3621                 /* Update the failing group/stage in the register file */
3622                 debug_info = gbl->error_stage;
3623                 debug_info |= gbl->error_substage << 8;
3624                 debug_info |= gbl->error_group << 16;
3625                 writel(debug_info, &sdr_reg_file->failing_stage);
3626         }
3627
3628         printf("%s: Calibration complete\n", __FILE__);
3629 }
3630
3631 /**
3632  * hc_initialize_rom_data() - Initialize ROM data
3633  *
3634  * Initialize ROM data.
3635  */
3636 static void hc_initialize_rom_data(void)
3637 {
3638         u32 i, addr;
3639
3640         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3641         for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3642                 writel(inst_rom_init[i], addr + (i << 2));
3643
3644         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3645         for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3646                 writel(ac_rom_init[i], addr + (i << 2));
3647 }
3648
3649 /**
3650  * initialize_reg_file() - Initialize SDR register file
3651  *
3652  * Initialize SDR register file.
3653  */
3654 static void initialize_reg_file(void)
3655 {
3656         /* Initialize the register file with the correct data */
3657         writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3658         writel(0, &sdr_reg_file->debug_data_addr);
3659         writel(0, &sdr_reg_file->cur_stage);
3660         writel(0, &sdr_reg_file->fom);
3661         writel(0, &sdr_reg_file->failing_stage);
3662         writel(0, &sdr_reg_file->debug1);
3663         writel(0, &sdr_reg_file->debug2);
3664 }
3665
3666 /**
3667  * initialize_hps_phy() - Initialize HPS PHY
3668  *
3669  * Initialize HPS PHY.
3670  */
3671 static void initialize_hps_phy(void)
3672 {
3673         uint32_t reg;
3674         /*
3675          * Tracking also gets configured here because it's in the
3676          * same register.
3677          */
3678         uint32_t trk_sample_count = 7500;
3679         uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3680         /*
3681          * Format is number of outer loops in the 16 MSB, sample
3682          * count in 16 LSB.
3683          */
3684
3685         reg = 0;
3686         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3687         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3688         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3689         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3690         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3691         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3692         /*
3693          * This field selects the intrinsic latency to RDATA_EN/FULL path.
3694          * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3695          */
3696         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3697         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3698                 trk_sample_count);
3699         writel(reg, &sdr_ctrl->phy_ctrl0);
3700
3701         reg = 0;
3702         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3703                 trk_sample_count >>
3704                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3705         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3706                 trk_long_idle_sample_count);
3707         writel(reg, &sdr_ctrl->phy_ctrl1);
3708
3709         reg = 0;
3710         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3711                 trk_long_idle_sample_count >>
3712                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3713         writel(reg, &sdr_ctrl->phy_ctrl2);
3714 }
3715
3716 /**
3717  * initialize_tracking() - Initialize tracking
3718  *
3719  * Initialize the register file with usable initial data.
3720  */
3721 static void initialize_tracking(void)
3722 {
3723         /*
3724          * Initialize the register file with the correct data.
3725          * Compute usable version of value in case we skip full
3726          * computation later.
3727          */
3728         writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3729                &sdr_reg_file->dtaps_per_ptap);
3730
3731         /* trk_sample_count */
3732         writel(7500, &sdr_reg_file->trk_sample_count);
3733
3734         /* longidle outer loop [15:0] */
3735         writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3736
3737         /*
3738          * longidle sample count [31:24]
3739          * trfc, worst case of 933Mhz 4Gb [23:16]
3740          * trcd, worst case [15:8]
3741          * vfifo wait [7:0]
3742          */
3743         writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3744                &sdr_reg_file->delays);
3745
3746         /* mux delay */
3747         writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3748                (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3749                &sdr_reg_file->trk_rw_mgr_addr);
3750
3751         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3752                &sdr_reg_file->trk_read_dqs_width);
3753
3754         /* trefi [7:0] */
3755         writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3756                &sdr_reg_file->trk_rfsh);
3757 }
3758
3759 int sdram_calibration_full(void)
3760 {
3761         struct param_type my_param;
3762         struct gbl_type my_gbl;
3763         uint32_t pass;
3764
3765         memset(&my_param, 0, sizeof(my_param));
3766         memset(&my_gbl, 0, sizeof(my_gbl));
3767
3768         param = &my_param;
3769         gbl = &my_gbl;
3770
3771         /* Set the calibration enabled by default */
3772         gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3773         /*
3774          * Only sweep all groups (regardless of fail state) by default
3775          * Set enabled read test by default.
3776          */
3777 #if DISABLE_GUARANTEED_READ
3778         gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3779 #endif
3780         /* Initialize the register file */
3781         initialize_reg_file();
3782
3783         /* Initialize any PHY CSR */
3784         initialize_hps_phy();
3785
3786         scc_mgr_initialize();
3787
3788         initialize_tracking();
3789
3790         printf("%s: Preparing to start memory calibration\n", __FILE__);
3791
3792         debug("%s:%d\n", __func__, __LINE__);
3793         debug_cond(DLEVEL == 1,
3794                    "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3795                    RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3796                    RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3797                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3798                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3799         debug_cond(DLEVEL == 1,
3800                    "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3801                    RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3802                    RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3803                    IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3804         debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3805                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3806         debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3807                    IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3808                    IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3809         debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3810                    IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3811                    IO_IO_OUT2_DELAY_MAX);
3812         debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3813                    IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3814
3815         hc_initialize_rom_data();
3816
3817         /* update info for sims */
3818         reg_file_set_stage(CAL_STAGE_NIL);
3819         reg_file_set_group(0);
3820
3821         /*
3822          * Load global needed for those actions that require
3823          * some dynamic calibration support.
3824          */
3825         dyn_calib_steps = STATIC_CALIB_STEPS;
3826         /*
3827          * Load global to allow dynamic selection of delay loop settings
3828          * based on calibration mode.
3829          */
3830         if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3831                 skip_delay_mask = 0xff;
3832         else
3833                 skip_delay_mask = 0x0;
3834
3835         pass = run_mem_calibrate();
3836         debug_mem_calibrate(pass);
3837         return pass;
3838 }