2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
10 #define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH \
11 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
12 #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH \
13 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
15 #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH \
16 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
17 #define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
19 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
20 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
21 #define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000
22 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400
23 #define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800
24 #define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00
26 #define RW_MGR_MEM_NUMBER_OF_RANKS 1
27 #define NUM_SHADOW_REGS 1
29 #define RW_MGR_RANK_NONE 0xFF
30 #define RW_MGR_RANK_ALL 0x00
32 #define RW_MGR_ODT_MODE_OFF 0
33 #define RW_MGR_ODT_MODE_READ_WRITE 1
35 #define NUM_CALIB_REPEAT 1
37 #define NUM_READ_TESTS 7
38 #define NUM_READ_PB_TESTS 7
39 #define NUM_WRITE_TESTS 15
40 #define NUM_WRITE_PB_TESTS 31
42 #define PASS_ALL_BITS 1
43 #define PASS_ONE_BIT 0
45 /* calibration stages */
46 #define CAL_STAGE_NIL 0
47 #define CAL_STAGE_VFIFO 1
48 #define CAL_STAGE_WLEVEL 2
49 #define CAL_STAGE_LFIFO 3
50 #define CAL_STAGE_WRITES 4
51 #define CAL_STAGE_FULLTEST 5
52 #define CAL_STAGE_REFRESH 6
53 #define CAL_STAGE_CAL_SKIPPED 7
54 #define CAL_STAGE_CAL_ABORTED 8
55 #define CAL_STAGE_VFIFO_AFTER_WRITES 9
57 /* calibration substages */
58 #define CAL_SUBSTAGE_NIL 0
59 #define CAL_SUBSTAGE_GUARANTEED_READ 1
60 #define CAL_SUBSTAGE_DQS_EN_PHASE 2
61 #define CAL_SUBSTAGE_VFIFO_CENTER 3
62 #define CAL_SUBSTAGE_WORKING_DELAY 1
63 #define CAL_SUBSTAGE_LAST_WORKING_DELAY 2
64 #define CAL_SUBSTAGE_WLEVEL_COPY 3
65 #define CAL_SUBSTAGE_WRITES_CENTER 1
66 #define CAL_SUBSTAGE_READ_LATENCY 1
67 #define CAL_SUBSTAGE_REFRESH 1
69 #define MAX_RANKS (RW_MGR_MEM_NUMBER_OF_RANKS)
70 #define MAX_DQS (RW_MGR_MEM_IF_WRITE_DQS_WIDTH > \
71 RW_MGR_MEM_IF_READ_DQS_WIDTH ? \
72 RW_MGR_MEM_IF_WRITE_DQS_WIDTH : \
73 RW_MGR_MEM_IF_READ_DQS_WIDTH)
74 #define MAX_DQ (RW_MGR_MEM_DATA_WIDTH)
75 #define MAX_DM (RW_MGR_MEM_DATA_MASK_WIDTH)
77 /* length of VFIFO, from SW_MACROS */
78 #define VFIFO_SIZE (READ_VALID_FIFO_SIZE)
80 #define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000
81 #define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100
82 #define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200
83 #define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300
84 #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400
85 #define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500
86 #define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700
87 #define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900
89 /* HHP-HPS-specific versions of some commands */
90 #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET 0x0600
91 #define SCC_MGR_IO_OE_DELAY_OFFSET 0x0800
92 #define SCC_MGR_HHP_GLOBALS_OFFSET 0x0A00
93 #define SCC_MGR_HHP_RFILE_OFFSET 0x0B00
94 #define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00
96 #define SDR_PHYGRP_SCCGRP_ADDRESS 0x0
97 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS 0x1000
98 #define SDR_PHYGRP_RWMGRGRP_ADDRESS 0x2000
99 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS 0x4000
100 #define SDR_PHYGRP_REGFILEGRP_ADDRESS 0x4800
102 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150
103 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
104 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158
106 #define PHY_MGR_CAL_RESET (0)
107 #define PHY_MGR_CAL_SUCCESS (1)
108 #define PHY_MGR_CAL_FAIL (2)
110 #define CALIB_SKIP_DELAY_LOOPS (1 << 0)
111 #define CALIB_SKIP_ALL_BITS_CHK (1 << 1)
112 #define CALIB_SKIP_DELAY_SWEEPS (1 << 2)
113 #define CALIB_SKIP_VFIFO (1 << 3)
114 #define CALIB_SKIP_LFIFO (1 << 4)
115 #define CALIB_SKIP_WLEVEL (1 << 5)
116 #define CALIB_SKIP_WRITES (1 << 6)
117 #define CALIB_SKIP_FULL_TEST (1 << 7)
118 #define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \
119 CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
120 CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
121 #define CALIB_IN_RTL_SIM (1 << 8)
123 /* Scan chain manager command addresses */
124 #define READ_SCC_OCT_OUT2_DELAY 0
125 #define READ_SCC_DQ_OUT2_DELAY 0
126 #define READ_SCC_DQS_IO_OUT2_DELAY 0
127 #define READ_SCC_DM_IO_OUT2_DELAY 0
129 /* HHP-HPS-specific values */
130 #define SCC_MGR_HHP_EXTRAS_OFFSET 0
131 #define SCC_MGR_HHP_DQSE_MAP_OFFSET 1
133 /* PHY Debug mode flag constants */
134 #define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
135 #define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
136 #define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
137 #define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
138 #define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
139 #define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
141 /* Init and Reset delay constants - Only use if defined by sequencer_defines.h,
142 * otherwise, revert to defaults
143 * Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 =
146 #ifdef TINIT_CNTR0_VAL
147 #define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL
149 #define SEQ_TINIT_CNTR0_VAL 0
152 #ifdef TINIT_CNTR1_VAL
153 #define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL
155 #define SEQ_TINIT_CNTR1_VAL 202
158 #ifdef TINIT_CNTR2_VAL
159 #define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL
161 #define SEQ_TINIT_CNTR2_VAL 131
165 /* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 =
168 #ifdef TRESET_CNTR0_VAL
169 #define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL
171 #define SEQ_TRESET_CNTR0_VAL 2
174 #ifdef TRESET_CNTR1_VAL
175 #define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL
177 #define SEQ_TRESET_CNTR1_VAL 252
180 #ifdef TRESET_CNTR2_VAL
181 #define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL
183 #define SEQ_TRESET_CNTR2_VAL 131
186 struct socfpga_sdr_rw_load_manager {
193 struct socfpga_sdr_rw_load_jump_manager {
200 struct socfpga_sdr_reg_file {
209 u32 trk_sample_count;
213 u32 trk_read_dqs_width;
217 /* parameter variable holder */
219 uint32_t dm_correct_mask;
220 uint32_t read_correct_mask;
221 uint32_t read_correct_mask_vg;
222 uint32_t write_correct_mask;
223 uint32_t write_correct_mask_vg;
225 /* set a particular entry to 1 if we need to skip a particular rank */
227 uint32_t skip_ranks[MAX_RANKS];
229 /* set a particular entry to 1 if we need to skip a particular group */
231 uint32_t skip_groups;
233 /* set a particular entry to 1 if the shadow register
234 (which represents a set of ranks) needs to be skipped */
236 uint32_t skip_shadow_regs[NUM_SHADOW_REGS];
241 /* global variable holder */
243 uint32_t phy_debug_mode_flags;
245 /* current read latency */
247 uint32_t curr_read_lat;
249 /* current write latency */
251 uint32_t curr_write_lat;
255 uint32_t error_substage;
256 uint32_t error_stage;
257 uint32_t error_group;
259 /* figure-of-merit in, figure-of-merit out */
264 /*USER Number of RW Mgr NOP cycles between
265 write command and write data */
266 uint32_t rw_wl_nop_cycles;
269 struct socfpga_sdr_scc_mgr {
280 /* PHY manager configuration registers. */
281 struct socfpga_phy_mgr_cfg {
287 u32 vfifo_rd_en_ovrd;
292 /* PHY manager command addresses. */
293 struct socfpga_phy_mgr_cmd {
295 u32 inc_vfifo_hard_phy;
301 struct socfpga_data_mgr {
307 #endif /* _SEQUENCER_H_ */