drivers/ddr/fsl/fsl_ddr_gen4.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <fsl_ddr_sdram.h>
  10 #include <asm/processor.h>
  11 #include <fsl_ddr.h>
  12
  13 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  14 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  15 #endif
  16
  17 /*
  18  * regs has the to-be-set values for DDR controller registers
  19  * ctrl_num is the DDR controller number
  20  * step: 0 goes through the initialization in one pass
  21  *       1 sets registers and returns before enabling controller
  22  *       2 resumes from step 1 and continues to initialize
  23  * Dividing the initialization to two steps to deassert DDR reset signal
  24  * to comply with JEDEC specs for RDIMMs.
  25  */
  26 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  27                              unsigned int ctrl_num, int step)
  28 {
  29         unsigned int i, bus_width;
  30         struct ccsr_ddr __iomem *ddr;
  31         u32 temp_sdram_cfg;
  32         u32 total_gb_size_per_controller;
  33         int timeout;
  34
  35         switch (ctrl_num) {
  36         case 0:
  37                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  38                 break;
  39 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  40         case 1:
  41                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  42                 break;
  43 #endif
  44 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  45         case 2:
  46                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  47                 break;
  48 #endif
  49 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  50         case 3:
  51                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  52                 break;
  53 #endif
  54         default:
  55                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  56                 return;
  57         }
  58
  59         if (step == 2)
  60                 goto step2;
  61
  62         if (regs->ddr_eor)
  63                 ddr_out32(&ddr->eor, regs->ddr_eor);
  64
  65         ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  66
  67         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  68                 if (i == 0) {
  69                         ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
  70                         ddr_out32(&ddr->cs0_config, regs->cs[i].config);
  71                         ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
  72
  73                 } else if (i == 1) {
  74                         ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
  75                         ddr_out32(&ddr->cs1_config, regs->cs[i].config);
  76                         ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
  77
  78                 } else if (i == 2) {
  79                         ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
  80                         ddr_out32(&ddr->cs2_config, regs->cs[i].config);
  81                         ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
  82
  83                 } else if (i == 3) {
  84                         ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
  85                         ddr_out32(&ddr->cs3_config, regs->cs[i].config);
  86                         ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
  87                 }
  88         }
  89
  90         ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  91         ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  92         ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  93         ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  94         ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
  95         ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
  96         ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
  97         ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
  98         ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
  99         ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
 100         ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 101         ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
 102         ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
 103         ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
 104         ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
 105         ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 106         ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
 107         ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 108         ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 109         ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 110         ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 111         ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 112         ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 113         ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 114         ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 115         ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
 116         ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
 117         ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
 118         ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
 119         ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
 120         ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
 121         ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
 122         ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
 123         ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 124         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 125         ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 126         ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
 127         ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 128         ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 129 #ifndef CONFIG_SYS_FSL_DDR_EMU
 130         /*
 131          * Skip these two registers if running on emulator
 132          * because emulator doesn't have skew between bytes.
 133          */
 134
 135         if (regs->ddr_wrlvl_cntl_2)
 136                 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 137         if (regs->ddr_wrlvl_cntl_3)
 138                 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 139 #endif
 140
 141         ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 142         ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 143         ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 144         ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
 145         ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
 146         ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
 147         ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
 148         ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 149         ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 150         ddr_out32(&ddr->err_disable, regs->err_disable);
 151         ddr_out32(&ddr->err_int_en, regs->err_int_en);
 152         for (i = 0; i < 32; i++) {
 153                 if (regs->debug[i]) {
 154                         debug("Write to debug_%d as %08x\n",
 155                               i+1, regs->debug[i]);
 156                         ddr_out32(&ddr->debug[i], regs->debug[i]);
 157                 }
 158         }
 159
 160         /*
 161          * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 162          * deasserted. Clocks start when any chip select is enabled and clock
 163          * control register is set. Because all DDR components are connected to
 164          * one reset signal, this needs to be done in two steps. Step 1 is to
 165          * get the clocks started. Step 2 resumes after reset signal is
 166          * deasserted.
 167          */
 168         if (step == 1) {
 169                 udelay(200);
 170                 return;
 171         }
 172
 173 step2:
 174         /* Set, but do not enable the memory */
 175         temp_sdram_cfg = regs->ddr_sdram_cfg;
 176         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 177         ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
 178
 179         /*
 180          * 500 painful micro-seconds must elapse between
 181          * the DDR clock setup and the DDR config enable.
 182          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 183          * we choose the max, that is 500 us for all of case.
 184          */
 185         udelay(500);
 186         asm volatile("sync;isync");
 187
 188         /* Let the controller go */
 189         temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 190         ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 191         asm volatile("sync;isync");
 192
 193         total_gb_size_per_controller = 0;
 194         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 195                 if (!(regs->cs[i].config & 0x80000000))
 196                         continue;
 197                 total_gb_size_per_controller += 1 << (
 198                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 199                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 200                         ((regs->cs[i].config >> 4) & 0x3) + 0 +
 201                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 202                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 203                         26);                    /* minus 26 (count of 64M) */
 204         }
 205         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 206                 total_gb_size_per_controller *= 3;
 207         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 208                 total_gb_size_per_controller <<= 1;
 209         /*
 210          * total memory / bus width = transactions needed
 211          * transactions needed / data rate = seconds
 212          * to add plenty of buffer, double the time
 213          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 214          * Let's wait for 800ms
 215          */
 216         bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
 217                         >> SDRAM_CFG_DBW_SHIFT);
 218         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 219                 (get_ddr_freq(0) >> 20)) << 2;
 220         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 221         debug("total %d GB\n", total_gb_size_per_controller);
 222         debug("Need to wait up to %d * 10ms\n", timeout);
 223
 224         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 225         while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 226                 (timeout >= 0)) {
 227                 udelay(10000);          /* throttle polling rate */
 228                 timeout--;
 229         }
 230
 231         if (timeout <= 0)
 232                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 233
 234 }