drivers/ddr/fsl/main.c

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  11  * Based on code from spd_sdram.c
  12  * Author: James Yang [at freescale.com]
  13  */
  14
  15 #include <common.h>
  16 #include <i2c.h>
  17 #include <fsl_ddr_sdram.h>
  18 #include <fsl_ddr.h>
  19
  20 /*
  21  * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
  22  * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
  23  * all Power SoCs. But it could be different for ARM SoCs. For example,
  24  * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
  25  * 0x00_8000_0000 ~ 0x00_ffff_ffff
  26  * 0x80_8000_0000 ~ 0xff_ffff_ffff
  27  */
  28 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
  29 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
  30 #endif
  31
  32 #ifdef CONFIG_PPC
  33 #include <asm/fsl_law.h>
  34
  35 void fsl_ddr_set_lawbar(
  36                 const common_timing_params_t *memctl_common_params,
  37                 unsigned int memctl_interleaved,
  38                 unsigned int ctrl_num);
  39 #endif
  40
  41 void fsl_ddr_set_intl3r(const unsigned int granule_size);
  42 #if defined(SPD_EEPROM_ADDRESS) || \
  43     defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  44     defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  45 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  46 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  47         [0][0] = SPD_EEPROM_ADDRESS,
  48 };
  49 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  50 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  51         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  52         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  53 };
  54 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  55 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  56         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  57         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  58 };
  59 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  60 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  61         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  62         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  63         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  64         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  65 };
  66 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  67 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  68         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  69         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  70         [2][0] = SPD_EEPROM_ADDRESS3,   /* controller 3 */
  71 };
  72 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  73 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  74         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  75         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  76         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  77         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  78         [2][0] = SPD_EEPROM_ADDRESS5,   /* controller 3 */
  79         [2][1] = SPD_EEPROM_ADDRESS6,   /* controller 3 */
  80 };
  81
  82 #endif
  83
  84 #define SPD_SPA0_ADDRESS        0x36
  85 #define SPD_SPA1_ADDRESS        0x37
  86
  87 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  88 {
  89         int ret;
  90 #ifdef CONFIG_SYS_FSL_DDR4
  91         uint8_t dummy = 0;
  92 #endif
  93
  94         i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
  95
  96 #ifdef CONFIG_SYS_FSL_DDR4
  97         /*
  98          * DDR4 SPD has 384 to 512 bytes
  99          * To access the lower 256 bytes, we need to set EE page address to 0
 100          * To access the upper 256 bytes, we need to set EE page address to 1
 101          * See Jedec standar No. 21-C for detail
 102          */
 103         i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
 104         ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
 105         if (!ret) {
 106                 i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
 107                 ret = i2c_read(i2c_address, 0, 1,
 108                                (uchar *)((ulong)spd + 256),
 109                                min(256,
 110                                    (int)sizeof(generic_spd_eeprom_t) - 256));
 111         }
 112 #else
 113         ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
 114                                 sizeof(generic_spd_eeprom_t));
 115 #endif
 116
 117         if (ret) {
 118                 if (i2c_address ==
 119 #ifdef SPD_EEPROM_ADDRESS
 120                                 SPD_EEPROM_ADDRESS
 121 #elif defined(SPD_EEPROM_ADDRESS1)
 122                                 SPD_EEPROM_ADDRESS1
 123 #endif
 124                                 ) {
 125                         printf("DDR: failed to read SPD from address %u\n",
 126                                 i2c_address);
 127                 } else {
 128                         debug("DDR: failed to read SPD from address %u\n",
 129                                 i2c_address);
 130                 }
 131                 memset(spd, 0, sizeof(generic_spd_eeprom_t));
 132         }
 133 }
 134
 135 __attribute__((weak, alias("__get_spd")))
 136 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
 137
 138 /* This function allows boards to update SPD address */
 139 __weak void update_spd_address(unsigned int ctrl_num,
 140                                unsigned int slot,
 141                                unsigned int *addr)
 142 {
 143 }
 144
 145 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 146                       unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 147 {
 148         unsigned int i;
 149         unsigned int i2c_address = 0;
 150
 151         if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
 152                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 153                 return;
 154         }
 155
 156         for (i = 0; i < dimm_slots_per_ctrl; i++) {
 157                 i2c_address = spd_i2c_addr[ctrl_num][i];
 158                 update_spd_address(ctrl_num, i, &i2c_address);
 159                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
 160         }
 161 }
 162 #else
 163 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 164                       unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 165 {
 166 }
 167 #endif /* SPD_EEPROM_ADDRESSx */
 168
 169 /*
 170  * ASSUMPTIONS:
 171  *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
 172  *    - Same memory data bus width on all controllers
 173  *
 174  * NOTES:
 175  *
 176  * The memory controller and associated documentation use confusing
 177  * terminology when referring to the orgranization of DRAM.
 178  *
 179  * Here is a terminology translation table:
 180  *
 181  * memory controller/documention  |industry   |this code  |signals
 182  * -------------------------------|-----------|-----------|-----------------
 183  * physical bank/bank             |rank       |rank       |chip select (CS)
 184  * logical bank/sub-bank          |bank       |bank       |bank address (BA)
 185  * page/row                       |row        |page       |row address
 186  * ???                            |column     |column     |column address
 187  *
 188  * The naming confusion is further exacerbated by the descriptions of the
 189  * memory controller interleaving feature, where accesses are interleaved
 190  * _BETWEEN_ two seperate memory controllers.  This is configured only in
 191  * CS0_CONFIG[INTLV_CTL] of each memory controller.
 192  *
 193  * memory controller documentation | number of chip selects
 194  *                                 | per memory controller supported
 195  * --------------------------------|-----------------------------------------
 196  * cache line interleaving         | 1 (CS0 only)
 197  * page interleaving               | 1 (CS0 only)
 198  * bank interleaving               | 1 (CS0 only)
 199  * superbank interleraving         | depends on bank (chip select)
 200  *                                 |   interleraving [rank interleaving]
 201  *                                 |   mode used on every memory controller
 202  *
 203  * Even further confusing is the existence of the interleaving feature
 204  * _WITHIN_ each memory controller.  The feature is referred to in
 205  * documentation as chip select interleaving or bank interleaving,
 206  * although it is configured in the DDR_SDRAM_CFG field.
 207  *
 208  * Name of field                | documentation name    | this code
 209  * -----------------------------|-----------------------|------------------
 210  * DDR_SDRAM_CFG[BA_INTLV_CTL]  | Bank (chip select)    | rank interleaving
 211  *                              |  interleaving
 212  */
 213
 214 const char *step_string_tbl[] = {
 215         "STEP_GET_SPD",
 216         "STEP_COMPUTE_DIMM_PARMS",
 217         "STEP_COMPUTE_COMMON_PARMS",
 218         "STEP_GATHER_OPTS",
 219         "STEP_ASSIGN_ADDRESSES",
 220         "STEP_COMPUTE_REGS",
 221         "STEP_PROGRAM_REGS",
 222         "STEP_ALL"
 223 };
 224
 225 const char * step_to_string(unsigned int step) {
 226
 227         unsigned int s = __ilog2(step);
 228
 229         if ((1 << s) != step)
 230                 return step_string_tbl[7];
 231
 232         if (s >= ARRAY_SIZE(step_string_tbl)) {
 233                 printf("Error for the step in %s\n", __func__);
 234                 s = 0;
 235         }
 236
 237         return step_string_tbl[s];
 238 }
 239
 240 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 241                           unsigned int dbw_cap_adj[])
 242 {
 243         unsigned int i, j;
 244         unsigned long long total_mem, current_mem_base, total_ctlr_mem;
 245         unsigned long long rank_density, ctlr_density = 0;
 246         unsigned int first_ctrl = pinfo->first_ctrl;
 247         unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 248
 249         /*
 250          * If a reduced data width is requested, but the SPD
 251          * specifies a physically wider device, adjust the
 252          * computed dimm capacities accordingly before
 253          * assigning addresses.
 254          */
 255         for (i = first_ctrl; i <= last_ctrl; i++) {
 256                 unsigned int found = 0;
 257
 258                 switch (pinfo->memctl_opts[i].data_bus_width) {
 259                 case 2:
 260                         /* 16-bit */
 261                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 262                                 unsigned int dw;
 263                                 if (!pinfo->dimm_params[i][j].n_ranks)
 264                                         continue;
 265                                 dw = pinfo->dimm_params[i][j].primary_sdram_width;
 266                                 if ((dw == 72 || dw == 64)) {
 267                                         dbw_cap_adj[i] = 2;
 268                                         break;
 269                                 } else if ((dw == 40 || dw == 32)) {
 270                                         dbw_cap_adj[i] = 1;
 271                                         break;
 272                                 }
 273                         }
 274                         break;
 275
 276                 case 1:
 277                         /* 32-bit */
 278                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 279                                 unsigned int dw;
 280                                 dw = pinfo->dimm_params[i][j].data_width;
 281                                 if (pinfo->dimm_params[i][j].n_ranks
 282                                     && (dw == 72 || dw == 64)) {
 283                                         /*
 284                                          * FIXME: can't really do it
 285                                          * like this because this just
 286                                          * further reduces the memory
 287                                          */
 288                                         found = 1;
 289                                         break;
 290                                 }
 291                         }
 292                         if (found) {
 293                                 dbw_cap_adj[i] = 1;
 294                         }
 295                         break;
 296
 297                 case 0:
 298                         /* 64-bit */
 299                         break;
 300
 301                 default:
 302                         printf("unexpected data bus width "
 303                                 "specified controller %u\n", i);
 304                         return 1;
 305                 }
 306                 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
 307         }
 308
 309         current_mem_base = pinfo->mem_base;
 310         total_mem = 0;
 311         if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
 312                 rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
 313                                         dbw_cap_adj[first_ctrl];
 314                 switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
 315                                         FSL_DDR_CS0_CS1_CS2_CS3) {
 316                 case FSL_DDR_CS0_CS1_CS2_CS3:
 317                         ctlr_density = 4 * rank_density;
 318                         break;
 319                 case FSL_DDR_CS0_CS1:
 320                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 321                         ctlr_density = 2 * rank_density;
 322                         break;
 323                 case FSL_DDR_CS2_CS3:
 324                 default:
 325                         ctlr_density = rank_density;
 326                         break;
 327                 }
 328                 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
 329                         rank_density, ctlr_density);
 330                 for (i = first_ctrl; i <= last_ctrl; i++) {
 331                         if (pinfo->memctl_opts[i].memctl_interleaving) {
 332                                 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
 333                                 case FSL_DDR_256B_INTERLEAVING:
 334                                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 335                                 case FSL_DDR_PAGE_INTERLEAVING:
 336                                 case FSL_DDR_BANK_INTERLEAVING:
 337                                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 338                                         total_ctlr_mem = 2 * ctlr_density;
 339                                         break;
 340                                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 341                                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 342                                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 343                                         total_ctlr_mem = 3 * ctlr_density;
 344                                         break;
 345                                 case FSL_DDR_4WAY_1KB_INTERLEAVING:
 346                                 case FSL_DDR_4WAY_4KB_INTERLEAVING:
 347                                 case FSL_DDR_4WAY_8KB_INTERLEAVING:
 348                                         total_ctlr_mem = 4 * ctlr_density;
 349                                         break;
 350                                 default:
 351                                         panic("Unknown interleaving mode");
 352                                 }
 353                                 pinfo->common_timing_params[i].base_address =
 354                                                         current_mem_base;
 355                                 pinfo->common_timing_params[i].total_mem =
 356                                                         total_ctlr_mem;
 357                                 total_mem = current_mem_base + total_ctlr_mem;
 358                                 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
 359                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 360                         } else {
 361                                 /* when 3rd controller not interleaved */
 362                                 current_mem_base = total_mem;
 363                                 total_ctlr_mem = 0;
 364                                 pinfo->common_timing_params[i].base_address =
 365                                                         current_mem_base;
 366                                 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 367                                         unsigned long long cap =
 368                                                 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 369                                         pinfo->dimm_params[i][j].base_address =
 370                                                 current_mem_base;
 371                                         debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 372                                         current_mem_base += cap;
 373                                         total_ctlr_mem += cap;
 374                                 }
 375                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 376                                 pinfo->common_timing_params[i].total_mem =
 377                                                         total_ctlr_mem;
 378                                 total_mem += total_ctlr_mem;
 379                         }
 380                 }
 381         } else {
 382                 /*
 383                  * Simple linear assignment if memory
 384                  * controllers are not interleaved.
 385                  */
 386                 for (i = first_ctrl; i <= last_ctrl; i++) {
 387                         total_ctlr_mem = 0;
 388                         pinfo->common_timing_params[i].base_address =
 389                                                 current_mem_base;
 390                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 391                                 /* Compute DIMM base addresses. */
 392                                 unsigned long long cap =
 393                                         pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 394                                 pinfo->dimm_params[i][j].base_address =
 395                                         current_mem_base;
 396                                 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 397                                 current_mem_base += cap;
 398                                 total_ctlr_mem += cap;
 399                         }
 400                         debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 401                         pinfo->common_timing_params[i].total_mem =
 402                                                         total_ctlr_mem;
 403                         total_mem += total_ctlr_mem;
 404                 }
 405         }
 406         debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
 407
 408         return total_mem;
 409 }
 410
 411 /* Use weak function to allow board file to override the address assignment */
 412 __attribute__((weak, alias("__step_assign_addresses")))
 413 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 414                           unsigned int dbw_cap_adj[]);
 415
 416 unsigned long long
 417 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 418                                        unsigned int size_only)
 419 {
 420         unsigned int i, j;
 421         unsigned long long total_mem = 0;
 422         int assert_reset = 0;
 423         unsigned int first_ctrl =  pinfo->first_ctrl;
 424         unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 425         __maybe_unused int retval;
 426         __maybe_unused bool goodspd = false;
 427         __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
 428
 429         fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 430         common_timing_params_t *timing_params = pinfo->common_timing_params;
 431         if (pinfo->board_need_mem_reset)
 432                 assert_reset = pinfo->board_need_mem_reset();
 433
 434         /* data bus width capacity adjust shift amount */
 435         unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
 436
 437         for (i = first_ctrl; i <= last_ctrl; i++)
 438                 dbw_capacity_adjust[i] = 0;
 439
 440         debug("starting at step %u (%s)\n",
 441               start_step, step_to_string(start_step));
 442
 443         switch (start_step) {
 444         case STEP_GET_SPD:
 445 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 446                 /* STEP 1:  Gather all DIMM SPD data */
 447                 for (i = first_ctrl; i <= last_ctrl; i++) {
 448                         fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
 449                                         dimm_slots_per_ctrl);
 450                 }
 451
 452         case STEP_COMPUTE_DIMM_PARMS:
 453                 /* STEP 2:  Compute DIMM parameters from SPD data */
 454
 455                 for (i = first_ctrl; i <= last_ctrl; i++) {
 456                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 457                                 generic_spd_eeprom_t *spd =
 458                                         &(pinfo->spd_installed_dimms[i][j]);
 459                                 dimm_params_t *pdimm =
 460                                         &(pinfo->dimm_params[i][j]);
 461                                 retval = compute_dimm_parameters(
 462                                                         i, spd, pdimm, j);
 463 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 464                                 if (!j && retval) {
 465                                         printf("SPD error on controller %d! "
 466                                         "Trying fallback to raw timing "
 467                                         "calculation\n", i);
 468                                         retval = fsl_ddr_get_dimm_params(pdimm,
 469                                                                          i, j);
 470                                 }
 471 #else
 472                                 if (retval == 2) {
 473                                         printf("Error: compute_dimm_parameters"
 474                                         " non-zero returned FATAL value "
 475                                         "for memctl=%u dimm=%u\n", i, j);
 476                                         return 0;
 477                                 }
 478 #endif
 479                                 if (retval) {
 480                                         debug("Warning: compute_dimm_parameters"
 481                                         " non-zero return value for memctl=%u "
 482                                         "dimm=%u\n", i, j);
 483                                 } else {
 484                                         goodspd = true;
 485                                 }
 486                         }
 487                 }
 488                 if (!goodspd) {
 489                         /*
 490                          * No valid SPD found
 491                          * Throw an error if this is for main memory, i.e.
 492                          * first_ctrl == 0. Otherwise, siliently return 0
 493                          * as the memory size.
 494                          */
 495                         if (first_ctrl == 0)
 496                                 printf("Error: No valid SPD detected.\n");
 497
 498                         return 0;
 499                 }
 500 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
 501         case STEP_COMPUTE_DIMM_PARMS:
 502                 for (i = first_ctrl; i <= last_ctrl; i++) {
 503                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 504                                 dimm_params_t *pdimm =
 505                                         &(pinfo->dimm_params[i][j]);
 506                                 fsl_ddr_get_dimm_params(pdimm, i, j);
 507                         }
 508                 }
 509                 debug("Filling dimm parameters from board specific file\n");
 510 #endif
 511         case STEP_COMPUTE_COMMON_PARMS:
 512                 /*
 513                  * STEP 3: Compute a common set of timing parameters
 514                  * suitable for all of the DIMMs on each memory controller
 515                  */
 516                 for (i = first_ctrl; i <= last_ctrl; i++) {
 517                         debug("Computing lowest common DIMM"
 518                                 " parameters for memctl=%u\n", i);
 519                         compute_lowest_common_dimm_parameters
 520                                 (i,
 521                                  pinfo->dimm_params[i],
 522                                  &timing_params[i],
 523                                  CONFIG_DIMM_SLOTS_PER_CTLR);
 524                 }
 525
 526         case STEP_GATHER_OPTS:
 527                 /* STEP 4:  Gather configuration requirements from user */
 528                 for (i = first_ctrl; i <= last_ctrl; i++) {
 529                         debug("Reloading memory controller "
 530                                 "configuration options for memctl=%u\n", i);
 531                         /*
 532                          * This "reloads" the memory controller options
 533                          * to defaults.  If the user "edits" an option,
 534                          * next_step points to the step after this,
 535                          * which is currently STEP_ASSIGN_ADDRESSES.
 536                          */
 537                         populate_memctl_options(
 538                                         &timing_params[i],
 539                                         &pinfo->memctl_opts[i],
 540                                         pinfo->dimm_params[i], i);
 541                         /*
 542                          * For RDIMMs, JEDEC spec requires clocks to be stable
 543                          * before reset signal is deasserted. For the boards
 544                          * using fixed parameters, this function should be
 545                          * be called from board init file.
 546                          */
 547                         if (timing_params[i].all_dimms_registered)
 548                                 assert_reset = 1;
 549                 }
 550                 if (assert_reset && !size_only) {
 551                         if (pinfo->board_mem_reset) {
 552                                 debug("Asserting mem reset\n");
 553                                 pinfo->board_mem_reset();
 554                         } else {
 555                                 debug("Asserting mem reset missing\n");
 556                         }
 557                 }
 558
 559         case STEP_ASSIGN_ADDRESSES:
 560                 /* STEP 5:  Assign addresses to chip selects */
 561                 check_interleaving_options(pinfo);
 562                 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
 563                 debug("Total mem %llu assigned\n", total_mem);
 564
 565         case STEP_COMPUTE_REGS:
 566                 /* STEP 6:  compute controller register values */
 567                 debug("FSL Memory ctrl register computation\n");
 568                 for (i = first_ctrl; i <= last_ctrl; i++) {
 569                         if (timing_params[i].ndimms_present == 0) {
 570                                 memset(&ddr_reg[i], 0,
 571                                         sizeof(fsl_ddr_cfg_regs_t));
 572                                 continue;
 573                         }
 574
 575                         compute_fsl_memctl_config_regs
 576                                 (i,
 577                                  &pinfo->memctl_opts[i],
 578                                  &ddr_reg[i], &timing_params[i],
 579                                  pinfo->dimm_params[i],
 580                                  dbw_capacity_adjust[i],
 581                                  size_only);
 582                 }
 583
 584         default:
 585                 break;
 586         }
 587
 588         {
 589                 /*
 590                  * Compute the amount of memory available just by
 591                  * looking for the highest valid CSn_BNDS value.
 592                  * This allows us to also experiment with using
 593                  * only CS0 when using dual-rank DIMMs.
 594                  */
 595                 unsigned int max_end = 0;
 596
 597                 for (i = first_ctrl; i <= last_ctrl; i++) {
 598                         for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 599                                 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 600                                 if (reg->cs[j].config & 0x80000000) {
 601                                         unsigned int end;
 602                                         /*
 603                                          * 0xfffffff is a special value we put
 604                                          * for unused bnds
 605                                          */
 606                                         if (reg->cs[j].bnds == 0xffffffff)
 607                                                 continue;
 608                                         end = reg->cs[j].bnds & 0xffff;
 609                                         if (end > max_end) {
 610                                                 max_end = end;
 611                                         }
 612                                 }
 613                         }
 614                 }
 615
 616                 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
 617                             0xFFFFFFULL) - pinfo->mem_base;
 618         }
 619
 620         return total_mem;
 621 }
 622
 623 phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 624 {
 625         unsigned int i, first_ctrl, last_ctrl;
 626 #ifdef CONFIG_PPC
 627         unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
 628 #endif
 629         unsigned long long total_memory;
 630         int deassert_reset = 0;
 631
 632         first_ctrl = pinfo->first_ctrl;
 633         last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 634
 635         /* Compute it once normally. */
 636 #ifdef CONFIG_FSL_DDR_INTERACTIVE
 637         if (tstc() && (getc() == 'd')) {        /* we got a key press of 'd' */
 638                 total_memory = fsl_ddr_interactive(pinfo, 0);
 639         } else if (fsl_ddr_interactive_env_var_exists()) {
 640                 total_memory = fsl_ddr_interactive(pinfo, 1);
 641         } else
 642 #endif
 643                 total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
 644
 645         /* setup 3-way interleaving before enabling DDRC */
 646         switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
 647         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 648         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 649         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 650                 fsl_ddr_set_intl3r(
 651                         pinfo->memctl_opts[first_ctrl].
 652                         memctl_interleaving_mode);
 653                 break;
 654         default:
 655                 break;
 656         }
 657
 658         /*
 659          * Program configuration registers.
 660          * JEDEC specs requires clocks to be stable before deasserting reset
 661          * for RDIMMs. Clocks start after chip select is enabled and clock
 662          * control register is set. During step 1, all controllers have their
 663          * registers set but not enabled. Step 2 proceeds after deasserting
 664          * reset through board FPGA or GPIO.
 665          * For non-registered DIMMs, initialization can go through but it is
 666          * also OK to follow the same flow.
 667          */
 668         if (pinfo->board_need_mem_reset)
 669                 deassert_reset = pinfo->board_need_mem_reset();
 670         for (i = first_ctrl; i <= last_ctrl; i++) {
 671                 if (pinfo->common_timing_params[i].all_dimms_registered)
 672                         deassert_reset = 1;
 673         }
 674         for (i = first_ctrl; i <= last_ctrl; i++) {
 675                 debug("Programming controller %u\n", i);
 676                 if (pinfo->common_timing_params[i].ndimms_present == 0) {
 677                         debug("No dimms present on controller %u; "
 678                                         "skipping programming\n", i);
 679                         continue;
 680                 }
 681                 /*
 682                  * The following call with step = 1 returns before enabling
 683                  * the controller. It has to finish with step = 2 later.
 684                  */
 685                 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
 686                                         deassert_reset ? 1 : 0);
 687         }
 688         if (deassert_reset) {
 689                 /* Use board FPGA or GPIO to deassert reset signal */
 690                 if (pinfo->board_mem_de_reset) {
 691                         debug("Deasserting mem reset\n");
 692                         pinfo->board_mem_de_reset();
 693                 } else {
 694                         debug("Deasserting mem reset missing\n");
 695                 }
 696                 for (i = first_ctrl; i <= last_ctrl; i++) {
 697                         /* Call with step = 2 to continue initialization */
 698                         fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
 699                                                 i, 2);
 700                 }
 701         }
 702
 703 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
 704         fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
 705 #endif
 706
 707 #ifdef CONFIG_PPC
 708         /* program LAWs */
 709         for (i = first_ctrl; i <= last_ctrl; i++) {
 710                 if (pinfo->memctl_opts[i].memctl_interleaving) {
 711                         switch (pinfo->memctl_opts[i].
 712                                 memctl_interleaving_mode) {
 713                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 714                         case FSL_DDR_PAGE_INTERLEAVING:
 715                         case FSL_DDR_BANK_INTERLEAVING:
 716                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 717                                 if (i % 2)
 718                                         break;
 719                                 if (i == 0) {
 720                                         law_memctl = LAW_TRGT_IF_DDR_INTRLV;
 721                                         fsl_ddr_set_lawbar(
 722                                                 &pinfo->common_timing_params[i],
 723                                                 law_memctl, i);
 724                                 }
 725 #if CONFIG_NUM_DDR_CONTROLLERS > 3
 726                                 else if (i == 2) {
 727                                         law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
 728                                         fsl_ddr_set_lawbar(
 729                                                 &pinfo->common_timing_params[i],
 730                                                 law_memctl, i);
 731                                 }
 732 #endif
 733                                 break;
 734                         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 735                         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 736                         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 737                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
 738                                 if (i == 0) {
 739                                         fsl_ddr_set_lawbar(
 740                                                 &pinfo->common_timing_params[i],
 741                                                 law_memctl, i);
 742                                 }
 743                                 break;
 744                         case FSL_DDR_4WAY_1KB_INTERLEAVING:
 745                         case FSL_DDR_4WAY_4KB_INTERLEAVING:
 746                         case FSL_DDR_4WAY_8KB_INTERLEAVING:
 747                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
 748                                 if (i == 0)
 749                                         fsl_ddr_set_lawbar(
 750                                                 &pinfo->common_timing_params[i],
 751                                                 law_memctl, i);
 752                                 /* place holder for future 4-way interleaving */
 753                                 break;
 754                         default:
 755                                 break;
 756                         }
 757                 } else {
 758                         switch (i) {
 759                         case 0:
 760                                 law_memctl = LAW_TRGT_IF_DDR_1;
 761                                 break;
 762                         case 1:
 763                                 law_memctl = LAW_TRGT_IF_DDR_2;
 764                                 break;
 765                         case 2:
 766                                 law_memctl = LAW_TRGT_IF_DDR_3;
 767                                 break;
 768                         case 3:
 769                                 law_memctl = LAW_TRGT_IF_DDR_4;
 770                                 break;
 771                         default:
 772                                 break;
 773                         }
 774                         fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
 775                                            law_memctl, i);
 776                 }
 777         }
 778 #endif
 779
 780         debug("total_memory by %s = %llu\n", __func__, total_memory);
 781
 782 #if !defined(CONFIG_PHYS_64BIT)
 783         /* Check for 4G or more.  Bad. */
 784         if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
 785                 puts("Detected ");
 786                 print_size(total_memory, " of memory\n");
 787                 printf("       This U-Boot only supports < 4G of DDR\n");
 788                 printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
 789                 printf("       "); /* re-align to match init_func_ram print */
 790                 total_memory = CONFIG_MAX_MEM_MAPPED;
 791         }
 792 #endif
 793
 794         return total_memory;
 795 }
 796
 797 /*
 798  * fsl_ddr_sdram(void) -- this is the main function to be
 799  * called by initdram() in the board file.
 800  *
 801  * It returns amount of memory configured in bytes.
 802  */
 803 phys_size_t fsl_ddr_sdram(void)
 804 {
 805         fsl_ddr_info_t info;
 806
 807         /* Reset info structure. */
 808         memset(&info, 0, sizeof(fsl_ddr_info_t));
 809         info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 810         info.first_ctrl = 0;
 811         info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
 812         info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
 813         info.board_need_mem_reset = board_need_mem_reset;
 814         info.board_mem_reset = board_assert_mem_reset;
 815         info.board_mem_de_reset = board_deassert_mem_reset;
 816
 817         return __fsl_ddr_sdram(&info);
 818 }
 819
 820 #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 821 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
 822                                 unsigned int first_ctrl,
 823                                 unsigned int num_ctrls,
 824                                 unsigned int dimm_slots_per_ctrl,
 825                                 int (*board_need_reset)(void),
 826                                 void (*board_reset)(void),
 827                                 void (*board_de_reset)(void))
 828 {
 829         fsl_ddr_info_t info;
 830
 831         /* Reset info structure. */
 832         memset(&info, 0, sizeof(fsl_ddr_info_t));
 833         info.mem_base = base;
 834         info.first_ctrl = first_ctrl;
 835         info.num_ctrls = num_ctrls;
 836         info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
 837         info.board_need_mem_reset = board_need_reset;
 838         info.board_mem_reset = board_reset;
 839         info.board_mem_de_reset = board_de_reset;
 840
 841         return __fsl_ddr_sdram(&info);
 842 }
 843 #endif
 844
 845 /*
 846  * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
 847  * size of the total memory without setting ddr control registers.
 848  */
 849 phys_size_t
 850 fsl_ddr_sdram_size(void)
 851 {
 852         fsl_ddr_info_t  info;
 853         unsigned long long total_memory = 0;
 854
 855         memset(&info, 0 , sizeof(fsl_ddr_info_t));
 856         info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 857         info.first_ctrl = 0;
 858         info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
 859         info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
 860         info.board_need_mem_reset = NULL;
 861
 862         /* Compute it once normally. */
 863         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
 864
 865         return total_memory;
 866 }