drivers/fsl_pci_init.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  16  * MA 02111-1307 USA
  17  */
  18 #define DEBUG
  19 #include <common.h>
  20
  21 #ifdef CONFIG_FSL_PCI_INIT
  22
  23 /*
  24  * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
  25  *
  26  * Initialize controller and call the common driver/pci pci_hose_scan to
  27  * scan for bridges and devices.
  28  *
  29  * Hose fields which need to be pre-initialized by board specific code:
  30  *   regions[]
  31  *   first_busno
  32  *
  33  * Fields updated:
  34  *   last_busno
  35  */
  36
  37 #include <pci.h>
  38 #include <asm/immap_fsl_pci.h>
  39
  40 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
  41                                 pci_dev_t dev, int sub_bus);
  42 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
  43                                 pci_dev_t dev, int sub_bus);
  44
  45 void pciauto_config_init(struct pci_controller *hose);
  46 void
  47 fsl_pci_init(struct pci_controller *hose)
  48 {
  49         u16 temp16;
  50         u32 temp32;
  51         int busno = hose->first_busno;
  52         int enabled;
  53         u16 ltssm;
  54         u8 temp8;
  55         int r;
  56         int bridge;
  57         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr;
  58         pci_dev_t dev = PCI_BDF(busno,0,0);
  59
  60         /* Initialize ATMU registers based on hose regions and flags */
  61         volatile pot_t *po=&pci->pot[1];        /* skip 0 */
  62         volatile pit_t *pi=&pci->pit[0];        /* ranges from: 3 to 1 */
  63
  64 #ifdef DEBUG
  65         int neg_link_w;
  66 #endif
  67
  68         for (r=0; r<hose->region_count; r++) {
  69                 if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
  70                         pi->pitar = (hose->regions[r].bus_start >> 12) & 0x000fffff;
  71                         pi->piwbar = (hose->regions[r].phys_start >> 12) & 0x000fffff;
  72                         pi->piwbear = 0;
  73                         pi->piwar = PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
  74                                 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP |
  75                                 (__ilog2(hose->regions[r].size) - 1);
  76                         pi++;
  77                 } else { /* Outbound */
  78                         po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff;
  79                         po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff;
  80                         po->potear = 0;
  81                         if (hose->regions[r].flags & PCI_REGION_IO)
  82                                 po->powar = POWAR_EN | POWAR_IO_READ | POWAR_IO_WRITE |
  83                                         (__ilog2(hose->regions[r].size) - 1);
  84                         else
  85                                 po->powar = POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE |
  86                                         (__ilog2(hose->regions[r].size) - 1);
  87                         po++;
  88                 }
  89         }
  90
  91         pci_register_hose(hose);
  92         pciauto_config_init(hose);      /* grab pci_{mem,prefetch,io} */
  93         hose->current_busno = hose->first_busno;
  94
  95         pci->pedr = 0xffffffff;         /* Clear any errors */
  96         pci->peer = 0xffffffff;         /* Enable Error Interupts */
  97         pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32);
  98         temp32 |= 0xf000e;              /* set URR, FER, NFER (but not CER) */
  99         pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
 100
 101         pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8);
 102         bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */
 103
 104         if ( bridge ) {
 105
 106                 pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
 107                 enabled = ltssm >= PCI_LTSSM_L0;
 108
 109                 if (!enabled) {
 110                         debug("....PCIE link error.  Skipping scan."
 111                               "LTSSM=0x%02x\n", temp16);
 112                         hose->last_busno = hose->first_busno;
 113                         return;
 114                 }
 115
 116                 pci->pme_msg_det = 0xffffffff;
 117                 pci->pme_msg_int_en = 0xffffffff;
 118 #ifdef DEBUG
 119                 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
 120                 neg_link_w = (temp16 & 0x3f0 ) >> 4;
 121                 debug("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
 122                       ltssm, neg_link_w);
 123 #endif
 124                 hose->current_busno++; /* Start scan with secondary */
 125                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 126
 127         } else {
 128 #if 0
 129 /* done in pci_hose_config_device() */
 130                 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
 131                 temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER |
 132                         PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
 133                 pci_hose_write_config_word(hose, dev, PCI_COMMAND, temp16);
 134                 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
 135                 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 136 #endif
 137         }
 138
 139         /* Call setup to allocate PCSRBAR window */
 140         pciauto_setup_device(hose, dev, 1, hose->pci_mem,
 141                              hose->pci_prefetch, hose->pci_io);
 142
 143         printf ("               Scanning PCI bus %02x\n", hose->current_busno);
 144         hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno);
 145
 146         if ( bridge ) { /* update limit regs and subordinate busno */
 147                 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
 148         }
 149
 150         /* Clear all error indications */
 151
 152         if (pci->pme_msg_det && pci->pme_msg_det != 0xffffffff) {
 153                 debug("pci_fsl_init: pme_msg_det@%x=%x.  Clearing\n",
 154                         &pci->pme_msg_det, pci->pme_msg_det);
 155                 pci->pme_msg_det = 0xffffffff;
 156         }
 157
 158         if (pci->pedr) {
 159                 debug("pci_fsl_init: pedr@%x=%x.  Clearing\n",
 160                         &pci->pedr, pci->pedr);
 161                 pci->pedr = 0xffffffff;
 162         }
 163
 164         pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
 165         if (temp16) {
 166                 debug("pci_fsl_init: PCI_DSR@%x=%x.  Clearing\n",
 167                         PCI_DSR, temp16);
 168                 pci_hose_write_config_word(hose, dev,
 169                                            PCI_DSR, 0xffff);
 170         }
 171
 172         pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
 173         if (temp16) {
 174                 debug("pci_fsl_init: PCI_SEC_STATUS@%x=%x.  Clearing\n",
 175                         PCI_SEC_STATUS, temp16);
 176                 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
 177         }
 178 }
 179
 180 #endif /* CONFIG_FSL_PCI */