drivers/mmc/dw_mmc.c

   1 /*
   2  * (C) Copyright 2012 SAMSUNG Electronics
   3  * Jaehoon Chung <jh80.chung@samsung.com>
   4  * Rajeshawari Shinde <rajeshwari.s@samsung.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <bouncebuf.h>
  10 #include <common.h>
  11 #include <errno.h>
  12 #include <malloc.h>
  13 #include <mmc.h>
  14 #include <dwmmc.h>
  15 #include <asm-generic/errno.h>
  16
  17 #define PAGE_SIZE 4096
  18
  19 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
  20 {
  21         unsigned long timeout = 1000;
  22         u32 ctrl;
  23
  24         dwmci_writel(host, DWMCI_CTRL, value);
  25
  26         while (timeout--) {
  27                 ctrl = dwmci_readl(host, DWMCI_CTRL);
  28                 if (!(ctrl & DWMCI_RESET_ALL))
  29                         return 1;
  30         }
  31         return 0;
  32 }
  33
  34 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
  35                 u32 desc0, u32 desc1, u32 desc2)
  36 {
  37         struct dwmci_idmac *desc = idmac;
  38
  39         desc->flags = desc0;
  40         desc->cnt = desc1;
  41         desc->addr = desc2;
  42         desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
  43 }
  44
  45 static void dwmci_prepare_data(struct dwmci_host *host,
  46                                struct mmc_data *data,
  47                                struct dwmci_idmac *cur_idmac,
  48                                void *bounce_buffer)
  49 {
  50         unsigned long ctrl;
  51         unsigned int i = 0, flags, cnt, blk_cnt;
  52         ulong data_start, data_end;
  53
  54
  55         blk_cnt = data->blocks;
  56
  57         dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  58
  59         data_start = (ulong)cur_idmac;
  60         dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
  61
  62         do {
  63                 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
  64                 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
  65                 if (blk_cnt <= 8) {
  66                         flags |= DWMCI_IDMAC_LD;
  67                         cnt = data->blocksize * blk_cnt;
  68                 } else
  69                         cnt = data->blocksize * 8;
  70
  71                 dwmci_set_idma_desc(cur_idmac, flags, cnt,
  72                                     (u32)bounce_buffer + (i * PAGE_SIZE));
  73
  74                 if (blk_cnt <= 8)
  75                         break;
  76                 blk_cnt -= 8;
  77                 cur_idmac++;
  78                 i++;
  79         } while(1);
  80
  81         data_end = (ulong)cur_idmac;
  82         flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
  83
  84         ctrl = dwmci_readl(host, DWMCI_CTRL);
  85         ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
  86         dwmci_writel(host, DWMCI_CTRL, ctrl);
  87
  88         ctrl = dwmci_readl(host, DWMCI_BMOD);
  89         ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
  90         dwmci_writel(host, DWMCI_BMOD, ctrl);
  91
  92         dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
  93         dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
  94 }
  95
  96 static int dwmci_set_transfer_mode(struct dwmci_host *host,
  97                 struct mmc_data *data)
  98 {
  99         unsigned long mode;
 100
 101         mode = DWMCI_CMD_DATA_EXP;
 102         if (data->flags & MMC_DATA_WRITE)
 103                 mode |= DWMCI_CMD_RW;
 104
 105         return mode;
 106 }
 107
 108 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 109                 struct mmc_data *data)
 110 {
 111         struct dwmci_host *host = mmc->priv;
 112         ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
 113                                  data ? DIV_ROUND_UP(data->blocks, 8) : 0);
 114         int ret = 0, flags = 0, i;
 115         unsigned int timeout = 100000;
 116         u32 retry = 10000;
 117         u32 mask, ctrl;
 118         ulong start = get_timer(0);
 119         struct bounce_buffer bbstate;
 120
 121         while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
 122                 if (get_timer(start) > timeout) {
 123                         debug("%s: Timeout on data busy\n", __func__);
 124                         return TIMEOUT;
 125                 }
 126         }
 127
 128         dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
 129
 130         if (data) {
 131                 if (data->flags == MMC_DATA_READ) {
 132                         bounce_buffer_start(&bbstate, (void*)data->dest,
 133                                             data->blocksize *
 134                                             data->blocks, GEN_BB_WRITE);
 135                 } else {
 136                         bounce_buffer_start(&bbstate, (void*)data->src,
 137                                             data->blocksize *
 138                                             data->blocks, GEN_BB_READ);
 139                 }
 140                 dwmci_prepare_data(host, data, cur_idmac,
 141                                    bbstate.bounce_buffer);
 142         }
 143
 144         dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 145
 146         if (data)
 147                 flags = dwmci_set_transfer_mode(host, data);
 148
 149         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 150                 return -1;
 151
 152         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 153                 flags |= DWMCI_CMD_ABORT_STOP;
 154         else
 155                 flags |= DWMCI_CMD_PRV_DAT_WAIT;
 156
 157         if (cmd->resp_type & MMC_RSP_PRESENT) {
 158                 flags |= DWMCI_CMD_RESP_EXP;
 159                 if (cmd->resp_type & MMC_RSP_136)
 160                         flags |= DWMCI_CMD_RESP_LENGTH;
 161         }
 162
 163         if (cmd->resp_type & MMC_RSP_CRC)
 164                 flags |= DWMCI_CMD_CHECK_CRC;
 165
 166         flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
 167
 168         debug("Sending CMD%d\n",cmd->cmdidx);
 169
 170         dwmci_writel(host, DWMCI_CMD, flags);
 171
 172         for (i = 0; i < retry; i++) {
 173                 mask = dwmci_readl(host, DWMCI_RINTSTS);
 174                 if (mask & DWMCI_INTMSK_CDONE) {
 175                         if (!data)
 176                                 dwmci_writel(host, DWMCI_RINTSTS, mask);
 177                         break;
 178                 }
 179         }
 180
 181         if (i == retry) {
 182                 debug("%s: Timeout.\n", __func__);
 183                 return TIMEOUT;
 184         }
 185
 186         if (mask & DWMCI_INTMSK_RTO) {
 187                 /*
 188                  * Timeout here is not necessarily fatal. (e)MMC cards
 189                  * will splat here when they receive CMD55 as they do
 190                  * not support this command and that is exactly the way
 191                  * to tell them apart from SD cards. Thus, this output
 192                  * below shall be debug(). eMMC cards also do not favor
 193                  * CMD8, please keep that in mind.
 194                  */
 195                 debug("%s: Response Timeout.\n", __func__);
 196                 return TIMEOUT;
 197         } else if (mask & DWMCI_INTMSK_RE) {
 198                 debug("%s: Response Error.\n", __func__);
 199                 return -EIO;
 200         }
 201
 202
 203         if (cmd->resp_type & MMC_RSP_PRESENT) {
 204                 if (cmd->resp_type & MMC_RSP_136) {
 205                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
 206                         cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
 207                         cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
 208                         cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
 209                 } else {
 210                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
 211                 }
 212         }
 213
 214         if (data) {
 215                 start = get_timer(0);
 216                 timeout = 1000;
 217                 for (;;) {
 218                         mask = dwmci_readl(host, DWMCI_RINTSTS);
 219                         /* Error during data transfer. */
 220                         if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
 221                                 debug("%s: DATA ERROR!\n", __func__);
 222                                 ret = -EINVAL;
 223                                 break;
 224                         }
 225
 226                         /* Data arrived correctly. */
 227                         if (mask & DWMCI_INTMSK_DTO) {
 228                                 ret = 0;
 229                                 break;
 230                         }
 231
 232                         /* Check for timeout. */
 233                         if (get_timer(start) > timeout) {
 234                                 debug("%s: Timeout waiting for data!\n",
 235                                        __func__);
 236                                 ret = TIMEOUT;
 237                                 break;
 238                         }
 239                 }
 240
 241                 dwmci_writel(host, DWMCI_RINTSTS, mask);
 242
 243                 ctrl = dwmci_readl(host, DWMCI_CTRL);
 244                 ctrl &= ~(DWMCI_DMA_EN);
 245                 dwmci_writel(host, DWMCI_CTRL, ctrl);
 246
 247                 bounce_buffer_stop(&bbstate);
 248         }
 249
 250         udelay(100);
 251
 252         return ret;
 253 }
 254
 255 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 256 {
 257         u32 div, status;
 258         int timeout = 10000;
 259         unsigned long sclk;
 260
 261         if ((freq == host->clock) || (freq == 0))
 262                 return 0;
 263         /*
 264          * If host->get_mmc_clk isn't defined,
 265          * then assume that host->bus_hz is source clock value.
 266          * host->bus_hz should be set by user.
 267          */
 268         if (host->get_mmc_clk)
 269                 sclk = host->get_mmc_clk(host);
 270         else if (host->bus_hz)
 271                 sclk = host->bus_hz;
 272         else {
 273                 debug("%s: Didn't get source clock value.\n", __func__);
 274                 return -EINVAL;
 275         }
 276
 277         if (sclk == freq)
 278                 div = 0;        /* bypass mode */
 279         else
 280                 div = DIV_ROUND_UP(sclk, 2 * freq);
 281
 282         dwmci_writel(host, DWMCI_CLKENA, 0);
 283         dwmci_writel(host, DWMCI_CLKSRC, 0);
 284
 285         dwmci_writel(host, DWMCI_CLKDIV, div);
 286         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 287                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 288
 289         do {
 290                 status = dwmci_readl(host, DWMCI_CMD);
 291                 if (timeout-- < 0) {
 292                         debug("%s: Timeout!\n", __func__);
 293                         return -ETIMEDOUT;
 294                 }
 295         } while (status & DWMCI_CMD_START);
 296
 297         dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
 298                         DWMCI_CLKEN_LOW_PWR);
 299
 300         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 301                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 302
 303         timeout = 10000;
 304         do {
 305                 status = dwmci_readl(host, DWMCI_CMD);
 306                 if (timeout-- < 0) {
 307                         debug("%s: Timeout!\n", __func__);
 308                         return -ETIMEDOUT;
 309                 }
 310         } while (status & DWMCI_CMD_START);
 311
 312         host->clock = freq;
 313
 314         return 0;
 315 }
 316
 317 static void dwmci_set_ios(struct mmc *mmc)
 318 {
 319         struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
 320         u32 ctype, regs;
 321
 322         debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
 323
 324         dwmci_setup_bus(host, mmc->clock);
 325         switch (mmc->bus_width) {
 326         case 8:
 327                 ctype = DWMCI_CTYPE_8BIT;
 328                 break;
 329         case 4:
 330                 ctype = DWMCI_CTYPE_4BIT;
 331                 break;
 332         default:
 333                 ctype = DWMCI_CTYPE_1BIT;
 334                 break;
 335         }
 336
 337         dwmci_writel(host, DWMCI_CTYPE, ctype);
 338
 339         regs = dwmci_readl(host, DWMCI_UHS_REG);
 340         if (mmc->ddr_mode)
 341                 regs |= DWMCI_DDR_MODE;
 342         else
 343                 regs &= ~DWMCI_DDR_MODE;
 344
 345         dwmci_writel(host, DWMCI_UHS_REG, regs);
 346
 347         if (host->clksel)
 348                 host->clksel(host);
 349 }
 350
 351 static int dwmci_init(struct mmc *mmc)
 352 {
 353         struct dwmci_host *host = mmc->priv;
 354
 355         if (host->board_init)
 356                 host->board_init(host);
 357
 358         dwmci_writel(host, DWMCI_PWREN, 1);
 359
 360         if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
 361                 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
 362                 return -EIO;
 363         }
 364
 365         /* Enumerate at 400KHz */
 366         dwmci_setup_bus(host, mmc->cfg->f_min);
 367
 368         dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
 369         dwmci_writel(host, DWMCI_INTMASK, 0);
 370
 371         dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
 372
 373         dwmci_writel(host, DWMCI_IDINTEN, 0);
 374         dwmci_writel(host, DWMCI_BMOD, 1);
 375
 376         if (host->fifoth_val) {
 377                 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
 378         }
 379
 380         dwmci_writel(host, DWMCI_CLKENA, 0);
 381         dwmci_writel(host, DWMCI_CLKSRC, 0);
 382
 383         return 0;
 384 }
 385
 386 static const struct mmc_ops dwmci_ops = {
 387         .send_cmd       = dwmci_send_cmd,
 388         .set_ios        = dwmci_set_ios,
 389         .init           = dwmci_init,
 390 };
 391
 392 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
 393 {
 394         host->cfg.name = host->name;
 395         host->cfg.ops = &dwmci_ops;
 396         host->cfg.f_min = min_clk;
 397         host->cfg.f_max = max_clk;
 398
 399         host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 400
 401         host->cfg.host_caps = host->caps;
 402
 403         if (host->buswidth == 8) {
 404                 host->cfg.host_caps |= MMC_MODE_8BIT;
 405                 host->cfg.host_caps &= ~MMC_MODE_4BIT;
 406         } else {
 407                 host->cfg.host_caps |= MMC_MODE_4BIT;
 408                 host->cfg.host_caps &= ~MMC_MODE_8BIT;
 409         }
 410         host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 411
 412         host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 413
 414         host->mmc = mmc_create(&host->cfg, host);
 415         if (host->mmc == NULL)
 416                 return -1;
 417
 418         return 0;
 419 }