drivers/mmc/dw_mmc.c

   1 /*
   2  * (C) Copyright 2012 SAMSUNG Electronics
   3  * Jaehoon Chung <jh80.chung@samsung.com>
   4  * Rajeshawari Shinde <rajeshwari.s@samsung.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <bouncebuf.h>
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <mmc.h>
  13 #include <dwmmc.h>
  14 #include <asm-generic/errno.h>
  15
  16 #define PAGE_SIZE 4096
  17
  18 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
  19 {
  20         unsigned long timeout = 1000;
  21         u32 ctrl;
  22
  23         dwmci_writel(host, DWMCI_CTRL, value);
  24
  25         while (timeout--) {
  26                 ctrl = dwmci_readl(host, DWMCI_CTRL);
  27                 if (!(ctrl & DWMCI_RESET_ALL))
  28                         return 1;
  29         }
  30         return 0;
  31 }
  32
  33 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
  34                 u32 desc0, u32 desc1, u32 desc2)
  35 {
  36         struct dwmci_idmac *desc = idmac;
  37
  38         desc->flags = desc0;
  39         desc->cnt = desc1;
  40         desc->addr = desc2;
  41         desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
  42 }
  43
  44 static void dwmci_prepare_data(struct dwmci_host *host,
  45                                struct mmc_data *data,
  46                                struct dwmci_idmac *cur_idmac,
  47                                void *bounce_buffer)
  48 {
  49         unsigned long ctrl;
  50         unsigned int i = 0, flags, cnt, blk_cnt;
  51         ulong data_start, data_end;
  52
  53
  54         blk_cnt = data->blocks;
  55
  56         dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  57
  58         data_start = (ulong)cur_idmac;
  59         dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
  60
  61         do {
  62                 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
  63                 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
  64                 if (blk_cnt <= 8) {
  65                         flags |= DWMCI_IDMAC_LD;
  66                         cnt = data->blocksize * blk_cnt;
  67                 } else
  68                         cnt = data->blocksize * 8;
  69
  70                 dwmci_set_idma_desc(cur_idmac, flags, cnt,
  71                                     (u32)bounce_buffer + (i * PAGE_SIZE));
  72
  73                 if (blk_cnt <= 8)
  74                         break;
  75                 blk_cnt -= 8;
  76                 cur_idmac++;
  77                 i++;
  78         } while(1);
  79
  80         data_end = (ulong)cur_idmac;
  81         flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
  82
  83         ctrl = dwmci_readl(host, DWMCI_CTRL);
  84         ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
  85         dwmci_writel(host, DWMCI_CTRL, ctrl);
  86
  87         ctrl = dwmci_readl(host, DWMCI_BMOD);
  88         ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
  89         dwmci_writel(host, DWMCI_BMOD, ctrl);
  90
  91         dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
  92         dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
  93 }
  94
  95 static int dwmci_set_transfer_mode(struct dwmci_host *host,
  96                 struct mmc_data *data)
  97 {
  98         unsigned long mode;
  99
 100         mode = DWMCI_CMD_DATA_EXP;
 101         if (data->flags & MMC_DATA_WRITE)
 102                 mode |= DWMCI_CMD_RW;
 103
 104         return mode;
 105 }
 106
 107 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 108                 struct mmc_data *data)
 109 {
 110         struct dwmci_host *host = mmc->priv;
 111         ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
 112                                  data ? DIV_ROUND_UP(data->blocks, 8) : 0);
 113         int ret = 0, flags = 0, i;
 114         unsigned int timeout = 100000;
 115         u32 retry = 10000;
 116         u32 mask, ctrl;
 117         ulong start = get_timer(0);
 118         struct bounce_buffer bbstate;
 119
 120         while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
 121                 if (get_timer(start) > timeout) {
 122                         printf("%s: Timeout on data busy\n", __func__);
 123                         return TIMEOUT;
 124                 }
 125         }
 126
 127         dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
 128
 129         if (data) {
 130                 if (data->flags == MMC_DATA_READ) {
 131                         bounce_buffer_start(&bbstate, (void*)data->dest,
 132                                             data->blocksize *
 133                                             data->blocks, GEN_BB_WRITE);
 134                 } else {
 135                         bounce_buffer_start(&bbstate, (void*)data->src,
 136                                             data->blocksize *
 137                                             data->blocks, GEN_BB_READ);
 138                 }
 139                 dwmci_prepare_data(host, data, cur_idmac,
 140                                    bbstate.bounce_buffer);
 141         }
 142
 143         dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 144
 145         if (data)
 146                 flags = dwmci_set_transfer_mode(host, data);
 147
 148         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 149                 return -1;
 150
 151         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 152                 flags |= DWMCI_CMD_ABORT_STOP;
 153         else
 154                 flags |= DWMCI_CMD_PRV_DAT_WAIT;
 155
 156         if (cmd->resp_type & MMC_RSP_PRESENT) {
 157                 flags |= DWMCI_CMD_RESP_EXP;
 158                 if (cmd->resp_type & MMC_RSP_136)
 159                         flags |= DWMCI_CMD_RESP_LENGTH;
 160         }
 161
 162         if (cmd->resp_type & MMC_RSP_CRC)
 163                 flags |= DWMCI_CMD_CHECK_CRC;
 164
 165         flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
 166
 167         debug("Sending CMD%d\n",cmd->cmdidx);
 168
 169         dwmci_writel(host, DWMCI_CMD, flags);
 170
 171         for (i = 0; i < retry; i++) {
 172                 mask = dwmci_readl(host, DWMCI_RINTSTS);
 173                 if (mask & DWMCI_INTMSK_CDONE) {
 174                         if (!data)
 175                                 dwmci_writel(host, DWMCI_RINTSTS, mask);
 176                         break;
 177                 }
 178         }
 179
 180         if (i == retry) {
 181                 printf("%s: Timeout.\n", __func__);
 182                 return TIMEOUT;
 183         }
 184
 185         if (mask & DWMCI_INTMSK_RTO) {
 186                 /*
 187                  * Timeout here is not necessarily fatal. (e)MMC cards
 188                  * will splat here when they receive CMD55 as they do
 189                  * not support this command and that is exactly the way
 190                  * to tell them apart from SD cards. Thus, this output
 191                  * below shall be debug(). eMMC cards also do not favor
 192                  * CMD8, please keep that in mind.
 193                  */
 194                 debug("%s: Response Timeout.\n", __func__);
 195                 return TIMEOUT;
 196         } else if (mask & DWMCI_INTMSK_RE) {
 197                 printf("%s: Response Error.\n", __func__);
 198                 return -1;
 199         }
 200
 201
 202         if (cmd->resp_type & MMC_RSP_PRESENT) {
 203                 if (cmd->resp_type & MMC_RSP_136) {
 204                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
 205                         cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
 206                         cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
 207                         cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
 208                 } else {
 209                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
 210                 }
 211         }
 212
 213         if (data) {
 214                 start = get_timer(0);
 215                 timeout = 1000;
 216                 for (;;) {
 217                         mask = dwmci_readl(host, DWMCI_RINTSTS);
 218                         /* Error during data transfer. */
 219                         if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
 220                                 printf("%s: DATA ERROR!\n", __func__);
 221                                 ret = -EINVAL;
 222                                 break;
 223                         }
 224
 225                         /* Data arrived correctly. */
 226                         if (mask & DWMCI_INTMSK_DTO) {
 227                                 ret = 0;
 228                                 break;
 229                         }
 230
 231                         /* Check for timeout. */
 232                         if (get_timer(start) > timeout) {
 233                                 printf("%s: Timeout waiting for data!\n",
 234                                        __func__);
 235                                 ret = TIMEOUT;
 236                                 break;
 237                         }
 238                 }
 239
 240                 dwmci_writel(host, DWMCI_RINTSTS, mask);
 241
 242                 ctrl = dwmci_readl(host, DWMCI_CTRL);
 243                 ctrl &= ~(DWMCI_DMA_EN);
 244                 dwmci_writel(host, DWMCI_CTRL, ctrl);
 245
 246                 bounce_buffer_stop(&bbstate);
 247         }
 248
 249         udelay(100);
 250
 251         return ret;
 252 }
 253
 254 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 255 {
 256         u32 div, status;
 257         int timeout = 10000;
 258         unsigned long sclk;
 259
 260         if ((freq == host->clock) || (freq == 0))
 261                 return 0;
 262         /*
 263          * If host->get_mmc_clk isn't defined,
 264          * then assume that host->bus_hz is source clock value.
 265          * host->bus_hz should be set by user.
 266          */
 267         if (host->get_mmc_clk)
 268                 sclk = host->get_mmc_clk(host);
 269         else if (host->bus_hz)
 270                 sclk = host->bus_hz;
 271         else {
 272                 printf("%s: Didn't get source clock value.\n", __func__);
 273                 return -EINVAL;
 274         }
 275
 276         if (sclk == freq)
 277                 div = 0;        /* bypass mode */
 278         else
 279                 div = DIV_ROUND_UP(sclk, 2 * freq);
 280
 281         dwmci_writel(host, DWMCI_CLKENA, 0);
 282         dwmci_writel(host, DWMCI_CLKSRC, 0);
 283
 284         dwmci_writel(host, DWMCI_CLKDIV, div);
 285         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 286                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 287
 288         do {
 289                 status = dwmci_readl(host, DWMCI_CMD);
 290                 if (timeout-- < 0) {
 291                         printf("%s: Timeout!\n", __func__);
 292                         return -ETIMEDOUT;
 293                 }
 294         } while (status & DWMCI_CMD_START);
 295
 296         dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
 297                         DWMCI_CLKEN_LOW_PWR);
 298
 299         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 300                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 301
 302         timeout = 10000;
 303         do {
 304                 status = dwmci_readl(host, DWMCI_CMD);
 305                 if (timeout-- < 0) {
 306                         printf("%s: Timeout!\n", __func__);
 307                         return -ETIMEDOUT;
 308                 }
 309         } while (status & DWMCI_CMD_START);
 310
 311         host->clock = freq;
 312
 313         return 0;
 314 }
 315
 316 static void dwmci_set_ios(struct mmc *mmc)
 317 {
 318         struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
 319         u32 ctype, regs;
 320
 321         debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
 322
 323         dwmci_setup_bus(host, mmc->clock);
 324         switch (mmc->bus_width) {
 325         case 8:
 326                 ctype = DWMCI_CTYPE_8BIT;
 327                 break;
 328         case 4:
 329                 ctype = DWMCI_CTYPE_4BIT;
 330                 break;
 331         default:
 332                 ctype = DWMCI_CTYPE_1BIT;
 333                 break;
 334         }
 335
 336         dwmci_writel(host, DWMCI_CTYPE, ctype);
 337
 338         regs = dwmci_readl(host, DWMCI_UHS_REG);
 339         if (mmc->ddr_mode)
 340                 regs |= DWMCI_DDR_MODE;
 341         else
 342                 regs &= ~DWMCI_DDR_MODE;
 343
 344         dwmci_writel(host, DWMCI_UHS_REG, regs);
 345
 346         if (host->clksel)
 347                 host->clksel(host);
 348 }
 349
 350 static int dwmci_init(struct mmc *mmc)
 351 {
 352         struct dwmci_host *host = mmc->priv;
 353
 354         if (host->board_init)
 355                 host->board_init(host);
 356
 357         dwmci_writel(host, DWMCI_PWREN, 1);
 358
 359         if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
 360                 printf("%s[%d] Fail-reset!!\n", __func__, __LINE__);
 361                 return -1;
 362         }
 363
 364         /* Enumerate at 400KHz */
 365         dwmci_setup_bus(host, mmc->cfg->f_min);
 366
 367         dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
 368         dwmci_writel(host, DWMCI_INTMASK, 0);
 369
 370         dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
 371
 372         dwmci_writel(host, DWMCI_IDINTEN, 0);
 373         dwmci_writel(host, DWMCI_BMOD, 1);
 374
 375         if (host->fifoth_val) {
 376                 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
 377         }
 378
 379         dwmci_writel(host, DWMCI_CLKENA, 0);
 380         dwmci_writel(host, DWMCI_CLKSRC, 0);
 381
 382         return 0;
 383 }
 384
 385 static const struct mmc_ops dwmci_ops = {
 386         .send_cmd       = dwmci_send_cmd,
 387         .set_ios        = dwmci_set_ios,
 388         .init           = dwmci_init,
 389 };
 390
 391 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
 392 {
 393         host->cfg.name = host->name;
 394         host->cfg.ops = &dwmci_ops;
 395         host->cfg.f_min = min_clk;
 396         host->cfg.f_max = max_clk;
 397
 398         host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 399
 400         host->cfg.host_caps = host->caps;
 401
 402         if (host->buswidth == 8) {
 403                 host->cfg.host_caps |= MMC_MODE_8BIT;
 404                 host->cfg.host_caps &= ~MMC_MODE_4BIT;
 405         } else {
 406                 host->cfg.host_caps |= MMC_MODE_4BIT;
 407                 host->cfg.host_caps &= ~MMC_MODE_8BIT;
 408         }
 409         host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 410
 411         host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 412
 413         host->mmc = mmc_create(&host->cfg, host);
 414         if (host->mmc == NULL)
 415                 return -1;
 416
 417         return 0;
 418 }