drivers/mmc/ftsdc010_esdhc.c

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <config.h>
  25 #include <common.h>
  26 #include <mmc.h>
  27
  28 #include <asm/io.h>
  29 #include <faraday/ftsdc010.h>
  30
  31 /*
  32  * supported mmc hosts
  33  * setting the number CONFIG_FTSDC010_NUMBER in your configuration file.
  34  */
  35 static struct mmc ftsdc010_dev[CONFIG_FTSDC010_NUMBER];
  36 static struct mmc_host ftsdc010_host[CONFIG_FTSDC010_NUMBER];
  37
  38 static struct ftsdc010_mmc *ftsdc010_get_base_mmc(int dev_index)
  39 {
  40         return (struct ftsdc010_mmc *)CONFIG_FTSDC010_BASE + dev_index;
  41 }
  42
  43 #ifdef DEBUG
  44 static void ftsdc010_dump_reg(struct mmc_host *host)
  45 {
  46         debug("cmd: %08x\n",            readl(&host->reg->cmd));
  47         debug("argu: %08x\n",           readl(&host->reg->argu));
  48         debug("rsp0: %08x\n",           readl(&host->reg->rsp0));
  49         debug("rsp1: %08x\n",           readl(&host->reg->rsp1));
  50         debug("rsp2: %08x\n",           readl(&host->reg->rsp2));
  51         debug("rsp3: %08x\n",           readl(&host->reg->rsp3));
  52         debug("rsp_cmd: %08x\n",        readl(&host->reg->rsp_cmd));
  53         debug("dcr: %08x\n",            readl(&host->reg->dcr));
  54         debug("dtr: %08x\n",            readl(&host->reg->dtr));
  55         debug("dlr: %08x\n",            readl(&host->reg->dlr));
  56         debug("status: %08x\n",         readl(&host->reg->status));
  57         debug("clr: %08x\n",            readl(&host->reg->clr));
  58         debug("int_mask: %08x\n",       readl(&host->reg->int_mask));
  59         debug("pcr: %08x\n",            readl(&host->reg->pcr));
  60         debug("ccr: %08x\n",            readl(&host->reg->ccr));
  61         debug("bwr: %08x\n",            readl(&host->reg->bwr));
  62         debug("dwr: %08x\n",            readl(&host->reg->dwr));
  63         debug("feature: %08x\n",        readl(&host->reg->feature));
  64         debug("rev: %08x\n",            readl(&host->reg->rev));
  65 }
  66 #endif
  67
  68 static unsigned int enable_imask(struct ftsdc010_mmc *reg, unsigned int imask)
  69 {
  70         unsigned int newmask;
  71
  72         newmask = readl(&reg->int_mask);
  73         newmask |= imask;
  74
  75         writel(newmask, &reg->int_mask);
  76
  77         return newmask;
  78 }
  79
  80 static void ftsdc010_pio_read(struct mmc_host *host, char *buf, unsigned int size)
  81 {
  82         unsigned int fifo;
  83         unsigned int fifo_words;
  84         unsigned int *ptr;
  85         unsigned int status;
  86         unsigned int retry = 0;
  87
  88         /* get_data_buffer */
  89         ptr = (unsigned int *)buf;
  90
  91         while (size) {
  92                 status = readl(&host->reg->status);
  93
  94                 if (status & FTSDC010_STATUS_FIFO_ORUN) {
  95                         fifo = host->fifo_len > size ?
  96                                 size : host->fifo_len;
  97
  98                         size -= fifo;
  99
 100                         fifo_words = fifo >> 2;
 101
 102                         while (fifo_words--)
 103                                 *ptr++ = readl(&host->reg->dwr);
 104
 105                         /*
 106                          * for adding some delays for SD card to put
 107                          * data into FIFO again
 108                          */
 109                         udelay(4*FTSDC010_DELAY_UNIT);
 110
 111 #ifdef CONFIG_FTSDC010_SDIO
 112                         /* sdio allow non-power-of-2 blksz */
 113                         if (fifo & 3) {
 114                                 unsigned int n = fifo & 3;
 115                                 unsigned int data = readl(&host->reg->dwr);
 116
 117                                 unsigned char *p = (unsigned char *)ptr;
 118
 119                                 while (n--) {
 120                                         *p++ = data;
 121                                         data >>= 8;
 122                                 }
 123                         }
 124 #endif
 125                 } else {
 126                         udelay(1);
 127                         if (++retry >= FTSDC010_PIO_RETRY) {
 128                                 debug("%s: PIO_RETRY timeout\n", __func__);
 129                                 return;
 130                         }
 131                 }
 132         }
 133 }
 134
 135 static void ftsdc010_pio_write(struct mmc_host *host, const char *buf,
 136                         unsigned int size)
 137 {
 138         unsigned int fifo;
 139         unsigned int *ptr;
 140         unsigned int status;
 141         unsigned int retry = 0;
 142
 143         /* get data buffer */
 144         ptr = (unsigned int *)buf;
 145
 146         while (size) {
 147                 status = readl(&host->reg->status);
 148
 149                 if (status & FTSDC010_STATUS_FIFO_ORUN) {
 150                         fifo = host->fifo_len > size ?
 151                                 size : host->fifo_len;
 152
 153                         size -= fifo;
 154
 155                         fifo = (fifo + 3) >> 2;
 156
 157                         while (fifo--) {
 158                                 writel(*ptr, &host->reg->dwr);
 159                                 ptr++;
 160                         }
 161
 162                 } else {
 163                         udelay(1);
 164                         if (++retry >= FTSDC010_PIO_RETRY) {
 165                                 debug("%s: PIO_RETRY timeout\n", __func__);
 166                                 return;
 167                         }
 168                 }
 169         }
 170 }
 171
 172 static int ftsdc010_pio_check_status(struct mmc *mmc, struct mmc_cmd *cmd,
 173                         struct mmc_data *data)
 174 {
 175         struct mmc_host *host = mmc->priv;
 176
 177         unsigned int sta, clear;
 178         unsigned int i;
 179
 180         /* check response and hardware status */
 181         clear = 0;
 182
 183         /* chech CMD_SEND */
 184         for (i = 0; i < FTSDC010_CMD_RETRY; i++) {
 185                 sta = readl(&host->reg->status);
 186                 /* Command Complete */
 187                 if (sta & FTSDC010_STATUS_CMD_SEND) {
 188                         if (!data)
 189                                 clear |= FTSDC010_CLR_CMD_SEND;
 190                         break;
 191                 }
 192         }
 193
 194         if (i > FTSDC010_CMD_RETRY) {
 195                 printf("%s: send command timeout\n", __func__);
 196                 return TIMEOUT;
 197         }
 198
 199         /* debug: print status register and command index*/
 200         debug("sta: %08x cmd %d\n", sta, cmd->cmdidx);
 201
 202         /* handle data FIFO */
 203         if ((sta & FTSDC010_STATUS_FIFO_ORUN) ||
 204                 (sta & FTSDC010_STATUS_FIFO_URUN)) {
 205
 206                 /* Wrong DATA FIFO Flag */
 207                 if (data == NULL)
 208                         printf("%s, data fifo wrong: sta: %08x cmd %d\n",
 209                                 __func__, sta, cmd->cmdidx);
 210
 211                 if (sta & FTSDC010_STATUS_FIFO_ORUN)
 212                         clear |= FTSDC010_STATUS_FIFO_ORUN;
 213                 if (sta & FTSDC010_STATUS_FIFO_URUN)
 214                         clear |= FTSDC010_STATUS_FIFO_URUN;
 215         }
 216
 217         /* check RSP TIMEOUT or FAIL */
 218         if (sta & FTSDC010_STATUS_RSP_TIMEOUT) {
 219                 /* RSP TIMEOUT */
 220                 debug("%s: RSP timeout: sta: %08x cmd %d\n",
 221                                 __func__, sta, cmd->cmdidx);
 222
 223                 clear |= FTSDC010_CLR_RSP_TIMEOUT;
 224                 writel(clear, &host->reg->clr);
 225
 226                 return TIMEOUT;
 227         } else if (sta & FTSDC010_STATUS_RSP_CRC_FAIL) {
 228                 /* clear response fail bit */
 229                 debug("%s: RSP CRC FAIL: sta: %08x cmd %d\n",
 230                                 __func__, sta, cmd->cmdidx);
 231
 232                 clear |= FTSDC010_CLR_RSP_CRC_FAIL;
 233                 writel(clear, &host->reg->clr);
 234
 235                 return 0;
 236         } else if (sta & FTSDC010_STATUS_RSP_CRC_OK) {
 237
 238                 /* clear response CRC OK bit */
 239                 clear |= FTSDC010_CLR_RSP_CRC_OK;
 240         }
 241
 242         /* check DATA TIMEOUT or FAIL */
 243         if (data) {
 244                 if (sta & FTSDC010_STATUS_DATA_TIMEOUT) {
 245                         /* DATA TIMEOUT */
 246                         debug("%s: DATA TIMEOUT: sta: %08x\n",
 247                                         __func__, sta);
 248
 249                         clear |= FTSDC010_STATUS_DATA_TIMEOUT;
 250                         writel(sta, &host->reg->clr);
 251                         return TIMEOUT;
 252                 } else if (sta & FTSDC010_STATUS_DATA_CRC_FAIL) {
 253                         /* Error Interrupt */
 254                         debug("%s: DATA CRC FAIL: sta: %08x\n",
 255                                         __func__, sta);
 256
 257                         clear |= FTSDC010_STATUS_DATA_CRC_FAIL;
 258                         writel(clear, &host->reg->clr);
 259
 260                         return 0;
 261                 } else if (sta & FTSDC010_STATUS_DATA_END) {
 262                         /* Transfer Complete */
 263                         clear |= FTSDC010_STATUS_DATA_END;
 264                 }
 265         }
 266
 267         /* transaction is success and clear status register */
 268         writel(clear, &host->reg->clr);
 269
 270         return 0;
 271 }
 272
 273 static int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 274                         struct mmc_data *data)
 275 {
 276         struct mmc_host *host = mmc->priv;
 277
 278 #ifdef CONFIG_FTSDC010_SDIO
 279         unsigned int scon;
 280 #endif
 281         unsigned int ccon;
 282         unsigned int mask, tmpmask;
 283         unsigned int ret;
 284
 285         if (data)
 286                 mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
 287         else if (cmd->resp_type & MMC_RSP_PRESENT)
 288                 mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
 289         else
 290                 mask = FTSDC010_INT_MASK_CMD_SEND;
 291
 292         /* write argu reg */
 293         debug("%s: cmd->arg: %08x\n", __func__, cmd->cmdarg);
 294         writel(cmd->cmdarg, &host->reg->argu);
 295
 296         /* setup cmd reg */
 297         debug("cmd: %d\n", cmd->cmdidx);
 298         debug("resp: %08x\n", cmd->resp_type);
 299
 300         /* setup commnad */
 301         ccon = FTSDC010_CMD_IDX(cmd->cmdidx);
 302
 303         /* setup command flags */
 304         ccon |= FTSDC010_CMD_CMD_EN;
 305
 306         /*
 307          * This hardware didn't support specific commands for mapping
 308          * MMC_RSP_BUSY and MMC_RSP_OPCODE. Hence we don't deal with it.
 309          */
 310         if (cmd->resp_type & MMC_RSP_PRESENT) {
 311                 ccon |= FTSDC010_CMD_NEED_RSP;
 312                 mask |= FTSDC010_INT_MASK_RSP_CRC_OK |
 313                         FTSDC010_INT_MASK_RSP_CRC_FAIL;
 314         }
 315
 316         if (cmd->resp_type & MMC_RSP_136)
 317                 ccon |= FTSDC010_CMD_LONG_RSP;
 318
 319         /* In Linux driver, MMC_CMD_APP_CMD is checked in last_opcode */
 320         if (host->last_opcode == MMC_CMD_APP_CMD)
 321                 ccon |= FTSDC010_CMD_APP_CMD;
 322
 323 #ifdef CONFIG_FTSDC010_SDIO
 324         scon = readl(&host->reg->sdio_ctrl1);
 325         if (host->card_type == MMC_TYPE_SDIO)
 326                 scon |= FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
 327         else
 328                 scon &= ~FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
 329         writel(scon, &host->reg->sdio_ctrl1);
 330 #endif
 331
 332         /* record last opcode for specifing the command type to hardware */
 333         host->last_opcode = cmd->cmdidx;
 334
 335         /* write int_mask reg */
 336         tmpmask = readl(&host->reg->int_mask);
 337         tmpmask |= mask;
 338         writel(tmpmask, &host->reg->int_mask);
 339
 340         /* write cmd reg */
 341         debug("%s: ccon: %08x\n", __func__, ccon);
 342         writel(ccon, &host->reg->cmd);
 343         udelay(4*FTSDC010_DELAY_UNIT);
 344
 345         /* read/write data */
 346         if (data && (data->flags & MMC_DATA_READ)) {
 347                 ftsdc010_pio_read(host, data->dest,
 348                                 data->blocksize * data->blocks);
 349         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 350                 ftsdc010_pio_write(host, data->src,
 351                                 data->blocksize * data->blocks);
 352         }
 353
 354         /* pio check response status */
 355         ret = ftsdc010_pio_check_status(mmc, cmd, data);
 356         if (!ret) {
 357                 /* if it is long response */
 358                 if (ccon & FTSDC010_CMD_LONG_RSP) {
 359                         cmd->response[0] = readl(&host->reg->rsp3);
 360                         cmd->response[1] = readl(&host->reg->rsp2);
 361                         cmd->response[2] = readl(&host->reg->rsp1);
 362                         cmd->response[3] = readl(&host->reg->rsp0);
 363
 364                 } else {
 365                         cmd->response[0] = readl(&host->reg->rsp0);
 366                 }
 367         }
 368
 369         udelay(FTSDC010_DELAY_UNIT);
 370         return ret;
 371 }
 372
 373 static unsigned int cal_blksz(unsigned int blksz)
 374 {
 375         unsigned int blksztwo = 0;
 376
 377         while (blksz >>= 1)
 378                 blksztwo++;
 379
 380         return blksztwo;
 381 }
 382
 383 static int ftsdc010_setup_data(struct mmc *mmc, struct mmc_data *data)
 384 {
 385         struct mmc_host *host = mmc->priv;
 386         unsigned int dcon, newmask;
 387
 388         /* configure data transfer paramter */
 389         if (!data)
 390                 return 0;
 391
 392         if (((data->blocksize - 1) & data->blocksize) != 0) {
 393                 printf("%s: can't do non-power-of 2 sized block transfers"
 394                         " (blksz %d)\n", __func__, data->blocksize);
 395                 return -1;
 396         }
 397
 398         /*
 399          * We cannot deal with unaligned blocks with more than
 400          * one block being transfered.
 401          */
 402         if ((data->blocksize <= 2) && (data->blocks > 1)) {
 403                         printf("%s: can't do non-word sized block transfers"
 404                                 " (blksz %d)\n", __func__, data->blocksize);
 405                         return -1;
 406         }
 407
 408         /* data length */
 409         dcon = data->blocksize * data->blocks;
 410         writel(dcon, &host->reg->dlr);
 411
 412         /* write data control */
 413         dcon = cal_blksz(data->blocksize);
 414
 415         /* add to IMASK register */
 416         newmask = (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT);
 417
 418         /*
 419          * enable UNDERRUN will trigger interrupt immediatedly
 420          * So setup it when rsp is received successfully
 421          */
 422         if (data->flags & MMC_DATA_WRITE) {
 423                 dcon |= FTSDC010_DCR_DATA_WRITE;
 424         } else {
 425                 dcon &= ~FTSDC010_DCR_DATA_WRITE;
 426                 newmask |= FTSDC010_STATUS_FIFO_ORUN;
 427         }
 428         enable_imask(host->reg, newmask);
 429
 430 #ifdef CONFIG_FTSDC010_SDIO
 431         /* always reset fifo since last transfer may fail */
 432         dcon |= FTSDC010_DCR_FIFO_RST;
 433
 434         /* handle sdio */
 435         dcon = data->blocksize | data->blocks << 15;
 436         if (data->blocks > 1)
 437                 dcon |= FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE;
 438 #endif
 439
 440         /* enable data transfer which will be pended until cmd is send */
 441         dcon |= FTSDC010_DCR_DATA_EN;
 442         writel(dcon, &host->reg->dcr);
 443
 444         return 0;
 445 }
 446
 447 static int ftsdc010_send_request(struct mmc *mmc, struct mmc_cmd *cmd,
 448                         struct mmc_data *data)
 449 {
 450         int ret;
 451
 452         if (data) {
 453                 ret = ftsdc010_setup_data(mmc, data);
 454
 455                 if (ret) {
 456                         printf("%s: setup data error\n", __func__);
 457                         return -1;
 458                 }
 459
 460                 if ((data->flags & MMC_DATA_BOTH_DIR) == MMC_DATA_BOTH_DIR) {
 461                         printf("%s: data is both direction\n", __func__);
 462                         return -1;
 463                 }
 464         }
 465
 466         /* Send command */
 467         ret = ftsdc010_send_cmd(mmc, cmd, data);
 468         return ret;
 469 }
 470
 471 static int ftsdc010_card_detect(struct mmc *mmc)
 472 {
 473         struct mmc_host *host = mmc->priv;
 474         unsigned int sta;
 475
 476         sta = readl(&host->reg->status);
 477         debug("%s: card status: %08x\n", __func__, sta);
 478
 479         return (sta & FTSDC010_STATUS_CARD_DETECT) ? 0 : 1;
 480 }
 481
 482 static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
 483                         struct mmc_data *data)
 484 {
 485         int ret;
 486
 487         if (ftsdc010_card_detect(mmc) == 0) {
 488                 printf("%s: no medium present\n", __func__);
 489                 return -1;
 490         } else {
 491                 ret = ftsdc010_send_request(mmc, cmd, data);
 492                 return ret;
 493         }
 494 }
 495
 496 static void ftsdc010_set_clk(struct mmc *mmc)
 497 {
 498         struct mmc_host *host = mmc->priv;
 499         unsigned char clk_div;
 500         unsigned char real_rate;
 501         unsigned int clock;
 502
 503         debug("%s: mmc_set_clock: %x\n", __func__, mmc->clock);
 504         clock = readl(&host->reg->ccr);
 505
 506         if (mmc->clock == 0) {
 507                 real_rate = 0;
 508                 clock |= FTSDC010_CCR_CLK_DIS;
 509         } else {
 510                 debug("%s, mmc->clock: %08x, origin clock: %08x\n",
 511                          __func__, mmc->clock, clock);
 512
 513                 for (clk_div = 0; clk_div <= 127; clk_div++) {
 514                         real_rate = (CONFIG_SYS_CLK_FREQ / 2) /
 515                                         (2 * (clk_div + 1));
 516
 517                         if (real_rate <= mmc->clock)
 518                                 break;
 519                 }
 520
 521                 debug("%s: computed real_rete: %x, clk_div: %x\n",
 522                          __func__, real_rate, clk_div);
 523
 524                 if (clk_div > 127)
 525                         debug("%s: no match clock rate, %x\n",
 526                                 __func__, mmc->clock);
 527
 528                 clock = (clock & ~FTSDC010_CCR_CLK_DIV(0x7f)) |
 529                                 FTSDC010_CCR_CLK_DIV(clk_div);
 530
 531                 clock &= ~FTSDC010_CCR_CLK_DIS;
 532         }
 533
 534         debug("%s, set clock: %08x\n", __func__, clock);
 535         writel(clock, &host->reg->ccr);
 536 }
 537
 538 static void ftsdc010_set_ios(struct mmc *mmc)
 539 {
 540         struct mmc_host *host = mmc->priv;
 541         unsigned int power;
 542         unsigned long val;
 543         unsigned int bus_width;
 544
 545         debug("%s: bus_width: %x, clock: %d\n",
 546                 __func__, mmc->bus_width, mmc->clock);
 547
 548         /* set pcr: power on */
 549         power = readl(&host->reg->pcr);
 550         power |= FTSDC010_PCR_POWER_ON;
 551         writel(power, &host->reg->pcr);
 552
 553         if (mmc->clock)
 554                 ftsdc010_set_clk(mmc);
 555
 556         /* set bwr: bus width reg */
 557         bus_width = readl(&host->reg->bwr);
 558         bus_width &= ~(FTSDC010_BWR_WIDE_8_BUS | FTSDC010_BWR_WIDE_4_BUS |
 559                         FTSDC010_BWR_SINGLE_BUS);
 560
 561         if (mmc->bus_width == 8)
 562                 bus_width |= FTSDC010_BWR_WIDE_8_BUS;
 563         else if (mmc->bus_width == 4)
 564                 bus_width |= FTSDC010_BWR_WIDE_4_BUS;
 565         else
 566                 bus_width |= FTSDC010_BWR_SINGLE_BUS;
 567
 568         writel(bus_width, &host->reg->bwr);
 569
 570         /* set fifo depth */
 571         val = readl(&host->reg->feature);
 572         host->fifo_len = FTSDC010_FEATURE_FIFO_DEPTH(val) * 4; /* 4 bytes */
 573
 574         /* set data timeout register */
 575         val = -1;
 576         writel(val, &host->reg->dtr);
 577 }
 578
 579 static void ftsdc010_reset(struct mmc_host *host)
 580 {
 581         unsigned int timeout;
 582
 583         /* Do SDC_RST: Software reset for all register */
 584         writel(FTSDC010_CMD_SDC_RST, &host->reg->cmd);
 585
 586         host->clock = 0;
 587
 588         /* this hardware has no reset finish flag to read */
 589         /* wait 100ms maximum */
 590         timeout = 100;
 591
 592         /* hw clears the bit when it's done */
 593         while (readl(&host->reg->dtr) != 0) {
 594                 if (timeout == 0) {
 595                         printf("%s: reset timeout error\n", __func__);
 596                         return;
 597                 }
 598                 timeout--;
 599                 udelay(10*FTSDC010_DELAY_UNIT);
 600         }
 601 }
 602
 603 static int ftsdc010_core_init(struct mmc *mmc)
 604 {
 605         struct mmc_host *host = mmc->priv;
 606         unsigned int mask;
 607         unsigned int major, minor, revision;
 608
 609         /* get hardware version */
 610         host->version = readl(&host->reg->rev);
 611
 612         major = FTSDC010_REV_MAJOR(host->version);
 613         minor = FTSDC010_REV_MINOR(host->version);
 614         revision = FTSDC010_REV_REVISION(host->version);
 615
 616         printf("ftsdc010 hardware ver: %d_%d_r%d\n", major, minor, revision);
 617
 618         /* Interrupt MASK register init - mask all */
 619         writel(0x0, &host->reg->int_mask);
 620
 621         mask = FTSDC010_INT_MASK_CMD_SEND |
 622                 FTSDC010_INT_MASK_DATA_END |
 623                 FTSDC010_INT_MASK_CARD_CHANGE;
 624 #ifdef CONFIG_FTSDC010_SDIO
 625         mask |= FTSDC010_INT_MASK_CP_READY |
 626                 FTSDC010_INT_MASK_CP_BUF_READY |
 627                 FTSDC010_INT_MASK_PLAIN_TEXT_READY |
 628                 FTSDC010_INT_MASK_SDIO_IRPT;
 629 #endif
 630
 631         writel(mask, &host->reg->int_mask);
 632
 633         return 0;
 634 }
 635
 636 int ftsdc010_mmc_init(int dev_index)
 637 {
 638         struct mmc *mmc;
 639         struct mmc_host *host;
 640
 641         mmc = &ftsdc010_dev[dev_index];
 642
 643         sprintf(mmc->name, "FTSDC010 SD/MMC");
 644         mmc->priv = &ftsdc010_host[dev_index];
 645         mmc->send_cmd = ftsdc010_request;
 646         mmc->set_ios = ftsdc010_set_ios;
 647         mmc->init = ftsdc010_core_init;
 648
 649         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 650
 651         mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
 652
 653         mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 654
 655         mmc->f_min = CONFIG_SYS_CLK_FREQ / 2 / (2*128);
 656         mmc->f_max = CONFIG_SYS_CLK_FREQ / 2 / 2;
 657
 658         ftsdc010_host[dev_index].clock = 0;
 659         ftsdc010_host[dev_index].reg = ftsdc010_get_base_mmc(dev_index);
 660         mmc_register(mmc);
 661
 662         /* reset mmc */
 663         host = (struct mmc_host *)mmc->priv;
 664         ftsdc010_reset(host);
 665
 666         return 0;
 667 }