drivers/mtd/nand/fsl_ifc_spl.c

   1 /*
   2  * NAND boot for Freescale Integrated Flash Controller, NAND FCM
   3  *
   4  * Copyright 2011 Freescale Semiconductor, Inc.
   5  * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <asm/fsl_ifc.h>
  13 #include <linux/mtd/nand.h>
  14
  15 static inline int is_blank(uchar *addr, int page_size)
  16 {
  17         int i;
  18
  19         for (i = 0; i < page_size; i++) {
  20                 if (__raw_readb(&addr[i]) != 0xff)
  21                         return 0;
  22         }
  23
  24         /*
  25          * For the SPL, don't worry about uncorrectable errors
  26          * where the main area is all FFs but shouldn't be.
  27          */
  28         return 1;
  29 }
  30
  31 /* returns nonzero if entire page is blank */
  32 static inline int check_read_ecc(uchar *buf, u32 *eccstat,
  33                                  unsigned int bufnum, int page_size)
  34 {
  35         u32 reg = eccstat[bufnum / 4];
  36         int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
  37
  38         if (errors == 0xf) { /* uncorrectable */
  39                 /* Blank pages fail hw ECC checks */
  40                 if (is_blank(buf, page_size))
  41                         return 1;
  42
  43                 puts("ecc error\n");
  44                 for (;;)
  45                         ;
  46         }
  47
  48         return 0;
  49 }
  50
  51 static inline void nand_wait(uchar *buf, int bufnum, int page_size)
  52 {
  53         struct fsl_ifc *ifc = IFC_BASE_ADDR;
  54         u32 status;
  55         u32 eccstat[4];
  56         int bufperpage = page_size / 512;
  57         int bufnum_end, i;
  58
  59         bufnum *= bufperpage;
  60         bufnum_end = bufnum + bufperpage - 1;
  61
  62         do {
  63                 status = in_be32(&ifc->ifc_nand.nand_evter_stat);
  64         } while (!(status & IFC_NAND_EVTER_STAT_OPC));
  65
  66         if (status & IFC_NAND_EVTER_STAT_FTOER) {
  67                 puts("flash time out error\n");
  68                 for (;;)
  69                         ;
  70         }
  71
  72         for (i = bufnum / 4; i <= bufnum_end / 4; i++)
  73                 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
  74
  75         for (i = bufnum; i <= bufnum_end; i++) {
  76                 if (check_read_ecc(buf, eccstat, i, page_size))
  77                         break;
  78         }
  79
  80         out_be32(&ifc->ifc_nand.nand_evter_stat, status);
  81 }
  82
  83 static inline int bad_block(uchar *marker, int port_size)
  84 {
  85         if (port_size == 8)
  86                 return __raw_readb(marker) != 0xff;
  87         else
  88                 return __raw_readw((u16 *)marker) != 0xffff;
  89 }
  90
  91 static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
  92 {
  93         struct fsl_ifc *ifc = IFC_BASE_ADDR;
  94         uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
  95         int page_size;
  96         int port_size;
  97         int pages_per_blk;
  98         int blk_size;
  99         int bad_marker = 0;
 100         int bufnum_mask, bufnum;
 101
 102         int csor, cspr;
 103         int pos = 0;
 104         int j = 0;
 105
 106         int sram_addr;
 107         int pg_no;
 108
 109         /* Get NAND Flash configuration */
 110         csor = CONFIG_SYS_NAND_CSOR;
 111         cspr = CONFIG_SYS_NAND_CSPR;
 112
 113         port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
 114
 115         if (csor & CSOR_NAND_PGS_4K) {
 116                 page_size = 4096;
 117                 bufnum_mask = 0x1;
 118         } else if (csor & CSOR_NAND_PGS_2K) {
 119                 page_size = 2048;
 120                 bufnum_mask = 0x3;
 121         } else {
 122                 page_size = 512;
 123                 bufnum_mask = 0xf;
 124
 125                 if (port_size == 8)
 126                         bad_marker = 5;
 127         }
 128
 129         pages_per_blk =
 130                 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
 131
 132         blk_size = pages_per_blk * page_size;
 133
 134         /* Open Full SRAM mapping for spare are access */
 135         out_be32(&ifc->ifc_nand.ncfgr, 0x0);
 136
 137         /* Clear Boot events */
 138         out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
 139
 140         /* Program FIR/FCR for Large/Small page */
 141         if (page_size > 512) {
 142                 out_be32(&ifc->ifc_nand.nand_fir0,
 143                          (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 144                          (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 145                          (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 146                          (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
 147                          (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
 148                 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
 149
 150                 out_be32(&ifc->ifc_nand.nand_fcr0,
 151                          (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
 152                          (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 153         } else {
 154                 out_be32(&ifc->ifc_nand.nand_fir0,
 155                          (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 156                          (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 157                          (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
 158                          (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
 159                 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
 160
 161                 out_be32(&ifc->ifc_nand.nand_fcr0,
 162                          NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 163         }
 164
 165         /* Program FBCR = 0 for full page read */
 166         out_be32(&ifc->ifc_nand.nand_fbcr, 0);
 167
 168         /* Read and copy u-boot on SDRAM from NAND device, In parallel
 169          * check for Bad block if found skip it and read continue to
 170          * next Block
 171          */
 172         while (pos < uboot_size) {
 173                 int i = 0;
 174                 do {
 175                         pg_no = offs / page_size;
 176                         bufnum = pg_no & bufnum_mask;
 177                         sram_addr = bufnum * page_size * 2;
 178
 179                         out_be32(&ifc->ifc_nand.row0, pg_no);
 180                         out_be32(&ifc->ifc_nand.col0, 0);
 181                         /* start read */
 182                         out_be32(&ifc->ifc_nand.nandseq_strt,
 183                                  IFC_NAND_SEQ_STRT_FIR_STRT);
 184
 185                         /* wait for read to complete */
 186                         nand_wait(&buf[sram_addr], bufnum, page_size);
 187
 188                         /*
 189                          * If either of the first two pages are marked bad,
 190                          * continue to the next block.
 191                          */
 192                         if (i++ < 2 &&
 193                             bad_block(&buf[sram_addr + page_size + bad_marker],
 194                                       port_size)) {
 195                                 puts("skipping\n");
 196                                 offs = (offs + blk_size) & ~(blk_size - 1);
 197                                 pos &= ~(blk_size - 1);
 198                                 break;
 199                         }
 200
 201                         for (j = 0; j < page_size; j++)
 202                                 dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
 203
 204                         pos += page_size;
 205                         offs += page_size;
 206                 } while ((offs & (blk_size - 1)) && (pos < uboot_size));
 207         }
 208 }
 209
 210 /*
 211  * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
 212  * configured and available since this code loads the main U-boot image
 213  * from NAND into SDRAM and starts from there.
 214  */
 215 void nand_boot(void)
 216 {
 217         __attribute__((noreturn)) void (*uboot)(void);
 218         /*
 219          * Load U-Boot image from NAND into RAM
 220          */
 221         nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
 222                   (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
 223
 224 #ifdef CONFIG_NAND_ENV_DST
 225         nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 226                   (uchar *)CONFIG_NAND_ENV_DST);
 227
 228 #ifdef CONFIG_ENV_OFFSET_REDUND
 229         nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
 230                   (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
 231 #endif
 232 #endif
 233         /*
 234          * Jump to U-Boot image
 235          */
 236 #ifdef CONFIG_SPL_FLUSH_IMAGE
 237         /*
 238          * Clean d-cache and invalidate i-cache, to
 239          * make sure that no stale data is executed.
 240          */
 241         flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
 242 #endif
 243         uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 244         uboot();
 245 }