2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/types.h>
22 #include <asm/errno.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/imx-common/regs-bch.h>
27 #include <asm/imx-common/regs-gpmi.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/imx-common/dma.h>
31 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
33 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
34 #if defined(CONFIG_SOC_MX6)
35 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
37 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
39 #define MXS_NAND_METADATA_SIZE 10
41 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
43 /* BCH timeout in microseconds */
44 #define MXS_NAND_BCH_TIMEOUT 10000
46 static struct bch_regs *bch_regs = (void *)BCH_BASE_ADDRESS;
47 static struct gpmi_regs *gpmi_regs = (void *)GPMI_BASE_ADDRESS;
48 struct mxs_nand_info {
51 uint32_t cmd_queue_len;
52 uint32_t data_buf_size;
58 uint8_t marking_block_bad;
61 /* Functions with altered behaviour */
62 int (*hooked_read_oob)(struct mtd_info *mtd,
63 loff_t from, struct mtd_oob_ops *ops);
64 int (*hooked_write_oob)(struct mtd_info *mtd,
65 loff_t to, struct mtd_oob_ops *ops);
66 int (*hooked_block_markbad)(struct mtd_info *mtd,
70 struct mxs_dma_desc **desc;
75 #define dump_reg(b, r) __dump_reg(&b->r, #r)
76 static inline void __dump_reg(void *addr, const char *name)
78 printf("%16s[%p]=%08x\n", name, addr, readl(addr));
81 #define dump_bch_reg(n) __dump_reg(&bch_regs->hw_bch_##n, #n)
82 #define dump_gpmi_reg(n) __dump_reg(&gpmi_regs->hw_gpmi_##n, #n)
83 static inline void dump_regs(void)
87 dump_bch_reg(status0);
90 dump_bch_reg(dbgkesread);
91 dump_bch_reg(dbgcsferead);
92 dump_bch_reg(dbgsyndegread);
93 dump_bch_reg(dbgahbmread);
94 dump_bch_reg(blockname);
95 dump_bch_reg(version);
99 dump_gpmi_reg(eccctrl);
100 dump_gpmi_reg(ecccount);
101 dump_gpmi_reg(payload);
102 dump_gpmi_reg(auxiliary);
103 dump_gpmi_reg(ctrl1);
106 dump_gpmi_reg(debug);
107 dump_gpmi_reg(version);
108 dump_gpmi_reg(debug2);
109 dump_gpmi_reg(debug3);
112 static inline int dbg_addr(void *addr)
114 if (((unsigned long)addr & ~0xfff) == BCH_BASE_ADDRESS)
119 static inline u32 mxs_readl(void *addr,
120 const char *fn, int ln)
122 u32 val = readl(addr);
123 static void *last_addr;
129 if (addr != last_addr || last_val != val) {
130 printf("%s@%d: Read %08x from %p\n", fn, ln, val, addr);
137 static inline void mxs_writel(u32 val, void *addr,
138 const char *fn, int ln)
141 printf("%s@%d: Writing %08x to %p...", fn, ln, val, addr);
144 printf(" result: %08x\n", readl(addr));
148 #define readl(a) mxs_readl(a, __func__, __LINE__)
151 #define writel(v, a) mxs_writel(v, a, __func__, __LINE__)
152 static inline void memdump(const void *addr, size_t len)
154 const char *buf = addr;
157 for (i = 0; i < len; i++) {
161 printf("%p:", &buf[i]);
163 printf(" %02x", buf[i]);
168 static inline void memdump(void *addr, size_t len)
172 static inline void dump_regs(void)
177 struct nand_ecclayout fake_ecc_layout;
180 * Cache management functions
182 #ifndef CONFIG_SYS_DCACHE_OFF
183 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
185 uint32_t addr = (uint32_t)info->data_buf;
187 flush_dcache_range(addr, addr + info->data_buf_size);
190 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
192 uint32_t addr = (uint32_t)info->data_buf;
194 invalidate_dcache_range(addr, addr + info->data_buf_size);
197 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
199 uint32_t addr = (uint32_t)info->cmd_buf;
201 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
204 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
205 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
206 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
209 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
211 struct mxs_dma_desc *desc;
213 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
214 printf("MXS NAND: Too many DMA descriptors requested\n");
218 desc = info->desc[info->desc_index];
224 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
227 struct mxs_dma_desc *desc;
229 for (i = 0; i < info->desc_index; i++) {
230 desc = info->desc[i];
231 memset(desc, 0, sizeof(struct mxs_dma_desc));
232 desc->address = (dma_addr_t)desc;
235 info->desc_index = 0;
238 static uint32_t mxs_nand_ecc_chunk_cnt(struct mtd_info *mtd)
240 struct nand_chip *nand = mtd->priv;
241 return mtd->writesize / nand->ecc.size;
244 static inline uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
246 return ecc_strength * 13;
249 static uint32_t mxs_nand_aux_status_offset(void)
251 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
254 static int mxs_nand_gpmi_init(void)
258 /* Reset the GPMI block. */
259 ret = mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
264 * Choose NAND mode, set IRQ polarity, disable write protection and
267 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
268 GPMI_CTRL1_GPMI_MODE,
269 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
270 GPMI_CTRL1_BCH_MODE);
271 writel(0x500 << 16, &gpmi_regs->hw_gpmi_timing1);
275 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
276 uint32_t page_oob_size)
281 * Determine the ECC layout with the formula:
282 * ECC bits per chunk = (total page spare data bits) /
283 * (bits per ECC level) / (chunks per page)
285 * total page spare data bits =
286 * (page oob size - meta data size) * (bits per byte)
288 ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
289 / (13 * mxs_nand_ecc_chunk_cnt(page_data_size));
291 return round_down(ecc_strength, 2);
294 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
295 uint32_t ecc_strength)
297 uint32_t chunk_data_size_in_bits;
298 uint32_t chunk_ecc_size_in_bits;
299 uint32_t chunk_total_size_in_bits;
300 uint32_t block_mark_chunk_number;
301 uint32_t block_mark_chunk_bit_offset;
302 uint32_t block_mark_bit_offset;
304 chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8;
305 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
307 chunk_total_size_in_bits =
308 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
310 /* Compute the bit offset of the block mark within the physical page. */
311 block_mark_bit_offset = page_data_size * 8;
313 /* Subtract the metadata bits. */
314 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
317 * Compute the chunk number (starting at zero) in which the block mark
320 block_mark_chunk_number =
321 block_mark_bit_offset / chunk_total_size_in_bits;
324 * Compute the bit offset of the block mark within its chunk, and
327 block_mark_chunk_bit_offset = block_mark_bit_offset -
328 (block_mark_chunk_number * chunk_total_size_in_bits);
330 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
334 * Now that we know the chunk number in which the block mark appears,
335 * we can subtract all the ECC bits that appear before it.
337 block_mark_bit_offset -=
338 block_mark_chunk_number * chunk_ecc_size_in_bits;
340 return block_mark_bit_offset;
343 static inline uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
345 uint32_t ecc_strength;
346 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
347 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
350 static inline uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
352 uint32_t ecc_strength;
353 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
354 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
358 * Wait for BCH complete IRQ and clear the IRQ
360 static int mxs_nand_wait_for_bch_complete(void)
362 int timeout = MXS_NAND_BCH_TIMEOUT;
365 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
366 BCH_CTRL_COMPLETE_IRQ, timeout);
368 debug("%s@%d: %d\n", __func__, __LINE__, ret);
369 mxs_nand_gpmi_init();
372 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
378 * This is the function that we install in the cmd_ctrl function pointer of the
379 * owning struct nand_chip. The only functions in the reference implementation
380 * that use these functions pointers are cmdfunc and select_chip.
382 * In this driver, we implement our own select_chip, so this function will only
383 * be called by the reference implementation's cmdfunc. For this reason, we can
384 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
387 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
389 struct nand_chip *nand = mtd->priv;
390 struct mxs_nand_info *nand_info = nand->priv;
391 struct mxs_dma_desc *d;
392 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
396 * If this condition is true, something is _VERY_ wrong in MTD
399 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
400 printf("MXS NAND: Command queue too long\n");
405 * Every operation begins with a command byte and a series of zero or
406 * more address bytes. These are distinguished by either the Address
407 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
408 * asserted. When MTD is ready to execute the command, it will
409 * deasert both latch enables.
411 * Rather than run a separate DMA operation for every single byte, we
412 * queue them up and run a single DMA operation for the entire series
413 * of command and data bytes.
415 if (ctrl & (NAND_ALE | NAND_CLE)) {
416 if (data != NAND_CMD_NONE)
417 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
422 * If control arrives here, MTD has deasserted both the ALE and CLE,
423 * which means it's ready to run an operation. Check if we have any
426 if (nand_info->cmd_queue_len == 0)
429 /* Compile the DMA descriptor -- a descriptor that sends command. */
430 d = mxs_nand_get_dma_desc(nand_info);
432 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
433 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
434 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
435 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
437 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
439 d->cmd.pio_words[0] =
440 GPMI_CTRL0_COMMAND_MODE_WRITE |
441 GPMI_CTRL0_WORD_LENGTH |
442 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
443 GPMI_CTRL0_ADDRESS_NAND_CLE |
444 GPMI_CTRL0_ADDRESS_INCREMENT |
445 nand_info->cmd_queue_len;
447 mxs_dma_desc_append(channel, d);
450 mxs_nand_flush_cmd_buf(nand_info);
452 /* Execute the DMA chain. */
453 ret = mxs_dma_go(channel);
457 printf("MXS NAND: Error sending command %08lx\n", d->cmd.pio_words[0]);
458 for (i = 0; i < nand_info->cmd_queue_len; i++) {
459 printf("%02x ", nand_info->cmd_buf[i]);
464 mxs_nand_return_dma_descs(nand_info);
466 /* Reset the command queue. */
467 nand_info->cmd_queue_len = 0;
471 * Test if the NAND flash is ready.
473 static int mxs_nand_device_ready(struct mtd_info *mtd)
475 struct nand_chip *chip = mtd->priv;
476 struct mxs_nand_info *nand_info = chip->priv;
479 tmp = readl(&gpmi_regs->hw_gpmi_stat);
480 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
486 * Select the NAND chip.
488 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
490 struct nand_chip *nand = mtd->priv;
491 struct mxs_nand_info *nand_info = nand->priv;
493 nand_info->cur_chip = chip;
497 * Handle block mark swapping.
499 * Note that, when this function is called, it doesn't know whether it's
500 * swapping the block mark, or swapping it *back* -- but it doesn't matter
501 * because the the operation is the same.
503 #ifndef CONFIG_NAND_MXS_NO_BBM_SWAP
504 static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
505 uint8_t *data_buf, uint8_t *oob_buf)
513 bit_offset = mxs_nand_mark_bit_offset(mtd);
514 buf_offset = mxs_nand_mark_byte_offset(mtd);
517 * Get the byte from the data area that overlays the block mark. Since
518 * the ECC engine applies its own view to the bits in the page, the
519 * physical block mark won't (in general) appear on a byte boundary in
522 src = data_buf[buf_offset] >> bit_offset;
523 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
527 debug("Swapping byte %02x @ %03x.%d with %02x @ %03x\n",
528 src & 0xff, buf_offset, bit_offset, dst & 0xff, 0);
532 data_buf[buf_offset] &= ~(0xff << bit_offset);
533 data_buf[buf_offset + 1] &= 0xff << bit_offset;
535 data_buf[buf_offset] |= dst << bit_offset;
536 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
539 static inline void mxs_nand_swap_block_mark(struct mtd_info *mtd,
540 uint8_t *data_buf, uint8_t *oob_buf)
546 * Read data from NAND.
548 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
550 struct nand_chip *nand = mtd->priv;
551 struct mxs_nand_info *nand_info = nand->priv;
552 struct mxs_dma_desc *d;
553 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
556 if (length > NAND_MAX_PAGESIZE) {
557 printf("MXS NAND: DMA buffer too big\n");
562 printf("MXS NAND: DMA buffer is NULL\n");
566 memset(buf, 0xee, length);
568 /* Compile the DMA descriptor - a descriptor that reads data. */
569 d = mxs_nand_get_dma_desc(nand_info);
571 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
572 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
573 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
574 (length << MXS_DMA_DESC_BYTES_OFFSET);
576 d->cmd.address = (dma_addr_t)nand_info->data_buf;
578 d->cmd.pio_words[0] =
579 GPMI_CTRL0_COMMAND_MODE_READ |
580 GPMI_CTRL0_WORD_LENGTH |
581 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
582 GPMI_CTRL0_ADDRESS_NAND_DATA |
585 mxs_dma_desc_append(channel, d);
586 #ifndef CONFIG_SOC_MX6Q
588 * A DMA descriptor that waits for the command to end and the chip to
591 * I think we actually should *not* be waiting for the chip to become
592 * ready because, after all, we don't care. I think the original code
593 * did that and no one has re-thought it yet.
595 d = mxs_nand_get_dma_desc(nand_info);
597 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
598 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
599 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
603 d->cmd.pio_words[0] =
604 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
605 GPMI_CTRL0_WORD_LENGTH |
606 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
607 GPMI_CTRL0_ADDRESS_NAND_DATA;
609 mxs_dma_desc_append(channel, d);
611 /* Execute the DMA chain. */
612 ret = mxs_dma_go(channel);
614 printf("%s: DMA read error\n", __func__);
618 /* Invalidate caches */
619 mxs_nand_inval_data_buf(nand_info);
621 memcpy(buf, nand_info->data_buf, length);
624 mxs_nand_return_dma_descs(nand_info);
628 * Write data to NAND.
630 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
633 struct nand_chip *nand = mtd->priv;
634 struct mxs_nand_info *nand_info = nand->priv;
635 struct mxs_dma_desc *d;
636 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
639 if (length > NAND_MAX_PAGESIZE) {
640 printf("MXS NAND: DMA buffer too big\n");
645 printf("MXS NAND: DMA buffer is NULL\n");
649 memcpy(nand_info->data_buf, buf, length);
651 /* Compile the DMA descriptor - a descriptor that writes data. */
652 d = mxs_nand_get_dma_desc(nand_info);
654 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
655 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
656 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
657 (length << MXS_DMA_DESC_BYTES_OFFSET);
659 d->cmd.address = (dma_addr_t)nand_info->data_buf;
661 d->cmd.pio_words[0] =
662 GPMI_CTRL0_COMMAND_MODE_WRITE |
663 GPMI_CTRL0_WORD_LENGTH |
664 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
665 GPMI_CTRL0_ADDRESS_NAND_DATA |
668 mxs_dma_desc_append(channel, d);
671 mxs_nand_flush_data_buf(nand_info);
673 /* Execute the DMA chain. */
674 ret = mxs_dma_go(channel);
676 printf("%s: DMA write error\n", __func__);
678 mxs_nand_return_dma_descs(nand_info);
682 * Read a single byte from NAND.
684 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
687 mxs_nand_read_buf(mtd, &buf, 1);
691 static void flush_buffers(struct mtd_info *mtd, struct mxs_nand_info *nand_info)
693 flush_dcache_range((unsigned long)nand_info->data_buf,
694 (unsigned long)nand_info->data_buf +
696 flush_dcache_range((unsigned long)nand_info->oob_buf,
697 (unsigned long)nand_info->oob_buf +
702 * Read a page from NAND.
704 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
705 uint8_t *buf, int oob_required,
708 struct mxs_nand_info *nand_info = nand->priv;
709 struct mxs_dma_desc *d;
710 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
711 uint32_t corrected = 0, failed = 0;
715 /* Compile the DMA descriptor - wait for ready. */
716 d = mxs_nand_get_dma_desc(nand_info);
718 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
719 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
720 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
724 d->cmd.pio_words[0] =
725 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
726 GPMI_CTRL0_WORD_LENGTH |
727 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
728 GPMI_CTRL0_ADDRESS_NAND_DATA;
730 mxs_dma_desc_append(channel, d);
732 /* Compile the DMA descriptor - enable the BCH block and read. */
733 d = mxs_nand_get_dma_desc(nand_info);
735 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
736 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
740 d->cmd.pio_words[0] =
741 GPMI_CTRL0_COMMAND_MODE_READ |
742 GPMI_CTRL0_WORD_LENGTH |
743 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
744 GPMI_CTRL0_ADDRESS_NAND_DATA |
745 (mtd->writesize + mtd->oobsize);
746 d->cmd.pio_words[1] = 0;
747 d->cmd.pio_words[2] =
748 GPMI_ECCCTRL_ENABLE_ECC |
749 GPMI_ECCCTRL_ECC_CMD_DECODE |
750 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
751 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
752 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
753 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
755 flush_buffers(mtd, nand_info);
757 mxs_dma_desc_append(channel, d);
759 /* Compile the DMA descriptor - disable the BCH block. */
760 d = mxs_nand_get_dma_desc(nand_info);
762 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
763 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
764 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
768 d->cmd.pio_words[0] =
769 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
770 GPMI_CTRL0_WORD_LENGTH |
771 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
772 GPMI_CTRL0_ADDRESS_NAND_DATA |
773 (mtd->writesize + mtd->oobsize);
774 d->cmd.pio_words[1] = 0;
775 d->cmd.pio_words[2] = 0;
777 mxs_dma_desc_append(channel, d);
779 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
780 d = mxs_nand_get_dma_desc(nand_info);
782 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
783 MXS_DMA_DESC_DEC_SEM;
787 mxs_dma_desc_append(channel, d);
789 /* Execute the DMA chain. */
790 ret = mxs_dma_go(channel);
792 printf("%s: DMA read error\n", __func__);
796 ret = mxs_nand_wait_for_bch_complete();
798 printf("MXS NAND: BCH read timeout\n");
802 /* Invalidate caches */
803 mxs_nand_inval_data_buf(nand_info);
805 /* Read DMA completed, now do the mark swapping. */
806 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
808 /* Loop over status bytes, accumulating ECC status. */
809 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
810 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd); i++) {
811 if (status[i] == 0x00)
814 if (status[i] == 0xff)
817 if (status[i] == 0xfe) {
822 corrected += status[i];
825 /* Propagate ECC status to the owning MTD. */
826 mtd->ecc_stats.failed += failed;
827 mtd->ecc_stats.corrected += corrected;
830 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
831 * details about our policy for delivering the OOB.
833 * We fill the caller's buffer with set bits, and then copy the block
834 * mark to the caller's buffer. Note that, if block mark swapping was
835 * necessary, it has already been done, so we can rely on the first
836 * byte of the auxiliary buffer to contain the block mark.
838 memset(nand->oob_poi, 0xff, mtd->oobsize);
840 nand->oob_poi[0] = nand_info->oob_buf[0];
842 memcpy(buf, nand_info->data_buf, mtd->writesize);
845 mxs_nand_return_dma_descs(nand_info);
851 * Write a page to NAND.
853 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
854 struct nand_chip *nand, const uint8_t *buf,
857 struct mxs_nand_info *nand_info = nand->priv;
858 struct mxs_dma_desc *d;
859 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
862 memcpy(nand_info->data_buf, buf, mtd->writesize);
863 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
865 /* Handle block mark swapping. */
866 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
868 /* Compile the DMA descriptor - write data. */
869 d = mxs_nand_get_dma_desc(nand_info);
871 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
872 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
873 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
877 d->cmd.pio_words[0] =
878 GPMI_CTRL0_COMMAND_MODE_WRITE |
879 GPMI_CTRL0_WORD_LENGTH |
880 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
881 GPMI_CTRL0_ADDRESS_NAND_DATA;
882 d->cmd.pio_words[1] = 0;
883 d->cmd.pio_words[2] =
884 GPMI_ECCCTRL_ENABLE_ECC |
885 GPMI_ECCCTRL_ECC_CMD_ENCODE |
886 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
887 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
888 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
889 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
891 flush_buffers(mtd, nand_info);
893 mxs_dma_desc_append(channel, d);
896 mxs_nand_flush_data_buf(nand_info);
898 /* Execute the DMA chain. */
899 ret = mxs_dma_go(channel);
901 printf("%s: DMA write error\n", __func__);
905 ret = mxs_nand_wait_for_bch_complete();
907 printf("%s: BCH write timeout\n", __func__);
912 mxs_nand_return_dma_descs(nand_info);
917 * Read OOB from NAND.
919 * This function is a veneer that replaces the function originally installed by
920 * the NAND Flash MTD code.
922 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
923 struct mtd_oob_ops *ops)
925 struct nand_chip *chip = mtd->priv;
926 struct mxs_nand_info *nand_info = chip->priv;
929 if (ops->mode == MTD_OPS_RAW)
930 nand_info->raw_oob_mode = 1;
932 nand_info->raw_oob_mode = 0;
934 ret = nand_info->hooked_read_oob(mtd, from, ops);
936 nand_info->raw_oob_mode = 0;
944 * This function is a veneer that replaces the function originally installed by
945 * the NAND Flash MTD code.
947 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
948 struct mtd_oob_ops *ops)
950 struct nand_chip *chip = mtd->priv;
951 struct mxs_nand_info *nand_info = chip->priv;
954 if (ops->mode == MTD_OPS_RAW)
955 nand_info->raw_oob_mode = 1;
957 nand_info->raw_oob_mode = 0;
959 ret = nand_info->hooked_write_oob(mtd, to, ops);
961 nand_info->raw_oob_mode = 0;
967 * Mark a block bad in NAND.
969 * This function is a veneer that replaces the function originally installed by
970 * the NAND Flash MTD code.
972 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
974 struct nand_chip *chip = mtd->priv;
975 struct mxs_nand_info *nand_info = chip->priv;
978 nand_info->marking_block_bad = 1;
980 ret = nand_info->hooked_block_markbad(mtd, ofs);
982 nand_info->marking_block_bad = 0;
988 * There are several places in this driver where we have to handle the OOB and
989 * block marks. This is the function where things are the most complicated, so
990 * this is where we try to explain it all. All the other places refer back to
993 * These are the rules, in order of decreasing importance:
995 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
996 * write operations take measures to protect it.
998 * 2) In read operations, the first byte of the OOB we return must reflect the
999 * true state of the block mark, no matter where that block mark appears in
1000 * the physical page.
1002 * 3) ECC-based read operations return an OOB full of set bits (since we never
1003 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
1006 * 4) "Raw" read operations return a direct view of the physical bytes in the
1007 * page, using the conventional definition of which bytes are data and which
1008 * are OOB. This gives the caller a way to see the actual, physical bytes
1009 * in the page, without the distortions applied by our ECC engine.
1011 * What we do for this specific read operation depends on whether we're doing
1012 * "raw" read, or an ECC-based read.
1014 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
1015 * easy. When reading a page, for example, the NAND Flash MTD code calls our
1016 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
1017 * ECC-based or raw view of the page is implicit in which function it calls
1018 * (there is a similar pair of ECC-based/raw functions for writing).
1020 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
1021 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
1022 * caller wants an ECC-based or raw view of the page is not propagated down to
1025 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
1026 * ecc.read_oob and ecc.write_oob function pointers in the owning
1027 * struct mtd_info with our own functions. These hook functions set the
1028 * raw_oob_mode field so that, when control finally arrives here, we'll know
1031 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
1034 struct mxs_nand_info *nand_info = nand->priv;
1037 * First, fill in the OOB buffer. If we're doing a raw read, we need to
1038 * get the bytes from the physical page. If we're not doing a raw read,
1039 * we need to fill the buffer with set bits.
1041 if (nand_info->raw_oob_mode) {
1043 * If control arrives here, we're doing a "raw" read. Send the
1044 * command to read the conventional OOB and read it.
1046 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1047 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
1050 * If control arrives here, we're not doing a "raw" read. Fill
1051 * the OOB buffer with set bits and correct the block mark.
1053 memset(nand->oob_poi, 0xff, mtd->oobsize);
1055 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1056 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
1064 * Write OOB data to NAND.
1066 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
1069 struct mxs_nand_info *nand_info = nand->priv;
1070 uint8_t block_mark = 0;
1073 * There are fundamental incompatibilities between the i.MX GPMI NFC and
1074 * the NAND Flash MTD model that make it essentially impossible to write
1075 * the out-of-band bytes.
1077 * We permit *ONE* exception. If the *intent* of writing the OOB is to
1078 * mark a block bad, we can do that.
1081 if (!nand_info->marking_block_bad) {
1082 printf("NXS NAND: Writing OOB isn't supported\n");
1086 /* Write the block mark. */
1087 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1088 nand->write_buf(mtd, &block_mark, 1);
1089 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1091 /* Check if it worked. */
1092 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
1099 * Claims all blocks are good.
1101 * In principle, this function is *only* called when the NAND Flash MTD system
1102 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
1103 * the driver for bad block information.
1105 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
1106 * this function is *only* called when we take it away.
1108 * Thus, this function is only called when we want *all* blocks to look good,
1109 * so it *always* return success.
1111 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
1117 * Nominally, the purpose of this function is to look for or create the bad
1118 * block table. In fact, since the we call this function at the very end of
1119 * the initialization process started by nand_scan(), and we don't have a
1120 * more formal mechanism, we "hook" this function to continue init process.
1122 * At this point, the physical NAND Flash chips have been identified and
1123 * counted, so we know the physical geometry. This enables us to make some
1124 * important configuration decisions.
1126 * The return value of this function propogates directly back to this driver's
1127 * call to nand_scan(). Anything other than zero will cause this driver to
1128 * tear everything down and declare failure.
1130 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
1132 struct nand_chip *nand = mtd->priv;
1133 struct mxs_nand_info *nand_info = nand->priv;
1136 /* Configure BCH and set NFC geometry */
1137 if (readl(&bch_regs->hw_bch_ctrl_reg) &
1138 (BCH_CTRL_SFTRST | BCH_CTRL_CLKGATE))
1139 /* When booting from NAND the BCH engine will already
1140 * be operational and obviously does not like being reset here.
1141 * There will be occasional read errors upon boot when this
1144 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1145 readl(&bch_regs->hw_bch_ctrl_reg);
1147 debug("mtd->writesize=%d\n", mtd->writesize);
1148 debug("mtd->oobsize=%d\n", mtd->oobsize);
1149 debug("ecc_strength=%d\n", mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize));
1151 /* Configure layout 0 */
1152 tmp = (mxs_nand_ecc_chunk_cnt(mtd) - 1)
1153 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1154 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1155 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1156 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1157 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
1158 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1159 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1161 tmp = (mtd->writesize + mtd->oobsize)
1162 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1163 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1164 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1165 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
1166 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1167 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1169 /* Set *all* chip selects to use layout 0 */
1170 writel(0, &bch_regs->hw_bch_layoutselect);
1172 /* Enable BCH complete interrupt */
1173 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1175 /* Hook some operations at the MTD level. */
1176 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1177 nand_info->hooked_read_oob = mtd->_read_oob;
1178 mtd->_read_oob = mxs_nand_hook_read_oob;
1181 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1182 nand_info->hooked_write_oob = mtd->_write_oob;
1183 mtd->_write_oob = mxs_nand_hook_write_oob;
1186 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1187 nand_info->hooked_block_markbad = mtd->_block_markbad;
1188 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1191 /* We use the reference implementation for bad block management. */
1192 return nand_default_bbt(mtd);
1196 * Allocate DMA buffers
1198 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1201 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1203 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1206 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1208 printf("%s: Error allocating DMA buffers\n", __func__);
1212 memset(buf, 0, nand_info->data_buf_size);
1214 nand_info->data_buf = buf;
1215 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1216 /* Command buffers */
1217 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1218 MXS_NAND_COMMAND_BUFFER_SIZE);
1219 if (!nand_info->cmd_buf) {
1221 printf("MXS NAND: Error allocating command buffers\n");
1224 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1225 nand_info->cmd_queue_len = 0;
1231 * Initializes the NFC hardware.
1233 int mxs_nand_init(struct mxs_nand_info *info)
1238 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1239 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1241 printf("MXS NAND: Unable to allocate DMA descriptor table\n");
1248 /* Allocate the DMA descriptors. */
1249 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1250 info->desc[i] = mxs_dma_desc_alloc();
1251 if (!info->desc[i]) {
1252 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1258 /* Init the DMA controller. */
1259 for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++) {
1260 const int chan = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + i;
1262 ret = mxs_dma_init_channel(chan);
1264 printf("Failed to initialize DMA channel %d\n", chan);
1269 ret = mxs_nand_gpmi_init();
1276 for (--i; i >= 0; i--)
1277 mxs_dma_release(i + MXS_DMA_CHANNEL_AHB_APBH_GPMI0);
1278 i = MXS_NAND_DMA_DESCRIPTOR_COUNT - 1;
1281 for (--i; i >= 0; i--)
1282 mxs_dma_desc_free(info->desc[i]);
1288 * This function is called during the driver binding process.
1290 * @param pdev the device structure used to store device specific
1291 * information that is used by the suspend, resume and
1294 * @return The function always returns 0.
1296 int board_nand_init(struct nand_chip *nand)
1298 struct mxs_nand_info *nand_info;
1301 nand_info = calloc(1, sizeof(struct mxs_nand_info));
1303 printf("MXS NAND: Failed to allocate private data\n");
1307 err = mxs_nand_alloc_buffers(nand_info);
1311 err = mxs_nand_init(nand_info);
1315 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1317 nand->priv = nand_info;
1318 nand->options |= NAND_NO_SUBPAGE_WRITE;
1319 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1320 nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1322 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1324 nand->dev_ready = mxs_nand_device_ready;
1325 nand->select_chip = mxs_nand_select_chip;
1326 nand->block_bad = mxs_nand_block_bad;
1327 nand->scan_bbt = mxs_nand_scan_bbt;
1329 nand->read_byte = mxs_nand_read_byte;
1331 nand->read_buf = mxs_nand_read_buf;
1332 nand->write_buf = mxs_nand_write_buf;
1334 nand->ecc.read_page = mxs_nand_ecc_read_page;
1335 nand->ecc.write_page = mxs_nand_ecc_write_page;
1336 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1337 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1339 nand->ecc.layout = &fake_ecc_layout;
1340 nand->ecc.mode = NAND_ECC_HW;
1341 nand->ecc.bytes = 9;
1342 nand->ecc.size = 512;
1343 nand->ecc.strength = 8;
1348 free(nand_info->data_buf);
1349 free(nand_info->cmd_buf);