drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ECC support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <common.h>
  36
  37 #define ENOTSUPP        524     /* Operation is not supported */
  38
  39 #include <malloc.h>
  40 #include <watchdog.h>
  41 #include <linux/err.h>
  42 #include <linux/compat.h>
  43 #include <linux/mtd/mtd.h>
  44 #include <linux/mtd/nand.h>
  45 #include <linux/mtd/nand_ecc.h>
  46 #include <linux/mtd/nand_bch.h>
  47
  48 #ifdef CONFIG_MTD_PARTITIONS
  49 #include <linux/mtd/partitions.h>
  50 #endif
  51
  52 #include <asm/io.h>
  53 #include <asm/errno.h>
  54
  55 /*
  56  * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
  57  * a flash.  NAND flash is initialized prior to interrupts so standard timers
  58  * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
  59  * which is greater than (max NAND reset time / NAND status read time).
  60  * A conservative default of 200000 (500 us / 25 ns) is used as a default.
  61  */
  62 #ifndef CONFIG_SYS_NAND_RESET_CNT
  63 #define CONFIG_SYS_NAND_RESET_CNT 200000
  64 #endif
  65
  66 /* Define default oob placement schemes for large and small page devices */
  67 static struct nand_ecclayout nand_oob_8 = {
  68         .eccbytes = 3,
  69         .eccpos = {0, 1, 2},
  70         .oobfree = {
  71                 {.offset = 3,
  72                  .length = 2},
  73                 {.offset = 6,
  74                  .length = 2} }
  75 };
  76
  77 static struct nand_ecclayout nand_oob_16 = {
  78         .eccbytes = 6,
  79         .eccpos = {0, 1, 2, 3, 6, 7},
  80         .oobfree = {
  81                 {.offset = 8,
  82                  . length = 8} }
  83 };
  84
  85 static struct nand_ecclayout nand_oob_64 = {
  86         .eccbytes = 24,
  87         .eccpos = {
  88                    40, 41, 42, 43, 44, 45, 46, 47,
  89                    48, 49, 50, 51, 52, 53, 54, 55,
  90                    56, 57, 58, 59, 60, 61, 62, 63},
  91         .oobfree = {
  92                 {.offset = 2,
  93                  .length = 38} }
  94 };
  95
  96 static struct nand_ecclayout nand_oob_128 = {
  97         .eccbytes = 48,
  98         .eccpos = {
  99                    80, 81, 82, 83, 84, 85, 86, 87,
 100                    88, 89, 90, 91, 92, 93, 94, 95,
 101                    96, 97, 98, 99, 100, 101, 102, 103,
 102                    104, 105, 106, 107, 108, 109, 110, 111,
 103                    112, 113, 114, 115, 116, 117, 118, 119,
 104                    120, 121, 122, 123, 124, 125, 126, 127},
 105         .oobfree = {
 106                 {.offset = 2,
 107                  .length = 78} }
 108 };
 109
 110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 111                            int new_state);
 112
 113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 114                              struct mtd_oob_ops *ops);
 115
 116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 117
 118 static int check_offs_len(struct mtd_info *mtd,
 119                                         loff_t ofs, uint64_t len)
 120 {
 121         struct nand_chip *chip = mtd->priv;
 122         int ret = 0;
 123
 124         /* Start address must align on block boundary */
 125         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 126                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
 127                 ret = -EINVAL;
 128         }
 129
 130         /* Length must align on block boundary */
 131         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 132                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
 133                                         __func__);
 134                 ret = -EINVAL;
 135         }
 136
 137         return ret;
 138 }
 139
 140 /**
 141  * nand_release_device - [GENERIC] release chip
 142  * @mtd: MTD device structure
 143  *
 144  * Deselect, release chip lock and wake up anyone waiting on the device.
 145  */
 146 static void nand_release_device(struct mtd_info *mtd)
 147 {
 148         struct nand_chip *chip = mtd->priv;
 149
 150         /* De-select the NAND device */
 151         chip->select_chip(mtd, -1);
 152 }
 153
 154 /**
 155  * nand_read_byte - [DEFAULT] read one byte from the chip
 156  * @mtd: MTD device structure
 157  *
 158  * Default read function for 8bit buswidth.
 159  */
 160 uint8_t nand_read_byte(struct mtd_info *mtd)
 161 {
 162         struct nand_chip *chip = mtd->priv;
 163         return readb(chip->IO_ADDR_R);
 164 }
 165
 166 /**
 167  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 168  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 169  * @mtd: MTD device structure
 170  *
 171  * Default read function for 16bit buswidth with endianness conversion.
 172  *
 173  */
 174 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 175 {
 176         struct nand_chip *chip = mtd->priv;
 177         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 178 }
 179
 180 /**
 181  * nand_read_word - [DEFAULT] read one word from the chip
 182  * @mtd: MTD device structure
 183  *
 184  * Default read function for 16bit buswidth without endianness conversion.
 185  */
 186 static u16 nand_read_word(struct mtd_info *mtd)
 187 {
 188         struct nand_chip *chip = mtd->priv;
 189         return readw(chip->IO_ADDR_R);
 190 }
 191
 192 /**
 193  * nand_select_chip - [DEFAULT] control CE line
 194  * @mtd: MTD device structure
 195  * @chipnr: chipnumber to select, -1 for deselect
 196  *
 197  * Default select function for 1 chip devices.
 198  */
 199 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 200 {
 201         struct nand_chip *chip = mtd->priv;
 202
 203         switch (chipnr) {
 204         case -1:
 205                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 206                 break;
 207         case 0:
 208                 break;
 209
 210         default:
 211                 BUG();
 212         }
 213 }
 214
 215 /**
 216  * nand_write_buf - [DEFAULT] write buffer to chip
 217  * @mtd: MTD device structure
 218  * @buf: data buffer
 219  * @len: number of bytes to write
 220  *
 221  * Default write function for 8bit buswidth.
 222  */
 223 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 224 {
 225         int i;
 226         struct nand_chip *chip = mtd->priv;
 227
 228         for (i = 0; i < len; i++)
 229                 writeb(buf[i], chip->IO_ADDR_W);
 230 }
 231
 232 /**
 233  * nand_read_buf - [DEFAULT] read chip data into buffer
 234  * @mtd: MTD device structure
 235  * @buf: buffer to store date
 236  * @len: number of bytes to read
 237  *
 238  * Default read function for 8bit buswidth.
 239  */
 240 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 241 {
 242         int i;
 243         struct nand_chip *chip = mtd->priv;
 244
 245         for (i = 0; i < len; i++)
 246                 buf[i] = readb(chip->IO_ADDR_R);
 247 }
 248
 249 /**
 250  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 251  * @mtd: MTD device structure
 252  * @buf: buffer containing the data to compare
 253  * @len: number of bytes to compare
 254  *
 255  * Default verify function for 8bit buswidth.
 256  */
 257 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 258 {
 259         int i;
 260         struct nand_chip *chip = mtd->priv;
 261
 262         for (i = 0; i < len; i++)
 263                 if (buf[i] != readb(chip->IO_ADDR_R))
 264                         return -EFAULT;
 265         return 0;
 266 }
 267
 268 /**
 269  * nand_write_buf16 - [DEFAULT] write buffer to chip
 270  * @mtd: MTD device structure
 271  * @buf: data buffer
 272  * @len: number of bytes to write
 273  *
 274  * Default write function for 16bit buswidth.
 275  */
 276 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 277 {
 278         int i;
 279         struct nand_chip *chip = mtd->priv;
 280         u16 *p = (u16 *) buf;
 281         len >>= 1;
 282
 283         for (i = 0; i < len; i++)
 284                 writew(p[i], chip->IO_ADDR_W);
 285
 286 }
 287
 288 /**
 289  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 290  * @mtd: MTD device structure
 291  * @buf: buffer to store date
 292  * @len: number of bytes to read
 293  *
 294  * Default read function for 16bit buswidth.
 295  */
 296 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 297 {
 298         int i;
 299         struct nand_chip *chip = mtd->priv;
 300         u16 *p = (u16 *) buf;
 301         len >>= 1;
 302
 303         for (i = 0; i < len; i++)
 304                 p[i] = readw(chip->IO_ADDR_R);
 305 }
 306
 307 /**
 308  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 309  * @mtd: MTD device structure
 310  * @buf: buffer containing the data to compare
 311  * @len: number of bytes to compare
 312  *
 313  * Default verify function for 16bit buswidth.
 314  */
 315 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 316 {
 317         int i;
 318         struct nand_chip *chip = mtd->priv;
 319         u16 *p = (u16 *) buf;
 320         len >>= 1;
 321
 322         for (i = 0; i < len; i++)
 323                 if (p[i] != readw(chip->IO_ADDR_R))
 324                         return -EFAULT;
 325
 326         return 0;
 327 }
 328
 329 /**
 330  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 331  * @mtd: MTD device structure
 332  * @ofs: offset from device start
 333  * @getchip: 0, if the chip is already selected
 334  *
 335  * Check, if the block is bad.
 336  */
 337 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 338 {
 339         int page, chipnr, res = 0, i = 0;
 340         struct nand_chip *chip = mtd->priv;
 341         u16 bad;
 342
 343         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 344                 ofs += mtd->erasesize - mtd->writesize;
 345
 346         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 347
 348         if (getchip) {
 349                 chipnr = (int)(ofs >> chip->chip_shift);
 350
 351                 nand_get_device(chip, mtd, FL_READING);
 352
 353                 /* Select the NAND device */
 354                 chip->select_chip(mtd, chipnr);
 355         }
 356
 357         do {
 358                 if (chip->options & NAND_BUSWIDTH_16) {
 359                         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 360                                         chip->badblockpos & 0xFE, page);
 361                         bad = cpu_to_le16(chip->read_word(mtd));
 362                         if (chip->badblockpos & 0x1)
 363                                 bad >>= 8;
 364                         else
 365                                 bad &= 0xFF;
 366                 } else {
 367                         chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
 368                                         page);
 369                         bad = chip->read_byte(mtd);
 370                 }
 371
 372                 if (likely(chip->badblockbits == 8))
 373                         res = bad != 0xFF;
 374                 else
 375                         res = hweight8(bad) < chip->badblockbits;
 376                 ofs += mtd->writesize;
 377                 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 378                 i++;
 379         } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
 380
 381         if (getchip)
 382                 nand_release_device(mtd);
 383
 384         return res;
 385 }
 386
 387 /**
 388  * nand_default_block_markbad - [DEFAULT] mark a block bad
 389  * @mtd: MTD device structure
 390  * @ofs: offset from device start
 391  *
 392  * This is the default implementation, which can be overridden by a hardware
 393  * specific driver. We try operations in the following order, according to our
 394  * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
 395  *  (1) erase the affected block, to allow OOB marker to be written cleanly
 396  *  (2) update in-memory BBT
 397  *  (3) write bad block marker to OOB area of affected block
 398  *  (4) update flash-based BBT
 399  * Note that we retain the first error encountered in (3) or (4), finish the
 400  * procedures, and dump the error in the end.
 401 */
 402 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 403 {
 404         struct nand_chip *chip = mtd->priv;
 405         uint8_t buf[2] = { 0, 0 };
 406         int block, res, ret = 0, i = 0;
 407         int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
 408
 409         if (write_oob) {
 410                 struct erase_info einfo;
 411
 412                 /* Attempt erase before marking OOB */
 413                 memset(&einfo, 0, sizeof(einfo));
 414                 einfo.mtd = mtd;
 415                 einfo.addr = ofs;
 416                 einfo.len = 1 << chip->phys_erase_shift;
 417                 nand_erase_nand(mtd, &einfo, 0);
 418         }
 419
 420         /* Get block number */
 421         block = (int)(ofs >> chip->bbt_erase_shift);
 422         /* Mark block bad in memory-based BBT */
 423         if (chip->bbt)
 424                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 425
 426         /* Write bad block marker to OOB */
 427         if (write_oob) {
 428                 struct mtd_oob_ops ops;
 429                 loff_t wr_ofs = ofs;
 430
 431                 nand_get_device(chip, mtd, FL_WRITING);
 432
 433                 ops.datbuf = NULL;
 434                 ops.oobbuf = buf;
 435                 ops.ooboffs = chip->badblockpos;
 436                 if (chip->options & NAND_BUSWIDTH_16) {
 437                         ops.ooboffs &= ~0x01;
 438                         ops.len = ops.ooblen = 2;
 439                 } else {
 440                         ops.len = ops.ooblen = 1;
 441                 }
 442                 ops.mode = MTD_OPS_PLACE_OOB;
 443
 444                 /* Write to first/last page(s) if necessary */
 445                 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 446                         wr_ofs += mtd->erasesize - mtd->writesize;
 447                 do {
 448                         res = nand_do_write_oob(mtd, wr_ofs, &ops);
 449                         if (!ret)
 450                                 ret = res;
 451
 452                         i++;
 453                         wr_ofs += mtd->writesize;
 454                 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
 455
 456                 nand_release_device(mtd);
 457         }
 458
 459         /* Update flash-based bad block table */
 460         if (chip->bbt_options & NAND_BBT_USE_FLASH) {
 461                 res = nand_update_bbt(mtd, ofs);
 462                 if (!ret)
 463                         ret = res;
 464         }
 465
 466         if (!ret)
 467                 mtd->ecc_stats.badblocks++;
 468
 469         return ret;
 470 }
 471
 472 /**
 473  * nand_check_wp - [GENERIC] check if the chip is write protected
 474  * @mtd: MTD device structure
 475  *
 476  * Check, if the device is write protected. The function expects, that the
 477  * device is already selected.
 478  */
 479 static int nand_check_wp(struct mtd_info *mtd)
 480 {
 481         struct nand_chip *chip = mtd->priv;
 482
 483         /* Broken xD cards report WP despite being writable */
 484         if (chip->options & NAND_BROKEN_XD)
 485                 return 0;
 486
 487         /* Check the WP bit */
 488         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 489         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 490 }
 491
 492 /**
 493  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 494  * @mtd: MTD device structure
 495  * @ofs: offset from device start
 496  * @getchip: 0, if the chip is already selected
 497  * @allowbbt: 1, if its allowed to access the bbt area
 498  *
 499  * Check, if the block is bad. Either by reading the bad block table or
 500  * calling of the scan function.
 501  */
 502 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 503                                int allowbbt)
 504 {
 505         struct nand_chip *chip = mtd->priv;
 506
 507         if (!(chip->options & NAND_BBT_SCANNED)) {
 508                 chip->options |= NAND_BBT_SCANNED;
 509                 chip->scan_bbt(mtd);
 510         }
 511
 512         if (!chip->bbt)
 513                 return chip->block_bad(mtd, ofs, getchip);
 514
 515         /* Return info from the table */
 516         return nand_isbad_bbt(mtd, ofs, allowbbt);
 517 }
 518
 519 /* Wait for the ready pin, after a command. The timeout is caught later. */
 520 void nand_wait_ready(struct mtd_info *mtd)
 521 {
 522         struct nand_chip *chip = mtd->priv;
 523         u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 524         u32 time_start;
 525
 526         time_start = get_timer(0);
 527
 528         /* Wait until command is processed or timeout occurs */
 529         while (get_timer(time_start) < timeo) {
 530                 if (chip->dev_ready)
 531                         if (chip->dev_ready(mtd))
 532                                 break;
 533         }
 534 }
 535
 536 /**
 537  * nand_command - [DEFAULT] Send command to NAND device
 538  * @mtd: MTD device structure
 539  * @command: the command to be sent
 540  * @column: the column address for this command, -1 if none
 541  * @page_addr: the page address for this command, -1 if none
 542  *
 543  * Send command to NAND device. This function is used for small page devices
 544  * (256/512 Bytes per page).
 545  */
 546 static void nand_command(struct mtd_info *mtd, unsigned int command,
 547                          int column, int page_addr)
 548 {
 549         register struct nand_chip *chip = mtd->priv;
 550         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 551         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 552
 553         /* Write out the command to the device */
 554         if (command == NAND_CMD_SEQIN) {
 555                 int readcmd;
 556
 557                 if (column >= mtd->writesize) {
 558                         /* OOB area */
 559                         column -= mtd->writesize;
 560                         readcmd = NAND_CMD_READOOB;
 561                 } else if (column < 256) {
 562                         /* First 256 bytes --> READ0 */
 563                         readcmd = NAND_CMD_READ0;
 564                 } else {
 565                         column -= 256;
 566                         readcmd = NAND_CMD_READ1;
 567                 }
 568                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 569                 ctrl &= ~NAND_CTRL_CHANGE;
 570         }
 571         chip->cmd_ctrl(mtd, command, ctrl);
 572
 573         /* Address cycle, when necessary */
 574         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 575         /* Serially input address */
 576         if (column != -1) {
 577                 /* Adjust columns for 16 bit buswidth */
 578                 if ((chip->options & NAND_BUSWIDTH_16) &&
 579                                 !nand_opcode_8bits(command))
 580                         column >>= 1;
 581                 chip->cmd_ctrl(mtd, column, ctrl);
 582                 ctrl &= ~NAND_CTRL_CHANGE;
 583         }
 584         if (page_addr != -1) {
 585                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 586                 ctrl &= ~NAND_CTRL_CHANGE;
 587                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 588                 /* One more address cycle for devices > 32MiB */
 589                 if (chip->chipsize > (32 << 20))
 590                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 591         }
 592         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 593
 594         /*
 595          * Program and erase have their own busy handlers status and sequential
 596          * in needs no delay
 597          */
 598         switch (command) {
 599
 600         case NAND_CMD_PAGEPROG:
 601         case NAND_CMD_ERASE1:
 602         case NAND_CMD_ERASE2:
 603         case NAND_CMD_SEQIN:
 604         case NAND_CMD_STATUS:
 605                 return;
 606
 607         case NAND_CMD_RESET:
 608                 if (chip->dev_ready)
 609                         break;
 610                 udelay(chip->chip_delay);
 611                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 612                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 613                 chip->cmd_ctrl(mtd,
 614                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 615                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 616                         (rst_sts_cnt--));
 617                 return;
 618
 619                 /* This applies to read commands */
 620         default:
 621                 /*
 622                  * If we don't have access to the busy pin, we apply the given
 623                  * command delay
 624                  */
 625                 if (!chip->dev_ready) {
 626                         udelay(chip->chip_delay);
 627                         return;
 628                 }
 629         }
 630         /*
 631          * Apply this short delay always to ensure that we do wait tWB in
 632          * any case on any machine.
 633          */
 634         ndelay(100);
 635
 636         nand_wait_ready(mtd);
 637 }
 638
 639 /**
 640  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 641  * @mtd: MTD device structure
 642  * @command: the command to be sent
 643  * @column: the column address for this command, -1 if none
 644  * @page_addr: the page address for this command, -1 if none
 645  *
 646  * Send command to NAND device. This is the version for the new large page
 647  * devices. We don't have the separate regions as we have in the small page
 648  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 649  */
 650 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 651                             int column, int page_addr)
 652 {
 653         register struct nand_chip *chip = mtd->priv;
 654         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 655
 656         /* Emulate NAND_CMD_READOOB */
 657         if (command == NAND_CMD_READOOB) {
 658                 column += mtd->writesize;
 659                 command = NAND_CMD_READ0;
 660         }
 661
 662         /* Command latch cycle */
 663         chip->cmd_ctrl(mtd, command & 0xff,
 664                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 665
 666         if (column != -1 || page_addr != -1) {
 667                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 668
 669                 /* Serially input address */
 670                 if (column != -1) {
 671                         /* Adjust columns for 16 bit buswidth */
 672                         if ((chip->options & NAND_BUSWIDTH_16) &&
 673                                         !nand_opcode_8bits(command))
 674                                 column >>= 1;
 675                         chip->cmd_ctrl(mtd, column, ctrl);
 676                         ctrl &= ~NAND_CTRL_CHANGE;
 677                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 678                 }
 679                 if (page_addr != -1) {
 680                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 681                         chip->cmd_ctrl(mtd, page_addr >> 8,
 682                                        NAND_NCE | NAND_ALE);
 683                         /* One more address cycle for devices > 128MiB */
 684                         if (chip->chipsize > (128 << 20))
 685                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 686                                                NAND_NCE | NAND_ALE);
 687                 }
 688         }
 689         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 690
 691         /*
 692          * Program and erase have their own busy handlers status, sequential
 693          * in, and deplete1 need no delay.
 694          */
 695         switch (command) {
 696
 697         case NAND_CMD_CACHEDPROG:
 698         case NAND_CMD_PAGEPROG:
 699         case NAND_CMD_ERASE1:
 700         case NAND_CMD_ERASE2:
 701         case NAND_CMD_SEQIN:
 702         case NAND_CMD_RNDIN:
 703         case NAND_CMD_STATUS:
 704         case NAND_CMD_DEPLETE1:
 705                 return;
 706
 707         case NAND_CMD_STATUS_ERROR:
 708         case NAND_CMD_STATUS_ERROR0:
 709         case NAND_CMD_STATUS_ERROR1:
 710         case NAND_CMD_STATUS_ERROR2:
 711         case NAND_CMD_STATUS_ERROR3:
 712                 /* Read error status commands require only a short delay */
 713                 udelay(chip->chip_delay);
 714                 return;
 715
 716         case NAND_CMD_RESET:
 717                 if (chip->dev_ready)
 718                         break;
 719                 udelay(chip->chip_delay);
 720                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 721                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 722                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 723                                NAND_NCE | NAND_CTRL_CHANGE);
 724                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 725                         (rst_sts_cnt--));
 726                 return;
 727
 728         case NAND_CMD_RNDOUT:
 729                 /* No ready / busy check necessary */
 730                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 731                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 732                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 733                                NAND_NCE | NAND_CTRL_CHANGE);
 734                 return;
 735
 736         case NAND_CMD_READ0:
 737                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 738                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 739                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 740                                NAND_NCE | NAND_CTRL_CHANGE);
 741
 742                 /* This applies to read commands */
 743         default:
 744                 /*
 745                  * If we don't have access to the busy pin, we apply the given
 746                  * command delay.
 747                  */
 748                 if (!chip->dev_ready) {
 749                         udelay(chip->chip_delay);
 750                         return;
 751                 }
 752         }
 753
 754         /*
 755          * Apply this short delay always to ensure that we do wait tWB in
 756          * any case on any machine.
 757          */
 758         ndelay(100);
 759
 760         nand_wait_ready(mtd);
 761 }
 762
 763 /**
 764  * nand_get_device - [GENERIC] Get chip for selected access
 765  * @chip: the nand chip descriptor
 766  * @mtd: MTD device structure
 767  * @new_state: the state which is requested
 768  *
 769  * Get the device and lock it for exclusive access
 770  */
 771 static int
 772 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 773 {
 774         chip->state = new_state;
 775         return 0;
 776 }
 777
 778 /**
 779  * nand_wait - [DEFAULT] wait until the command is done
 780  * @mtd: MTD device structure
 781  * @chip: NAND chip structure
 782  *
 783  * Wait for command done. This applies to erase and program only. Erase can
 784  * take up to 400ms and program up to 20ms according to general NAND and
 785  * SmartMedia specs.
 786  */
 787 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 788 {
 789         unsigned long   timeo;
 790         int state = chip->state;
 791         u32 time_start;
 792
 793         if (state == FL_ERASING)
 794                 timeo = (CONFIG_SYS_HZ * 400) / 1000;
 795         else
 796                 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 797
 798         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 799                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 800         else
 801                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 802
 803         time_start = get_timer(0);
 804
 805         while (1) {
 806                 if (get_timer(time_start) > timeo) {
 807                         printf("Timeout!");
 808                         return 0x01;
 809                 }
 810
 811                 if (chip->dev_ready) {
 812                         if (chip->dev_ready(mtd))
 813                                 break;
 814                 } else {
 815                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 816                                 break;
 817                 }
 818         }
 819 #ifdef PPCHAMELON_NAND_TIMER_HACK
 820         time_start = get_timer(0);
 821         while (get_timer(time_start) < 10)
 822                 ;
 823 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 824
 825         return (int)chip->read_byte(mtd);
 826 }
 827
 828 /**
 829  * nand_read_page_raw - [INTERN] read raw page data without ecc
 830  * @mtd: mtd info structure
 831  * @chip: nand chip info structure
 832  * @buf: buffer to store read data
 833  * @oob_required: caller requires OOB data read to chip->oob_poi
 834  * @page: page number to read
 835  *
 836  * Not for syndrome calculating ECC controllers, which use a special oob layout.
 837  */
 838 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 839                               uint8_t *buf, int oob_required, int page)
 840 {
 841         chip->read_buf(mtd, buf, mtd->writesize);
 842         if (oob_required)
 843                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 844         return 0;
 845 }
 846
 847 /**
 848  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
 849  * @mtd: mtd info structure
 850  * @chip: nand chip info structure
 851  * @buf: buffer to store read data
 852  * @oob_required: caller requires OOB data read to chip->oob_poi
 853  * @page: page number to read
 854  *
 855  * We need a special oob layout and handling even when OOB isn't used.
 856  */
 857 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
 858                                        struct nand_chip *chip, uint8_t *buf,
 859                                        int oob_required, int page)
 860 {
 861         int eccsize = chip->ecc.size;
 862         int eccbytes = chip->ecc.bytes;
 863         uint8_t *oob = chip->oob_poi;
 864         int steps, size;
 865
 866         for (steps = chip->ecc.steps; steps > 0; steps--) {
 867                 chip->read_buf(mtd, buf, eccsize);
 868                 buf += eccsize;
 869
 870                 if (chip->ecc.prepad) {
 871                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 872                         oob += chip->ecc.prepad;
 873                 }
 874
 875                 chip->read_buf(mtd, oob, eccbytes);
 876                 oob += eccbytes;
 877
 878                 if (chip->ecc.postpad) {
 879                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 880                         oob += chip->ecc.postpad;
 881                 }
 882         }
 883
 884         size = mtd->oobsize - (oob - chip->oob_poi);
 885         if (size)
 886                 chip->read_buf(mtd, oob, size);
 887
 888         return 0;
 889 }
 890
 891 /**
 892  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
 893  * @mtd: mtd info structure
 894  * @chip: nand chip info structure
 895  * @buf: buffer to store read data
 896  * @oob_required: caller requires OOB data read to chip->oob_poi
 897  * @page: page number to read
 898  */
 899 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 900                                 uint8_t *buf, int oob_required, int page)
 901 {
 902         int i, eccsize = chip->ecc.size;
 903         int eccbytes = chip->ecc.bytes;
 904         int eccsteps = chip->ecc.steps;
 905         uint8_t *p = buf;
 906         uint8_t *ecc_calc = chip->buffers->ecccalc;
 907         uint8_t *ecc_code = chip->buffers->ecccode;
 908         uint32_t *eccpos = chip->ecc.layout->eccpos;
 909
 910         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
 911
 912         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 913                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 914
 915         for (i = 0; i < chip->ecc.total; i++)
 916                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 917
 918         eccsteps = chip->ecc.steps;
 919         p = buf;
 920
 921         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 922                 int stat;
 923
 924                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 925                 if (stat < 0)
 926                         mtd->ecc_stats.failed++;
 927                 else
 928                         mtd->ecc_stats.corrected += stat;
 929         }
 930         return 0;
 931 }
 932
 933 /**
 934  * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
 935  * @mtd: mtd info structure
 936  * @chip: nand chip info structure
 937  * @data_offs: offset of requested data within the page
 938  * @readlen: data length
 939  * @bufpoi: buffer to store read data
 940  */
 941 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 942                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
 943 {
 944         int start_step, end_step, num_steps;
 945         uint32_t *eccpos = chip->ecc.layout->eccpos;
 946         uint8_t *p;
 947         int data_col_addr, i, gaps = 0;
 948         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
 949         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
 950         int index = 0;
 951
 952         /* Column address within the page aligned to ECC size (256bytes) */
 953         start_step = data_offs / chip->ecc.size;
 954         end_step = (data_offs + readlen - 1) / chip->ecc.size;
 955         num_steps = end_step - start_step + 1;
 956
 957         /* Data size aligned to ECC ecc.size */
 958         datafrag_len = num_steps * chip->ecc.size;
 959         eccfrag_len = num_steps * chip->ecc.bytes;
 960
 961         data_col_addr = start_step * chip->ecc.size;
 962         /* If we read not a page aligned data */
 963         if (data_col_addr != 0)
 964                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
 965
 966         p = bufpoi + data_col_addr;
 967         chip->read_buf(mtd, p, datafrag_len);
 968
 969         /* Calculate ECC */
 970         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
 971                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
 972
 973         /*
 974          * The performance is faster if we position offsets according to
 975          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
 976          */
 977         for (i = 0; i < eccfrag_len - 1; i++) {
 978                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
 979                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
 980                         gaps = 1;
 981                         break;
 982                 }
 983         }
 984         if (gaps) {
 985                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 986                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 987         } else {
 988                 /*
 989                  * Send the command to read the particular ECC bytes take care
 990                  * about buswidth alignment in read_buf.
 991                  */
 992                 index = start_step * chip->ecc.bytes;
 993
 994                 aligned_pos = eccpos[index] & ~(busw - 1);
 995                 aligned_len = eccfrag_len;
 996                 if (eccpos[index] & (busw - 1))
 997                         aligned_len++;
 998                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
 999                         aligned_len++;
1000
1001                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1002                                         mtd->writesize + aligned_pos, -1);
1003                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1004         }
1005
1006         for (i = 0; i < eccfrag_len; i++)
1007                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1008
1009         p = bufpoi + data_col_addr;
1010         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1011                 int stat;
1012
1013                 stat = chip->ecc.correct(mtd, p,
1014                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1015                 if (stat < 0)
1016                         mtd->ecc_stats.failed++;
1017                 else
1018                         mtd->ecc_stats.corrected += stat;
1019         }
1020         return 0;
1021 }
1022
1023 /**
1024  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1025  * @mtd: mtd info structure
1026  * @chip: nand chip info structure
1027  * @buf: buffer to store read data
1028  * @oob_required: caller requires OOB data read to chip->oob_poi
1029  * @page: page number to read
1030  *
1031  * Not for syndrome calculating ECC controllers which need a special oob layout.
1032  */
1033 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1034                                 uint8_t *buf, int oob_required, int page)
1035 {
1036         int i, eccsize = chip->ecc.size;
1037         int eccbytes = chip->ecc.bytes;
1038         int eccsteps = chip->ecc.steps;
1039         uint8_t *p = buf;
1040         uint8_t *ecc_calc = chip->buffers->ecccalc;
1041         uint8_t *ecc_code = chip->buffers->ecccode;
1042         uint32_t *eccpos = chip->ecc.layout->eccpos;
1043
1044         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1045                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1046                 chip->read_buf(mtd, p, eccsize);
1047                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1048         }
1049         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1050
1051         for (i = 0; i < chip->ecc.total; i++)
1052                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1053
1054         eccsteps = chip->ecc.steps;
1055         p = buf;
1056
1057         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1058                 int stat;
1059
1060                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1061                 if (stat < 0)
1062                         mtd->ecc_stats.failed++;
1063                 else
1064                         mtd->ecc_stats.corrected += stat;
1065         }
1066         return 0;
1067 }
1068
1069 /**
1070  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1071  * @mtd: mtd info structure
1072  * @chip: nand chip info structure
1073  * @buf: buffer to store read data
1074  * @oob_required: caller requires OOB data read to chip->oob_poi
1075  * @page: page number to read
1076  *
1077  * Hardware ECC for large page chips, require OOB to be read first. For this
1078  * ECC mode, the write_page method is re-used from ECC_HW. These methods
1079  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1080  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1081  * the data area, by overwriting the NAND manufacturer bad block markings.
1082  */
1083 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1084         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1085 {
1086         int i, eccsize = chip->ecc.size;
1087         int eccbytes = chip->ecc.bytes;
1088         int eccsteps = chip->ecc.steps;
1089         uint8_t *p = buf;
1090         uint8_t *ecc_code = chip->buffers->ecccode;
1091         uint32_t *eccpos = chip->ecc.layout->eccpos;
1092         uint8_t *ecc_calc = chip->buffers->ecccalc;
1093
1094         /* Read the OOB area first */
1095         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1096         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1097         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1098
1099         for (i = 0; i < chip->ecc.total; i++)
1100                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1101
1102         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1103                 int stat;
1104
1105                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1106                 chip->read_buf(mtd, p, eccsize);
1107                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1108
1109                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1110                 if (stat < 0)
1111                         mtd->ecc_stats.failed++;
1112                 else
1113                         mtd->ecc_stats.corrected += stat;
1114         }
1115         return 0;
1116 }
1117
1118 /**
1119  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1120  * @mtd: mtd info structure
1121  * @chip: nand chip info structure
1122  * @buf: buffer to store read data
1123  * @oob_required: caller requires OOB data read to chip->oob_poi
1124  * @page: page number to read
1125  *
1126  * The hw generator calculates the error syndrome automatically. Therefore we
1127  * need a special oob layout and handling.
1128  */
1129 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1130                                    uint8_t *buf, int oob_required, int page)
1131 {
1132         int i, eccsize = chip->ecc.size;
1133         int eccbytes = chip->ecc.bytes;
1134         int eccsteps = chip->ecc.steps;
1135         uint8_t *p = buf;
1136         uint8_t *oob = chip->oob_poi;
1137
1138         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1139                 int stat;
1140
1141                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1142                 chip->read_buf(mtd, p, eccsize);
1143
1144                 if (chip->ecc.prepad) {
1145                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1146                         oob += chip->ecc.prepad;
1147                 }
1148
1149                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1150                 chip->read_buf(mtd, oob, eccbytes);
1151                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1152
1153                 if (stat < 0)
1154                         mtd->ecc_stats.failed++;
1155                 else
1156                         mtd->ecc_stats.corrected += stat;
1157
1158                 oob += eccbytes;
1159
1160                 if (chip->ecc.postpad) {
1161                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1162                         oob += chip->ecc.postpad;
1163                 }
1164         }
1165
1166         /* Calculate remaining oob bytes */
1167         i = mtd->oobsize - (oob - chip->oob_poi);
1168         if (i)
1169                 chip->read_buf(mtd, oob, i);
1170
1171         return 0;
1172 }
1173
1174 /**
1175  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1176  * @chip: nand chip structure
1177  * @oob: oob destination address
1178  * @ops: oob ops structure
1179  * @len: size of oob to transfer
1180  */
1181 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1182                                   struct mtd_oob_ops *ops, size_t len)
1183 {
1184         switch (ops->mode) {
1185
1186         case MTD_OPS_PLACE_OOB:
1187         case MTD_OPS_RAW:
1188                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1189                 return oob + len;
1190
1191         case MTD_OPS_AUTO_OOB: {
1192                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1193                 uint32_t boffs = 0, roffs = ops->ooboffs;
1194                 size_t bytes = 0;
1195
1196                 for (; free->length && len; free++, len -= bytes) {
1197                         /* Read request not from offset 0? */
1198                         if (unlikely(roffs)) {
1199                                 if (roffs >= free->length) {
1200                                         roffs -= free->length;
1201                                         continue;
1202                                 }
1203                                 boffs = free->offset + roffs;
1204                                 bytes = min_t(size_t, len,
1205                                               (free->length - roffs));
1206                                 roffs = 0;
1207                         } else {
1208                                 bytes = min_t(size_t, len, free->length);
1209                                 boffs = free->offset;
1210                         }
1211                         memcpy(oob, chip->oob_poi + boffs, bytes);
1212                         oob += bytes;
1213                 }
1214                 return oob;
1215         }
1216         default:
1217                 BUG();
1218         }
1219         return NULL;
1220 }
1221
1222 /**
1223  * nand_do_read_ops - [INTERN] Read data with ECC
1224  * @mtd: MTD device structure
1225  * @from: offset to read from
1226  * @ops: oob ops structure
1227  *
1228  * Internal function. Called with chip held.
1229  */
1230 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1231                             struct mtd_oob_ops *ops)
1232 {
1233         int chipnr, page, realpage, col, bytes, aligned, oob_required;
1234         struct nand_chip *chip = mtd->priv;
1235         struct mtd_ecc_stats stats;
1236         int ret = 0;
1237         uint32_t readlen = ops->len;
1238         uint32_t oobreadlen = ops->ooblen;
1239         uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1240                 mtd->oobavail : mtd->oobsize;
1241
1242         uint8_t *bufpoi, *oob, *buf;
1243         unsigned int max_bitflips = 0;
1244
1245         stats = mtd->ecc_stats;
1246
1247         chipnr = (int)(from >> chip->chip_shift);
1248         chip->select_chip(mtd, chipnr);
1249
1250         realpage = (int)(from >> chip->page_shift);
1251         page = realpage & chip->pagemask;
1252
1253         col = (int)(from & (mtd->writesize - 1));
1254
1255         buf = ops->datbuf;
1256         oob = ops->oobbuf;
1257         oob_required = oob ? 1 : 0;
1258
1259         while (1) {
1260                 WATCHDOG_RESET();
1261
1262                 bytes = min(mtd->writesize - col, readlen);
1263                 aligned = (bytes == mtd->writesize);
1264
1265                 /* Is the current page in the buffer? */
1266                 if (realpage != chip->pagebuf || oob) {
1267                         bufpoi = aligned ? buf : chip->buffers->databuf;
1268
1269                         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1270
1271                         /*
1272                          * Now read the page into the buffer.  Absent an error,
1273                          * the read methods return max bitflips per ecc step.
1274                          */
1275                         if (unlikely(ops->mode == MTD_OPS_RAW))
1276                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1277                                                               oob_required,
1278                                                               page);
1279                         else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1280                             !oob)
1281                                 ret = chip->ecc.read_subpage(mtd, chip,
1282                                                         col, bytes, bufpoi);
1283                         else
1284                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1285                                                           oob_required, page);
1286                         if (ret < 0) {
1287                                 if (!aligned)
1288                                         /* Invalidate page cache */
1289                                         chip->pagebuf = -1;
1290                                 break;
1291                         }
1292
1293                         max_bitflips = max_t(unsigned int, max_bitflips, ret);
1294
1295                         /* Transfer not aligned data */
1296                         if (!aligned) {
1297                                 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1298                                     !(mtd->ecc_stats.failed - stats.failed) &&
1299                                     (ops->mode != MTD_OPS_RAW)) {
1300                                         chip->pagebuf = realpage;
1301                                         chip->pagebuf_bitflips = ret;
1302                                 } else {
1303                                         /* Invalidate page cache */
1304                                         chip->pagebuf = -1;
1305                                 }
1306                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1307                         }
1308
1309                         buf += bytes;
1310
1311                         if (unlikely(oob)) {
1312                                 int toread = min(oobreadlen, max_oobsize);
1313
1314                                 if (toread) {
1315                                         oob = nand_transfer_oob(chip,
1316                                                 oob, ops, toread);
1317                                         oobreadlen -= toread;
1318                                 }
1319                         }
1320                 } else {
1321                         memcpy(buf, chip->buffers->databuf + col, bytes);
1322                         buf += bytes;
1323                         max_bitflips = max_t(unsigned int, max_bitflips,
1324                                              chip->pagebuf_bitflips);
1325                 }
1326
1327                 readlen -= bytes;
1328
1329                 if (!readlen)
1330                         break;
1331
1332                 /* For subsequent reads align to page boundary */
1333                 col = 0;
1334                 /* Increment page address */
1335                 realpage++;
1336
1337                 page = realpage & chip->pagemask;
1338                 /* Check, if we cross a chip boundary */
1339                 if (!page) {
1340                         chipnr++;
1341                         chip->select_chip(mtd, -1);
1342                         chip->select_chip(mtd, chipnr);
1343                 }
1344         }
1345
1346         ops->retlen = ops->len - (size_t) readlen;
1347         if (oob)
1348                 ops->oobretlen = ops->ooblen - oobreadlen;
1349
1350         if (ret)
1351                 return ret;
1352
1353         if (mtd->ecc_stats.failed - stats.failed)
1354                 return -EBADMSG;
1355
1356         return max_bitflips;
1357 }
1358
1359 /**
1360  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1361  * @mtd: MTD device structure
1362  * @from: offset to read from
1363  * @len: number of bytes to read
1364  * @retlen: pointer to variable to store the number of read bytes
1365  * @buf: the databuffer to put data
1366  *
1367  * Get hold of the chip and call nand_do_read.
1368  */
1369 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1370                      size_t *retlen, uint8_t *buf)
1371 {
1372         struct nand_chip *chip = mtd->priv;
1373         struct mtd_oob_ops ops;
1374         int ret;
1375
1376         nand_get_device(chip, mtd, FL_READING);
1377         ops.len = len;
1378         ops.datbuf = buf;
1379         ops.oobbuf = NULL;
1380         ops.mode = MTD_OPS_PLACE_OOB;
1381         ret = nand_do_read_ops(mtd, from, &ops);
1382         *retlen = ops.retlen;
1383         nand_release_device(mtd);
1384         return ret;
1385 }
1386
1387 /**
1388  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1389  * @mtd: mtd info structure
1390  * @chip: nand chip info structure
1391  * @page: page number to read
1392  */
1393 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1394                              int page)
1395 {
1396         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1397         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1398         return 0;
1399 }
1400
1401 /**
1402  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1403  *                          with syndromes
1404  * @mtd: mtd info structure
1405  * @chip: nand chip info structure
1406  * @page: page number to read
1407  */
1408 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1409                                   int page)
1410 {
1411         uint8_t *buf = chip->oob_poi;
1412         int length = mtd->oobsize;
1413         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1414         int eccsize = chip->ecc.size;
1415         uint8_t *bufpoi = buf;
1416         int i, toread, sndrnd = 0, pos;
1417
1418         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1419         for (i = 0; i < chip->ecc.steps; i++) {
1420                 if (sndrnd) {
1421                         pos = eccsize + i * (eccsize + chunk);
1422                         if (mtd->writesize > 512)
1423                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1424                         else
1425                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1426                 } else
1427                         sndrnd = 1;
1428                 toread = min_t(int, length, chunk);
1429                 chip->read_buf(mtd, bufpoi, toread);
1430                 bufpoi += toread;
1431                 length -= toread;
1432         }
1433         if (length > 0)
1434                 chip->read_buf(mtd, bufpoi, length);
1435
1436         return 0;
1437 }
1438
1439 /**
1440  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1441  * @mtd: mtd info structure
1442  * @chip: nand chip info structure
1443  * @page: page number to write
1444  */
1445 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1446                               int page)
1447 {
1448         int status = 0;
1449         const uint8_t *buf = chip->oob_poi;
1450         int length = mtd->oobsize;
1451
1452         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1453         chip->write_buf(mtd, buf, length);
1454         /* Send command to program the OOB data */
1455         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1456
1457         status = chip->waitfunc(mtd, chip);
1458
1459         return status & NAND_STATUS_FAIL ? -EIO : 0;
1460 }
1461
1462 /**
1463  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1464  *                           with syndrome - only for large page flash
1465  * @mtd: mtd info structure
1466  * @chip: nand chip info structure
1467  * @page: page number to write
1468  */
1469 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1470                                    struct nand_chip *chip, int page)
1471 {
1472         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1473         int eccsize = chip->ecc.size, length = mtd->oobsize;
1474         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1475         const uint8_t *bufpoi = chip->oob_poi;
1476
1477         /*
1478          * data-ecc-data-ecc ... ecc-oob
1479          * or
1480          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1481          */
1482         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1483                 pos = steps * (eccsize + chunk);
1484                 steps = 0;
1485         } else
1486                 pos = eccsize;
1487
1488         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1489         for (i = 0; i < steps; i++) {
1490                 if (sndcmd) {
1491                         if (mtd->writesize <= 512) {
1492                                 uint32_t fill = 0xFFFFFFFF;
1493
1494                                 len = eccsize;
1495                                 while (len > 0) {
1496                                         int num = min_t(int, len, 4);
1497                                         chip->write_buf(mtd, (uint8_t *)&fill,
1498                                                         num);
1499                                         len -= num;
1500                                 }
1501                         } else {
1502                                 pos = eccsize + i * (eccsize + chunk);
1503                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1504                         }
1505                 } else
1506                         sndcmd = 1;
1507                 len = min_t(int, length, chunk);
1508                 chip->write_buf(mtd, bufpoi, len);
1509                 bufpoi += len;
1510                 length -= len;
1511         }
1512         if (length > 0)
1513                 chip->write_buf(mtd, bufpoi, length);
1514
1515         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1516         status = chip->waitfunc(mtd, chip);
1517
1518         return status & NAND_STATUS_FAIL ? -EIO : 0;
1519 }
1520
1521 /**
1522  * nand_do_read_oob - [INTERN] NAND read out-of-band
1523  * @mtd: MTD device structure
1524  * @from: offset to read from
1525  * @ops: oob operations description structure
1526  *
1527  * NAND read out-of-band data from the spare area.
1528  */
1529 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1530                             struct mtd_oob_ops *ops)
1531 {
1532         int page, realpage, chipnr;
1533         struct nand_chip *chip = mtd->priv;
1534         struct mtd_ecc_stats stats;
1535         int readlen = ops->ooblen;
1536         int len;
1537         uint8_t *buf = ops->oobbuf;
1538         int ret = 0;
1539
1540         MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1541                         __func__, (unsigned long long)from, readlen);
1542
1543         stats = mtd->ecc_stats;
1544
1545         if (ops->mode == MTD_OPS_AUTO_OOB)
1546                 len = chip->ecc.layout->oobavail;
1547         else
1548                 len = mtd->oobsize;
1549
1550         if (unlikely(ops->ooboffs >= len)) {
1551                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1552                                         "outside oob\n", __func__);
1553                 return -EINVAL;
1554         }
1555
1556         /* Do not allow reads past end of device */
1557         if (unlikely(from >= mtd->size ||
1558                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1559                                         (from >> chip->page_shift)) * len)) {
1560                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1561                                         "of device\n", __func__);
1562                 return -EINVAL;
1563         }
1564
1565         chipnr = (int)(from >> chip->chip_shift);
1566         chip->select_chip(mtd, chipnr);
1567
1568         /* Shift to get page */
1569         realpage = (int)(from >> chip->page_shift);
1570         page = realpage & chip->pagemask;
1571
1572         while (1) {
1573                 WATCHDOG_RESET();
1574                 if (ops->mode == MTD_OPS_RAW)
1575                         ret = chip->ecc.read_oob_raw(mtd, chip, page);
1576                 else
1577                         ret = chip->ecc.read_oob(mtd, chip, page);
1578
1579                 if (ret < 0)
1580                         break;
1581
1582                 len = min(len, readlen);
1583                 buf = nand_transfer_oob(chip, buf, ops, len);
1584
1585                 readlen -= len;
1586                 if (!readlen)
1587                         break;
1588
1589                 /* Increment page address */
1590                 realpage++;
1591
1592                 page = realpage & chip->pagemask;
1593                 /* Check, if we cross a chip boundary */
1594                 if (!page) {
1595                         chipnr++;
1596                         chip->select_chip(mtd, -1);
1597                         chip->select_chip(mtd, chipnr);
1598                 }
1599         }
1600
1601         ops->oobretlen = ops->ooblen - readlen;
1602
1603         if (ret < 0)
1604                 return ret;
1605
1606         if (mtd->ecc_stats.failed - stats.failed)
1607                 return -EBADMSG;
1608
1609         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1610 }
1611
1612 /**
1613  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1614  * @mtd: MTD device structure
1615  * @from: offset to read from
1616  * @ops: oob operation description structure
1617  *
1618  * NAND read data and/or out-of-band data.
1619  */
1620 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1621                          struct mtd_oob_ops *ops)
1622 {
1623         struct nand_chip *chip = mtd->priv;
1624         int ret = -ENOTSUPP;
1625
1626         ops->retlen = 0;
1627
1628         /* Do not allow reads past end of device */
1629         if (ops->datbuf && (from + ops->len) > mtd->size) {
1630                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1631                                 "beyond end of device\n", __func__);
1632                 return -EINVAL;
1633         }
1634
1635         nand_get_device(chip, mtd, FL_READING);
1636
1637         switch (ops->mode) {
1638         case MTD_OPS_PLACE_OOB:
1639         case MTD_OPS_AUTO_OOB:
1640         case MTD_OPS_RAW:
1641                 break;
1642
1643         default:
1644                 goto out;
1645         }
1646
1647         if (!ops->datbuf)
1648                 ret = nand_do_read_oob(mtd, from, ops);
1649         else
1650                 ret = nand_do_read_ops(mtd, from, ops);
1651
1652 out:
1653         nand_release_device(mtd);
1654         return ret;
1655 }
1656
1657
1658 /**
1659  * nand_write_page_raw - [INTERN] raw page write function
1660  * @mtd: mtd info structure
1661  * @chip: nand chip info structure
1662  * @buf: data buffer
1663  * @oob_required: must write chip->oob_poi to OOB
1664  *
1665  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1666  */
1667 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1668                                 const uint8_t *buf, int oob_required)
1669 {
1670         chip->write_buf(mtd, buf, mtd->writesize);
1671         if (oob_required)
1672                 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1673
1674         return 0;
1675 }
1676
1677 /**
1678  * nand_write_page_raw_syndrome - [INTERN] raw page write function
1679  * @mtd: mtd info structure
1680  * @chip: nand chip info structure
1681  * @buf: data buffer
1682  * @oob_required: must write chip->oob_poi to OOB
1683  *
1684  * We need a special oob layout and handling even when ECC isn't checked.
1685  */
1686 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1687                                         struct nand_chip *chip,
1688                                         const uint8_t *buf, int oob_required)
1689 {
1690         int eccsize = chip->ecc.size;
1691         int eccbytes = chip->ecc.bytes;
1692         uint8_t *oob = chip->oob_poi;
1693         int steps, size;
1694
1695         for (steps = chip->ecc.steps; steps > 0; steps--) {
1696                 chip->write_buf(mtd, buf, eccsize);
1697                 buf += eccsize;
1698
1699                 if (chip->ecc.prepad) {
1700                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1701                         oob += chip->ecc.prepad;
1702                 }
1703
1704                 chip->read_buf(mtd, oob, eccbytes);
1705                 oob += eccbytes;
1706
1707                 if (chip->ecc.postpad) {
1708                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1709                         oob += chip->ecc.postpad;
1710                 }
1711         }
1712
1713         size = mtd->oobsize - (oob - chip->oob_poi);
1714         if (size)
1715                 chip->write_buf(mtd, oob, size);
1716
1717         return 0;
1718 }
1719 /**
1720  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1721  * @mtd: mtd info structure
1722  * @chip: nand chip info structure
1723  * @buf: data buffer
1724  * @oob_required: must write chip->oob_poi to OOB
1725  */
1726 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1727                                   const uint8_t *buf, int oob_required)
1728 {
1729         int i, eccsize = chip->ecc.size;
1730         int eccbytes = chip->ecc.bytes;
1731         int eccsteps = chip->ecc.steps;
1732         uint8_t *ecc_calc = chip->buffers->ecccalc;
1733         const uint8_t *p = buf;
1734         uint32_t *eccpos = chip->ecc.layout->eccpos;
1735
1736         /* Software ECC calculation */
1737         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1738                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1739
1740         for (i = 0; i < chip->ecc.total; i++)
1741                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1742
1743         return chip->ecc.write_page_raw(mtd, chip, buf, 1);
1744 }
1745
1746 /**
1747  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1748  * @mtd: mtd info structure
1749  * @chip: nand chip info structure
1750  * @buf: data buffer
1751  * @oob_required: must write chip->oob_poi to OOB
1752  */
1753 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1754                                   const uint8_t *buf, int oob_required)
1755 {
1756         int i, eccsize = chip->ecc.size;
1757         int eccbytes = chip->ecc.bytes;
1758         int eccsteps = chip->ecc.steps;
1759         uint8_t *ecc_calc = chip->buffers->ecccalc;
1760         const uint8_t *p = buf;
1761         uint32_t *eccpos = chip->ecc.layout->eccpos;
1762
1763         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1764                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1765                 chip->write_buf(mtd, p, eccsize);
1766                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1767         }
1768
1769         for (i = 0; i < chip->ecc.total; i++)
1770                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1771
1772         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1773
1774         return 0;
1775 }
1776
1777 /**
1778  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
1779  * @mtd: mtd info structure
1780  * @chip: nand chip info structure
1781  * @buf: data buffer
1782  * @oob_required: must write chip->oob_poi to OOB
1783  *
1784  * The hw generator calculates the error syndrome automatically. Therefore we
1785  * need a special oob layout and handling.
1786  */
1787 static int nand_write_page_syndrome(struct mtd_info *mtd,
1788                                     struct nand_chip *chip,
1789                                     const uint8_t *buf, int oob_required)
1790 {
1791         int i, eccsize = chip->ecc.size;
1792         int eccbytes = chip->ecc.bytes;
1793         int eccsteps = chip->ecc.steps;
1794         const uint8_t *p = buf;
1795         uint8_t *oob = chip->oob_poi;
1796
1797         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1798
1799                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1800                 chip->write_buf(mtd, p, eccsize);
1801
1802                 if (chip->ecc.prepad) {
1803                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1804                         oob += chip->ecc.prepad;
1805                 }
1806
1807                 chip->ecc.calculate(mtd, p, oob);
1808                 chip->write_buf(mtd, oob, eccbytes);
1809                 oob += eccbytes;
1810
1811                 if (chip->ecc.postpad) {
1812                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1813                         oob += chip->ecc.postpad;
1814                 }
1815         }
1816
1817         /* Calculate remaining oob bytes */
1818         i = mtd->oobsize - (oob - chip->oob_poi);
1819         if (i)
1820                 chip->write_buf(mtd, oob, i);
1821
1822         return 0;
1823 }
1824
1825 /**
1826  * nand_write_page - [REPLACEABLE] write one page
1827  * @mtd: MTD device structure
1828  * @chip: NAND chip descriptor
1829  * @buf: the data to write
1830  * @oob_required: must write chip->oob_poi to OOB
1831  * @page: page number to write
1832  * @cached: cached programming
1833  * @raw: use _raw version of write_page
1834  */
1835 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1836                            const uint8_t *buf, int oob_required, int page,
1837                            int cached, int raw)
1838 {
1839         int status;
1840
1841         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1842
1843         if (unlikely(raw))
1844                 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
1845         else
1846                 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
1847
1848         if (status < 0)
1849                 return status;
1850
1851         /*
1852          * Cached progamming disabled for now. Not sure if it's worth the
1853          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
1854          */
1855         cached = 0;
1856
1857         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1858
1859                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1860                 status = chip->waitfunc(mtd, chip);
1861                 /*
1862                  * See if operation failed and additional status checks are
1863                  * available.
1864                  */
1865                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1866                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1867                                                page);
1868
1869                 if (status & NAND_STATUS_FAIL)
1870                         return -EIO;
1871         } else {
1872                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1873                 status = chip->waitfunc(mtd, chip);
1874         }
1875
1876 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1877         /* Send command to read back the data */
1878         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1879
1880         if (chip->verify_buf(mtd, buf, mtd->writesize))
1881                 return -EIO;
1882
1883         /* Make sure the next page prog is preceded by a status read */
1884         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1885 #endif
1886         return 0;
1887 }
1888
1889 /**
1890  * nand_fill_oob - [INTERN] Transfer client buffer to oob
1891  * @mtd: MTD device structure
1892  * @oob: oob data buffer
1893  * @len: oob data write length
1894  * @ops: oob ops structure
1895  */
1896 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
1897                               struct mtd_oob_ops *ops)
1898 {
1899         struct nand_chip *chip = mtd->priv;
1900
1901         /*
1902          * Initialise to all 0xFF, to avoid the possibility of left over OOB
1903          * data from a previous OOB read.
1904          */
1905         memset(chip->oob_poi, 0xff, mtd->oobsize);
1906
1907         switch (ops->mode) {
1908
1909         case MTD_OPS_PLACE_OOB:
1910         case MTD_OPS_RAW:
1911                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1912                 return oob + len;
1913
1914         case MTD_OPS_AUTO_OOB: {
1915                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1916                 uint32_t boffs = 0, woffs = ops->ooboffs;
1917                 size_t bytes = 0;
1918
1919                 for (; free->length && len; free++, len -= bytes) {
1920                         /* Write request not from offset 0? */
1921                         if (unlikely(woffs)) {
1922                                 if (woffs >= free->length) {
1923                                         woffs -= free->length;
1924                                         continue;
1925                                 }
1926                                 boffs = free->offset + woffs;
1927                                 bytes = min_t(size_t, len,
1928                                               (free->length - woffs));
1929                                 woffs = 0;
1930                         } else {
1931                                 bytes = min_t(size_t, len, free->length);
1932                                 boffs = free->offset;
1933                         }
1934                         memcpy(chip->oob_poi + boffs, oob, bytes);
1935                         oob += bytes;
1936                 }
1937                 return oob;
1938         }
1939         default:
1940                 BUG();
1941         }
1942         return NULL;
1943 }
1944
1945 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
1946
1947 /**
1948  * nand_do_write_ops - [INTERN] NAND write with ECC
1949  * @mtd: MTD device structure
1950  * @to: offset to write to
1951  * @ops: oob operations description structure
1952  *
1953  * NAND write with ECC.
1954  */
1955 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1956                              struct mtd_oob_ops *ops)
1957 {
1958         int chipnr, realpage, page, blockmask, column;
1959         struct nand_chip *chip = mtd->priv;
1960         uint32_t writelen = ops->len;
1961
1962         uint32_t oobwritelen = ops->ooblen;
1963         uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
1964                                 mtd->oobavail : mtd->oobsize;
1965
1966         uint8_t *oob = ops->oobbuf;
1967         uint8_t *buf = ops->datbuf;
1968         int ret, subpage;
1969         int oob_required = oob ? 1 : 0;
1970
1971         ops->retlen = 0;
1972         if (!writelen)
1973                 return 0;
1974
1975         column = to & (mtd->writesize - 1);
1976         subpage = column || (writelen & (mtd->writesize - 1));
1977
1978         if (subpage && oob)
1979                 return -EINVAL;
1980
1981         chipnr = (int)(to >> chip->chip_shift);
1982         chip->select_chip(mtd, chipnr);
1983
1984         /* Check, if it is write protected */
1985         if (nand_check_wp(mtd)) {
1986                 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1987                 return -EIO;
1988         }
1989
1990         realpage = (int)(to >> chip->page_shift);
1991         page = realpage & chip->pagemask;
1992         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1993
1994         /* Invalidate the page cache, when we write to the cached page */
1995         if (to <= (chip->pagebuf << chip->page_shift) &&
1996             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1997                 chip->pagebuf = -1;
1998
1999         /* Don't allow multipage oob writes with offset */
2000         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2001                 return -EINVAL;
2002
2003         while (1) {
2004                 WATCHDOG_RESET();
2005
2006                 int bytes = mtd->writesize;
2007                 int cached = writelen > bytes && page != blockmask;
2008                 uint8_t *wbuf = buf;
2009
2010                 /* Partial page write? */
2011                 if (unlikely(column || writelen < mtd->writesize)) {
2012                         cached = 0;
2013                         bytes = min_t(int, bytes - column, (int) writelen);
2014                         chip->pagebuf = -1;
2015                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2016                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2017                         wbuf = chip->buffers->databuf;
2018                 }
2019
2020                 if (unlikely(oob)) {
2021                         size_t len = min(oobwritelen, oobmaxlen);
2022                         oob = nand_fill_oob(mtd, oob, len, ops);
2023                         oobwritelen -= len;
2024                 } else {
2025                         /* We still need to erase leftover OOB data */
2026                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2027                 }
2028
2029                 ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
2030                                        cached, (ops->mode == MTD_OPS_RAW));
2031                 if (ret)
2032                         break;
2033
2034                 writelen -= bytes;
2035                 if (!writelen)
2036                         break;
2037
2038                 column = 0;
2039                 buf += bytes;
2040                 realpage++;
2041
2042                 page = realpage & chip->pagemask;
2043                 /* Check, if we cross a chip boundary */
2044                 if (!page) {
2045                         chipnr++;
2046                         chip->select_chip(mtd, -1);
2047                         chip->select_chip(mtd, chipnr);
2048                 }
2049         }
2050
2051         ops->retlen = ops->len - writelen;
2052         if (unlikely(oob))
2053                 ops->oobretlen = ops->ooblen;
2054         return ret;
2055 }
2056
2057 /**
2058  * nand_write - [MTD Interface] NAND write with ECC
2059  * @mtd: MTD device structure
2060  * @to: offset to write to
2061  * @len: number of bytes to write
2062  * @retlen: pointer to variable to store the number of written bytes
2063  * @buf: the data to write
2064  *
2065  * NAND write with ECC.
2066  */
2067 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2068                           size_t *retlen, const uint8_t *buf)
2069 {
2070         struct nand_chip *chip = mtd->priv;
2071         struct mtd_oob_ops ops;
2072         int ret;
2073
2074         nand_get_device(chip, mtd, FL_WRITING);
2075         ops.len = len;
2076         ops.datbuf = (uint8_t *)buf;
2077         ops.oobbuf = NULL;
2078         ops.mode = MTD_OPS_PLACE_OOB;
2079         ret = nand_do_write_ops(mtd, to, &ops);
2080         *retlen = ops.retlen;
2081         nand_release_device(mtd);
2082         return ret;
2083 }
2084
2085 /**
2086  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2087  * @mtd: MTD device structure
2088  * @to: offset to write to
2089  * @ops: oob operation description structure
2090  *
2091  * NAND write out-of-band.
2092  */
2093 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2094                              struct mtd_oob_ops *ops)
2095 {
2096         int chipnr, page, status, len;
2097         struct nand_chip *chip = mtd->priv;
2098
2099         MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2100                          __func__, (unsigned int)to, (int)ops->ooblen);
2101
2102         if (ops->mode == MTD_OPS_AUTO_OOB)
2103                 len = chip->ecc.layout->oobavail;
2104         else
2105                 len = mtd->oobsize;
2106
2107         /* Do not allow write past end of page */
2108         if ((ops->ooboffs + ops->ooblen) > len) {
2109                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2110                                 "past end of page\n", __func__);
2111                 return -EINVAL;
2112         }
2113
2114         if (unlikely(ops->ooboffs >= len)) {
2115                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2116                                 "write outside oob\n", __func__);
2117                 return -EINVAL;
2118         }
2119
2120         /* Do not allow write past end of device */
2121         if (unlikely(to >= mtd->size ||
2122                      ops->ooboffs + ops->ooblen >
2123                         ((mtd->size >> chip->page_shift) -
2124                          (to >> chip->page_shift)) * len)) {
2125                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2126                                 "end of device\n", __func__);
2127                 return -EINVAL;
2128         }
2129
2130         chipnr = (int)(to >> chip->chip_shift);
2131         chip->select_chip(mtd, chipnr);
2132
2133         /* Shift to get page */
2134         page = (int)(to >> chip->page_shift);
2135
2136         /*
2137          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2138          * of my DiskOnChip 2000 test units) will clear the whole data page too
2139          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2140          * it in the doc2000 driver in August 1999.  dwmw2.
2141          */
2142         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2143
2144         /* Check, if it is write protected */
2145         if (nand_check_wp(mtd))
2146                 return -EROFS;
2147
2148         /* Invalidate the page cache, if we write to the cached page */
2149         if (page == chip->pagebuf)
2150                 chip->pagebuf = -1;
2151
2152         nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2153
2154         if (ops->mode == MTD_OPS_RAW)
2155                 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2156         else
2157                 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2158
2159         if (status)
2160                 return status;
2161
2162         ops->oobretlen = ops->ooblen;
2163
2164         return 0;
2165 }
2166
2167 /**
2168  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2169  * @mtd: MTD device structure
2170  * @to: offset to write to
2171  * @ops: oob operation description structure
2172  */
2173 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2174                           struct mtd_oob_ops *ops)
2175 {
2176         struct nand_chip *chip = mtd->priv;
2177         int ret = -ENOTSUPP;
2178
2179         ops->retlen = 0;
2180
2181         /* Do not allow writes past end of device */
2182         if (ops->datbuf && (to + ops->len) > mtd->size) {
2183                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2184                                 "end of device\n", __func__);
2185                 return -EINVAL;
2186         }
2187
2188         nand_get_device(chip, mtd, FL_WRITING);
2189
2190         switch (ops->mode) {
2191         case MTD_OPS_PLACE_OOB:
2192         case MTD_OPS_AUTO_OOB:
2193         case MTD_OPS_RAW:
2194                 break;
2195
2196         default:
2197                 goto out;
2198         }
2199
2200         if (!ops->datbuf)
2201                 ret = nand_do_write_oob(mtd, to, ops);
2202         else
2203                 ret = nand_do_write_ops(mtd, to, ops);
2204
2205 out:
2206         nand_release_device(mtd);
2207         return ret;
2208 }
2209
2210 /**
2211  * single_erase_cmd - [GENERIC] NAND standard block erase command function
2212  * @mtd: MTD device structure
2213  * @page: the page address of the block which will be erased
2214  *
2215  * Standard erase command for NAND chips.
2216  */
2217 static void single_erase_cmd(struct mtd_info *mtd, int page)
2218 {
2219         struct nand_chip *chip = mtd->priv;
2220         /* Send commands to erase a block */
2221         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2222         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2223 }
2224
2225 /**
2226  * multi_erase_cmd - [GENERIC] AND specific block erase command function
2227  * @mtd: MTD device structure
2228  * @page: the page address of the block which will be erased
2229  *
2230  * AND multi block erase command function. Erase 4 consecutive blocks.
2231  */
2232 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2233 {
2234         struct nand_chip *chip = mtd->priv;
2235         /* Send commands to erase a block */
2236         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2237         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2238         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2239         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2240         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2241 }
2242
2243 /**
2244  * nand_erase - [MTD Interface] erase block(s)
2245  * @mtd: MTD device structure
2246  * @instr: erase instruction
2247  *
2248  * Erase one ore more blocks.
2249  */
2250 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2251 {
2252         return nand_erase_nand(mtd, instr, 0);
2253 }
2254
2255 #define BBT_PAGE_MASK   0xffffff3f
2256 /**
2257  * nand_erase_nand - [INTERN] erase block(s)
2258  * @mtd: MTD device structure
2259  * @instr: erase instruction
2260  * @allowbbt: allow erasing the bbt area
2261  *
2262  * Erase one ore more blocks.
2263  */
2264 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2265                     int allowbbt)
2266 {
2267         int page, status, pages_per_block, ret, chipnr;
2268         struct nand_chip *chip = mtd->priv;
2269         loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2270         unsigned int bbt_masked_page = 0xffffffff;
2271         loff_t len;
2272
2273         MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2274                                 __func__, (unsigned long long)instr->addr,
2275                                 (unsigned long long)instr->len);
2276
2277         if (check_offs_len(mtd, instr->addr, instr->len))
2278                 return -EINVAL;
2279
2280         /* Grab the lock and see if the device is available */
2281         nand_get_device(chip, mtd, FL_ERASING);
2282
2283         /* Shift to get first page */
2284         page = (int)(instr->addr >> chip->page_shift);
2285         chipnr = (int)(instr->addr >> chip->chip_shift);
2286
2287         /* Calculate pages in each block */
2288         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2289
2290         /* Select the NAND device */
2291         chip->select_chip(mtd, chipnr);
2292
2293         /* Check, if it is write protected */
2294         if (nand_check_wp(mtd)) {
2295                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2296                                         __func__);
2297                 instr->state = MTD_ERASE_FAILED;
2298                 goto erase_exit;
2299         }
2300
2301         /*
2302          * If BBT requires refresh, set the BBT page mask to see if the BBT
2303          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2304          * can not be matched. This is also done when the bbt is actually
2305          * erased to avoid recursive updates.
2306          */
2307         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2308                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2309
2310         /* Loop through the pages */
2311         len = instr->len;
2312
2313         instr->state = MTD_ERASING;
2314
2315         while (len) {
2316                 WATCHDOG_RESET();
2317                 /* Check if we have a bad block, we do not erase bad blocks! */
2318                 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2319                                         chip->page_shift, 0, allowbbt)) {
2320                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2321                                    __func__, page);
2322                         instr->state = MTD_ERASE_FAILED;
2323                         goto erase_exit;
2324                 }
2325
2326                 /*
2327                  * Invalidate the page cache, if we erase the block which
2328                  * contains the current cached page.
2329                  */
2330                 if (page <= chip->pagebuf && chip->pagebuf <
2331                     (page + pages_per_block))
2332                         chip->pagebuf = -1;
2333
2334                 chip->erase_cmd(mtd, page & chip->pagemask);
2335
2336                 status = chip->waitfunc(mtd, chip);
2337
2338                 /*
2339                  * See if operation failed and additional status checks are
2340                  * available
2341                  */
2342                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2343                         status = chip->errstat(mtd, chip, FL_ERASING,
2344                                                status, page);
2345
2346                 /* See if block erase succeeded */
2347                 if (status & NAND_STATUS_FAIL) {
2348                         MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2349                                         "page 0x%08x\n", __func__, page);
2350                         instr->state = MTD_ERASE_FAILED;
2351                         instr->fail_addr =
2352                                 ((loff_t)page << chip->page_shift);
2353                         goto erase_exit;
2354                 }
2355
2356                 /*
2357                  * If BBT requires refresh, set the BBT rewrite flag to the
2358                  * page being erased.
2359                  */
2360                 if (bbt_masked_page != 0xffffffff &&
2361                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2362                         rewrite_bbt[chipnr] =
2363                                 ((loff_t)page << chip->page_shift);
2364
2365                 /* Increment page address and decrement length */
2366                 len -= (1 << chip->phys_erase_shift);
2367                 page += pages_per_block;
2368
2369                 /* Check, if we cross a chip boundary */
2370                 if (len && !(page & chip->pagemask)) {
2371                         chipnr++;
2372                         chip->select_chip(mtd, -1);
2373                         chip->select_chip(mtd, chipnr);
2374
2375                         /*
2376                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2377                          * page mask to see if this BBT should be rewritten.
2378                          */
2379                         if (bbt_masked_page != 0xffffffff &&
2380                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2381                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2382                                         BBT_PAGE_MASK;
2383                 }
2384         }
2385         instr->state = MTD_ERASE_DONE;
2386
2387 erase_exit:
2388
2389         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2390
2391         /* Deselect and wake up anyone waiting on the device */
2392         nand_release_device(mtd);
2393
2394         /* Do call back function */
2395         if (!ret)
2396                 mtd_erase_callback(instr);
2397
2398         /*
2399          * If BBT requires refresh and erase was successful, rewrite any
2400          * selected bad block tables.
2401          */
2402         if (bbt_masked_page == 0xffffffff || ret)
2403                 return ret;
2404
2405         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2406                 if (!rewrite_bbt[chipnr])
2407                         continue;
2408                 /* Update the BBT for chip */
2409                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2410                         "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2411                         rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2412                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2413         }
2414
2415         /* Return more or less happy */
2416         return ret;
2417 }
2418
2419 /**
2420  * nand_sync - [MTD Interface] sync
2421  * @mtd: MTD device structure
2422  *
2423  * Sync is actually a wait for chip ready function.
2424  */
2425 static void nand_sync(struct mtd_info *mtd)
2426 {
2427         struct nand_chip *chip = mtd->priv;
2428
2429         MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2430
2431         /* Grab the lock and see if the device is available */
2432         nand_get_device(chip, mtd, FL_SYNCING);
2433         /* Release it and go back */
2434         nand_release_device(mtd);
2435 }
2436
2437 /**
2438  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2439  * @mtd: MTD device structure
2440  * @offs: offset relative to mtd start
2441  */
2442 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2443 {
2444         return nand_block_checkbad(mtd, offs, 1, 0);
2445 }
2446
2447 /**
2448  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2449  * @mtd: MTD device structure
2450  * @ofs: offset relative to mtd start
2451  */
2452 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2453 {
2454         struct nand_chip *chip = mtd->priv;
2455         int ret;
2456
2457         ret = nand_block_isbad(mtd, ofs);
2458         if (ret) {
2459                 /* If it was bad already, return success and do nothing */
2460                 if (ret > 0)
2461                         return 0;
2462                 return ret;
2463         }
2464
2465         return chip->block_markbad(mtd, ofs);
2466 }
2467
2468  /**
2469  * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2470  * @mtd: MTD device structure
2471  * @chip: nand chip info structure
2472  * @addr: feature address.
2473  * @subfeature_param: the subfeature parameters, a four bytes array.
2474  */
2475 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2476                         int addr, uint8_t *subfeature_param)
2477 {
2478         int status;
2479
2480         if (!chip->onfi_version)
2481                 return -EINVAL;
2482
2483         chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2484         chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2485         status = chip->waitfunc(mtd, chip);
2486         if (status & NAND_STATUS_FAIL)
2487                 return -EIO;
2488         return 0;
2489 }
2490
2491 /**
2492  * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2493  * @mtd: MTD device structure
2494  * @chip: nand chip info structure
2495  * @addr: feature address.
2496  * @subfeature_param: the subfeature parameters, a four bytes array.
2497  */
2498 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2499                         int addr, uint8_t *subfeature_param)
2500 {
2501         if (!chip->onfi_version)
2502                 return -EINVAL;
2503
2504         /* clear the sub feature parameters */
2505         memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2506
2507         chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2508         chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2509         return 0;
2510 }
2511
2512 /* Set default functions */
2513 static void nand_set_defaults(struct nand_chip *chip, int busw)
2514 {
2515         /* check for proper chip_delay setup, set 20us if not */
2516         if (!chip->chip_delay)
2517                 chip->chip_delay = 20;
2518
2519         /* check, if a user supplied command function given */
2520         if (chip->cmdfunc == NULL)
2521                 chip->cmdfunc = nand_command;
2522
2523         /* check, if a user supplied wait function given */
2524         if (chip->waitfunc == NULL)
2525                 chip->waitfunc = nand_wait;
2526
2527         if (!chip->select_chip)
2528                 chip->select_chip = nand_select_chip;
2529         if (!chip->read_byte)
2530                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2531         if (!chip->read_word)
2532                 chip->read_word = nand_read_word;
2533         if (!chip->block_bad)
2534                 chip->block_bad = nand_block_bad;
2535         if (!chip->block_markbad)
2536                 chip->block_markbad = nand_default_block_markbad;
2537         if (!chip->write_buf)
2538                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2539         if (!chip->read_buf)
2540                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2541         if (!chip->verify_buf)
2542                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2543         if (!chip->scan_bbt)
2544                 chip->scan_bbt = nand_default_bbt;
2545         if (!chip->controller)
2546                 chip->controller = &chip->hwcontrol;
2547 }
2548
2549 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2550 /* Sanitize ONFI strings so we can safely print them */
2551 static void sanitize_string(char *s, size_t len)
2552 {
2553         ssize_t i;
2554
2555         /* Null terminate */
2556         s[len - 1] = 0;
2557
2558         /* Remove non printable chars */
2559         for (i = 0; i < len - 1; i++) {
2560                 if (s[i] < ' ' || s[i] > 127)
2561                         s[i] = '?';
2562         }
2563
2564         /* Remove trailing spaces */
2565         strim(s);
2566 }
2567
2568 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2569 {
2570         int i;
2571         while (len--) {
2572                 crc ^= *p++ << 8;
2573                 for (i = 0; i < 8; i++)
2574                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2575         }
2576
2577         return crc;
2578 }
2579
2580 /*
2581  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2582  */
2583 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2584                                         int *busw)
2585 {
2586         struct nand_onfi_params *p = &chip->onfi_params;
2587         int i, j;
2588         int val;
2589
2590         /* Try ONFI for unknown chip or LP */
2591         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2592         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2593                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2594                 return 0;
2595
2596         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2597         for (i = 0; i < 3; i++) {
2598                 for (j = 0; j < sizeof(*p); j++)
2599                         ((uint8_t *)p)[j] = chip->read_byte(mtd);
2600                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2601                                 le16_to_cpu(p->crc)) {
2602                         pr_info("ONFI param page %d valid\n", i);
2603                         break;
2604                 }
2605         }
2606
2607         if (i == 3)
2608                 return 0;
2609
2610         /* Check version */
2611         val = le16_to_cpu(p->revision);
2612         if (val & (1 << 5))
2613                 chip->onfi_version = 23;
2614         else if (val & (1 << 4))
2615                 chip->onfi_version = 22;
2616         else if (val & (1 << 3))
2617                 chip->onfi_version = 21;
2618         else if (val & (1 << 2))
2619                 chip->onfi_version = 20;
2620         else if (val & (1 << 1))
2621                 chip->onfi_version = 10;
2622         else
2623                 chip->onfi_version = 0;
2624
2625         if (!chip->onfi_version) {
2626                 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2627                 return 0;
2628         }
2629
2630         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2631         sanitize_string(p->model, sizeof(p->model));
2632         if (!mtd->name)
2633                 mtd->name = p->model;
2634         mtd->writesize = le32_to_cpu(p->byte_per_page);
2635         mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2636         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2637         chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2638         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2639         *busw = 0;
2640         if (le16_to_cpu(p->features) & 1)
2641                 *busw = NAND_BUSWIDTH_16;
2642
2643         pr_info("ONFI flash detected\n");
2644         return 1;
2645 }
2646 #else
2647 static inline int nand_flash_detect_onfi(struct mtd_info *mtd,
2648                                         struct nand_chip *chip,
2649                                         int *busw)
2650 {
2651         return 0;
2652 }
2653 #endif
2654
2655 /*
2656  * nand_id_has_period - Check if an ID string has a given wraparound period
2657  * @id_data: the ID string
2658  * @arrlen: the length of the @id_data array
2659  * @period: the period of repitition
2660  *
2661  * Check if an ID string is repeated within a given sequence of bytes at
2662  * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
2663  * period of 2). This is a helper function for nand_id_len(). Returns non-zero
2664  * if the repetition has a period of @period; otherwise, returns zero.
2665  */
2666 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
2667 {
2668         int i, j;
2669         for (i = 0; i < period; i++)
2670                 for (j = i + period; j < arrlen; j += period)
2671                         if (id_data[i] != id_data[j])
2672                                 return 0;
2673         return 1;
2674 }
2675
2676 /*
2677  * nand_id_len - Get the length of an ID string returned by CMD_READID
2678  * @id_data: the ID string
2679  * @arrlen: the length of the @id_data array
2680
2681  * Returns the length of the ID string, according to known wraparound/trailing
2682  * zero patterns. If no pattern exists, returns the length of the array.
2683  */
2684 static int nand_id_len(u8 *id_data, int arrlen)
2685 {
2686         int last_nonzero, period;
2687
2688         /* Find last non-zero byte */
2689         for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
2690                 if (id_data[last_nonzero])
2691                         break;
2692
2693         /* All zeros */
2694         if (last_nonzero < 0)
2695                 return 0;
2696
2697         /* Calculate wraparound period */
2698         for (period = 1; period < arrlen; period++)
2699                 if (nand_id_has_period(id_data, arrlen, period))
2700                         break;
2701
2702         /* There's a repeated pattern */
2703         if (period < arrlen)
2704                 return period;
2705
2706         /* There are trailing zeros */
2707         if (last_nonzero < arrlen - 1)
2708                 return last_nonzero + 1;
2709
2710         /* No pattern detected */
2711         return arrlen;
2712 }
2713
2714 /*
2715  * Many new NAND share similar device ID codes, which represent the size of the
2716  * chip. The rest of the parameters must be decoded according to generic or
2717  * manufacturer-specific "extended ID" decoding patterns.
2718  */
2719 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
2720                                 u8 id_data[8], int *busw)
2721 {
2722         int extid, id_len;
2723         /* The 3rd id byte holds MLC / multichip data */
2724         chip->cellinfo = id_data[2];
2725         /* The 4th id byte is the important one */
2726         extid = id_data[3];
2727
2728         id_len = nand_id_len(id_data, 8);
2729
2730         /*
2731          * Field definitions are in the following datasheets:
2732          * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2733          * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
2734          * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
2735          *
2736          * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
2737          * ID to decide what to do.
2738          */
2739         if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
2740                         (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2741                         id_data[5] != 0x00) {
2742                 /* Calc pagesize */
2743                 mtd->writesize = 2048 << (extid & 0x03);
2744                 extid >>= 2;
2745                 /* Calc oobsize */
2746                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
2747                 case 1:
2748                         mtd->oobsize = 128;
2749                         break;
2750                 case 2:
2751                         mtd->oobsize = 218;
2752                         break;
2753                 case 3:
2754                         mtd->oobsize = 400;
2755                         break;
2756                 case 4:
2757                         mtd->oobsize = 436;
2758                         break;
2759                 case 5:
2760                         mtd->oobsize = 512;
2761                         break;
2762                 case 6:
2763                 default: /* Other cases are "reserved" (unknown) */
2764                         mtd->oobsize = 640;
2765                         break;
2766                 }
2767                 extid >>= 2;
2768                 /* Calc blocksize */
2769                 mtd->erasesize = (128 * 1024) <<
2770                         (((extid >> 1) & 0x04) | (extid & 0x03));
2771                 *busw = 0;
2772         } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
2773                         (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2774                 unsigned int tmp;
2775
2776                 /* Calc pagesize */
2777                 mtd->writesize = 2048 << (extid & 0x03);
2778                 extid >>= 2;
2779                 /* Calc oobsize */
2780                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
2781                 case 0:
2782                         mtd->oobsize = 128;
2783                         break;
2784                 case 1:
2785                         mtd->oobsize = 224;
2786                         break;
2787                 case 2:
2788                         mtd->oobsize = 448;
2789                         break;
2790                 case 3:
2791                         mtd->oobsize = 64;
2792                         break;
2793                 case 4:
2794                         mtd->oobsize = 32;
2795                         break;
2796                 case 5:
2797                         mtd->oobsize = 16;
2798                         break;
2799                 default:
2800                         mtd->oobsize = 640;
2801                         break;
2802                 }
2803                 extid >>= 2;
2804                 /* Calc blocksize */
2805                 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
2806                 if (tmp < 0x03)
2807                         mtd->erasesize = (128 * 1024) << tmp;
2808                 else if (tmp == 0x03)
2809                         mtd->erasesize = 768 * 1024;
2810                 else
2811                         mtd->erasesize = (64 * 1024) << tmp;
2812                 *busw = 0;
2813         } else {
2814                 /* Calc pagesize */
2815                 mtd->writesize = 1024 << (extid & 0x03);
2816                 extid >>= 2;
2817                 /* Calc oobsize */
2818                 mtd->oobsize = (8 << (extid & 0x01)) *
2819                         (mtd->writesize >> 9);
2820                 extid >>= 2;
2821                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2822                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2823                 extid >>= 2;
2824                 /* Get buswidth information */
2825                 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2826         }
2827 }
2828
2829  /*
2830  * Old devices have chip data hardcoded in the device ID table. nand_decode_id
2831  * decodes a matching ID table entry and assigns the MTD size parameters for
2832  * the chip.
2833  */
2834 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
2835                                 const struct nand_flash_dev *type, u8 id_data[8],
2836                                 int *busw)
2837 {
2838         int maf_id = id_data[0];
2839
2840         mtd->erasesize = type->erasesize;
2841         mtd->writesize = type->pagesize;
2842         mtd->oobsize = mtd->writesize / 32;
2843         *busw = type->options & NAND_BUSWIDTH_16;
2844
2845         /*
2846          * Check for Spansion/AMD ID + repeating 5th, 6th byte since
2847          * some Spansion chips have erasesize that conflicts with size
2848          * listed in nand_ids table.
2849          * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
2850          */
2851         if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
2852                         && id_data[6] == 0x00 && id_data[7] == 0x00
2853                         && mtd->writesize == 512) {
2854                 mtd->erasesize = 128 * 1024;
2855                 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
2856         }
2857 }
2858
2859  /*
2860  * Set the bad block marker/indicator (BBM/BBI) patterns according to some
2861  * heuristic patterns using various detected parameters (e.g., manufacturer,
2862  * page size, cell-type information).
2863  */
2864 static void nand_decode_bbm_options(struct mtd_info *mtd,
2865                                     struct nand_chip *chip, u8 id_data[8])
2866 {
2867         int maf_id = id_data[0];
2868
2869         /* Set the bad block position */
2870         if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
2871                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
2872         else
2873                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
2874
2875         /*
2876          * Bad block marker is stored in the last page of each block on Samsung
2877          * and Hynix MLC devices; stored in first two pages of each block on
2878          * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
2879          * AMD/Spansion, and Macronix.  All others scan only the first page.
2880          */
2881         if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2882                         (maf_id == NAND_MFR_SAMSUNG ||
2883                          maf_id == NAND_MFR_HYNIX))
2884                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
2885         else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2886                                 (maf_id == NAND_MFR_SAMSUNG ||
2887                                  maf_id == NAND_MFR_HYNIX ||
2888                                  maf_id == NAND_MFR_TOSHIBA ||
2889                                  maf_id == NAND_MFR_AMD ||
2890                                  maf_id == NAND_MFR_MACRONIX)) ||
2891                         (mtd->writesize == 2048 &&
2892                          maf_id == NAND_MFR_MICRON))
2893                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
2894 }
2895
2896 /*
2897  * Get the flash and manufacturer id and lookup if the type is supported.
2898  */
2899 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2900                                                   struct nand_chip *chip,
2901                                                   int busw,
2902                                                   int *maf_id, int *dev_id,
2903                                                   const struct nand_flash_dev *type)
2904 {
2905         const char *name;
2906         int i, maf_idx;
2907         u8 id_data[8];
2908
2909         /* Select the device */
2910         chip->select_chip(mtd, 0);
2911
2912         /*
2913          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2914          * after power-up.
2915          */
2916         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2917
2918         /* Send the command for reading device ID */
2919         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2920
2921         /* Read manufacturer and device IDs */
2922         *maf_id = chip->read_byte(mtd);
2923         *dev_id = chip->read_byte(mtd);
2924
2925         /*
2926          * Try again to make sure, as some systems the bus-hold or other
2927          * interface concerns can cause random data which looks like a
2928          * possibly credible NAND flash to appear. If the two results do
2929          * not match, ignore the device completely.
2930          */
2931
2932         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2933
2934         /* Read entire ID string */
2935         for (i = 0; i < 8; i++)
2936                 id_data[i] = chip->read_byte(mtd);
2937
2938         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2939                 pr_info("%s: second ID read did not match "
2940                         "%02x,%02x against %02x,%02x\n", __func__,
2941                         *maf_id, *dev_id, id_data[0], id_data[1]);
2942                 return ERR_PTR(-ENODEV);
2943         }
2944
2945         if (!type)
2946                 type = nand_flash_ids;
2947
2948         for (; type->name != NULL; type++)
2949                 if (*dev_id == type->id)
2950                         break;
2951
2952         chip->onfi_version = 0;
2953         if (!type->name || !type->pagesize) {
2954                 /* Check is chip is ONFI compliant */
2955                 if (nand_flash_detect_onfi(mtd, chip, &busw))
2956                         goto ident_done;
2957         }
2958
2959         if (!type->name)
2960                 return ERR_PTR(-ENODEV);
2961
2962         if (!mtd->name)
2963                 mtd->name = type->name;
2964
2965         chip->chipsize = (uint64_t)type->chipsize << 20;
2966
2967         if (!type->pagesize && chip->init_size) {
2968                 /* Set the pagesize, oobsize, erasesize by the driver */
2969                 busw = chip->init_size(mtd, chip, id_data);
2970         } else if (!type->pagesize) {
2971                 /* Decode parameters from extended ID */
2972                 nand_decode_ext_id(mtd, chip, id_data, &busw);
2973         } else {
2974                 nand_decode_id(mtd, chip, type, id_data, &busw);
2975         }
2976         /* Get chip options, preserve non chip based options */
2977         chip->options |= type->options;
2978
2979         /*
2980          * Check if chip is not a Samsung device. Do not clear the
2981          * options for chips which do not have an extended id.
2982          */
2983         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2984                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2985 ident_done:
2986
2987         /* Try to identify manufacturer */
2988         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2989                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2990                         break;
2991         }
2992
2993         /*
2994          * Check, if buswidth is correct. Hardware drivers should set
2995          * chip correct!
2996          */
2997         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2998                 pr_info("NAND device: Manufacturer ID:"
2999                         " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3000                         *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3001                 pr_warn("NAND bus width %d instead %d bit\n",
3002                            (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3003                            busw ? 16 : 8);
3004                 return ERR_PTR(-EINVAL);
3005         }
3006
3007         nand_decode_bbm_options(mtd, chip, id_data);
3008
3009         /* Calculate the address shift from the page size */
3010         chip->page_shift = ffs(mtd->writesize) - 1;
3011         /* Convert chipsize to number of pages per chip -1 */
3012         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3013
3014         chip->bbt_erase_shift = chip->phys_erase_shift =
3015                 ffs(mtd->erasesize) - 1;
3016         if (chip->chipsize & 0xffffffff)
3017                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3018         else {
3019                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3020                 chip->chip_shift += 32 - 1;
3021         }
3022
3023         chip->badblockbits = 8;
3024
3025         /* Check for AND chips with 4 page planes */
3026         if (chip->options & NAND_4PAGE_ARRAY)
3027                 chip->erase_cmd = multi_erase_cmd;
3028         else
3029                 chip->erase_cmd = single_erase_cmd;
3030
3031         /* Do not replace user supplied command function! */
3032         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3033                 chip->cmdfunc = nand_command_lp;
3034
3035         name = type->name;
3036 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3037         if (chip->onfi_version)
3038                 name = chip->onfi_params.model;
3039 #endif
3040         pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3041                 " page size: %d, OOB size: %d\n",
3042                 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3043                 name,
3044                 mtd->writesize, mtd->oobsize);
3045
3046         return type;
3047 }
3048
3049 /**
3050  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3051  * @mtd: MTD device structure
3052  * @maxchips: number of chips to scan for
3053  * @table: alternative NAND ID table
3054  *
3055  * This is the first phase of the normal nand_scan() function. It reads the
3056  * flash ID and sets up MTD fields accordingly.
3057  *
3058  * The mtd->owner field must be set to the module of the caller.
3059  */
3060 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3061                     const struct nand_flash_dev *table)
3062 {
3063         int i, busw, nand_maf_id, nand_dev_id;
3064         struct nand_chip *chip = mtd->priv;
3065         const struct nand_flash_dev *type;
3066
3067         /* Get buswidth to select the correct functions */
3068         busw = chip->options & NAND_BUSWIDTH_16;
3069         /* Set the default functions */
3070         nand_set_defaults(chip, busw);
3071
3072         /* Read the flash type */
3073         type = nand_get_flash_type(mtd, chip, busw,
3074                                 &nand_maf_id, &nand_dev_id, table);
3075
3076         if (IS_ERR(type)) {
3077 #ifndef CONFIG_SYS_NAND_QUIET_TEST
3078                 pr_warn("No NAND device found\n");
3079 #endif
3080                 chip->select_chip(mtd, -1);
3081                 return PTR_ERR(type);
3082         }
3083
3084         /* Check for a chip array */
3085         for (i = 1; i < maxchips; i++) {
3086                 chip->select_chip(mtd, i);
3087                 /* See comment in nand_get_flash_type for reset */
3088                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3089                 /* Send the command for reading device ID */
3090                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3091                 /* Read manufacturer and device IDs */
3092                 if (nand_maf_id != chip->read_byte(mtd) ||
3093                     nand_dev_id != chip->read_byte(mtd))
3094                         break;
3095         }
3096 #ifdef DEBUG
3097         if (i > 1)
3098                 pr_info("%d NAND chips detected\n", i);
3099 #endif
3100
3101         /* Store the number of chips and calc total size for mtd */
3102         chip->numchips = i;
3103         mtd->size = i * chip->chipsize;
3104
3105         return 0;
3106 }
3107
3108
3109 /**
3110  * nand_scan_tail - [NAND Interface] Scan for the NAND device
3111  * @mtd: MTD device structure
3112  *
3113  * This is the second phase of the normal nand_scan() function. It fills out
3114  * all the uninitialized function pointers with the defaults and scans for a
3115  * bad block table if appropriate.
3116  */
3117 int nand_scan_tail(struct mtd_info *mtd)
3118 {
3119         int i;
3120         struct nand_chip *chip = mtd->priv;
3121
3122         /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3123         BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3124                         !(chip->bbt_options & NAND_BBT_USE_FLASH));
3125
3126         if (!(chip->options & NAND_OWN_BUFFERS))
3127                 chip->buffers = memalign(ARCH_DMA_MINALIGN,
3128                                          sizeof(*chip->buffers));
3129         if (!chip->buffers)
3130                 return -ENOMEM;
3131
3132         /* Set the internal oob buffer location, just after the page data */
3133         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3134
3135         /*
3136          * If no default placement scheme is given, select an appropriate one.
3137          */
3138         if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3139                 switch (mtd->oobsize) {
3140                 case 8:
3141                         chip->ecc.layout = &nand_oob_8;
3142                         break;
3143                 case 16:
3144                         chip->ecc.layout = &nand_oob_16;
3145                         break;
3146                 case 64:
3147                         chip->ecc.layout = &nand_oob_64;
3148                         break;
3149                 case 128:
3150                         chip->ecc.layout = &nand_oob_128;
3151                         break;
3152                 default:
3153                         pr_warn("No oob scheme defined for oobsize %d\n",
3154                                    mtd->oobsize);
3155                 }
3156         }
3157
3158         if (!chip->write_page)
3159                 chip->write_page = nand_write_page;
3160
3161         /* set for ONFI nand */
3162         if (!chip->onfi_set_features)
3163                 chip->onfi_set_features = nand_onfi_set_features;
3164         if (!chip->onfi_get_features)
3165                 chip->onfi_get_features = nand_onfi_get_features;
3166
3167         /*
3168          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3169          * selected and we have 256 byte pagesize fallback to software ECC
3170          */
3171
3172         switch (chip->ecc.mode) {
3173         case NAND_ECC_HW_OOB_FIRST:
3174                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3175                 if (!chip->ecc.calculate || !chip->ecc.correct ||
3176                      !chip->ecc.hwctl) {
3177                         pr_warn("No ECC functions supplied; "
3178                                    "hardware ECC not possible\n");
3179                         BUG();
3180                 }
3181                 if (!chip->ecc.read_page)
3182                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3183
3184         case NAND_ECC_HW:
3185                 /* Use standard hwecc read page function? */
3186                 if (!chip->ecc.read_page)
3187                         chip->ecc.read_page = nand_read_page_hwecc;
3188                 if (!chip->ecc.write_page)
3189                         chip->ecc.write_page = nand_write_page_hwecc;
3190                 if (!chip->ecc.read_page_raw)
3191                         chip->ecc.read_page_raw = nand_read_page_raw;
3192                 if (!chip->ecc.write_page_raw)
3193                         chip->ecc.write_page_raw = nand_write_page_raw;
3194                 if (!chip->ecc.read_oob)
3195                         chip->ecc.read_oob = nand_read_oob_std;
3196                 if (!chip->ecc.write_oob)
3197                         chip->ecc.write_oob = nand_write_oob_std;
3198
3199         case NAND_ECC_HW_SYNDROME:
3200                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3201                      !chip->ecc.hwctl) &&
3202                     (!chip->ecc.read_page ||
3203                      chip->ecc.read_page == nand_read_page_hwecc ||
3204                      !chip->ecc.write_page ||
3205                      chip->ecc.write_page == nand_write_page_hwecc)) {
3206                         pr_warn("No ECC functions supplied; "
3207                                    "hardware ECC not possible\n");
3208                         BUG();
3209                 }
3210                 /* Use standard syndrome read/write page function? */
3211                 if (!chip->ecc.read_page)
3212                         chip->ecc.read_page = nand_read_page_syndrome;
3213                 if (!chip->ecc.write_page)
3214                         chip->ecc.write_page = nand_write_page_syndrome;
3215                 if (!chip->ecc.read_page_raw)
3216                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3217                 if (!chip->ecc.write_page_raw)
3218                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3219                 if (!chip->ecc.read_oob)
3220                         chip->ecc.read_oob = nand_read_oob_syndrome;
3221                 if (!chip->ecc.write_oob)
3222                         chip->ecc.write_oob = nand_write_oob_syndrome;
3223
3224                 if (mtd->writesize >= chip->ecc.size) {
3225                         if (!chip->ecc.strength) {
3226                                 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3227                                 BUG();
3228                         }
3229                         break;
3230                 }
3231                 pr_warn("%d byte HW ECC not possible on "
3232                            "%d byte page size, fallback to SW ECC\n",
3233                            chip->ecc.size, mtd->writesize);
3234                 chip->ecc.mode = NAND_ECC_SOFT;
3235
3236         case NAND_ECC_SOFT:
3237                 chip->ecc.calculate = nand_calculate_ecc;
3238                 chip->ecc.correct = nand_correct_data;
3239                 chip->ecc.read_page = nand_read_page_swecc;
3240                 chip->ecc.read_subpage = nand_read_subpage;
3241                 chip->ecc.write_page = nand_write_page_swecc;
3242                 chip->ecc.read_page_raw = nand_read_page_raw;
3243                 chip->ecc.write_page_raw = nand_write_page_raw;
3244                 chip->ecc.read_oob = nand_read_oob_std;
3245                 chip->ecc.write_oob = nand_write_oob_std;
3246                 if (!chip->ecc.size)
3247                         chip->ecc.size = 256;
3248                 chip->ecc.bytes = 3;
3249                 chip->ecc.strength = 1;
3250                 break;
3251
3252         case NAND_ECC_SOFT_BCH:
3253                 if (!mtd_nand_has_bch()) {
3254                         pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3255                         return -EINVAL;
3256                 }
3257                 chip->ecc.calculate = nand_bch_calculate_ecc;
3258                 chip->ecc.correct = nand_bch_correct_data;
3259                 chip->ecc.read_page = nand_read_page_swecc;
3260                 chip->ecc.read_subpage = nand_read_subpage;
3261                 chip->ecc.write_page = nand_write_page_swecc;
3262                 chip->ecc.read_page_raw = nand_read_page_raw;
3263                 chip->ecc.write_page_raw = nand_write_page_raw;
3264                 chip->ecc.read_oob = nand_read_oob_std;
3265                 chip->ecc.write_oob = nand_write_oob_std;
3266                 /*
3267                  * Board driver should supply ecc.size and ecc.bytes values to
3268                  * select how many bits are correctable; see nand_bch_init()
3269                  * for details. Otherwise, default to 4 bits for large page
3270                  * devices.
3271                  */
3272                 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3273                         chip->ecc.size = 512;
3274                         chip->ecc.bytes = 7;
3275                 }
3276                 chip->ecc.priv = nand_bch_init(mtd,
3277                                                chip->ecc.size,
3278                                                chip->ecc.bytes,
3279                                                &chip->ecc.layout);
3280                 if (!chip->ecc.priv)
3281                         pr_warn("BCH ECC initialization failed!\n");
3282                 chip->ecc.strength =
3283                         chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
3284                 break;
3285
3286         case NAND_ECC_NONE:
3287                 pr_warn("NAND_ECC_NONE selected by board driver. "
3288                         "This is not recommended !!\n");
3289                 chip->ecc.read_page = nand_read_page_raw;
3290                 chip->ecc.write_page = nand_write_page_raw;
3291                 chip->ecc.read_oob = nand_read_oob_std;
3292                 chip->ecc.read_page_raw = nand_read_page_raw;
3293                 chip->ecc.write_page_raw = nand_write_page_raw;
3294                 chip->ecc.write_oob = nand_write_oob_std;
3295                 chip->ecc.size = mtd->writesize;
3296                 chip->ecc.bytes = 0;
3297                 break;
3298
3299         default:
3300                 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3301                 BUG();
3302         }
3303
3304         /* For many systems, the standard OOB write also works for raw */
3305         if (!chip->ecc.read_oob_raw)
3306                 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3307         if (!chip->ecc.write_oob_raw)
3308                 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3309
3310         /*
3311          * The number of bytes available for a client to place data into
3312          * the out of band area.
3313          */
3314         chip->ecc.layout->oobavail = 0;
3315         for (i = 0; chip->ecc.layout->oobfree[i].length
3316                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3317                 chip->ecc.layout->oobavail +=
3318                         chip->ecc.layout->oobfree[i].length;
3319         mtd->oobavail = chip->ecc.layout->oobavail;
3320
3321         /*
3322          * Set the number of read / write steps for one page depending on ECC
3323          * mode.
3324          */
3325         chip->ecc.steps = mtd->writesize / chip->ecc.size;
3326         if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3327                 pr_warn("Invalid ECC parameters\n");
3328                 BUG();
3329         }
3330         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3331
3332         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3333         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3334             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3335                 switch (chip->ecc.steps) {
3336                 case 2:
3337                         mtd->subpage_sft = 1;
3338                         break;
3339                 case 4:
3340                 case 8:
3341                 case 16:
3342                         mtd->subpage_sft = 2;
3343                         break;
3344                 }
3345         }
3346         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3347
3348         /* Initialize state */
3349         chip->state = FL_READY;
3350
3351         /* De-select the device */
3352         chip->select_chip(mtd, -1);
3353
3354         /* Invalidate the pagebuffer reference */
3355         chip->pagebuf = -1;
3356
3357         /* Large page NAND with SOFT_ECC should support subpage reads */
3358         if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3359                 chip->options |= NAND_SUBPAGE_READ;
3360
3361         /* Fill in remaining MTD driver data */
3362         mtd->type = MTD_NANDFLASH;
3363         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3364                                                 MTD_CAP_NANDFLASH;
3365         mtd->_erase = nand_erase;
3366         mtd->_point = NULL;
3367         mtd->_unpoint = NULL;
3368         mtd->_read = nand_read;
3369         mtd->_write = nand_write;
3370         mtd->_read_oob = nand_read_oob;
3371         mtd->_write_oob = nand_write_oob;
3372         mtd->_sync = nand_sync;
3373         mtd->_lock = NULL;
3374         mtd->_unlock = NULL;
3375         mtd->_block_isbad = nand_block_isbad;
3376         mtd->_block_markbad = nand_block_markbad;
3377
3378         /* propagate ecc info to mtd_info */
3379         mtd->ecclayout = chip->ecc.layout;
3380         mtd->ecc_strength = chip->ecc.strength;
3381         /*
3382          * Initialize bitflip_threshold to its default prior scan_bbt() call.
3383          * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3384          * properly set.
3385          */
3386         if (!mtd->bitflip_threshold)
3387                 mtd->bitflip_threshold = mtd->ecc_strength;
3388
3389         /* Check, if we should skip the bad block table scan */
3390         if (chip->options & NAND_SKIP_BBTSCAN)
3391                 chip->options |= NAND_BBT_SCANNED;
3392
3393         return 0;
3394 }
3395
3396 /**
3397  * nand_scan - [NAND Interface] Scan for the NAND device
3398  * @mtd: MTD device structure
3399  * @maxchips: number of chips to scan for
3400  *
3401  * This fills out all the uninitialized function pointers with the defaults.
3402  * The flash ID is read and the mtd/chip structures are filled with the
3403  * appropriate values. The mtd->owner field must be set to the module of the
3404  * caller.
3405  */
3406 int nand_scan(struct mtd_info *mtd, int maxchips)
3407 {
3408         int ret;
3409
3410         ret = nand_scan_ident(mtd, maxchips, NULL);
3411         if (!ret)
3412                 ret = nand_scan_tail(mtd);
3413         return ret;
3414 }
3415
3416 /**
3417  * nand_release - [NAND Interface] Free resources held by the NAND device
3418  * @mtd: MTD device structure
3419  */
3420 void nand_release(struct mtd_info *mtd)
3421 {
3422         struct nand_chip *chip = mtd->priv;
3423
3424         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3425                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3426
3427 #ifdef CONFIG_MTD_PARTITIONS
3428         /* Deregister partitions */
3429         del_mtd_partitions(mtd);
3430 #endif
3431
3432         /* Free bad block table memory */
3433         kfree(chip->bbt);
3434         if (!(chip->options & NAND_OWN_BUFFERS))
3435                 kfree(chip->buffers);
3436
3437         /* Free bad block descriptor memory */
3438         if (chip->badblock_pattern && chip->badblock_pattern->options
3439                         & NAND_BBT_DYNAMICSTRUCT)
3440                 kfree(chip->badblock_pattern);
3441 }