drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ECC support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <common.h>
  36
  37 #define ENOTSUPP        524     /* Operation is not supported */
  38
  39 #include <malloc.h>
  40 #include <watchdog.h>
  41 #include <linux/err.h>
  42 #include <linux/compat.h>
  43 #include <linux/mtd/mtd.h>
  44 #include <linux/mtd/nand.h>
  45 #include <linux/mtd/nand_ecc.h>
  46 #include <linux/mtd/nand_bch.h>
  47
  48 #ifdef CONFIG_MTD_PARTITIONS
  49 #include <linux/mtd/partitions.h>
  50 #endif
  51
  52 #include <asm/io.h>
  53 #include <asm/errno.h>
  54
  55 /*
  56  * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
  57  * a flash.  NAND flash is initialized prior to interrupts so standard timers
  58  * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
  59  * which is greater than (max NAND reset time / NAND status read time).
  60  * A conservative default of 200000 (500 us / 25 ns) is used as a default.
  61  */
  62 #ifndef CONFIG_SYS_NAND_RESET_CNT
  63 #define CONFIG_SYS_NAND_RESET_CNT 200000
  64 #endif
  65
  66 /* Define default oob placement schemes for large and small page devices */
  67 static struct nand_ecclayout nand_oob_8 = {
  68         .eccbytes = 3,
  69         .eccpos = {0, 1, 2},
  70         .oobfree = {
  71                 {.offset = 3,
  72                  .length = 2},
  73                 {.offset = 6,
  74                  .length = 2} }
  75 };
  76
  77 static struct nand_ecclayout nand_oob_16 = {
  78         .eccbytes = 6,
  79         .eccpos = {0, 1, 2, 3, 6, 7},
  80         .oobfree = {
  81                 {.offset = 8,
  82                  . length = 8} }
  83 };
  84
  85 static struct nand_ecclayout nand_oob_64 = {
  86         .eccbytes = 24,
  87         .eccpos = {
  88                    40, 41, 42, 43, 44, 45, 46, 47,
  89                    48, 49, 50, 51, 52, 53, 54, 55,
  90                    56, 57, 58, 59, 60, 61, 62, 63},
  91         .oobfree = {
  92                 {.offset = 2,
  93                  .length = 38} }
  94 };
  95
  96 static struct nand_ecclayout nand_oob_128 = {
  97         .eccbytes = 48,
  98         .eccpos = {
  99                    80, 81, 82, 83, 84, 85, 86, 87,
 100                    88, 89, 90, 91, 92, 93, 94, 95,
 101                    96, 97, 98, 99, 100, 101, 102, 103,
 102                    104, 105, 106, 107, 108, 109, 110, 111,
 103                    112, 113, 114, 115, 116, 117, 118, 119,
 104                    120, 121, 122, 123, 124, 125, 126, 127},
 105         .oobfree = {
 106                 {.offset = 2,
 107                  .length = 78} }
 108 };
 109
 110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 111                            int new_state);
 112
 113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 114                              struct mtd_oob_ops *ops);
 115
 116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 117
 118 static int check_offs_len(struct mtd_info *mtd,
 119                                         loff_t ofs, uint64_t len)
 120 {
 121         struct nand_chip *chip = mtd->priv;
 122         int ret = 0;
 123
 124         /* Start address must align on block boundary */
 125         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 126                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
 127                 ret = -EINVAL;
 128         }
 129
 130         /* Length must align on block boundary */
 131         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 132                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
 133                                         __func__);
 134                 ret = -EINVAL;
 135         }
 136
 137         return ret;
 138 }
 139
 140 /**
 141  * nand_release_device - [GENERIC] release chip
 142  * @mtd: MTD device structure
 143  *
 144  * Deselect, release chip lock and wake up anyone waiting on the device.
 145  */
 146 static void nand_release_device(struct mtd_info *mtd)
 147 {
 148         struct nand_chip *chip = mtd->priv;
 149
 150         /* De-select the NAND device */
 151         chip->select_chip(mtd, -1);
 152 }
 153
 154 /**
 155  * nand_read_byte - [DEFAULT] read one byte from the chip
 156  * @mtd: MTD device structure
 157  *
 158  * Default read function for 8bit buswidth.
 159  */
 160 uint8_t nand_read_byte(struct mtd_info *mtd)
 161 {
 162         struct nand_chip *chip = mtd->priv;
 163         return readb(chip->IO_ADDR_R);
 164 }
 165
 166 /**
 167  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 168  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 169  * @mtd: MTD device structure
 170  *
 171  * Default read function for 16bit buswidth with endianness conversion.
 172  *
 173  */
 174 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 175 {
 176         struct nand_chip *chip = mtd->priv;
 177         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 178 }
 179
 180 /**
 181  * nand_read_word - [DEFAULT] read one word from the chip
 182  * @mtd: MTD device structure
 183  *
 184  * Default read function for 16bit buswidth without endianness conversion.
 185  */
 186 static u16 nand_read_word(struct mtd_info *mtd)
 187 {
 188         struct nand_chip *chip = mtd->priv;
 189         return readw(chip->IO_ADDR_R);
 190 }
 191
 192 /**
 193  * nand_select_chip - [DEFAULT] control CE line
 194  * @mtd: MTD device structure
 195  * @chipnr: chipnumber to select, -1 for deselect
 196  *
 197  * Default select function for 1 chip devices.
 198  */
 199 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 200 {
 201         struct nand_chip *chip = mtd->priv;
 202
 203         switch (chipnr) {
 204         case -1:
 205                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 206                 break;
 207         case 0:
 208                 break;
 209
 210         default:
 211                 BUG();
 212         }
 213 }
 214
 215 /**
 216  * nand_write_buf - [DEFAULT] write buffer to chip
 217  * @mtd: MTD device structure
 218  * @buf: data buffer
 219  * @len: number of bytes to write
 220  *
 221  * Default write function for 8bit buswidth.
 222  */
 223 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 224 {
 225         int i;
 226         struct nand_chip *chip = mtd->priv;
 227
 228         for (i = 0; i < len; i++)
 229                 writeb(buf[i], chip->IO_ADDR_W);
 230 }
 231
 232 /**
 233  * nand_read_buf - [DEFAULT] read chip data into buffer
 234  * @mtd: MTD device structure
 235  * @buf: buffer to store date
 236  * @len: number of bytes to read
 237  *
 238  * Default read function for 8bit buswidth.
 239  */
 240 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 241 {
 242         int i;
 243         struct nand_chip *chip = mtd->priv;
 244
 245         for (i = 0; i < len; i++)
 246                 buf[i] = readb(chip->IO_ADDR_R);
 247 }
 248
 249 /**
 250  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 251  * @mtd: MTD device structure
 252  * @buf: buffer containing the data to compare
 253  * @len: number of bytes to compare
 254  *
 255  * Default verify function for 8bit buswidth.
 256  */
 257 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 258 {
 259         int i;
 260         struct nand_chip *chip = mtd->priv;
 261
 262         for (i = 0; i < len; i++)
 263                 if (buf[i] != readb(chip->IO_ADDR_R))
 264                         return -EFAULT;
 265         return 0;
 266 }
 267
 268 /**
 269  * nand_write_buf16 - [DEFAULT] write buffer to chip
 270  * @mtd: MTD device structure
 271  * @buf: data buffer
 272  * @len: number of bytes to write
 273  *
 274  * Default write function for 16bit buswidth.
 275  */
 276 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 277 {
 278         int i;
 279         struct nand_chip *chip = mtd->priv;
 280         u16 *p = (u16 *) buf;
 281         len >>= 1;
 282
 283         for (i = 0; i < len; i++)
 284                 writew(p[i], chip->IO_ADDR_W);
 285
 286 }
 287
 288 /**
 289  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 290  * @mtd: MTD device structure
 291  * @buf: buffer to store date
 292  * @len: number of bytes to read
 293  *
 294  * Default read function for 16bit buswidth.
 295  */
 296 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 297 {
 298         int i;
 299         struct nand_chip *chip = mtd->priv;
 300         u16 *p = (u16 *) buf;
 301         len >>= 1;
 302
 303         for (i = 0; i < len; i++)
 304                 p[i] = readw(chip->IO_ADDR_R);
 305 }
 306
 307 /**
 308  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 309  * @mtd: MTD device structure
 310  * @buf: buffer containing the data to compare
 311  * @len: number of bytes to compare
 312  *
 313  * Default verify function for 16bit buswidth.
 314  */
 315 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 316 {
 317         int i;
 318         struct nand_chip *chip = mtd->priv;
 319         u16 *p = (u16 *) buf;
 320         len >>= 1;
 321
 322         for (i = 0; i < len; i++)
 323                 if (p[i] != readw(chip->IO_ADDR_R))
 324                         return -EFAULT;
 325
 326         return 0;
 327 }
 328
 329 /**
 330  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 331  * @mtd: MTD device structure
 332  * @ofs: offset from device start
 333  * @getchip: 0, if the chip is already selected
 334  *
 335  * Check, if the block is bad.
 336  */
 337 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 338 {
 339         int page, chipnr, res = 0, i = 0;
 340         struct nand_chip *chip = mtd->priv;
 341         u16 bad;
 342
 343         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 344                 ofs += mtd->erasesize - mtd->writesize;
 345
 346         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 347
 348         if (getchip) {
 349                 chipnr = (int)(ofs >> chip->chip_shift);
 350
 351                 nand_get_device(chip, mtd, FL_READING);
 352
 353                 /* Select the NAND device */
 354                 chip->select_chip(mtd, chipnr);
 355         }
 356
 357         do {
 358                 if (chip->options & NAND_BUSWIDTH_16) {
 359                         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 360                                         chip->badblockpos & 0xFE, page);
 361                         bad = cpu_to_le16(chip->read_word(mtd));
 362                         if (chip->badblockpos & 0x1)
 363                                 bad >>= 8;
 364                         else
 365                                 bad &= 0xFF;
 366                 } else {
 367                         chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
 368                                         page);
 369                         bad = chip->read_byte(mtd);
 370                 }
 371
 372                 if (likely(chip->badblockbits == 8))
 373                         res = bad != 0xFF;
 374                 else
 375                         res = hweight8(bad) < chip->badblockbits;
 376                 ofs += mtd->writesize;
 377                 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 378                 i++;
 379         } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
 380
 381         if (getchip)
 382                 nand_release_device(mtd);
 383
 384         return res;
 385 }
 386
 387 /**
 388  * nand_default_block_markbad - [DEFAULT] mark a block bad
 389  * @mtd: MTD device structure
 390  * @ofs: offset from device start
 391  *
 392  * This is the default implementation, which can be overridden by a hardware
 393  * specific driver. We try operations in the following order, according to our
 394  * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
 395  *  (1) erase the affected block, to allow OOB marker to be written cleanly
 396  *  (2) update in-memory BBT
 397  *  (3) write bad block marker to OOB area of affected block
 398  *  (4) update flash-based BBT
 399  * Note that we retain the first error encountered in (3) or (4), finish the
 400  * procedures, and dump the error in the end.
 401 */
 402 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 403 {
 404         struct nand_chip *chip = mtd->priv;
 405         uint8_t buf[2] = { 0, 0 };
 406         int block, res, ret = 0, i = 0;
 407         int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
 408
 409         if (write_oob) {
 410                 struct erase_info einfo;
 411
 412                 /* Attempt erase before marking OOB */
 413                 memset(&einfo, 0, sizeof(einfo));
 414                 einfo.mtd = mtd;
 415                 einfo.addr = ofs;
 416                 einfo.len = 1 << chip->phys_erase_shift;
 417                 nand_erase_nand(mtd, &einfo, 0);
 418         }
 419
 420         /* Get block number */
 421         block = (int)(ofs >> chip->bbt_erase_shift);
 422         /* Mark block bad in memory-based BBT */
 423         if (chip->bbt)
 424                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 425
 426         /* Write bad block marker to OOB */
 427         if (write_oob) {
 428                 struct mtd_oob_ops ops;
 429                 loff_t wr_ofs = ofs;
 430
 431                 nand_get_device(chip, mtd, FL_WRITING);
 432
 433                 ops.datbuf = NULL;
 434                 ops.oobbuf = buf;
 435                 ops.ooboffs = chip->badblockpos;
 436                 if (chip->options & NAND_BUSWIDTH_16) {
 437                         ops.ooboffs &= ~0x01;
 438                         ops.len = ops.ooblen = 2;
 439                 } else {
 440                         ops.len = ops.ooblen = 1;
 441                 }
 442                 ops.mode = MTD_OPS_PLACE_OOB;
 443
 444                 /* Write to first/last page(s) if necessary */
 445                 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 446                         wr_ofs += mtd->erasesize - mtd->writesize;
 447                 do {
 448                         res = nand_do_write_oob(mtd, wr_ofs, &ops);
 449                         if (!ret)
 450                                 ret = res;
 451
 452                         i++;
 453                         wr_ofs += mtd->writesize;
 454                 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
 455
 456                 nand_release_device(mtd);
 457         }
 458
 459         /* Update flash-based bad block table */
 460         if (chip->bbt_options & NAND_BBT_USE_FLASH) {
 461                 res = nand_update_bbt(mtd, ofs);
 462                 if (!ret)
 463                         ret = res;
 464         }
 465
 466         if (!ret)
 467                 mtd->ecc_stats.badblocks++;
 468
 469         return ret;
 470 }
 471
 472 /**
 473  * nand_check_wp - [GENERIC] check if the chip is write protected
 474  * @mtd: MTD device structure
 475  *
 476  * Check, if the device is write protected. The function expects, that the
 477  * device is already selected.
 478  */
 479 static int nand_check_wp(struct mtd_info *mtd)
 480 {
 481         struct nand_chip *chip = mtd->priv;
 482
 483         /* Broken xD cards report WP despite being writable */
 484         if (chip->options & NAND_BROKEN_XD)
 485                 return 0;
 486
 487         /* Check the WP bit */
 488         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 489         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 490 }
 491
 492 /**
 493  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 494  * @mtd: MTD device structure
 495  * @ofs: offset from device start
 496  * @getchip: 0, if the chip is already selected
 497  * @allowbbt: 1, if its allowed to access the bbt area
 498  *
 499  * Check, if the block is bad. Either by reading the bad block table or
 500  * calling of the scan function.
 501  */
 502 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 503                                int allowbbt)
 504 {
 505         struct nand_chip *chip = mtd->priv;
 506
 507         if (!(chip->options & NAND_BBT_SCANNED)) {
 508                 chip->options |= NAND_BBT_SCANNED;
 509                 chip->scan_bbt(mtd);
 510         }
 511
 512         if (!chip->bbt)
 513                 return chip->block_bad(mtd, ofs, getchip);
 514
 515         /* Return info from the table */
 516         return nand_isbad_bbt(mtd, ofs, allowbbt);
 517 }
 518
 519 /* Wait for the ready pin, after a command. The timeout is caught later. */
 520 void nand_wait_ready(struct mtd_info *mtd)
 521 {
 522         struct nand_chip *chip = mtd->priv;
 523         u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 524         u32 time_start;
 525
 526         time_start = get_timer(0);
 527
 528         /* Wait until command is processed or timeout occurs */
 529         while (get_timer(time_start) < timeo) {
 530                 if (chip->dev_ready)
 531                         if (chip->dev_ready(mtd))
 532                                 break;
 533         }
 534 }
 535
 536 /**
 537  * nand_command - [DEFAULT] Send command to NAND device
 538  * @mtd: MTD device structure
 539  * @command: the command to be sent
 540  * @column: the column address for this command, -1 if none
 541  * @page_addr: the page address for this command, -1 if none
 542  *
 543  * Send command to NAND device. This function is used for small page devices
 544  * (256/512 Bytes per page).
 545  */
 546 static void nand_command(struct mtd_info *mtd, unsigned int command,
 547                          int column, int page_addr)
 548 {
 549         register struct nand_chip *chip = mtd->priv;
 550         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 551         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 552
 553         /* Write out the command to the device */
 554         if (command == NAND_CMD_SEQIN) {
 555                 int readcmd;
 556
 557                 if (column >= mtd->writesize) {
 558                         /* OOB area */
 559                         column -= mtd->writesize;
 560                         readcmd = NAND_CMD_READOOB;
 561                 } else if (column < 256) {
 562                         /* First 256 bytes --> READ0 */
 563                         readcmd = NAND_CMD_READ0;
 564                 } else {
 565                         column -= 256;
 566                         readcmd = NAND_CMD_READ1;
 567                 }
 568                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 569                 ctrl &= ~NAND_CTRL_CHANGE;
 570         }
 571         chip->cmd_ctrl(mtd, command, ctrl);
 572
 573         /* Address cycle, when necessary */
 574         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 575         /* Serially input address */
 576         if (column != -1) {
 577                 /* Adjust columns for 16 bit buswidth */
 578                 if (chip->options & NAND_BUSWIDTH_16)
 579                         column >>= 1;
 580                 chip->cmd_ctrl(mtd, column, ctrl);
 581                 ctrl &= ~NAND_CTRL_CHANGE;
 582         }
 583         if (page_addr != -1) {
 584                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 585                 ctrl &= ~NAND_CTRL_CHANGE;
 586                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 587                 /* One more address cycle for devices > 32MiB */
 588                 if (chip->chipsize > (32 << 20))
 589                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 590         }
 591         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 592
 593         /*
 594          * Program and erase have their own busy handlers status and sequential
 595          * in needs no delay
 596          */
 597         switch (command) {
 598
 599         case NAND_CMD_PAGEPROG:
 600         case NAND_CMD_ERASE1:
 601         case NAND_CMD_ERASE2:
 602         case NAND_CMD_SEQIN:
 603         case NAND_CMD_STATUS:
 604                 return;
 605
 606         case NAND_CMD_RESET:
 607                 if (chip->dev_ready)
 608                         break;
 609                 udelay(chip->chip_delay);
 610                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 611                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 612                 chip->cmd_ctrl(mtd,
 613                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 614                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 615                         (rst_sts_cnt--));
 616                 return;
 617
 618                 /* This applies to read commands */
 619         default:
 620                 /*
 621                  * If we don't have access to the busy pin, we apply the given
 622                  * command delay
 623                  */
 624                 if (!chip->dev_ready) {
 625                         udelay(chip->chip_delay);
 626                         return;
 627                 }
 628         }
 629         /*
 630          * Apply this short delay always to ensure that we do wait tWB in
 631          * any case on any machine.
 632          */
 633         ndelay(100);
 634
 635         nand_wait_ready(mtd);
 636 }
 637
 638 /**
 639  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 640  * @mtd: MTD device structure
 641  * @command: the command to be sent
 642  * @column: the column address for this command, -1 if none
 643  * @page_addr: the page address for this command, -1 if none
 644  *
 645  * Send command to NAND device. This is the version for the new large page
 646  * devices. We don't have the separate regions as we have in the small page
 647  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 648  */
 649 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 650                             int column, int page_addr)
 651 {
 652         register struct nand_chip *chip = mtd->priv;
 653         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 654
 655         /* Emulate NAND_CMD_READOOB */
 656         if (command == NAND_CMD_READOOB) {
 657                 column += mtd->writesize;
 658                 command = NAND_CMD_READ0;
 659         }
 660
 661         /* Command latch cycle */
 662         chip->cmd_ctrl(mtd, command & 0xff,
 663                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 664
 665         if (column != -1 || page_addr != -1) {
 666                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 667
 668                 /* Serially input address */
 669                 if (column != -1) {
 670                         /* Adjust columns for 16 bit buswidth */
 671                         if (chip->options & NAND_BUSWIDTH_16)
 672                                 column >>= 1;
 673                         chip->cmd_ctrl(mtd, column, ctrl);
 674                         ctrl &= ~NAND_CTRL_CHANGE;
 675                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 676                 }
 677                 if (page_addr != -1) {
 678                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 679                         chip->cmd_ctrl(mtd, page_addr >> 8,
 680                                        NAND_NCE | NAND_ALE);
 681                         /* One more address cycle for devices > 128MiB */
 682                         if (chip->chipsize > (128 << 20))
 683                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 684                                                NAND_NCE | NAND_ALE);
 685                 }
 686         }
 687         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 688
 689         /*
 690          * Program and erase have their own busy handlers status, sequential
 691          * in, and deplete1 need no delay.
 692          */
 693         switch (command) {
 694
 695         case NAND_CMD_CACHEDPROG:
 696         case NAND_CMD_PAGEPROG:
 697         case NAND_CMD_ERASE1:
 698         case NAND_CMD_ERASE2:
 699         case NAND_CMD_SEQIN:
 700         case NAND_CMD_RNDIN:
 701         case NAND_CMD_STATUS:
 702         case NAND_CMD_DEPLETE1:
 703                 return;
 704
 705         case NAND_CMD_STATUS_ERROR:
 706         case NAND_CMD_STATUS_ERROR0:
 707         case NAND_CMD_STATUS_ERROR1:
 708         case NAND_CMD_STATUS_ERROR2:
 709         case NAND_CMD_STATUS_ERROR3:
 710                 /* Read error status commands require only a short delay */
 711                 udelay(chip->chip_delay);
 712                 return;
 713
 714         case NAND_CMD_RESET:
 715                 if (chip->dev_ready)
 716                         break;
 717                 udelay(chip->chip_delay);
 718                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 719                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 720                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 721                                NAND_NCE | NAND_CTRL_CHANGE);
 722                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 723                         (rst_sts_cnt--));
 724                 return;
 725
 726         case NAND_CMD_RNDOUT:
 727                 /* No ready / busy check necessary */
 728                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 729                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 730                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 731                                NAND_NCE | NAND_CTRL_CHANGE);
 732                 return;
 733
 734         case NAND_CMD_READ0:
 735                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 736                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 737                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 738                                NAND_NCE | NAND_CTRL_CHANGE);
 739
 740                 /* This applies to read commands */
 741         default:
 742                 /*
 743                  * If we don't have access to the busy pin, we apply the given
 744                  * command delay.
 745                  */
 746                 if (!chip->dev_ready) {
 747                         udelay(chip->chip_delay);
 748                         return;
 749                 }
 750         }
 751
 752         /*
 753          * Apply this short delay always to ensure that we do wait tWB in
 754          * any case on any machine.
 755          */
 756         ndelay(100);
 757
 758         nand_wait_ready(mtd);
 759 }
 760
 761 /**
 762  * nand_get_device - [GENERIC] Get chip for selected access
 763  * @chip: the nand chip descriptor
 764  * @mtd: MTD device structure
 765  * @new_state: the state which is requested
 766  *
 767  * Get the device and lock it for exclusive access
 768  */
 769 static int
 770 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 771 {
 772         chip->state = new_state;
 773         return 0;
 774 }
 775
 776 /**
 777  * nand_wait - [DEFAULT] wait until the command is done
 778  * @mtd: MTD device structure
 779  * @chip: NAND chip structure
 780  *
 781  * Wait for command done. This applies to erase and program only. Erase can
 782  * take up to 400ms and program up to 20ms according to general NAND and
 783  * SmartMedia specs.
 784  */
 785 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 786 {
 787         unsigned long   timeo;
 788         int state = chip->state;
 789         u32 time_start;
 790
 791         if (state == FL_ERASING)
 792                 timeo = (CONFIG_SYS_HZ * 400) / 1000;
 793         else
 794                 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 795
 796         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 797                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 798         else
 799                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 800
 801         time_start = get_timer(0);
 802
 803         while (1) {
 804                 if (get_timer(time_start) > timeo) {
 805                         printf("Timeout!");
 806                         return 0x01;
 807                 }
 808
 809                 if (chip->dev_ready) {
 810                         if (chip->dev_ready(mtd))
 811                                 break;
 812                 } else {
 813                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 814                                 break;
 815                 }
 816         }
 817 #ifdef PPCHAMELON_NAND_TIMER_HACK
 818         time_start = get_timer(0);
 819         while (get_timer(time_start) < 10)
 820                 ;
 821 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 822
 823         return (int)chip->read_byte(mtd);
 824 }
 825
 826 /**
 827  * nand_read_page_raw - [INTERN] read raw page data without ecc
 828  * @mtd: mtd info structure
 829  * @chip: nand chip info structure
 830  * @buf: buffer to store read data
 831  * @oob_required: caller requires OOB data read to chip->oob_poi
 832  * @page: page number to read
 833  *
 834  * Not for syndrome calculating ECC controllers, which use a special oob layout.
 835  */
 836 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 837                               uint8_t *buf, int oob_required, int page)
 838 {
 839         chip->read_buf(mtd, buf, mtd->writesize);
 840         if (oob_required)
 841                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 842         return 0;
 843 }
 844
 845 /**
 846  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
 847  * @mtd: mtd info structure
 848  * @chip: nand chip info structure
 849  * @buf: buffer to store read data
 850  * @oob_required: caller requires OOB data read to chip->oob_poi
 851  * @page: page number to read
 852  *
 853  * We need a special oob layout and handling even when OOB isn't used.
 854  */
 855 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
 856                                        struct nand_chip *chip, uint8_t *buf,
 857                                        int oob_required, int page)
 858 {
 859         int eccsize = chip->ecc.size;
 860         int eccbytes = chip->ecc.bytes;
 861         uint8_t *oob = chip->oob_poi;
 862         int steps, size;
 863
 864         for (steps = chip->ecc.steps; steps > 0; steps--) {
 865                 chip->read_buf(mtd, buf, eccsize);
 866                 buf += eccsize;
 867
 868                 if (chip->ecc.prepad) {
 869                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 870                         oob += chip->ecc.prepad;
 871                 }
 872
 873                 chip->read_buf(mtd, oob, eccbytes);
 874                 oob += eccbytes;
 875
 876                 if (chip->ecc.postpad) {
 877                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 878                         oob += chip->ecc.postpad;
 879                 }
 880         }
 881
 882         size = mtd->oobsize - (oob - chip->oob_poi);
 883         if (size)
 884                 chip->read_buf(mtd, oob, size);
 885
 886         return 0;
 887 }
 888
 889 /**
 890  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
 891  * @mtd: mtd info structure
 892  * @chip: nand chip info structure
 893  * @buf: buffer to store read data
 894  * @oob_required: caller requires OOB data read to chip->oob_poi
 895  * @page: page number to read
 896  */
 897 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 898                                 uint8_t *buf, int oob_required, int page)
 899 {
 900         int i, eccsize = chip->ecc.size;
 901         int eccbytes = chip->ecc.bytes;
 902         int eccsteps = chip->ecc.steps;
 903         uint8_t *p = buf;
 904         uint8_t *ecc_calc = chip->buffers->ecccalc;
 905         uint8_t *ecc_code = chip->buffers->ecccode;
 906         uint32_t *eccpos = chip->ecc.layout->eccpos;
 907
 908         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
 909
 910         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 911                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 912
 913         for (i = 0; i < chip->ecc.total; i++)
 914                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 915
 916         eccsteps = chip->ecc.steps;
 917         p = buf;
 918
 919         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 920                 int stat;
 921
 922                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 923                 if (stat < 0)
 924                         mtd->ecc_stats.failed++;
 925                 else
 926                         mtd->ecc_stats.corrected += stat;
 927         }
 928         return 0;
 929 }
 930
 931 /**
 932  * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
 933  * @mtd: mtd info structure
 934  * @chip: nand chip info structure
 935  * @data_offs: offset of requested data within the page
 936  * @readlen: data length
 937  * @bufpoi: buffer to store read data
 938  */
 939 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 940                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
 941 {
 942         int start_step, end_step, num_steps;
 943         uint32_t *eccpos = chip->ecc.layout->eccpos;
 944         uint8_t *p;
 945         int data_col_addr, i, gaps = 0;
 946         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
 947         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
 948         int index = 0;
 949
 950         /* Column address within the page aligned to ECC size (256bytes) */
 951         start_step = data_offs / chip->ecc.size;
 952         end_step = (data_offs + readlen - 1) / chip->ecc.size;
 953         num_steps = end_step - start_step + 1;
 954
 955         /* Data size aligned to ECC ecc.size */
 956         datafrag_len = num_steps * chip->ecc.size;
 957         eccfrag_len = num_steps * chip->ecc.bytes;
 958
 959         data_col_addr = start_step * chip->ecc.size;
 960         /* If we read not a page aligned data */
 961         if (data_col_addr != 0)
 962                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
 963
 964         p = bufpoi + data_col_addr;
 965         chip->read_buf(mtd, p, datafrag_len);
 966
 967         /* Calculate ECC */
 968         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
 969                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
 970
 971         /*
 972          * The performance is faster if we position offsets according to
 973          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
 974          */
 975         for (i = 0; i < eccfrag_len - 1; i++) {
 976                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
 977                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
 978                         gaps = 1;
 979                         break;
 980                 }
 981         }
 982         if (gaps) {
 983                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 984                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 985         } else {
 986                 /*
 987                  * Send the command to read the particular ECC bytes take care
 988                  * about buswidth alignment in read_buf.
 989                  */
 990                 index = start_step * chip->ecc.bytes;
 991
 992                 aligned_pos = eccpos[index] & ~(busw - 1);
 993                 aligned_len = eccfrag_len;
 994                 if (eccpos[index] & (busw - 1))
 995                         aligned_len++;
 996                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
 997                         aligned_len++;
 998
 999                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1000                                         mtd->writesize + aligned_pos, -1);
1001                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1002         }
1003
1004         for (i = 0; i < eccfrag_len; i++)
1005                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1006
1007         p = bufpoi + data_col_addr;
1008         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1009                 int stat;
1010
1011                 stat = chip->ecc.correct(mtd, p,
1012                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1013                 if (stat < 0)
1014                         mtd->ecc_stats.failed++;
1015                 else
1016                         mtd->ecc_stats.corrected += stat;
1017         }
1018         return 0;
1019 }
1020
1021 /**
1022  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1023  * @mtd: mtd info structure
1024  * @chip: nand chip info structure
1025  * @buf: buffer to store read data
1026  * @oob_required: caller requires OOB data read to chip->oob_poi
1027  * @page: page number to read
1028  *
1029  * Not for syndrome calculating ECC controllers which need a special oob layout.
1030  */
1031 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1032                                 uint8_t *buf, int oob_required, int page)
1033 {
1034         int i, eccsize = chip->ecc.size;
1035         int eccbytes = chip->ecc.bytes;
1036         int eccsteps = chip->ecc.steps;
1037         uint8_t *p = buf;
1038         uint8_t *ecc_calc = chip->buffers->ecccalc;
1039         uint8_t *ecc_code = chip->buffers->ecccode;
1040         uint32_t *eccpos = chip->ecc.layout->eccpos;
1041
1042         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1043                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1044                 chip->read_buf(mtd, p, eccsize);
1045                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1046         }
1047         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1048
1049         for (i = 0; i < chip->ecc.total; i++)
1050                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1051
1052         eccsteps = chip->ecc.steps;
1053         p = buf;
1054
1055         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1056                 int stat;
1057
1058                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1059                 if (stat < 0)
1060                         mtd->ecc_stats.failed++;
1061                 else
1062                         mtd->ecc_stats.corrected += stat;
1063         }
1064         return 0;
1065 }
1066
1067 /**
1068  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1069  * @mtd: mtd info structure
1070  * @chip: nand chip info structure
1071  * @buf: buffer to store read data
1072  * @oob_required: caller requires OOB data read to chip->oob_poi
1073  * @page: page number to read
1074  *
1075  * Hardware ECC for large page chips, require OOB to be read first. For this
1076  * ECC mode, the write_page method is re-used from ECC_HW. These methods
1077  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1078  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1079  * the data area, by overwriting the NAND manufacturer bad block markings.
1080  */
1081 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1082         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1083 {
1084         int i, eccsize = chip->ecc.size;
1085         int eccbytes = chip->ecc.bytes;
1086         int eccsteps = chip->ecc.steps;
1087         uint8_t *p = buf;
1088         uint8_t *ecc_code = chip->buffers->ecccode;
1089         uint32_t *eccpos = chip->ecc.layout->eccpos;
1090         uint8_t *ecc_calc = chip->buffers->ecccalc;
1091
1092         /* Read the OOB area first */
1093         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1094         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1095         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1096
1097         for (i = 0; i < chip->ecc.total; i++)
1098                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1099
1100         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1101                 int stat;
1102
1103                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1104                 chip->read_buf(mtd, p, eccsize);
1105                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1106
1107                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1108                 if (stat < 0)
1109                         mtd->ecc_stats.failed++;
1110                 else
1111                         mtd->ecc_stats.corrected += stat;
1112         }
1113         return 0;
1114 }
1115
1116 /**
1117  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1118  * @mtd: mtd info structure
1119  * @chip: nand chip info structure
1120  * @buf: buffer to store read data
1121  * @oob_required: caller requires OOB data read to chip->oob_poi
1122  * @page: page number to read
1123  *
1124  * The hw generator calculates the error syndrome automatically. Therefore we
1125  * need a special oob layout and handling.
1126  */
1127 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1128                                    uint8_t *buf, int oob_required, int page)
1129 {
1130         int i, eccsize = chip->ecc.size;
1131         int eccbytes = chip->ecc.bytes;
1132         int eccsteps = chip->ecc.steps;
1133         uint8_t *p = buf;
1134         uint8_t *oob = chip->oob_poi;
1135
1136         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1137                 int stat;
1138
1139                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1140                 chip->read_buf(mtd, p, eccsize);
1141
1142                 if (chip->ecc.prepad) {
1143                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1144                         oob += chip->ecc.prepad;
1145                 }
1146
1147                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1148                 chip->read_buf(mtd, oob, eccbytes);
1149                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1150
1151                 if (stat < 0)
1152                         mtd->ecc_stats.failed++;
1153                 else
1154                         mtd->ecc_stats.corrected += stat;
1155
1156                 oob += eccbytes;
1157
1158                 if (chip->ecc.postpad) {
1159                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1160                         oob += chip->ecc.postpad;
1161                 }
1162         }
1163
1164         /* Calculate remaining oob bytes */
1165         i = mtd->oobsize - (oob - chip->oob_poi);
1166         if (i)
1167                 chip->read_buf(mtd, oob, i);
1168
1169         return 0;
1170 }
1171
1172 /**
1173  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1174  * @chip: nand chip structure
1175  * @oob: oob destination address
1176  * @ops: oob ops structure
1177  * @len: size of oob to transfer
1178  */
1179 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1180                                   struct mtd_oob_ops *ops, size_t len)
1181 {
1182         switch (ops->mode) {
1183
1184         case MTD_OPS_PLACE_OOB:
1185         case MTD_OPS_RAW:
1186                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1187                 return oob + len;
1188
1189         case MTD_OPS_AUTO_OOB: {
1190                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1191                 uint32_t boffs = 0, roffs = ops->ooboffs;
1192                 size_t bytes = 0;
1193
1194                 for (; free->length && len; free++, len -= bytes) {
1195                         /* Read request not from offset 0? */
1196                         if (unlikely(roffs)) {
1197                                 if (roffs >= free->length) {
1198                                         roffs -= free->length;
1199                                         continue;
1200                                 }
1201                                 boffs = free->offset + roffs;
1202                                 bytes = min_t(size_t, len,
1203                                               (free->length - roffs));
1204                                 roffs = 0;
1205                         } else {
1206                                 bytes = min_t(size_t, len, free->length);
1207                                 boffs = free->offset;
1208                         }
1209                         memcpy(oob, chip->oob_poi + boffs, bytes);
1210                         oob += bytes;
1211                 }
1212                 return oob;
1213         }
1214         default:
1215                 BUG();
1216         }
1217         return NULL;
1218 }
1219
1220 /**
1221  * nand_do_read_ops - [INTERN] Read data with ECC
1222  * @mtd: MTD device structure
1223  * @from: offset to read from
1224  * @ops: oob ops structure
1225  *
1226  * Internal function. Called with chip held.
1227  */
1228 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1229                             struct mtd_oob_ops *ops)
1230 {
1231         int chipnr, page, realpage, col, bytes, aligned, oob_required;
1232         struct nand_chip *chip = mtd->priv;
1233         struct mtd_ecc_stats stats;
1234         int ret = 0;
1235         uint32_t readlen = ops->len;
1236         uint32_t oobreadlen = ops->ooblen;
1237         uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1238                 mtd->oobavail : mtd->oobsize;
1239
1240         uint8_t *bufpoi, *oob, *buf;
1241
1242         stats = mtd->ecc_stats;
1243
1244         chipnr = (int)(from >> chip->chip_shift);
1245         chip->select_chip(mtd, chipnr);
1246
1247         realpage = (int)(from >> chip->page_shift);
1248         page = realpage & chip->pagemask;
1249
1250         col = (int)(from & (mtd->writesize - 1));
1251
1252         buf = ops->datbuf;
1253         oob = ops->oobbuf;
1254         oob_required = oob ? 1 : 0;
1255
1256         while (1) {
1257                 WATCHDOG_RESET();
1258
1259                 bytes = min(mtd->writesize - col, readlen);
1260                 aligned = (bytes == mtd->writesize);
1261
1262                 /* Is the current page in the buffer? */
1263                 if (realpage != chip->pagebuf || oob) {
1264                         bufpoi = aligned ? buf : chip->buffers->databuf;
1265
1266                         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1267
1268                         /* Now read the page into the buffer */
1269                         if (unlikely(ops->mode == MTD_OPS_RAW))
1270                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1271                                                               oob_required,
1272                                                               page);
1273                         else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1274                             !oob)
1275                                 ret = chip->ecc.read_subpage(mtd, chip,
1276                                                         col, bytes, bufpoi);
1277                         else
1278                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1279                                                           oob_required, page);
1280                         if (ret < 0) {
1281                                 if (!aligned)
1282                                         /* Invalidate page cache */
1283                                         chip->pagebuf = -1;
1284                                 break;
1285                         }
1286
1287                         /* Transfer not aligned data */
1288                         if (!aligned) {
1289                                 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1290                                     !(mtd->ecc_stats.failed - stats.failed) &&
1291                                     (ops->mode != MTD_OPS_RAW))
1292                                         chip->pagebuf = realpage;
1293                                 else
1294                                         /* Invalidate page cache */
1295                                         chip->pagebuf = -1;
1296                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1297                         }
1298
1299                         buf += bytes;
1300
1301                         if (unlikely(oob)) {
1302                                 int toread = min(oobreadlen, max_oobsize);
1303
1304                                 if (toread) {
1305                                         oob = nand_transfer_oob(chip,
1306                                                 oob, ops, toread);
1307                                         oobreadlen -= toread;
1308                                 }
1309                         }
1310                 } else {
1311                         memcpy(buf, chip->buffers->databuf + col, bytes);
1312                         buf += bytes;
1313                 }
1314
1315                 readlen -= bytes;
1316
1317                 if (!readlen)
1318                         break;
1319
1320                 /* For subsequent reads align to page boundary */
1321                 col = 0;
1322                 /* Increment page address */
1323                 realpage++;
1324
1325                 page = realpage & chip->pagemask;
1326                 /* Check, if we cross a chip boundary */
1327                 if (!page) {
1328                         chipnr++;
1329                         chip->select_chip(mtd, -1);
1330                         chip->select_chip(mtd, chipnr);
1331                 }
1332         }
1333
1334         ops->retlen = ops->len - (size_t) readlen;
1335         if (oob)
1336                 ops->oobretlen = ops->ooblen - oobreadlen;
1337
1338         if (ret)
1339                 return ret;
1340
1341         if (mtd->ecc_stats.failed - stats.failed)
1342                 return -EBADMSG;
1343
1344         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1345 }
1346
1347 /**
1348  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1349  * @mtd: MTD device structure
1350  * @from: offset to read from
1351  * @len: number of bytes to read
1352  * @retlen: pointer to variable to store the number of read bytes
1353  * @buf: the databuffer to put data
1354  *
1355  * Get hold of the chip and call nand_do_read.
1356  */
1357 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1358                      size_t *retlen, uint8_t *buf)
1359 {
1360         struct nand_chip *chip = mtd->priv;
1361         struct mtd_oob_ops ops;
1362         int ret;
1363
1364         nand_get_device(chip, mtd, FL_READING);
1365         ops.len = len;
1366         ops.datbuf = buf;
1367         ops.oobbuf = NULL;
1368         ops.mode = MTD_OPS_PLACE_OOB;
1369         ret = nand_do_read_ops(mtd, from, &ops);
1370         *retlen = ops.retlen;
1371         nand_release_device(mtd);
1372         return ret;
1373 }
1374
1375 /**
1376  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1377  * @mtd: mtd info structure
1378  * @chip: nand chip info structure
1379  * @page: page number to read
1380  */
1381 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1382                              int page)
1383 {
1384         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1385         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1386         return 0;
1387 }
1388
1389 /**
1390  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1391  *                          with syndromes
1392  * @mtd: mtd info structure
1393  * @chip: nand chip info structure
1394  * @page: page number to read
1395  */
1396 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1397                                   int page)
1398 {
1399         uint8_t *buf = chip->oob_poi;
1400         int length = mtd->oobsize;
1401         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1402         int eccsize = chip->ecc.size;
1403         uint8_t *bufpoi = buf;
1404         int i, toread, sndrnd = 0, pos;
1405
1406         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1407         for (i = 0; i < chip->ecc.steps; i++) {
1408                 if (sndrnd) {
1409                         pos = eccsize + i * (eccsize + chunk);
1410                         if (mtd->writesize > 512)
1411                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1412                         else
1413                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1414                 } else
1415                         sndrnd = 1;
1416                 toread = min_t(int, length, chunk);
1417                 chip->read_buf(mtd, bufpoi, toread);
1418                 bufpoi += toread;
1419                 length -= toread;
1420         }
1421         if (length > 0)
1422                 chip->read_buf(mtd, bufpoi, length);
1423
1424         return 0;
1425 }
1426
1427 /**
1428  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1429  * @mtd: mtd info structure
1430  * @chip: nand chip info structure
1431  * @page: page number to write
1432  */
1433 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1434                               int page)
1435 {
1436         int status = 0;
1437         const uint8_t *buf = chip->oob_poi;
1438         int length = mtd->oobsize;
1439
1440         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1441         chip->write_buf(mtd, buf, length);
1442         /* Send command to program the OOB data */
1443         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1444
1445         status = chip->waitfunc(mtd, chip);
1446
1447         return status & NAND_STATUS_FAIL ? -EIO : 0;
1448 }
1449
1450 /**
1451  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1452  *                           with syndrome - only for large page flash
1453  * @mtd: mtd info structure
1454  * @chip: nand chip info structure
1455  * @page: page number to write
1456  */
1457 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1458                                    struct nand_chip *chip, int page)
1459 {
1460         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1461         int eccsize = chip->ecc.size, length = mtd->oobsize;
1462         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1463         const uint8_t *bufpoi = chip->oob_poi;
1464
1465         /*
1466          * data-ecc-data-ecc ... ecc-oob
1467          * or
1468          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1469          */
1470         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1471                 pos = steps * (eccsize + chunk);
1472                 steps = 0;
1473         } else
1474                 pos = eccsize;
1475
1476         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1477         for (i = 0; i < steps; i++) {
1478                 if (sndcmd) {
1479                         if (mtd->writesize <= 512) {
1480                                 uint32_t fill = 0xFFFFFFFF;
1481
1482                                 len = eccsize;
1483                                 while (len > 0) {
1484                                         int num = min_t(int, len, 4);
1485                                         chip->write_buf(mtd, (uint8_t *)&fill,
1486                                                         num);
1487                                         len -= num;
1488                                 }
1489                         } else {
1490                                 pos = eccsize + i * (eccsize + chunk);
1491                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1492                         }
1493                 } else
1494                         sndcmd = 1;
1495                 len = min_t(int, length, chunk);
1496                 chip->write_buf(mtd, bufpoi, len);
1497                 bufpoi += len;
1498                 length -= len;
1499         }
1500         if (length > 0)
1501                 chip->write_buf(mtd, bufpoi, length);
1502
1503         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1504         status = chip->waitfunc(mtd, chip);
1505
1506         return status & NAND_STATUS_FAIL ? -EIO : 0;
1507 }
1508
1509 /**
1510  * nand_do_read_oob - [INTERN] NAND read out-of-band
1511  * @mtd: MTD device structure
1512  * @from: offset to read from
1513  * @ops: oob operations description structure
1514  *
1515  * NAND read out-of-band data from the spare area.
1516  */
1517 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1518                             struct mtd_oob_ops *ops)
1519 {
1520         int page, realpage, chipnr;
1521         struct nand_chip *chip = mtd->priv;
1522         struct mtd_ecc_stats stats;
1523         int readlen = ops->ooblen;
1524         int len;
1525         uint8_t *buf = ops->oobbuf;
1526         int ret = 0;
1527
1528         MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1529                         __func__, (unsigned long long)from, readlen);
1530
1531         stats = mtd->ecc_stats;
1532
1533         if (ops->mode == MTD_OPS_AUTO_OOB)
1534                 len = chip->ecc.layout->oobavail;
1535         else
1536                 len = mtd->oobsize;
1537
1538         if (unlikely(ops->ooboffs >= len)) {
1539                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1540                                         "outside oob\n", __func__);
1541                 return -EINVAL;
1542         }
1543
1544         /* Do not allow reads past end of device */
1545         if (unlikely(from >= mtd->size ||
1546                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1547                                         (from >> chip->page_shift)) * len)) {
1548                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1549                                         "of device\n", __func__);
1550                 return -EINVAL;
1551         }
1552
1553         chipnr = (int)(from >> chip->chip_shift);
1554         chip->select_chip(mtd, chipnr);
1555
1556         /* Shift to get page */
1557         realpage = (int)(from >> chip->page_shift);
1558         page = realpage & chip->pagemask;
1559
1560         while (1) {
1561                 WATCHDOG_RESET();
1562                 if (ops->mode == MTD_OPS_RAW)
1563                         ret = chip->ecc.read_oob_raw(mtd, chip, page);
1564                 else
1565                         ret = chip->ecc.read_oob(mtd, chip, page);
1566
1567                 if (ret < 0)
1568                         break;
1569
1570                 len = min(len, readlen);
1571                 buf = nand_transfer_oob(chip, buf, ops, len);
1572
1573                 readlen -= len;
1574                 if (!readlen)
1575                         break;
1576
1577                 /* Increment page address */
1578                 realpage++;
1579
1580                 page = realpage & chip->pagemask;
1581                 /* Check, if we cross a chip boundary */
1582                 if (!page) {
1583                         chipnr++;
1584                         chip->select_chip(mtd, -1);
1585                         chip->select_chip(mtd, chipnr);
1586                 }
1587         }
1588
1589         ops->oobretlen = ops->ooblen - readlen;
1590
1591         if (ret < 0)
1592                 return ret;
1593
1594         if (mtd->ecc_stats.failed - stats.failed)
1595                 return -EBADMSG;
1596
1597         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1598 }
1599
1600 /**
1601  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1602  * @mtd: MTD device structure
1603  * @from: offset to read from
1604  * @ops: oob operation description structure
1605  *
1606  * NAND read data and/or out-of-band data.
1607  */
1608 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1609                          struct mtd_oob_ops *ops)
1610 {
1611         struct nand_chip *chip = mtd->priv;
1612         int ret = -ENOTSUPP;
1613
1614         ops->retlen = 0;
1615
1616         /* Do not allow reads past end of device */
1617         if (ops->datbuf && (from + ops->len) > mtd->size) {
1618                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1619                                 "beyond end of device\n", __func__);
1620                 return -EINVAL;
1621         }
1622
1623         nand_get_device(chip, mtd, FL_READING);
1624
1625         switch (ops->mode) {
1626         case MTD_OPS_PLACE_OOB:
1627         case MTD_OPS_AUTO_OOB:
1628         case MTD_OPS_RAW:
1629                 break;
1630
1631         default:
1632                 goto out;
1633         }
1634
1635         if (!ops->datbuf)
1636                 ret = nand_do_read_oob(mtd, from, ops);
1637         else
1638                 ret = nand_do_read_ops(mtd, from, ops);
1639
1640 out:
1641         nand_release_device(mtd);
1642         return ret;
1643 }
1644
1645
1646 /**
1647  * nand_write_page_raw - [INTERN] raw page write function
1648  * @mtd: mtd info structure
1649  * @chip: nand chip info structure
1650  * @buf: data buffer
1651  * @oob_required: must write chip->oob_poi to OOB
1652  *
1653  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1654  */
1655 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1656                                 const uint8_t *buf, int oob_required)
1657 {
1658         chip->write_buf(mtd, buf, mtd->writesize);
1659         if (oob_required)
1660                 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1661
1662         return 0;
1663 }
1664
1665 /**
1666  * nand_write_page_raw_syndrome - [INTERN] raw page write function
1667  * @mtd: mtd info structure
1668  * @chip: nand chip info structure
1669  * @buf: data buffer
1670  * @oob_required: must write chip->oob_poi to OOB
1671  *
1672  * We need a special oob layout and handling even when ECC isn't checked.
1673  */
1674 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1675                                         struct nand_chip *chip,
1676                                         const uint8_t *buf, int oob_required)
1677 {
1678         int eccsize = chip->ecc.size;
1679         int eccbytes = chip->ecc.bytes;
1680         uint8_t *oob = chip->oob_poi;
1681         int steps, size;
1682
1683         for (steps = chip->ecc.steps; steps > 0; steps--) {
1684                 chip->write_buf(mtd, buf, eccsize);
1685                 buf += eccsize;
1686
1687                 if (chip->ecc.prepad) {
1688                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1689                         oob += chip->ecc.prepad;
1690                 }
1691
1692                 chip->read_buf(mtd, oob, eccbytes);
1693                 oob += eccbytes;
1694
1695                 if (chip->ecc.postpad) {
1696                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1697                         oob += chip->ecc.postpad;
1698                 }
1699         }
1700
1701         size = mtd->oobsize - (oob - chip->oob_poi);
1702         if (size)
1703                 chip->write_buf(mtd, oob, size);
1704
1705         return 0;
1706 }
1707 /**
1708  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1709  * @mtd: mtd info structure
1710  * @chip: nand chip info structure
1711  * @buf: data buffer
1712  * @oob_required: must write chip->oob_poi to OOB
1713  */
1714 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1715                                   const uint8_t *buf, int oob_required)
1716 {
1717         int i, eccsize = chip->ecc.size;
1718         int eccbytes = chip->ecc.bytes;
1719         int eccsteps = chip->ecc.steps;
1720         uint8_t *ecc_calc = chip->buffers->ecccalc;
1721         const uint8_t *p = buf;
1722         uint32_t *eccpos = chip->ecc.layout->eccpos;
1723
1724         /* Software ECC calculation */
1725         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1726                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1727
1728         for (i = 0; i < chip->ecc.total; i++)
1729                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1730
1731         return chip->ecc.write_page_raw(mtd, chip, buf, 1);
1732 }
1733
1734 /**
1735  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1736  * @mtd: mtd info structure
1737  * @chip: nand chip info structure
1738  * @buf: data buffer
1739  * @oob_required: must write chip->oob_poi to OOB
1740  */
1741 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1742                                   const uint8_t *buf, int oob_required)
1743 {
1744         int i, eccsize = chip->ecc.size;
1745         int eccbytes = chip->ecc.bytes;
1746         int eccsteps = chip->ecc.steps;
1747         uint8_t *ecc_calc = chip->buffers->ecccalc;
1748         const uint8_t *p = buf;
1749         uint32_t *eccpos = chip->ecc.layout->eccpos;
1750
1751         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1752                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1753                 chip->write_buf(mtd, p, eccsize);
1754                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1755         }
1756
1757         for (i = 0; i < chip->ecc.total; i++)
1758                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1759
1760         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1761
1762         return 0;
1763 }
1764
1765 /**
1766  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
1767  * @mtd: mtd info structure
1768  * @chip: nand chip info structure
1769  * @buf: data buffer
1770  * @oob_required: must write chip->oob_poi to OOB
1771  *
1772  * The hw generator calculates the error syndrome automatically. Therefore we
1773  * need a special oob layout and handling.
1774  */
1775 static int nand_write_page_syndrome(struct mtd_info *mtd,
1776                                     struct nand_chip *chip,
1777                                     const uint8_t *buf, int oob_required)
1778 {
1779         int i, eccsize = chip->ecc.size;
1780         int eccbytes = chip->ecc.bytes;
1781         int eccsteps = chip->ecc.steps;
1782         const uint8_t *p = buf;
1783         uint8_t *oob = chip->oob_poi;
1784
1785         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1786
1787                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1788                 chip->write_buf(mtd, p, eccsize);
1789
1790                 if (chip->ecc.prepad) {
1791                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1792                         oob += chip->ecc.prepad;
1793                 }
1794
1795                 chip->ecc.calculate(mtd, p, oob);
1796                 chip->write_buf(mtd, oob, eccbytes);
1797                 oob += eccbytes;
1798
1799                 if (chip->ecc.postpad) {
1800                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1801                         oob += chip->ecc.postpad;
1802                 }
1803         }
1804
1805         /* Calculate remaining oob bytes */
1806         i = mtd->oobsize - (oob - chip->oob_poi);
1807         if (i)
1808                 chip->write_buf(mtd, oob, i);
1809
1810         return 0;
1811 }
1812
1813 /**
1814  * nand_write_page - [REPLACEABLE] write one page
1815  * @mtd: MTD device structure
1816  * @chip: NAND chip descriptor
1817  * @buf: the data to write
1818  * @oob_required: must write chip->oob_poi to OOB
1819  * @page: page number to write
1820  * @cached: cached programming
1821  * @raw: use _raw version of write_page
1822  */
1823 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1824                            const uint8_t *buf, int oob_required, int page,
1825                            int cached, int raw)
1826 {
1827         int status;
1828
1829         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1830
1831         if (unlikely(raw))
1832                 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
1833         else
1834                 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
1835
1836         if (status < 0)
1837                 return status;
1838
1839         /*
1840          * Cached progamming disabled for now. Not sure if it's worth the
1841          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
1842          */
1843         cached = 0;
1844
1845         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1846
1847                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1848                 status = chip->waitfunc(mtd, chip);
1849                 /*
1850                  * See if operation failed and additional status checks are
1851                  * available.
1852                  */
1853                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1854                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1855                                                page);
1856
1857                 if (status & NAND_STATUS_FAIL)
1858                         return -EIO;
1859         } else {
1860                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1861                 status = chip->waitfunc(mtd, chip);
1862         }
1863
1864 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1865         /* Send command to read back the data */
1866         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1867
1868         if (chip->verify_buf(mtd, buf, mtd->writesize))
1869                 return -EIO;
1870
1871         /* Make sure the next page prog is preceded by a status read */
1872         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1873 #endif
1874         return 0;
1875 }
1876
1877 /**
1878  * nand_fill_oob - [INTERN] Transfer client buffer to oob
1879  * @mtd: MTD device structure
1880  * @oob: oob data buffer
1881  * @len: oob data write length
1882  * @ops: oob ops structure
1883  */
1884 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
1885                               struct mtd_oob_ops *ops)
1886 {
1887         struct nand_chip *chip = mtd->priv;
1888
1889         /*
1890          * Initialise to all 0xFF, to avoid the possibility of left over OOB
1891          * data from a previous OOB read.
1892          */
1893         memset(chip->oob_poi, 0xff, mtd->oobsize);
1894
1895         switch (ops->mode) {
1896
1897         case MTD_OPS_PLACE_OOB:
1898         case MTD_OPS_RAW:
1899                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1900                 return oob + len;
1901
1902         case MTD_OPS_AUTO_OOB: {
1903                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1904                 uint32_t boffs = 0, woffs = ops->ooboffs;
1905                 size_t bytes = 0;
1906
1907                 for (; free->length && len; free++, len -= bytes) {
1908                         /* Write request not from offset 0? */
1909                         if (unlikely(woffs)) {
1910                                 if (woffs >= free->length) {
1911                                         woffs -= free->length;
1912                                         continue;
1913                                 }
1914                                 boffs = free->offset + woffs;
1915                                 bytes = min_t(size_t, len,
1916                                               (free->length - woffs));
1917                                 woffs = 0;
1918                         } else {
1919                                 bytes = min_t(size_t, len, free->length);
1920                                 boffs = free->offset;
1921                         }
1922                         memcpy(chip->oob_poi + boffs, oob, bytes);
1923                         oob += bytes;
1924                 }
1925                 return oob;
1926         }
1927         default:
1928                 BUG();
1929         }
1930         return NULL;
1931 }
1932
1933 /**
1934  * nand_do_write_ops - [INTERN] NAND write with ECC
1935  * @mtd: MTD device structure
1936  * @to: offset to write to
1937  * @ops: oob operations description structure
1938  *
1939  * NAND write with ECC.
1940  */
1941 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1942                              struct mtd_oob_ops *ops)
1943 {
1944         int chipnr, realpage, page, blockmask, column;
1945         struct nand_chip *chip = mtd->priv;
1946         uint32_t writelen = ops->len;
1947
1948         uint32_t oobwritelen = ops->ooblen;
1949         uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
1950                                 mtd->oobavail : mtd->oobsize;
1951
1952         uint8_t *oob = ops->oobbuf;
1953         uint8_t *buf = ops->datbuf;
1954         int ret, subpage;
1955         int oob_required = oob ? 1 : 0;
1956
1957         ops->retlen = 0;
1958         if (!writelen)
1959                 return 0;
1960
1961         column = to & (mtd->writesize - 1);
1962         subpage = column || (writelen & (mtd->writesize - 1));
1963
1964         if (subpage && oob)
1965                 return -EINVAL;
1966
1967         chipnr = (int)(to >> chip->chip_shift);
1968         chip->select_chip(mtd, chipnr);
1969
1970         /* Check, if it is write protected */
1971         if (nand_check_wp(mtd)) {
1972                 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1973                 return -EIO;
1974         }
1975
1976         realpage = (int)(to >> chip->page_shift);
1977         page = realpage & chip->pagemask;
1978         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1979
1980         /* Invalidate the page cache, when we write to the cached page */
1981         if (to <= (chip->pagebuf << chip->page_shift) &&
1982             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1983                 chip->pagebuf = -1;
1984
1985         /* Don't allow multipage oob writes with offset */
1986         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
1987                 return -EINVAL;
1988
1989         while (1) {
1990                 WATCHDOG_RESET();
1991
1992                 int bytes = mtd->writesize;
1993                 int cached = writelen > bytes && page != blockmask;
1994                 uint8_t *wbuf = buf;
1995
1996                 /* Partial page write? */
1997                 if (unlikely(column || writelen < mtd->writesize)) {
1998                         cached = 0;
1999                         bytes = min_t(int, bytes - column, (int) writelen);
2000                         chip->pagebuf = -1;
2001                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2002                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2003                         wbuf = chip->buffers->databuf;
2004                 }
2005
2006                 if (unlikely(oob)) {
2007                         size_t len = min(oobwritelen, oobmaxlen);
2008                         oob = nand_fill_oob(mtd, oob, len, ops);
2009                         oobwritelen -= len;
2010                 } else {
2011                         /* We still need to erase leftover OOB data */
2012                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2013                 }
2014
2015                 ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
2016                                        cached, (ops->mode == MTD_OPS_RAW));
2017                 if (ret)
2018                         break;
2019
2020                 writelen -= bytes;
2021                 if (!writelen)
2022                         break;
2023
2024                 column = 0;
2025                 buf += bytes;
2026                 realpage++;
2027
2028                 page = realpage & chip->pagemask;
2029                 /* Check, if we cross a chip boundary */
2030                 if (!page) {
2031                         chipnr++;
2032                         chip->select_chip(mtd, -1);
2033                         chip->select_chip(mtd, chipnr);
2034                 }
2035         }
2036
2037         ops->retlen = ops->len - writelen;
2038         if (unlikely(oob))
2039                 ops->oobretlen = ops->ooblen;
2040         return ret;
2041 }
2042
2043 /**
2044  * nand_write - [MTD Interface] NAND write with ECC
2045  * @mtd: MTD device structure
2046  * @to: offset to write to
2047  * @len: number of bytes to write
2048  * @retlen: pointer to variable to store the number of written bytes
2049  * @buf: the data to write
2050  *
2051  * NAND write with ECC.
2052  */
2053 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2054                           size_t *retlen, const uint8_t *buf)
2055 {
2056         struct nand_chip *chip = mtd->priv;
2057         struct mtd_oob_ops ops;
2058         int ret;
2059
2060         nand_get_device(chip, mtd, FL_WRITING);
2061         ops.len = len;
2062         ops.datbuf = (uint8_t *)buf;
2063         ops.oobbuf = NULL;
2064         ops.mode = MTD_OPS_PLACE_OOB;
2065         ret = nand_do_write_ops(mtd, to, &ops);
2066         *retlen = ops.retlen;
2067         nand_release_device(mtd);
2068         return ret;
2069 }
2070
2071 /**
2072  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2073  * @mtd: MTD device structure
2074  * @to: offset to write to
2075  * @ops: oob operation description structure
2076  *
2077  * NAND write out-of-band.
2078  */
2079 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2080                              struct mtd_oob_ops *ops)
2081 {
2082         int chipnr, page, status, len;
2083         struct nand_chip *chip = mtd->priv;
2084
2085         MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2086                          __func__, (unsigned int)to, (int)ops->ooblen);
2087
2088         if (ops->mode == MTD_OPS_AUTO_OOB)
2089                 len = chip->ecc.layout->oobavail;
2090         else
2091                 len = mtd->oobsize;
2092
2093         /* Do not allow write past end of page */
2094         if ((ops->ooboffs + ops->ooblen) > len) {
2095                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2096                                 "past end of page\n", __func__);
2097                 return -EINVAL;
2098         }
2099
2100         if (unlikely(ops->ooboffs >= len)) {
2101                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2102                                 "write outside oob\n", __func__);
2103                 return -EINVAL;
2104         }
2105
2106         /* Do not allow write past end of device */
2107         if (unlikely(to >= mtd->size ||
2108                      ops->ooboffs + ops->ooblen >
2109                         ((mtd->size >> chip->page_shift) -
2110                          (to >> chip->page_shift)) * len)) {
2111                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2112                                 "end of device\n", __func__);
2113                 return -EINVAL;
2114         }
2115
2116         chipnr = (int)(to >> chip->chip_shift);
2117         chip->select_chip(mtd, chipnr);
2118
2119         /* Shift to get page */
2120         page = (int)(to >> chip->page_shift);
2121
2122         /*
2123          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2124          * of my DiskOnChip 2000 test units) will clear the whole data page too
2125          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2126          * it in the doc2000 driver in August 1999.  dwmw2.
2127          */
2128         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2129
2130         /* Check, if it is write protected */
2131         if (nand_check_wp(mtd))
2132                 return -EROFS;
2133
2134         /* Invalidate the page cache, if we write to the cached page */
2135         if (page == chip->pagebuf)
2136                 chip->pagebuf = -1;
2137
2138         nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2139
2140         if (ops->mode == MTD_OPS_RAW)
2141                 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2142         else
2143                 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2144
2145         if (status)
2146                 return status;
2147
2148         ops->oobretlen = ops->ooblen;
2149
2150         return 0;
2151 }
2152
2153 /**
2154  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2155  * @mtd: MTD device structure
2156  * @to: offset to write to
2157  * @ops: oob operation description structure
2158  */
2159 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2160                           struct mtd_oob_ops *ops)
2161 {
2162         struct nand_chip *chip = mtd->priv;
2163         int ret = -ENOTSUPP;
2164
2165         ops->retlen = 0;
2166
2167         /* Do not allow writes past end of device */
2168         if (ops->datbuf && (to + ops->len) > mtd->size) {
2169                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2170                                 "end of device\n", __func__);
2171                 return -EINVAL;
2172         }
2173
2174         nand_get_device(chip, mtd, FL_WRITING);
2175
2176         switch (ops->mode) {
2177         case MTD_OPS_PLACE_OOB:
2178         case MTD_OPS_AUTO_OOB:
2179         case MTD_OPS_RAW:
2180                 break;
2181
2182         default:
2183                 goto out;
2184         }
2185
2186         if (!ops->datbuf)
2187                 ret = nand_do_write_oob(mtd, to, ops);
2188         else
2189                 ret = nand_do_write_ops(mtd, to, ops);
2190
2191 out:
2192         nand_release_device(mtd);
2193         return ret;
2194 }
2195
2196 /**
2197  * single_erase_cmd - [GENERIC] NAND standard block erase command function
2198  * @mtd: MTD device structure
2199  * @page: the page address of the block which will be erased
2200  *
2201  * Standard erase command for NAND chips.
2202  */
2203 static void single_erase_cmd(struct mtd_info *mtd, int page)
2204 {
2205         struct nand_chip *chip = mtd->priv;
2206         /* Send commands to erase a block */
2207         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2208         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2209 }
2210
2211 /**
2212  * multi_erase_cmd - [GENERIC] AND specific block erase command function
2213  * @mtd: MTD device structure
2214  * @page: the page address of the block which will be erased
2215  *
2216  * AND multi block erase command function. Erase 4 consecutive blocks.
2217  */
2218 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2219 {
2220         struct nand_chip *chip = mtd->priv;
2221         /* Send commands to erase a block */
2222         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2223         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2224         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2225         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2226         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2227 }
2228
2229 /**
2230  * nand_erase - [MTD Interface] erase block(s)
2231  * @mtd: MTD device structure
2232  * @instr: erase instruction
2233  *
2234  * Erase one ore more blocks.
2235  */
2236 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2237 {
2238         return nand_erase_nand(mtd, instr, 0);
2239 }
2240
2241 #define BBT_PAGE_MASK   0xffffff3f
2242 /**
2243  * nand_erase_nand - [INTERN] erase block(s)
2244  * @mtd: MTD device structure
2245  * @instr: erase instruction
2246  * @allowbbt: allow erasing the bbt area
2247  *
2248  * Erase one ore more blocks.
2249  */
2250 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2251                     int allowbbt)
2252 {
2253         int page, status, pages_per_block, ret, chipnr;
2254         struct nand_chip *chip = mtd->priv;
2255         loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2256         unsigned int bbt_masked_page = 0xffffffff;
2257         loff_t len;
2258
2259         MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2260                                 __func__, (unsigned long long)instr->addr,
2261                                 (unsigned long long)instr->len);
2262
2263         if (check_offs_len(mtd, instr->addr, instr->len))
2264                 return -EINVAL;
2265
2266         /* Grab the lock and see if the device is available */
2267         nand_get_device(chip, mtd, FL_ERASING);
2268
2269         /* Shift to get first page */
2270         page = (int)(instr->addr >> chip->page_shift);
2271         chipnr = (int)(instr->addr >> chip->chip_shift);
2272
2273         /* Calculate pages in each block */
2274         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2275
2276         /* Select the NAND device */
2277         chip->select_chip(mtd, chipnr);
2278
2279         /* Check, if it is write protected */
2280         if (nand_check_wp(mtd)) {
2281                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2282                                         __func__);
2283                 instr->state = MTD_ERASE_FAILED;
2284                 goto erase_exit;
2285         }
2286
2287         /*
2288          * If BBT requires refresh, set the BBT page mask to see if the BBT
2289          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2290          * can not be matched. This is also done when the bbt is actually
2291          * erased to avoid recursive updates.
2292          */
2293         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2294                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2295
2296         /* Loop through the pages */
2297         len = instr->len;
2298
2299         instr->state = MTD_ERASING;
2300
2301         while (len) {
2302                 WATCHDOG_RESET();
2303                 /* Check if we have a bad block, we do not erase bad blocks! */
2304                 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2305                                         chip->page_shift, 0, allowbbt)) {
2306                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2307                                    __func__, page);
2308                         instr->state = MTD_ERASE_FAILED;
2309                         goto erase_exit;
2310                 }
2311
2312                 /*
2313                  * Invalidate the page cache, if we erase the block which
2314                  * contains the current cached page.
2315                  */
2316                 if (page <= chip->pagebuf && chip->pagebuf <
2317                     (page + pages_per_block))
2318                         chip->pagebuf = -1;
2319
2320                 chip->erase_cmd(mtd, page & chip->pagemask);
2321
2322                 status = chip->waitfunc(mtd, chip);
2323
2324                 /*
2325                  * See if operation failed and additional status checks are
2326                  * available
2327                  */
2328                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2329                         status = chip->errstat(mtd, chip, FL_ERASING,
2330                                                status, page);
2331
2332                 /* See if block erase succeeded */
2333                 if (status & NAND_STATUS_FAIL) {
2334                         MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2335                                         "page 0x%08x\n", __func__, page);
2336                         instr->state = MTD_ERASE_FAILED;
2337                         instr->fail_addr =
2338                                 ((loff_t)page << chip->page_shift);
2339                         goto erase_exit;
2340                 }
2341
2342                 /*
2343                  * If BBT requires refresh, set the BBT rewrite flag to the
2344                  * page being erased.
2345                  */
2346                 if (bbt_masked_page != 0xffffffff &&
2347                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2348                         rewrite_bbt[chipnr] =
2349                                 ((loff_t)page << chip->page_shift);
2350
2351                 /* Increment page address and decrement length */
2352                 len -= (1 << chip->phys_erase_shift);
2353                 page += pages_per_block;
2354
2355                 /* Check, if we cross a chip boundary */
2356                 if (len && !(page & chip->pagemask)) {
2357                         chipnr++;
2358                         chip->select_chip(mtd, -1);
2359                         chip->select_chip(mtd, chipnr);
2360
2361                         /*
2362                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2363                          * page mask to see if this BBT should be rewritten.
2364                          */
2365                         if (bbt_masked_page != 0xffffffff &&
2366                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2367                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2368                                         BBT_PAGE_MASK;
2369                 }
2370         }
2371         instr->state = MTD_ERASE_DONE;
2372
2373 erase_exit:
2374
2375         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2376
2377         /* Deselect and wake up anyone waiting on the device */
2378         nand_release_device(mtd);
2379
2380         /* Do call back function */
2381         if (!ret)
2382                 mtd_erase_callback(instr);
2383
2384         /*
2385          * If BBT requires refresh and erase was successful, rewrite any
2386          * selected bad block tables.
2387          */
2388         if (bbt_masked_page == 0xffffffff || ret)
2389                 return ret;
2390
2391         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2392                 if (!rewrite_bbt[chipnr])
2393                         continue;
2394                 /* Update the BBT for chip */
2395                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2396                         "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2397                         rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2398                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2399         }
2400
2401         /* Return more or less happy */
2402         return ret;
2403 }
2404
2405 /**
2406  * nand_sync - [MTD Interface] sync
2407  * @mtd: MTD device structure
2408  *
2409  * Sync is actually a wait for chip ready function.
2410  */
2411 static void nand_sync(struct mtd_info *mtd)
2412 {
2413         struct nand_chip *chip = mtd->priv;
2414
2415         MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2416
2417         /* Grab the lock and see if the device is available */
2418         nand_get_device(chip, mtd, FL_SYNCING);
2419         /* Release it and go back */
2420         nand_release_device(mtd);
2421 }
2422
2423 /**
2424  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2425  * @mtd: MTD device structure
2426  * @offs: offset relative to mtd start
2427  */
2428 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2429 {
2430         return nand_block_checkbad(mtd, offs, 1, 0);
2431 }
2432
2433 /**
2434  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2435  * @mtd: MTD device structure
2436  * @ofs: offset relative to mtd start
2437  */
2438 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2439 {
2440         struct nand_chip *chip = mtd->priv;
2441         int ret;
2442
2443         ret = nand_block_isbad(mtd, ofs);
2444         if (ret) {
2445                 /* If it was bad already, return success and do nothing */
2446                 if (ret > 0)
2447                         return 0;
2448                 return ret;
2449         }
2450
2451         return chip->block_markbad(mtd, ofs);
2452 }
2453
2454  /**
2455  * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2456  * @mtd: MTD device structure
2457  * @chip: nand chip info structure
2458  * @addr: feature address.
2459  * @subfeature_param: the subfeature parameters, a four bytes array.
2460  */
2461 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2462                         int addr, uint8_t *subfeature_param)
2463 {
2464         int status;
2465
2466         if (!chip->onfi_version)
2467                 return -EINVAL;
2468
2469         chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2470         chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2471         status = chip->waitfunc(mtd, chip);
2472         if (status & NAND_STATUS_FAIL)
2473                 return -EIO;
2474         return 0;
2475 }
2476
2477 /**
2478  * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2479  * @mtd: MTD device structure
2480  * @chip: nand chip info structure
2481  * @addr: feature address.
2482  * @subfeature_param: the subfeature parameters, a four bytes array.
2483  */
2484 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2485                         int addr, uint8_t *subfeature_param)
2486 {
2487         if (!chip->onfi_version)
2488                 return -EINVAL;
2489
2490         /* clear the sub feature parameters */
2491         memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2492
2493         chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2494         chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2495         return 0;
2496 }
2497
2498 /* Set default functions */
2499 static void nand_set_defaults(struct nand_chip *chip, int busw)
2500 {
2501         /* check for proper chip_delay setup, set 20us if not */
2502         if (!chip->chip_delay)
2503                 chip->chip_delay = 20;
2504
2505         /* check, if a user supplied command function given */
2506         if (chip->cmdfunc == NULL)
2507                 chip->cmdfunc = nand_command;
2508
2509         /* check, if a user supplied wait function given */
2510         if (chip->waitfunc == NULL)
2511                 chip->waitfunc = nand_wait;
2512
2513         if (!chip->select_chip)
2514                 chip->select_chip = nand_select_chip;
2515         if (!chip->read_byte)
2516                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2517         if (!chip->read_word)
2518                 chip->read_word = nand_read_word;
2519         if (!chip->block_bad)
2520                 chip->block_bad = nand_block_bad;
2521         if (!chip->block_markbad)
2522                 chip->block_markbad = nand_default_block_markbad;
2523         if (!chip->write_buf)
2524                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2525         if (!chip->read_buf)
2526                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2527         if (!chip->verify_buf)
2528                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2529         if (!chip->scan_bbt)
2530                 chip->scan_bbt = nand_default_bbt;
2531         if (!chip->controller)
2532                 chip->controller = &chip->hwcontrol;
2533 }
2534
2535 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2536 /* Sanitize ONFI strings so we can safely print them */
2537 static void sanitize_string(char *s, size_t len)
2538 {
2539         ssize_t i;
2540
2541         /* Null terminate */
2542         s[len - 1] = 0;
2543
2544         /* Remove non printable chars */
2545         for (i = 0; i < len - 1; i++) {
2546                 if (s[i] < ' ' || s[i] > 127)
2547                         s[i] = '?';
2548         }
2549
2550         /* Remove trailing spaces */
2551         strim(s);
2552 }
2553
2554 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2555 {
2556         int i;
2557         while (len--) {
2558                 crc ^= *p++ << 8;
2559                 for (i = 0; i < 8; i++)
2560                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2561         }
2562
2563         return crc;
2564 }
2565
2566 /*
2567  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2568  */
2569 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2570                                         int *busw)
2571 {
2572         struct nand_onfi_params *p = &chip->onfi_params;
2573         int i;
2574         int val;
2575
2576         /* Try ONFI for unknown chip or LP */
2577         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2578         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2579                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2580                 return 0;
2581
2582         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2583         for (i = 0; i < 3; i++) {
2584                 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2585                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2586                                 le16_to_cpu(p->crc)) {
2587                         pr_info("ONFI param page %d valid\n", i);
2588                         break;
2589                 }
2590         }
2591
2592         if (i == 3)
2593                 return 0;
2594
2595         /* Check version */
2596         val = le16_to_cpu(p->revision);
2597         if (val & (1 << 5))
2598                 chip->onfi_version = 23;
2599         else if (val & (1 << 4))
2600                 chip->onfi_version = 22;
2601         else if (val & (1 << 3))
2602                 chip->onfi_version = 21;
2603         else if (val & (1 << 2))
2604                 chip->onfi_version = 20;
2605         else if (val & (1 << 1))
2606                 chip->onfi_version = 10;
2607         else
2608                 chip->onfi_version = 0;
2609
2610         if (!chip->onfi_version) {
2611                 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2612                 return 0;
2613         }
2614
2615         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2616         sanitize_string(p->model, sizeof(p->model));
2617         if (!mtd->name)
2618                 mtd->name = p->model;
2619         mtd->writesize = le32_to_cpu(p->byte_per_page);
2620         mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2621         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2622         chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2623         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2624         *busw = 0;
2625         if (le16_to_cpu(p->features) & 1)
2626                 *busw = NAND_BUSWIDTH_16;
2627
2628         pr_info("ONFI flash detected\n");
2629         return 1;
2630 }
2631 #else
2632 static inline int nand_flash_detect_onfi(struct mtd_info *mtd,
2633                                         struct nand_chip *chip,
2634                                         int *busw)
2635 {
2636         return 0;
2637 }
2638 #endif
2639
2640 /*
2641  * nand_id_has_period - Check if an ID string has a given wraparound period
2642  * @id_data: the ID string
2643  * @arrlen: the length of the @id_data array
2644  * @period: the period of repitition
2645  *
2646  * Check if an ID string is repeated within a given sequence of bytes at
2647  * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
2648  * period of 2). This is a helper function for nand_id_len(). Returns non-zero
2649  * if the repetition has a period of @period; otherwise, returns zero.
2650  */
2651 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
2652 {
2653         int i, j;
2654         for (i = 0; i < period; i++)
2655                 for (j = i + period; j < arrlen; j += period)
2656                         if (id_data[i] != id_data[j])
2657                                 return 0;
2658         return 1;
2659 }
2660
2661 /*
2662  * nand_id_len - Get the length of an ID string returned by CMD_READID
2663  * @id_data: the ID string
2664  * @arrlen: the length of the @id_data array
2665
2666  * Returns the length of the ID string, according to known wraparound/trailing
2667  * zero patterns. If no pattern exists, returns the length of the array.
2668  */
2669 static int nand_id_len(u8 *id_data, int arrlen)
2670 {
2671         int last_nonzero, period;
2672
2673         /* Find last non-zero byte */
2674         for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
2675                 if (id_data[last_nonzero])
2676                         break;
2677
2678         /* All zeros */
2679         if (last_nonzero < 0)
2680                 return 0;
2681
2682         /* Calculate wraparound period */
2683         for (period = 1; period < arrlen; period++)
2684                 if (nand_id_has_period(id_data, arrlen, period))
2685                         break;
2686
2687         /* There's a repeated pattern */
2688         if (period < arrlen)
2689                 return period;
2690
2691         /* There are trailing zeros */
2692         if (last_nonzero < arrlen - 1)
2693                 return last_nonzero + 1;
2694
2695         /* No pattern detected */
2696         return arrlen;
2697 }
2698
2699 /*
2700  * Many new NAND share similar device ID codes, which represent the size of the
2701  * chip. The rest of the parameters must be decoded according to generic or
2702  * manufacturer-specific "extended ID" decoding patterns.
2703  */
2704 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
2705                                 u8 id_data[8], int *busw)
2706 {
2707         int extid, id_len;
2708         /* The 3rd id byte holds MLC / multichip data */
2709         chip->cellinfo = id_data[2];
2710         /* The 4th id byte is the important one */
2711         extid = id_data[3];
2712
2713         id_len = nand_id_len(id_data, 8);
2714
2715         /*
2716          * Field definitions are in the following datasheets:
2717          * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2718          * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
2719          * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
2720          *
2721          * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
2722          * ID to decide what to do.
2723          */
2724         if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
2725                         (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2726                         id_data[5] != 0x00) {
2727                 /* Calc pagesize */
2728                 mtd->writesize = 2048 << (extid & 0x03);
2729                 extid >>= 2;
2730                 /* Calc oobsize */
2731                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
2732                 case 1:
2733                         mtd->oobsize = 128;
2734                         break;
2735                 case 2:
2736                         mtd->oobsize = 218;
2737                         break;
2738                 case 3:
2739                         mtd->oobsize = 400;
2740                         break;
2741                 case 4:
2742                         mtd->oobsize = 436;
2743                         break;
2744                 case 5:
2745                         mtd->oobsize = 512;
2746                         break;
2747                 case 6:
2748                 default: /* Other cases are "reserved" (unknown) */
2749                         mtd->oobsize = 640;
2750                         break;
2751                 }
2752                 extid >>= 2;
2753                 /* Calc blocksize */
2754                 mtd->erasesize = (128 * 1024) <<
2755                         (((extid >> 1) & 0x04) | (extid & 0x03));
2756                 *busw = 0;
2757         } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
2758                         (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2759                 unsigned int tmp;
2760
2761                 /* Calc pagesize */
2762                 mtd->writesize = 2048 << (extid & 0x03);
2763                 extid >>= 2;
2764                 /* Calc oobsize */
2765                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
2766                 case 0:
2767                         mtd->oobsize = 128;
2768                         break;
2769                 case 1:
2770                         mtd->oobsize = 224;
2771                         break;
2772                 case 2:
2773                         mtd->oobsize = 448;
2774                         break;
2775                 case 3:
2776                         mtd->oobsize = 64;
2777                         break;
2778                 case 4:
2779                         mtd->oobsize = 32;
2780                         break;
2781                 case 5:
2782                         mtd->oobsize = 16;
2783                         break;
2784                 default:
2785                         mtd->oobsize = 640;
2786                         break;
2787                 }
2788                 extid >>= 2;
2789                 /* Calc blocksize */
2790                 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
2791                 if (tmp < 0x03)
2792                         mtd->erasesize = (128 * 1024) << tmp;
2793                 else if (tmp == 0x03)
2794                         mtd->erasesize = 768 * 1024;
2795                 else
2796                         mtd->erasesize = (64 * 1024) << tmp;
2797                 *busw = 0;
2798         } else {
2799                 /* Calc pagesize */
2800                 mtd->writesize = 1024 << (extid & 0x03);
2801                 extid >>= 2;
2802                 /* Calc oobsize */
2803                 mtd->oobsize = (8 << (extid & 0x01)) *
2804                         (mtd->writesize >> 9);
2805                 extid >>= 2;
2806                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2807                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2808                 extid >>= 2;
2809                 /* Get buswidth information */
2810                 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2811         }
2812 }
2813
2814  /*
2815  * Old devices have chip data hardcoded in the device ID table. nand_decode_id
2816  * decodes a matching ID table entry and assigns the MTD size parameters for
2817  * the chip.
2818  */
2819 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
2820                                 const struct nand_flash_dev *type, u8 id_data[8],
2821                                 int *busw)
2822 {
2823         int maf_id = id_data[0];
2824
2825         mtd->erasesize = type->erasesize;
2826         mtd->writesize = type->pagesize;
2827         mtd->oobsize = mtd->writesize / 32;
2828         *busw = type->options & NAND_BUSWIDTH_16;
2829
2830         /*
2831          * Check for Spansion/AMD ID + repeating 5th, 6th byte since
2832          * some Spansion chips have erasesize that conflicts with size
2833          * listed in nand_ids table.
2834          * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
2835          */
2836         if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
2837                         && id_data[6] == 0x00 && id_data[7] == 0x00
2838                         && mtd->writesize == 512) {
2839                 mtd->erasesize = 128 * 1024;
2840                 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
2841         }
2842 }
2843
2844  /*
2845  * Set the bad block marker/indicator (BBM/BBI) patterns according to some
2846  * heuristic patterns using various detected parameters (e.g., manufacturer,
2847  * page size, cell-type information).
2848  */
2849 static void nand_decode_bbm_options(struct mtd_info *mtd,
2850                                     struct nand_chip *chip, u8 id_data[8])
2851 {
2852         int maf_id = id_data[0];
2853
2854         /* Set the bad block position */
2855         if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
2856                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
2857         else
2858                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
2859
2860         /*
2861          * Bad block marker is stored in the last page of each block on Samsung
2862          * and Hynix MLC devices; stored in first two pages of each block on
2863          * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
2864          * AMD/Spansion, and Macronix.  All others scan only the first page.
2865          */
2866         if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2867                         (maf_id == NAND_MFR_SAMSUNG ||
2868                          maf_id == NAND_MFR_HYNIX))
2869                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
2870         else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2871                                 (maf_id == NAND_MFR_SAMSUNG ||
2872                                  maf_id == NAND_MFR_HYNIX ||
2873                                  maf_id == NAND_MFR_TOSHIBA ||
2874                                  maf_id == NAND_MFR_AMD ||
2875                                  maf_id == NAND_MFR_MACRONIX)) ||
2876                         (mtd->writesize == 2048 &&
2877                          maf_id == NAND_MFR_MICRON))
2878                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
2879 }
2880
2881 /*
2882  * Get the flash and manufacturer id and lookup if the type is supported.
2883  */
2884 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2885                                                   struct nand_chip *chip,
2886                                                   int busw,
2887                                                   int *maf_id, int *dev_id,
2888                                                   const struct nand_flash_dev *type)
2889 {
2890         const char *name;
2891         int i, maf_idx;
2892         u8 id_data[8];
2893
2894         /* Select the device */
2895         chip->select_chip(mtd, 0);
2896
2897         /*
2898          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2899          * after power-up.
2900          */
2901         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2902
2903         /* Send the command for reading device ID */
2904         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2905
2906         /* Read manufacturer and device IDs */
2907         *maf_id = chip->read_byte(mtd);
2908         *dev_id = chip->read_byte(mtd);
2909
2910         /*
2911          * Try again to make sure, as some systems the bus-hold or other
2912          * interface concerns can cause random data which looks like a
2913          * possibly credible NAND flash to appear. If the two results do
2914          * not match, ignore the device completely.
2915          */
2916
2917         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2918
2919         /* Read entire ID string */
2920         for (i = 0; i < 8; i++)
2921                 id_data[i] = chip->read_byte(mtd);
2922
2923         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2924                 pr_info("%s: second ID read did not match "
2925                         "%02x,%02x against %02x,%02x\n", __func__,
2926                         *maf_id, *dev_id, id_data[0], id_data[1]);
2927                 return ERR_PTR(-ENODEV);
2928         }
2929
2930         if (!type)
2931                 type = nand_flash_ids;
2932
2933         for (; type->name != NULL; type++)
2934                 if (*dev_id == type->id)
2935                         break;
2936
2937         chip->onfi_version = 0;
2938         if (!type->name || !type->pagesize) {
2939                 /* Check is chip is ONFI compliant */
2940                 if (nand_flash_detect_onfi(mtd, chip, &busw))
2941                         goto ident_done;
2942         }
2943
2944         if (!type->name)
2945                 return ERR_PTR(-ENODEV);
2946
2947         if (!mtd->name)
2948                 mtd->name = type->name;
2949
2950         chip->chipsize = (uint64_t)type->chipsize << 20;
2951
2952         if (!type->pagesize && chip->init_size) {
2953                 /* Set the pagesize, oobsize, erasesize by the driver */
2954                 busw = chip->init_size(mtd, chip, id_data);
2955         } else if (!type->pagesize) {
2956                 /* Decode parameters from extended ID */
2957                 nand_decode_ext_id(mtd, chip, id_data, &busw);
2958         } else {
2959                 nand_decode_id(mtd, chip, type, id_data, &busw);
2960         }
2961         /* Get chip options, preserve non chip based options */
2962         chip->options |= type->options;
2963
2964         /*
2965          * Check if chip is not a Samsung device. Do not clear the
2966          * options for chips which do not have an extended id.
2967          */
2968         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2969                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2970 ident_done:
2971
2972         /* Try to identify manufacturer */
2973         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2974                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2975                         break;
2976         }
2977
2978         /*
2979          * Check, if buswidth is correct. Hardware drivers should set
2980          * chip correct!
2981          */
2982         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2983                 pr_info("NAND device: Manufacturer ID:"
2984                         " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2985                         *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2986                 pr_warn("NAND bus width %d instead %d bit\n",
2987                            (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2988                            busw ? 16 : 8);
2989                 return ERR_PTR(-EINVAL);
2990         }
2991
2992         nand_decode_bbm_options(mtd, chip, id_data);
2993
2994         /* Calculate the address shift from the page size */
2995         chip->page_shift = ffs(mtd->writesize) - 1;
2996         /* Convert chipsize to number of pages per chip -1 */
2997         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2998
2999         chip->bbt_erase_shift = chip->phys_erase_shift =
3000                 ffs(mtd->erasesize) - 1;
3001         if (chip->chipsize & 0xffffffff)
3002                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3003         else {
3004                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3005                 chip->chip_shift += 32 - 1;
3006         }
3007
3008         chip->badblockbits = 8;
3009
3010         /* Check for AND chips with 4 page planes */
3011         if (chip->options & NAND_4PAGE_ARRAY)
3012                 chip->erase_cmd = multi_erase_cmd;
3013         else
3014                 chip->erase_cmd = single_erase_cmd;
3015
3016         /* Do not replace user supplied command function! */
3017         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3018                 chip->cmdfunc = nand_command_lp;
3019
3020         name = type->name;
3021 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3022         if (chip->onfi_version)
3023                 name = chip->onfi_params.model;
3024 #endif
3025         pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3026                 " page size: %d, OOB size: %d\n",
3027                 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3028                 name,
3029                 mtd->writesize, mtd->oobsize);
3030
3031         return type;
3032 }
3033
3034 /**
3035  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3036  * @mtd: MTD device structure
3037  * @maxchips: number of chips to scan for
3038  * @table: alternative NAND ID table
3039  *
3040  * This is the first phase of the normal nand_scan() function. It reads the
3041  * flash ID and sets up MTD fields accordingly.
3042  *
3043  * The mtd->owner field must be set to the module of the caller.
3044  */
3045 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3046                     const struct nand_flash_dev *table)
3047 {
3048         int i, busw, nand_maf_id, nand_dev_id;
3049         struct nand_chip *chip = mtd->priv;
3050         const struct nand_flash_dev *type;
3051
3052         /* Get buswidth to select the correct functions */
3053         busw = chip->options & NAND_BUSWIDTH_16;
3054         /* Set the default functions */
3055         nand_set_defaults(chip, busw);
3056
3057         /* Read the flash type */
3058         type = nand_get_flash_type(mtd, chip, busw,
3059                                 &nand_maf_id, &nand_dev_id, table);
3060
3061         if (IS_ERR(type)) {
3062 #ifndef CONFIG_SYS_NAND_QUIET_TEST
3063                 pr_warn("No NAND device found\n");
3064 #endif
3065                 chip->select_chip(mtd, -1);
3066                 return PTR_ERR(type);
3067         }
3068
3069         /* Check for a chip array */
3070         for (i = 1; i < maxchips; i++) {
3071                 chip->select_chip(mtd, i);
3072                 /* See comment in nand_get_flash_type for reset */
3073                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3074                 /* Send the command for reading device ID */
3075                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3076                 /* Read manufacturer and device IDs */
3077                 if (nand_maf_id != chip->read_byte(mtd) ||
3078                     nand_dev_id != chip->read_byte(mtd))
3079                         break;
3080         }
3081 #ifdef DEBUG
3082         if (i > 1)
3083                 pr_info("%d NAND chips detected\n", i);
3084 #endif
3085
3086         /* Store the number of chips and calc total size for mtd */
3087         chip->numchips = i;
3088         mtd->size = i * chip->chipsize;
3089
3090         return 0;
3091 }
3092
3093
3094 /**
3095  * nand_scan_tail - [NAND Interface] Scan for the NAND device
3096  * @mtd: MTD device structure
3097  *
3098  * This is the second phase of the normal nand_scan() function. It fills out
3099  * all the uninitialized function pointers with the defaults and scans for a
3100  * bad block table if appropriate.
3101  */
3102 int nand_scan_tail(struct mtd_info *mtd)
3103 {
3104         int i;
3105         struct nand_chip *chip = mtd->priv;
3106
3107         /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3108         BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3109                         !(chip->bbt_options & NAND_BBT_USE_FLASH));
3110
3111         if (!(chip->options & NAND_OWN_BUFFERS))
3112                 chip->buffers = memalign(ARCH_DMA_MINALIGN,
3113                                          sizeof(*chip->buffers));
3114         if (!chip->buffers)
3115                 return chip->options & NAND_OWN_BUFFERS ? -EINVAL : -ENOMEM;
3116
3117         /* Set the internal oob buffer location, just after the page data */
3118         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3119
3120         /*
3121          * If no default placement scheme is given, select an appropriate one.
3122          */
3123         if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3124                 switch (mtd->oobsize) {
3125                 case 8:
3126                         chip->ecc.layout = &nand_oob_8;
3127                         break;
3128                 case 16:
3129                         chip->ecc.layout = &nand_oob_16;
3130                         break;
3131                 case 64:
3132                         chip->ecc.layout = &nand_oob_64;
3133                         break;
3134                 case 128:
3135                         chip->ecc.layout = &nand_oob_128;
3136                         break;
3137                 default:
3138                         pr_warn("No oob scheme defined for oobsize %d\n",
3139                                    mtd->oobsize);
3140                 }
3141         }
3142
3143         if (!chip->write_page)
3144                 chip->write_page = nand_write_page;
3145
3146         /* set for ONFI nand */
3147         if (!chip->onfi_set_features)
3148                 chip->onfi_set_features = nand_onfi_set_features;
3149         if (!chip->onfi_get_features)
3150                 chip->onfi_get_features = nand_onfi_get_features;
3151
3152         /*
3153          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3154          * selected and we have 256 byte pagesize fallback to software ECC
3155          */
3156
3157         switch (chip->ecc.mode) {
3158         case NAND_ECC_HW_OOB_FIRST:
3159                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3160                 if (!chip->ecc.calculate || !chip->ecc.correct ||
3161                      !chip->ecc.hwctl) {
3162                         pr_warn("No ECC functions supplied; "
3163                                    "hardware ECC not possible\n");
3164                         BUG();
3165                 }
3166                 if (!chip->ecc.read_page)
3167                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3168
3169         case NAND_ECC_HW:
3170                 /* Use standard hwecc read page function? */
3171                 if (!chip->ecc.read_page)
3172                         chip->ecc.read_page = nand_read_page_hwecc;
3173                 if (!chip->ecc.write_page)
3174                         chip->ecc.write_page = nand_write_page_hwecc;
3175                 if (!chip->ecc.read_page_raw)
3176                         chip->ecc.read_page_raw = nand_read_page_raw;
3177                 if (!chip->ecc.write_page_raw)
3178                         chip->ecc.write_page_raw = nand_write_page_raw;
3179                 if (!chip->ecc.read_oob)
3180                         chip->ecc.read_oob = nand_read_oob_std;
3181                 if (!chip->ecc.write_oob)
3182                         chip->ecc.write_oob = nand_write_oob_std;
3183
3184         case NAND_ECC_HW_SYNDROME:
3185                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3186                      !chip->ecc.hwctl) &&
3187                     (!chip->ecc.read_page ||
3188                      chip->ecc.read_page == nand_read_page_hwecc ||
3189                      !chip->ecc.write_page ||
3190                      chip->ecc.write_page == nand_write_page_hwecc)) {
3191                         pr_warn("No ECC functions supplied; "
3192                                    "hardware ECC not possible\n");
3193                         BUG();
3194                 }
3195                 /* Use standard syndrome read/write page function? */
3196                 if (!chip->ecc.read_page)
3197                         chip->ecc.read_page = nand_read_page_syndrome;
3198                 if (!chip->ecc.write_page)
3199                         chip->ecc.write_page = nand_write_page_syndrome;
3200                 if (!chip->ecc.read_page_raw)
3201                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3202                 if (!chip->ecc.write_page_raw)
3203                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3204                 if (!chip->ecc.read_oob)
3205                         chip->ecc.read_oob = nand_read_oob_syndrome;
3206                 if (!chip->ecc.write_oob)
3207                         chip->ecc.write_oob = nand_write_oob_syndrome;
3208
3209                 if (mtd->writesize >= chip->ecc.size) {
3210                         if (!chip->ecc.strength) {
3211                                 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3212                                 BUG();
3213                         }
3214                         break;
3215                 }
3216                 pr_warn("%d byte HW ECC not possible on "
3217                            "%d byte page size, fallback to SW ECC\n",
3218                            chip->ecc.size, mtd->writesize);
3219                 chip->ecc.mode = NAND_ECC_SOFT;
3220
3221         case NAND_ECC_SOFT:
3222                 chip->ecc.calculate = nand_calculate_ecc;
3223                 chip->ecc.correct = nand_correct_data;
3224                 chip->ecc.read_page = nand_read_page_swecc;
3225                 chip->ecc.read_subpage = nand_read_subpage;
3226                 chip->ecc.write_page = nand_write_page_swecc;
3227                 chip->ecc.read_page_raw = nand_read_page_raw;
3228                 chip->ecc.write_page_raw = nand_write_page_raw;
3229                 chip->ecc.read_oob = nand_read_oob_std;
3230                 chip->ecc.write_oob = nand_write_oob_std;
3231                 if (!chip->ecc.size)
3232                         chip->ecc.size = 256;
3233                 chip->ecc.bytes = 3;
3234                 chip->ecc.strength = 1;
3235                 break;
3236
3237         case NAND_ECC_SOFT_BCH:
3238                 if (!mtd_nand_has_bch()) {
3239                         pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3240                         return -EINVAL;
3241                 }
3242                 chip->ecc.calculate = nand_bch_calculate_ecc;
3243                 chip->ecc.correct = nand_bch_correct_data;
3244                 chip->ecc.read_page = nand_read_page_swecc;
3245                 chip->ecc.read_subpage = nand_read_subpage;
3246                 chip->ecc.write_page = nand_write_page_swecc;
3247                 chip->ecc.read_page_raw = nand_read_page_raw;
3248                 chip->ecc.write_page_raw = nand_write_page_raw;
3249                 chip->ecc.read_oob = nand_read_oob_std;
3250                 chip->ecc.write_oob = nand_write_oob_std;
3251                 /*
3252                  * Board driver should supply ecc.size and ecc.bytes values to
3253                  * select how many bits are correctable; see nand_bch_init()
3254                  * for details. Otherwise, default to 4 bits for large page
3255                  * devices.
3256                  */
3257                 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3258                         chip->ecc.size = 512;
3259                         chip->ecc.bytes = 7;
3260                 }
3261                 chip->ecc.priv = nand_bch_init(mtd,
3262                                                chip->ecc.size,
3263                                                chip->ecc.bytes,
3264                                                &chip->ecc.layout);
3265                 if (!chip->ecc.priv)
3266                         pr_warn("BCH ECC initialization failed!\n");
3267                 chip->ecc.strength =
3268                         chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
3269                 break;
3270
3271         case NAND_ECC_NONE:
3272                 pr_warn("NAND_ECC_NONE selected by board driver. "
3273                         "This is not recommended !!\n");
3274                 chip->ecc.read_page = nand_read_page_raw;
3275                 chip->ecc.write_page = nand_write_page_raw;
3276                 chip->ecc.read_oob = nand_read_oob_std;
3277                 chip->ecc.read_page_raw = nand_read_page_raw;
3278                 chip->ecc.write_page_raw = nand_write_page_raw;
3279                 chip->ecc.write_oob = nand_write_oob_std;
3280                 chip->ecc.size = mtd->writesize;
3281                 chip->ecc.bytes = 0;
3282                 break;
3283
3284         default:
3285                 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3286                 BUG();
3287         }
3288
3289         /* For many systems, the standard OOB write also works for raw */
3290         if (!chip->ecc.read_oob_raw)
3291                 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3292         if (!chip->ecc.write_oob_raw)
3293                 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3294
3295         /*
3296          * The number of bytes available for a client to place data into
3297          * the out of band area.
3298          */
3299         chip->ecc.layout->oobavail = 0;
3300         for (i = 0; chip->ecc.layout->oobfree[i].length
3301                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3302                 chip->ecc.layout->oobavail +=
3303                         chip->ecc.layout->oobfree[i].length;
3304         mtd->oobavail = chip->ecc.layout->oobavail;
3305
3306         /*
3307          * Set the number of read / write steps for one page depending on ECC
3308          * mode.
3309          */
3310         chip->ecc.steps = mtd->writesize / chip->ecc.size;
3311         if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3312                 pr_warn("Invalid ECC parameters\n");
3313                 pr_warn("steps=%d size=%d writesize=%d\n",
3314                         chip->ecc.steps, chip->ecc.size, mtd->writesize);
3315                 BUG();
3316         }
3317         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3318
3319         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3320         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3321             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3322                 switch (chip->ecc.steps) {
3323                 case 2:
3324                         mtd->subpage_sft = 1;
3325                         break;
3326                 case 4:
3327                 case 8:
3328                 case 16:
3329                         mtd->subpage_sft = 2;
3330                         break;
3331                 }
3332         }
3333         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3334
3335         /* Initialize state */
3336         chip->state = FL_READY;
3337
3338         /* De-select the device */
3339         chip->select_chip(mtd, -1);
3340
3341         /* Invalidate the pagebuffer reference */
3342         chip->pagebuf = -1;
3343
3344         /* Large page NAND with SOFT_ECC should support subpage reads */
3345         if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3346                 chip->options |= NAND_SUBPAGE_READ;
3347
3348         /* Fill in remaining MTD driver data */
3349         mtd->type = MTD_NANDFLASH;
3350         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3351                                                 MTD_CAP_NANDFLASH;
3352         mtd->_erase = nand_erase;
3353         mtd->_point = NULL;
3354         mtd->_unpoint = NULL;
3355         mtd->_read = nand_read;
3356         mtd->_write = nand_write;
3357         mtd->_read_oob = nand_read_oob;
3358         mtd->_write_oob = nand_write_oob;
3359         mtd->_sync = nand_sync;
3360         mtd->_lock = NULL;
3361         mtd->_unlock = NULL;
3362         mtd->_block_isbad = nand_block_isbad;
3363         mtd->_block_markbad = nand_block_markbad;
3364
3365         /* propagate ecc info to mtd_info */
3366         mtd->ecclayout = chip->ecc.layout;
3367         mtd->ecc_strength = chip->ecc.strength;
3368         /*
3369          * Initialize bitflip_threshold to its default prior scan_bbt() call.
3370          * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3371          * properly set.
3372          */
3373         if (!mtd->bitflip_threshold)
3374                 mtd->bitflip_threshold = mtd->ecc_strength;
3375
3376         /* Check, if we should skip the bad block table scan */
3377         if (chip->options & NAND_SKIP_BBTSCAN)
3378                 chip->options |= NAND_BBT_SCANNED;
3379
3380         return 0;
3381 }
3382
3383 /**
3384  * nand_scan - [NAND Interface] Scan for the NAND device
3385  * @mtd: MTD device structure
3386  * @maxchips: number of chips to scan for
3387  *
3388  * This fills out all the uninitialized function pointers with the defaults.
3389  * The flash ID is read and the mtd/chip structures are filled with the
3390  * appropriate values. The mtd->owner field must be set to the module of the
3391  * caller.
3392  */
3393 int nand_scan(struct mtd_info *mtd, int maxchips)
3394 {
3395         int ret;
3396
3397         ret = nand_scan_ident(mtd, maxchips, NULL);
3398         if (!ret)
3399                 ret = nand_scan_tail(mtd);
3400         return ret;
3401 }
3402
3403 /**
3404  * nand_release - [NAND Interface] Free resources held by the NAND device
3405  * @mtd: MTD device structure
3406  */
3407 void nand_release(struct mtd_info *mtd)
3408 {
3409         struct nand_chip *chip = mtd->priv;
3410
3411         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3412                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3413
3414 #ifdef CONFIG_MTD_PARTITIONS
3415         /* Deregister partitions */
3416         del_mtd_partitions(mtd);
3417 #endif
3418
3419         /* Free bad block table memory */
3420         kfree(chip->bbt);
3421         if (!(chip->options & NAND_OWN_BUFFERS))
3422                 kfree(chip->buffers);
3423
3424         /* Free bad block descriptor memory */
3425         if (chip->badblock_pattern && chip->badblock_pattern->options
3426                         & NAND_BBT_DYNAMICSTRUCT)
3427                 kfree(chip->badblock_pattern);
3428 }