2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
3 * Rohit Choraria <rohitkc@ti.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/mem.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/omap_gpmc.h>
14 #include <linux/mtd/nand_ecc.h>
15 #include <linux/bch.h>
16 #include <linux/compiler.h>
19 #include <asm/arch/elm.h>
23 static __maybe_unused struct nand_ecclayout hw_nand_oob =
24 GPMC_NAND_HW_ECC_LAYOUT;
25 static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob =
26 GPMC_NAND_HW_BCH8_ECC_LAYOUT;
28 static struct gpmc __iomem *gpmc_cfg = (void __iomem *)GPMC_BASE;
30 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
31 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
32 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
34 static struct nand_bbt_descr bbt_main_descr = {
35 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
36 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
37 .offs = 0, /* may be overwritten depending on ECC layout */
39 .veroffs = 4, /* may be overwritten depending on ECC layout */
41 .pattern = bbt_pattern,
44 static struct nand_bbt_descr bbt_mirror_descr = {
45 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
46 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
47 .offs = 0, /* may be overwritten depending on ECC layout */
49 .veroffs = 4, /* may be overwritten depending on ECC layout */
51 .pattern = mirror_pattern,
56 * omap_nand_hwcontrol - Set the address pointers corretly for the
57 * following address/data/command operation
59 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
62 register struct nand_chip *this = mtd->priv;
65 * Point the IO_ADDR to DATA and ADDRESS registers instead
69 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
70 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
72 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
73 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
75 case NAND_CTRL_CHANGE | NAND_NCE:
76 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
80 if (cmd != NAND_CMD_NONE)
81 writeb(cmd, this->IO_ADDR_W);
84 #ifdef CONFIG_SPL_BUILD
85 /* Check wait pin as dev ready indicator */
86 int omap_spl_dev_ready(struct mtd_info *mtd)
88 return readl(&gpmc_cfg->status) & (1 << 8);
93 * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
95 * @mtd: MTD device structure
98 static void __maybe_unused omap_hwecc_init(struct nand_chip *chip)
101 * Init ECC Control Register
102 * Clear all ECC | Enable Reg1
104 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
105 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
109 * gen_true_ecc - This function will generate true ECC value, which
110 * can be used when correcting data read from NAND flash memory core
112 * @ecc_buf: buffer to store ecc code
114 * @return: re-formatted ECC value
116 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
118 return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
119 ((ecc_buf[2] & 0x0F) << 8);
123 * omap_correct_data - Compares the ecc read from nand spare area with ECC
124 * registers values and corrects one bit error if it has occured
125 * Further details can be had from OMAP TRM and the following selected links:
126 * http://en.wikipedia.org/wiki/Hamming_code
127 * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
129 * @mtd: MTD device structure
131 * @read_ecc: ecc read from nand flash
132 * @calc_ecc: ecc read from ECC registers
134 * @return 0 if data is OK or corrected, else returns -1
136 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
137 uint8_t *read_ecc, uint8_t *calc_ecc)
139 uint32_t orig_ecc, new_ecc, res, hm;
140 uint16_t parity_bits, byte;
143 /* Regenerate the orginal ECC */
144 orig_ecc = gen_true_ecc(read_ecc);
145 new_ecc = gen_true_ecc(calc_ecc);
146 /* Get the XOR of real ecc */
147 res = orig_ecc ^ new_ecc;
149 /* Get the hamming width */
151 /* Single bit errors can be corrected! */
153 /* Correctable data! */
154 parity_bits = res >> 16;
155 bit = (parity_bits & 0x7);
156 byte = (parity_bits >> 3) & 0x1FF;
157 /* Flip the bit to correct */
158 dat[byte] ^= (0x1 << bit);
159 } else if (hm == 1) {
160 printf("Error: Ecc is wrong\n");
161 /* ECC itself is corrupted */
165 * hm distance != parity pairs OR one, could mean 2 bit
166 * error OR potentially be on a blank page..
167 * orig_ecc: contains spare area data from nand flash.
168 * new_ecc: generated ecc while reading data area.
169 * Note: if the ecc = 0, all data bits from which it was
170 * generated are 0xFF.
171 * The 3 byte(24 bits) ecc is generated per 512byte
172 * chunk of a page. If orig_ecc(from spare area)
173 * is 0xFF && new_ecc(computed now from data area)=0x0,
174 * this means that data area is 0xFF and spare area is
175 * 0xFF. A sure sign of a erased page!
177 if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
179 printf("Error: Bad compare! failed\n");
180 /* detected 2 bit error */
188 * omap_calculate_ecc - Generate non-inverted ECC bytes.
190 * Using noninverted ECC can be considered ugly since writing a blank
191 * page ie. padding will clear the ECC bytes. This is no problem as
192 * long nobody is trying to write data on the seemingly unused page.
193 * Reading an erased page will produce an ECC mismatch between
194 * generated and read ECC bytes that has to be dealt with separately.
195 * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
196 * is used, the result of read will be 0x0 while the ECC offsets of the
197 * spare area will be 0xFF which will result in an ECC mismatch.
198 * @mtd: MTD structure
200 * @ecc_code: ecc_code buffer
202 static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd,
203 const uint8_t *dat, uint8_t *ecc_code)
207 /* Start Reading from HW ECC1_Result = 0x200 */
208 val = readl(&gpmc_cfg->ecc1_result);
210 ecc_code[0] = val & 0xFF;
211 ecc_code[1] = (val >> 16) & 0xFF;
212 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
215 * Stop reading anymore ECC vals and clear old results
216 * enable will be called if more reads are required
218 writel(0x000, &gpmc_cfg->ecc_config);
224 * omap_enable_ecc - This function enables the hardware ecc functionality
225 * @mtd: MTD device structure
226 * @mode: Read/Write mode
228 static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
230 struct nand_chip *chip = mtd->priv;
231 uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
236 /* Clear the ecc result registers, select ecc reg as 1 */
237 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
240 * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
241 * tell all regs to generate size0 sized regs
242 * we just have a single ECC engine for all CS
244 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
245 &gpmc_cfg->ecc_size_config);
246 val = (dev_width << 7) | (cs << 1) | (1 << 0);
247 writel(val, &gpmc_cfg->ecc_config);
250 printf("Error: Unrecognized Mode[%d]!\n", mode);
255 * Generic BCH interface
257 struct nand_bch_priv {
261 struct bch_control *control;
269 /* GPMC ecc engine settings */
270 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
271 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
273 /* BCH nibbles for diff bch levels */
274 #define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1)
275 #define ECC_BCH4_NIBBLES 13
276 #define ECC_BCH8_NIBBLES 26
277 #define ECC_BCH16_NIBBLES 52
280 * This can be a single instance cause all current users have only one NAND
281 * with nearly the same setup (BCH8, some with ELM and others with sw BCH
283 * When some users with other BCH strength will exists this have to change!
285 static __maybe_unused struct nand_bch_priv bch_priv = {
286 .mode = NAND_ECC_HW_BCH,
288 .nibbles = ECC_BCH8_NIBBLES,
293 * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
295 * @mtd: MTD device structure
296 * @mode: Read/Write mode
299 static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
302 uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
304 uint32_t unused_length = 0;
306 uint32_t wr_mode = BCH_WRAPMODE_6;
307 struct nand_bch_priv *bch = chip->priv;
309 /* Clear the ecc result registers, select ecc reg as 1 */
310 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
313 wr_mode = BCH_WRAPMODE_1;
315 switch (bch->nibbles) {
316 case ECC_BCH4_NIBBLES:
319 case ECC_BCH8_NIBBLES:
322 case ECC_BCH16_NIBBLES:
328 * This is ecc_size_config for ELM mode.
329 * Here we are using different settings for read and write access and
330 * also depending on BCH strength.
334 /* write access only setup eccsize1 config */
335 val = ((unused_length + bch->nibbles) << 22);
341 * by default eccsize0 selected for ecc1resultsize
344 val = (bch->nibbles << 12);
345 /* eccsize1 config */
346 val |= (unused_length << 22);
351 * This ecc_size_config setting is for BCH sw library.
353 * Note: we only support BCH8 currently with BCH sw library!
354 * Should be really easy to adopt to BCH4, however some omap3 have
357 * Here we are using wrapping mode 6 both for reading and writing, with:
358 * size0 = 0 (no additional protected byte in spare area)
359 * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
361 val = (32 << 22) | (0 << 12);
363 /* ecc size configuration */
364 writel(val, &gpmc_cfg->ecc_size_config);
367 * Configure the ecc engine in gpmc
368 * We assume 512 Byte sector pages for access to NAND.
370 val = 1 << 16; /* select BCH mode */
371 val |= bch->type << 12; /* setup BCH type */
372 val |= wr_mode << 8; /* setup wrapping mode */
373 val |= dev_width << 7; /* setup device width (16 or 8 bit) */
374 val |= (chip->ecc.size / 512 - 1) << 4; /* set ECC size */
375 val |= cs << 1; /* setup chip select to work on */
376 val |= 1 << 0; /* enable ECC engine */
378 debug("set ECC_CONFIG=0x%08x\n", val);
379 writel(val, &gpmc_cfg->ecc_config);
383 * omap_enable_ecc_bch - This function enables the bch h/w ecc functionality
384 * @mtd: MTD device structure
385 * @mode: Read/Write mode
388 static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
390 struct nand_chip *chip = mtd->priv;
392 omap_hwecc_init_bch(chip, mode);
396 * omap_ecc_disable - Disable H/W ECC calculation
398 * @mtd: MTD device structure
400 static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd)
402 writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config);
406 * BCH8 support (needs ELM and thus AM33xx-only)
410 * omap_read_bch8_result - Read BCH result for BCH8 level
412 * @mtd: MTD device structure
413 * @big_endian: When set read register 3 first
414 * @ecc_code: Read syndrome from BCH result registers
416 static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian,
423 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
424 ecc_code[i++] = readl(ptr) & 0xFF;
426 for (j = 0; j < 3; j++) {
427 ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
428 ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
429 ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
430 ecc_code[i++] = readl(ptr) & 0xFF;
434 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
435 for (j = 0; j < 3; j++) {
436 ecc_code[i++] = readl(ptr) & 0xFF;
437 ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
438 ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
439 ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
442 ecc_code[i++] = readl(ptr) & 0xFF;
443 ecc_code[i++] = 0; /* 14th byte is always zero */
448 * omap_rotate_ecc_bch - Rotate the syndrome bytes
450 * @mtd: MTD device structure
451 * @calc_ecc: ECC read from ECC registers
452 * @syndrome: Rotated syndrome will be returned in this array
455 static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
458 struct nand_chip *chip = mtd->priv;
459 struct nand_bch_priv *bch = chip->priv;
478 for (i = 0, j = n_bytes - 1; i < n_bytes; i++, j--)
479 syndrome[i] = calc_ecc[j];
483 * omap_calculate_ecc_bch - Read BCH ECC result
485 * @mtd: MTD structure
487 * @ecc_code: ecc_code buffer
489 static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
492 struct nand_chip *chip = mtd->priv;
493 struct nand_bch_priv *bch = chip->priv;
494 uint8_t big_endian = 1;
497 if (bch->type == ECC_BCH8)
498 omap_read_bch8_result(mtd, big_endian, ecc_code);
499 else /* BCH4 and BCH16 currently not supported */
503 * Stop reading anymore ECC vals and clear old results
504 * enable will be called if more reads are required
506 omap_ecc_disable(mtd);
512 * omap_fix_errors_bch - Correct bch error in the data
514 * @mtd: MTD device structure
515 * @data: Data read from flash
516 * @error_count:Number of errors in data
517 * @error_loc: Locations of errors in the data
520 static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
521 uint32_t error_count, uint32_t *error_loc)
523 struct nand_chip *chip = mtd->priv;
524 struct nand_bch_priv *bch = chip->priv;
526 uint32_t error_byte_pos;
527 uint32_t error_bit_mask;
528 uint32_t last_bit = (bch->nibbles * 4) - 1;
530 /* Flip all bits as specified by the error location array. */
531 /* FOR( each found error location flip the bit ) */
532 for (count = 0; count < error_count; count++) {
533 if (error_loc[count] > last_bit) {
534 /* Remove the ECC spare bits from correction. */
535 error_loc[count] -= (last_bit + 1);
536 /* Offset bit in data region */
537 error_byte_pos = ((512 * 8) -
538 (error_loc[count]) - 1) / 8;
540 error_bit_mask = 0x1 << (error_loc[count] % 8);
541 /* Toggle the error bit to make the correction. */
542 data[error_byte_pos] ^= error_bit_mask;
548 * omap_correct_data_bch - Compares the ecc read from nand spare area
549 * with ECC registers values and corrects one bit error if it has occured
551 * @mtd: MTD device structure
553 * @read_ecc: ecc read from nand flash (ignored)
554 * @calc_ecc: ecc read from ECC registers
556 * @return 0 if data is OK or corrected, else returns -1
558 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
559 uint8_t *read_ecc, uint8_t *calc_ecc)
561 struct nand_chip *chip = mtd->priv;
562 struct nand_bch_priv *bch = chip->priv;
563 uint8_t syndrome[28];
564 uint32_t error_count = 0;
565 uint32_t error_loc[8];
566 uint32_t i, ecc_flag;
569 for (i = 0; i < chip->ecc.bytes; i++)
570 if (read_ecc[i] != 0xff)
577 elm_config((enum bch_level)(bch->type));
580 * while reading ECC result we read it in big endian.
581 * Hence while loading to ELM we have rotate to get the right endian.
583 omap_rotate_ecc_bch(mtd, calc_ecc, syndrome);
585 /* use elm module to check for errors */
586 if (elm_check_error(syndrome, bch->nibbles, &error_count,
588 printf("ECC: uncorrectable.\n");
592 /* correct bch error */
594 omap_fix_errors_bch(mtd, dat, error_count, error_loc);
600 * omap_read_page_bch - hardware ecc based page read function
601 * @mtd: mtd info structure
602 * @chip: nand chip info structure
603 * @buf: buffer to store read data
604 * @oob_required: caller expects OOB data read to chip->oob_poi
605 * @page: page number to read
608 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
609 uint8_t *buf, int oob_required, int page)
611 int i, eccsize = chip->ecc.size;
612 int eccbytes = chip->ecc.bytes;
613 int eccsteps = chip->ecc.steps;
615 uint8_t *ecc_calc = chip->buffers->ecccalc;
616 uint8_t *ecc_code = chip->buffers->ecccode;
617 uint32_t *eccpos = chip->ecc.layout->eccpos;
618 uint8_t *oob = &chip->oob_poi[eccpos[0]];
624 oob_pos = (eccsize * eccsteps) + eccpos[0];
626 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
628 chip->ecc.hwctl(mtd, NAND_ECC_READ);
630 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
631 chip->read_buf(mtd, p, eccsize);
633 /* read respective ecc from oob area */
634 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
635 chip->read_buf(mtd, oob, eccbytes);
637 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
643 for (i = 0; i < chip->ecc.total; i++)
644 ecc_code[i] = chip->oob_poi[eccpos[i]];
646 eccsteps = chip->ecc.steps;
649 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
652 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
654 mtd->ecc_stats.failed++;
656 mtd->ecc_stats.corrected += stat;
660 #endif /* CONFIG_AM33XX */
663 * OMAP3 BCH8 support (with BCH library)
665 #ifdef CONFIG_NAND_OMAP_BCH8
667 * omap_calculate_ecc_bch - Read BCH ECC result
669 * @mtd: MTD device structure
670 * @dat: The pointer to data on which ecc is computed (unused here)
671 * @ecc: The ECC output buffer
673 static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
678 unsigned long nsectors, val1, val2, val3, val4;
680 nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;
682 for (i = 0; i < nsectors; i++) {
683 /* Read hw-computed remainder */
684 val1 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[0]);
685 val2 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[1]);
686 val3 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[2]);
687 val4 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[3]);
690 * Add constant polynomial to remainder, in order to get an ecc
691 * sequence of 0xFFs for a buffer filled with 0xFFs.
693 *ecc++ = 0xef ^ (val4 & 0xFF);
694 *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
695 *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
696 *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
697 *ecc++ = 0xed ^ (val3 & 0xFF);
698 *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
699 *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
700 *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
701 *ecc++ = 0x97 ^ (val2 & 0xFF);
702 *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
703 *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
704 *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
705 *ecc++ = 0xb5 ^ (val1 & 0xFF);
709 * Stop reading anymore ECC vals and clear old results
710 * enable will be called if more reads are required
712 omap_ecc_disable(mtd);
718 * omap_correct_data_bch - Decode received data and correct errors
719 * @mtd: MTD device structure
721 * @read_ecc: ecc read from nand flash
722 * @calc_ecc: ecc read from HW ECC registers
724 static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data,
725 u_char *read_ecc, u_char *calc_ecc)
728 /* cannot correct more than 8 errors */
729 unsigned int errloc[8];
730 struct nand_chip *chip = mtd->priv;
731 struct nand_bch_priv *chip_priv = chip->priv;
732 struct bch_control *bch = chip_priv->control;
734 count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc);
737 for (i = 0; i < count; i++) {
738 /* correct data only, not ecc bytes */
739 if (errloc[i] < 8*512)
740 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
741 printf("corrected bitflip %u\n", errloc[i]);
743 printf("read_ecc: ");
745 * BCH8 have 13 bytes of ECC; BCH4 needs adoption
748 for (i = 0; i < 13; i++)
749 printf("%02x ", read_ecc[i]);
751 printf("calc_ecc: ");
752 for (i = 0; i < 13; i++)
753 printf("%02x ", calc_ecc[i]);
757 } else if (count < 0) {
758 printf("ecc unrecoverable error\n");
764 * omap_free_bch - Release BCH ecc resources
765 * @mtd: MTD device structure
767 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
769 struct nand_chip *chip = mtd->priv;
770 struct nand_bch_priv *chip_priv = chip->priv;
771 struct bch_control *bch = NULL;
774 bch = chip_priv->control;
778 chip_priv->control = NULL;
781 #endif /* CONFIG_NAND_OMAP_BCH8 */
783 #ifndef CONFIG_SPL_BUILD
785 * omap_nand_switch_ecc - switch the ECC operation between different engines
786 * (h/w and s/w) and different algorithms (hamming and BCHx)
788 * @hardware - true if one of the HW engines should be used
789 * @eccstrength - the number of bits that could be corrected
790 * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
792 void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
794 struct nand_chip *nand;
795 struct mtd_info *mtd;
797 if (nand_curr_device < 0 ||
798 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
799 !nand_info[nand_curr_device].name) {
800 printf("Error: Can't switch ecc, no devices available\n");
804 mtd = &nand_info[nand_curr_device];
807 nand->options |= NAND_OWN_BUFFERS;
809 /* Reset ecc interface */
810 nand->ecc.mode = NAND_ECC_NONE;
811 nand->ecc.read_page = NULL;
812 nand->ecc.write_page = NULL;
813 nand->ecc.read_oob = NULL;
814 nand->ecc.write_oob = NULL;
815 nand->ecc.hwctl = NULL;
816 nand->ecc.correct = NULL;
817 nand->ecc.calculate = NULL;
818 nand->ecc.strength = eccstrength;
820 /* Setup the ecc configurations again */
822 if (eccstrength == 1) {
823 nand->ecc.mode = NAND_ECC_HW;
824 nand->ecc.layout = &hw_nand_oob;
825 nand->ecc.size = 512;
827 nand->ecc.hwctl = omap_enable_hwecc;
828 nand->ecc.correct = omap_correct_data;
829 nand->ecc.calculate = omap_calculate_ecc;
830 omap_hwecc_init(nand);
831 printf("1-bit hamming HW ECC selected\n");
833 #if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
834 else if (eccstrength == 8) {
835 nand->ecc.mode = NAND_ECC_HW;
836 nand->ecc.layout = &hw_bch8_nand_oob;
837 nand->ecc.size = 512;
839 nand->ecc.bytes = 14;
840 nand->ecc.read_page = omap_read_page_bch;
842 nand->ecc.bytes = 13;
844 nand->ecc.hwctl = omap_enable_ecc_bch;
845 nand->ecc.correct = omap_correct_data_bch;
846 nand->ecc.calculate = omap_calculate_ecc_bch;
847 omap_hwecc_init_bch(nand, NAND_ECC_READ);
848 printf("8-bit BCH HW ECC selected\n");
852 nand->ecc.mode = NAND_ECC_SOFT;
853 /* Use mtd default settings */
854 nand->ecc.layout = NULL;
856 printf("SW ECC selected\n");
859 /* Update NAND handling after ECC mode switch */
862 nand->options &= ~NAND_OWN_BUFFERS;
864 #endif /* CONFIG_SPL_BUILD */
867 * Board-specific NAND initialization. The following members of the
868 * argument are board-specific:
869 * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
870 * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
871 * - cmd_ctrl: hardwarespecific function for accesing control-lines
872 * - waitfunc: hardwarespecific function for accesing device ready/busy line
873 * - ecc.hwctl: function to enable (reset) hardware ecc generator
874 * - ecc.mode: mode of ecc, see defines
875 * - chip_delay: chip dependent delay for transfering data from array to
877 * - options: various chip options. They can partly be set to inform
878 * nand_scan about special functionality. See the defines for further
881 int board_nand_init(struct nand_chip *nand)
883 int32_t gpmc_config = 0;
887 * xloader/Uboot's gpmc configuration would have configured GPMC for
888 * nand type of memory. The following logic scans and latches on to the
889 * first CS with NAND type memory.
890 * TBD: need to make this logic generic to handle multiple CS NAND
893 while (cs < GPMC_MAX_CS) {
894 /* Check if NAND type is set */
895 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
901 if (cs >= GPMC_MAX_CS) {
902 printf("NAND: Unable to find NAND settings in "
903 "GPMC Configuration - quitting\n");
907 gpmc_config = readl(&gpmc_cfg->config);
908 /* Disable Write protect */
910 writel(gpmc_config, &gpmc_cfg->config);
912 nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
913 nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
915 nand->cmd_ctrl = omap_nand_hwcontrol;
916 nand->options = NAND_NO_PADDING | NAND_CACHEPRG;
917 /* If we are 16 bit dev, our gpmc config tells us that */
918 if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
919 nand->options |= NAND_BUSWIDTH_16;
921 nand->chip_delay = 100;
923 #if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
925 /* AM33xx uses the ELM */
926 /* required in case of BCH */
930 * Whereas other OMAP based SoC do not have the ELM, they use the BCH
933 bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */);
934 if (!bch_priv.control) {
935 printf("Failed to initialize BCH engine\n");
939 /* BCH info that will be correct for SPL or overridden otherwise. */
940 nand->priv = &bch_priv;
943 /* Default ECC mode */
944 #if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
945 nand->ecc.mode = NAND_ECC_HW;
946 nand->ecc.layout = &hw_bch8_nand_oob;
947 nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
948 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
949 nand->ecc.strength = 8;
950 nand->ecc.hwctl = omap_enable_ecc_bch;
951 nand->ecc.correct = omap_correct_data_bch;
952 nand->ecc.calculate = omap_calculate_ecc_bch;
954 nand->ecc.read_page = omap_read_page_bch;
956 omap_hwecc_init_bch(nand, NAND_ECC_READ);
958 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
959 nand->ecc.mode = NAND_ECC_SOFT;
961 nand->ecc.mode = NAND_ECC_HW;
962 nand->ecc.layout = &hw_nand_oob;
963 nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
964 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
965 nand->ecc.hwctl = omap_enable_hwecc;
966 nand->ecc.correct = omap_correct_data;
967 nand->ecc.calculate = omap_calculate_ecc;
968 nand->ecc.strength = 1;
969 omap_hwecc_init(nand);
972 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
973 if (nand->ecc.layout) {
974 bbt_main_descr.offs = nand->ecc.layout->oobfree[0].offset;
975 bbt_main_descr.veroffs = bbt_main_descr.offs +
978 bbt_mirror_descr.offs = nand->ecc.layout->oobfree[0].offset;
979 bbt_mirror_descr.veroffs = bbt_mirror_descr.offs +
980 sizeof(mirror_pattern);
983 nand->bbt_options |= NAND_BBT_USE_FLASH;
984 nand->bbt_td = &bbt_main_descr;
985 nand->bbt_md = &bbt_mirror_descr;
988 #ifdef CONFIG_SPL_BUILD
989 if (nand->options & NAND_BUSWIDTH_16)
990 nand->read_buf = nand_read_buf16;
992 nand->read_buf = nand_read_buf;
993 nand->dev_ready = omap_spl_dev_ready;