drivers/net/davinci_emac.c

   1 /*
   2  * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
   3  *
   4  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   5  *
   6  * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
   7  * follows:
   8  *
   9  * ----------------------------------------------------------------------------
  10  *
  11  * dm644x_emac.c
  12  *
  13  * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
  14  *
  15  * Copyright (C) 2005 Texas Instruments.
  16  *
  17  * ----------------------------------------------------------------------------
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  *  You should have received a copy of the GNU General Public License
  30  *  along with this program; if not, write to the Free Software
  31  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  32  * ----------------------------------------------------------------------------
  33
  34  * Modifications:
  35  * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
  36  * ver  1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
  37  *
  38  */
  39 #include <common.h>
  40 #include <command.h>
  41 #include <net.h>
  42 #include <miiphy.h>
  43 #include <malloc.h>
  44 #include <asm/arch/emac_defs.h>
  45 #include <asm/io.h>
  46 #include "davinci_emac.h"
  47
  48 unsigned int    emac_dbg = 0;
  49 #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
  50
  51 #ifdef DAVINCI_EMAC_GIG_ENABLE
  52 #define emac_gigabit_enable(phy_addr)   davinci_eth_gigabit_enable(phy_addr)
  53 #else
  54 #define emac_gigabit_enable(phy_addr)   /* no gigabit to enable */
  55 #endif
  56
  57 #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
  58 #define CONFIG_SYS_EMAC_TI_CLKDIV       ((EMAC_MDIO_BUS_FREQ / \
  59                 EMAC_MDIO_CLOCK_FREQ) - 1)
  60 #endif
  61
  62 static void davinci_eth_mdio_enable(void);
  63
  64 static int gen_init_phy(int phy_addr);
  65 static int gen_is_phy_connected(int phy_addr);
  66 static int gen_get_link_speed(int phy_addr);
  67 static int gen_auto_negotiate(int phy_addr);
  68
  69 void eth_mdio_enable(void)
  70 {
  71         davinci_eth_mdio_enable();
  72 }
  73
  74 /* EMAC Addresses */
  75 static volatile emac_regs       *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
  76 static volatile ewrap_regs      *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
  77 static volatile mdio_regs       *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
  78
  79 /* EMAC descriptors */
  80 static volatile emac_desc       *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
  81 static volatile emac_desc       *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
  82 static volatile emac_desc       *emac_rx_active_head = 0;
  83 static volatile emac_desc       *emac_rx_active_tail = 0;
  84 static int                      emac_rx_queue_active = 0;
  85
  86 /* Receive packet buffers */
  87 static unsigned char            emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
  88
  89 #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
  90 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT       3
  91 #endif
  92
  93 /* PHY address for a discovered PHY (0xff - not found) */
  94 static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
  95
  96 /* number of PHY found active */
  97 static u_int8_t num_phy;
  98
  99 phy_t                           phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
 100
 101 static int davinci_eth_set_mac_addr(struct eth_device *dev)
 102 {
 103         unsigned long           mac_hi;
 104         unsigned long           mac_lo;
 105
 106         /*
 107          * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
 108          * receive)
 109          *  Using channel 0 only - other channels are disabled
 110          *  */
 111         writel(0, &adap_emac->MACINDEX);
 112         mac_hi = (dev->enetaddr[3] << 24) |
 113                  (dev->enetaddr[2] << 16) |
 114                  (dev->enetaddr[1] << 8)  |
 115                  (dev->enetaddr[0]);
 116         mac_lo = (dev->enetaddr[5] << 8) |
 117                  (dev->enetaddr[4]);
 118
 119         writel(mac_hi, &adap_emac->MACADDRHI);
 120 #if defined(DAVINCI_EMAC_VERSION2)
 121         writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
 122                &adap_emac->MACADDRLO);
 123 #else
 124         writel(mac_lo, &adap_emac->MACADDRLO);
 125 #endif
 126
 127         writel(0, &adap_emac->MACHASH1);
 128         writel(0, &adap_emac->MACHASH2);
 129
 130         /* Set source MAC address - REQUIRED */
 131         writel(mac_hi, &adap_emac->MACSRCADDRHI);
 132         writel(mac_lo, &adap_emac->MACSRCADDRLO);
 133
 134
 135         return 0;
 136 }
 137
 138 static void davinci_eth_mdio_enable(void)
 139 {
 140         u_int32_t       clkdiv;
 141
 142         clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
 143
 144         writel((clkdiv & 0xff) |
 145                MDIO_CONTROL_ENABLE |
 146                MDIO_CONTROL_FAULT |
 147                MDIO_CONTROL_FAULT_ENABLE,
 148                &adap_mdio->CONTROL);
 149
 150         while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
 151                 ;
 152 }
 153
 154 /*
 155  * Tries to find an active connected PHY. Returns 1 if address if found.
 156  * If no active PHY (or more than one PHY) found returns 0.
 157  * Sets active_phy_addr variable.
 158  */
 159 static int davinci_eth_phy_detect(void)
 160 {
 161         u_int32_t       phy_act_state;
 162         int             i;
 163         int             j;
 164         unsigned int    count = 0;
 165
 166         for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
 167                 active_phy_addr[i] = 0xff;
 168
 169         udelay(1000);
 170         phy_act_state = readl(&adap_mdio->ALIVE);
 171
 172         if (phy_act_state == 0)
 173                 return 0;               /* No active PHYs */
 174
 175         debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
 176
 177         for (i = 0, j = 0; i < 32; i++)
 178                 if (phy_act_state & (1 << i)) {
 179                         count++;
 180                         if (count < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
 181                                 active_phy_addr[j++] = i;
 182                         } else {
 183                                 printf("%s: to many PHYs detected.\n",
 184                                         __func__);
 185                                 count = 0;
 186                                 break;
 187                         }
 188                 }
 189
 190         num_phy = count;
 191
 192         return count;
 193 }
 194
 195
 196 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
 197 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
 198 {
 199         int     tmp;
 200
 201         while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
 202                 ;
 203
 204         writel(MDIO_USERACCESS0_GO |
 205                MDIO_USERACCESS0_WRITE_READ |
 206                ((reg_num & 0x1f) << 21) |
 207                ((phy_addr & 0x1f) << 16),
 208                &adap_mdio->USERACCESS0);
 209
 210         /* Wait for command to complete */
 211         while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
 212                 ;
 213
 214         if (tmp & MDIO_USERACCESS0_ACK) {
 215                 *data = tmp & 0xffff;
 216                 return(1);
 217         }
 218
 219         *data = -1;
 220         return(0);
 221 }
 222
 223 /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
 224 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
 225 {
 226
 227         while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
 228                 ;
 229
 230         writel(MDIO_USERACCESS0_GO |
 231                MDIO_USERACCESS0_WRITE_WRITE |
 232                ((reg_num & 0x1f) << 21) |
 233                ((phy_addr & 0x1f) << 16) |
 234                (data & 0xffff),
 235                &adap_mdio->USERACCESS0);
 236
 237         /* Wait for command to complete */
 238         while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
 239                 ;
 240
 241         return(1);
 242 }
 243
 244 /* PHY functions for a generic PHY */
 245 static int gen_init_phy(int phy_addr)
 246 {
 247         int     ret = 1;
 248
 249         if (gen_get_link_speed(phy_addr)) {
 250                 /* Try another time */
 251                 ret = gen_get_link_speed(phy_addr);
 252         }
 253
 254         return(ret);
 255 }
 256
 257 static int gen_is_phy_connected(int phy_addr)
 258 {
 259         u_int16_t       dummy;
 260
 261         return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
 262 }
 263
 264 static int get_active_phy(void)
 265 {
 266         int i;
 267
 268         for (i = 0; i < num_phy; i++)
 269                 if (phy[i].get_link_speed(active_phy_addr[i]))
 270                         return i;
 271
 272         return -1;      /* Return error if no link */
 273 }
 274
 275 static int gen_get_link_speed(int phy_addr)
 276 {
 277         u_int16_t       tmp;
 278
 279         if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
 280                         (tmp & 0x04)) {
 281 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 282                 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
 283                 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
 284
 285                 /* Speed doesn't matter, there is no setting for it in EMAC. */
 286                 if (tmp & (LPA_100FULL | LPA_10FULL)) {
 287                         /* set EMAC for Full Duplex  */
 288                         writel(EMAC_MACCONTROL_MIIEN_ENABLE |
 289                                         EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
 290                                         &adap_emac->MACCONTROL);
 291                 } else {
 292                         /*set EMAC for Half Duplex  */
 293                         writel(EMAC_MACCONTROL_MIIEN_ENABLE,
 294                                         &adap_emac->MACCONTROL);
 295                 }
 296
 297                 if (tmp & (LPA_100FULL | LPA_100HALF))
 298                         writel(readl(&adap_emac->MACCONTROL) |
 299                                         EMAC_MACCONTROL_RMIISPEED_100,
 300                                          &adap_emac->MACCONTROL);
 301                 else
 302                         writel(readl(&adap_emac->MACCONTROL) &
 303                                         ~EMAC_MACCONTROL_RMIISPEED_100,
 304                                          &adap_emac->MACCONTROL);
 305 #endif
 306                 return(1);
 307         }
 308
 309         return(0);
 310 }
 311
 312 static int gen_auto_negotiate(int phy_addr)
 313 {
 314         u_int16_t       tmp;
 315         u_int16_t       val;
 316         unsigned long   cntr = 0;
 317
 318         if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
 319                 return 0;
 320
 321         val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
 322                                                 BMCR_SPEED100;
 323         davinci_eth_phy_write(phy_addr, MII_BMCR, val);
 324
 325         if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
 326                 return 0;
 327
 328         val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
 329                                                         ADVERTISE_10HALF);
 330         davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
 331
 332         if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
 333                 return(0);
 334
 335         /* Restart Auto_negotiation  */
 336         tmp |= BMCR_ANRESTART;
 337         davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
 338
 339         /*check AutoNegotiate complete */
 340         do {
 341                 udelay(40000);
 342                 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
 343                         return 0;
 344
 345                 if (tmp & BMSR_ANEGCOMPLETE)
 346                         break;
 347
 348                 cntr++;
 349         } while (cntr < 200);
 350
 351         if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
 352                 return(0);
 353
 354         if (!(tmp & BMSR_ANEGCOMPLETE))
 355                 return(0);
 356
 357         return(gen_get_link_speed(phy_addr));
 358 }
 359 /* End of generic PHY functions */
 360
 361
 362 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 363 static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
 364 {
 365         return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1);
 366 }
 367
 368 static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value)
 369 {
 370         return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1);
 371 }
 372 #endif
 373
 374 static void  __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
 375 {
 376         u_int16_t data;
 377
 378         if (davinci_eth_phy_read(phy_addr, 0, &data)) {
 379                 if (data & (1 << 6)) { /* speed selection MSB */
 380                         /*
 381                          * Check if link detected is giga-bit
 382                          * If Gigabit mode detected, enable gigbit in MAC
 383                          */
 384                         writel(readl(&adap_emac->MACCONTROL) |
 385                                 EMAC_MACCONTROL_GIGFORCE |
 386                                 EMAC_MACCONTROL_GIGABIT_ENABLE,
 387                                 &adap_emac->MACCONTROL);
 388                 }
 389         }
 390 }
 391
 392 /* Eth device open */
 393 static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
 394 {
 395         dv_reg_p                addr;
 396         u_int32_t               clkdiv, cnt;
 397         volatile emac_desc      *rx_desc;
 398         int                     index;
 399
 400         debug_emac("+ emac_open\n");
 401
 402         /* Reset EMAC module and disable interrupts in wrapper */
 403         writel(1, &adap_emac->SOFTRESET);
 404         while (readl(&adap_emac->SOFTRESET) != 0)
 405                 ;
 406 #if defined(DAVINCI_EMAC_VERSION2)
 407         writel(1, &adap_ewrap->softrst);
 408         while (readl(&adap_ewrap->softrst) != 0)
 409                 ;
 410 #else
 411         writel(0, &adap_ewrap->EWCTL);
 412         for (cnt = 0; cnt < 5; cnt++) {
 413                 clkdiv = readl(&adap_ewrap->EWCTL);
 414         }
 415 #endif
 416
 417 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 418         defined(CONFIG_MACH_DAVINCI_DA850_EVM)
 419         adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
 420         adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
 421         adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
 422 #endif
 423         rx_desc = emac_rx_desc;
 424
 425         writel(1, &adap_emac->TXCONTROL);
 426         writel(1, &adap_emac->RXCONTROL);
 427
 428         davinci_eth_set_mac_addr(dev);
 429
 430         /* Set DMA 8 TX / 8 RX Head pointers to 0 */
 431         addr = &adap_emac->TX0HDP;
 432         for(cnt = 0; cnt < 16; cnt++)
 433                 writel(0, addr++);
 434
 435         addr = &adap_emac->RX0HDP;
 436         for(cnt = 0; cnt < 16; cnt++)
 437                 writel(0, addr++);
 438
 439         /* Clear Statistics (do this before setting MacControl register) */
 440         addr = &adap_emac->RXGOODFRAMES;
 441         for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
 442                 writel(0, addr++);
 443
 444         /* No multicast addressing */
 445         writel(0, &adap_emac->MACHASH1);
 446         writel(0, &adap_emac->MACHASH2);
 447
 448         /* Create RX queue and set receive process in place */
 449         emac_rx_active_head = emac_rx_desc;
 450         for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
 451                 rx_desc->next = (u_int32_t)(rx_desc + 1);
 452                 rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
 453                 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
 454                 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
 455                 rx_desc++;
 456         }
 457
 458         /* Finalize the rx desc list */
 459         rx_desc--;
 460         rx_desc->next = 0;
 461         emac_rx_active_tail = rx_desc;
 462         emac_rx_queue_active = 1;
 463
 464         /* Enable TX/RX */
 465         writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
 466         writel(0, &adap_emac->RXBUFFEROFFSET);
 467
 468         /*
 469          * No fancy configs - Use this for promiscous debug
 470          *   - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
 471          */
 472         writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
 473
 474         /* Enable ch 0 only */
 475         writel(1, &adap_emac->RXUNICASTSET);
 476
 477         /* Enable MII interface and Full duplex mode */
 478 #ifdef CONFIG_SOC_DA8XX
 479         writel((EMAC_MACCONTROL_MIIEN_ENABLE |
 480                 EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
 481                 EMAC_MACCONTROL_RMIISPEED_100),
 482                &adap_emac->MACCONTROL);
 483 #else
 484         writel((EMAC_MACCONTROL_MIIEN_ENABLE |
 485                 EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
 486                &adap_emac->MACCONTROL);
 487 #endif
 488
 489         /* Init MDIO & get link state */
 490         clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
 491         writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
 492                &adap_mdio->CONTROL);
 493
 494         /* We need to wait for MDIO to start */
 495         udelay(1000);
 496
 497         index = get_active_phy();
 498         if (index == -1)
 499                 return(0);
 500
 501         emac_gigabit_enable(active_phy_addr[index]);
 502
 503         /* Start receive process */
 504         writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP);
 505
 506         debug_emac("- emac_open\n");
 507
 508         return(1);
 509 }
 510
 511 /* EMAC Channel Teardown */
 512 static void davinci_eth_ch_teardown(int ch)
 513 {
 514         dv_reg          dly = 0xff;
 515         dv_reg          cnt;
 516
 517         debug_emac("+ emac_ch_teardown\n");
 518
 519         if (ch == EMAC_CH_TX) {
 520                 /* Init TX channel teardown */
 521                 writel(0, &adap_emac->TXTEARDOWN);
 522                 do {
 523                         /*
 524                          * Wait here for Tx teardown completion interrupt to
 525                          * occur. Note: A task delay can be called here to pend
 526                          * rather than occupying CPU cycles - anyway it has
 527                          * been found that teardown takes very few cpu cycles
 528                          * and does not affect functionality
 529                          */
 530                         dly--;
 531                         udelay(1);
 532                         if (dly == 0)
 533                                 break;
 534                         cnt = readl(&adap_emac->TX0CP);
 535                 } while (cnt != 0xfffffffc);
 536                 writel(cnt, &adap_emac->TX0CP);
 537                 writel(0, &adap_emac->TX0HDP);
 538         } else {
 539                 /* Init RX channel teardown */
 540                 writel(0, &adap_emac->RXTEARDOWN);
 541                 do {
 542                         /*
 543                          * Wait here for Rx teardown completion interrupt to
 544                          * occur. Note: A task delay can be called here to pend
 545                          * rather than occupying CPU cycles - anyway it has
 546                          * been found that teardown takes very few cpu cycles
 547                          * and does not affect functionality
 548                          */
 549                         dly--;
 550                         udelay(1);
 551                         if (dly == 0)
 552                                 break;
 553                         cnt = readl(&adap_emac->RX0CP);
 554                 } while (cnt != 0xfffffffc);
 555                 writel(cnt, &adap_emac->RX0CP);
 556                 writel(0, &adap_emac->RX0HDP);
 557         }
 558
 559         debug_emac("- emac_ch_teardown\n");
 560 }
 561
 562 /* Eth device close */
 563 static void davinci_eth_close(struct eth_device *dev)
 564 {
 565         debug_emac("+ emac_close\n");
 566
 567         davinci_eth_ch_teardown(EMAC_CH_TX);    /* TX Channel teardown */
 568         davinci_eth_ch_teardown(EMAC_CH_RX);    /* RX Channel teardown */
 569
 570         /* Reset EMAC module and disable interrupts in wrapper */
 571         writel(1, &adap_emac->SOFTRESET);
 572 #if defined(DAVINCI_EMAC_VERSION2)
 573         writel(1, &adap_ewrap->softrst);
 574 #else
 575         writel(0, &adap_ewrap->EWCTL);
 576 #endif
 577
 578 #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 579         defined(CONFIG_MACH_DAVINCI_DA850_EVM)
 580         adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
 581         adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
 582         adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
 583 #endif
 584         debug_emac("- emac_close\n");
 585 }
 586
 587 static int tx_send_loop = 0;
 588
 589 /*
 590  * This function sends a single packet on the network and returns
 591  * positive number (number of bytes transmitted) or negative for error
 592  */
 593 static int davinci_eth_send_packet (struct eth_device *dev,
 594                                         volatile void *packet, int length)
 595 {
 596         int ret_status = -1;
 597         int index;
 598         tx_send_loop = 0;
 599
 600         index = get_active_phy();
 601         if (index == -1) {
 602                 printf(" WARN: emac_send_packet: No link\n");
 603                 return (ret_status);
 604         }
 605
 606         emac_gigabit_enable(active_phy_addr[index]);
 607
 608         /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
 609         if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
 610                 length = EMAC_MIN_ETHERNET_PKT_SIZE;
 611         }
 612
 613         /* Populate the TX descriptor */
 614         emac_tx_desc->next = 0;
 615         emac_tx_desc->buffer = (u_int8_t *) packet;
 616         emac_tx_desc->buff_off_len = (length & 0xffff);
 617         emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
 618                                       EMAC_CPPI_SOP_BIT |
 619                                       EMAC_CPPI_OWNERSHIP_BIT |
 620                                       EMAC_CPPI_EOP_BIT);
 621         /* Send the packet */
 622         writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP);
 623
 624         /* Wait for packet to complete or link down */
 625         while (1) {
 626                 if (!phy[index].get_link_speed(active_phy_addr[index])) {
 627                         davinci_eth_ch_teardown (EMAC_CH_TX);
 628                         return (ret_status);
 629                 }
 630
 631                 emac_gigabit_enable(active_phy_addr[index]);
 632
 633                 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
 634                         ret_status = length;
 635                         break;
 636                 }
 637                 tx_send_loop++;
 638         }
 639
 640         return (ret_status);
 641 }
 642
 643 /*
 644  * This function handles receipt of a packet from the network
 645  */
 646 static int davinci_eth_rcv_packet (struct eth_device *dev)
 647 {
 648         volatile emac_desc *rx_curr_desc;
 649         volatile emac_desc *curr_desc;
 650         volatile emac_desc *tail_desc;
 651         int status, ret = -1;
 652
 653         rx_curr_desc = emac_rx_active_head;
 654         status = rx_curr_desc->pkt_flag_len;
 655         if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
 656                 if (status & EMAC_CPPI_RX_ERROR_FRAME) {
 657                         /* Error in packet - discard it and requeue desc */
 658                         printf ("WARN: emac_rcv_pkt: Error in packet\n");
 659                 } else {
 660                         NetReceive (rx_curr_desc->buffer,
 661                                     (rx_curr_desc->buff_off_len & 0xffff));
 662                         ret = rx_curr_desc->buff_off_len & 0xffff;
 663                 }
 664
 665                 /* Ack received packet descriptor */
 666                 writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP);
 667                 curr_desc = rx_curr_desc;
 668                 emac_rx_active_head =
 669                         (volatile emac_desc *) rx_curr_desc->next;
 670
 671                 if (status & EMAC_CPPI_EOQ_BIT) {
 672                         if (emac_rx_active_head) {
 673                                 writel((unsigned long)emac_rx_active_head,
 674                                        &adap_emac->RX0HDP);
 675                         } else {
 676                                 emac_rx_queue_active = 0;
 677                                 printf ("INFO:emac_rcv_packet: RX Queue not active\n");
 678                         }
 679                 }
 680
 681                 /* Recycle RX descriptor */
 682                 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
 683                 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
 684                 rx_curr_desc->next = 0;
 685
 686                 if (emac_rx_active_head == 0) {
 687                         printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
 688                         emac_rx_active_head = curr_desc;
 689                         emac_rx_active_tail = curr_desc;
 690                         if (emac_rx_queue_active != 0) {
 691                                 writel((unsigned long)emac_rx_active_head,
 692                                        &adap_emac->RX0HDP);
 693                                 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
 694                                 emac_rx_queue_active = 1;
 695                         }
 696                 } else {
 697                         tail_desc = emac_rx_active_tail;
 698                         emac_rx_active_tail = curr_desc;
 699                         tail_desc->next = (unsigned int) curr_desc;
 700                         status = tail_desc->pkt_flag_len;
 701                         if (status & EMAC_CPPI_EOQ_BIT) {
 702                                 writel((unsigned long)curr_desc,
 703                                        &adap_emac->RX0HDP);
 704                                 status &= ~EMAC_CPPI_EOQ_BIT;
 705                                 tail_desc->pkt_flag_len = status;
 706                         }
 707                 }
 708                 return (ret);
 709         }
 710         return (0);
 711 }
 712
 713 /*
 714  * This function initializes the emac hardware. It does NOT initialize
 715  * EMAC modules power or pin multiplexors, that is done by board_init()
 716  * much earlier in bootup process. Returns 1 on success, 0 otherwise.
 717  */
 718 int davinci_emac_initialize(void)
 719 {
 720         u_int32_t       phy_id;
 721         u_int16_t       tmp;
 722         int             i;
 723         int             ret;
 724         struct eth_device *dev;
 725
 726         dev = malloc(sizeof *dev);
 727
 728         if (dev == NULL)
 729                 return -1;
 730
 731         memset(dev, 0, sizeof *dev);
 732         sprintf(dev->name, "DaVinci-EMAC");
 733
 734         dev->iobase = 0;
 735         dev->init = davinci_eth_open;
 736         dev->halt = davinci_eth_close;
 737         dev->send = davinci_eth_send_packet;
 738         dev->recv = davinci_eth_rcv_packet;
 739         dev->write_hwaddr = davinci_eth_set_mac_addr;
 740
 741         eth_register(dev);
 742
 743         davinci_eth_mdio_enable();
 744
 745         /* let the EMAC detect the PHYs */
 746         udelay(5000);
 747
 748         for (i = 0; i < 256; i++) {
 749                 if (readl(&adap_mdio->ALIVE))
 750                         break;
 751                 udelay(1000);
 752         }
 753
 754         if (i >= 256) {
 755                 printf("No ETH PHY detected!!!\n");
 756                 return(0);
 757         }
 758
 759         /* Find if PHY(s) is/are connected */
 760         ret = davinci_eth_phy_detect();
 761         if (!ret)
 762                 return(0);
 763         else
 764                 debug_emac(" %d ETH PHY detected\n", ret);
 765
 766         /* Get PHY ID and initialize phy_ops for a detected PHY */
 767         for (i = 0; i < num_phy; i++) {
 768                 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
 769                                                         &tmp)) {
 770                         active_phy_addr[i] = 0xff;
 771                         continue;
 772                 }
 773
 774                 phy_id = (tmp << 16) & 0xffff0000;
 775
 776                 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
 777                                                         &tmp)) {
 778                         active_phy_addr[i] = 0xff;
 779                         continue;
 780                 }
 781
 782                 phy_id |= tmp & 0x0000ffff;
 783
 784                 switch (phy_id) {
 785                 case PHY_KSZ8873:
 786                         sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
 787                                                 active_phy_addr[i]);
 788                         phy[i].init = ksz8873_init_phy;
 789                         phy[i].is_phy_connected = ksz8873_is_phy_connected;
 790                         phy[i].get_link_speed = ksz8873_get_link_speed;
 791                         phy[i].auto_negotiate = ksz8873_auto_negotiate;
 792                         break;
 793                 case PHY_LXT972:
 794                         sprintf(phy[i].name, "LXT972 @ 0x%02x",
 795                                                 active_phy_addr[i]);
 796                         phy[i].init = lxt972_init_phy;
 797                         phy[i].is_phy_connected = lxt972_is_phy_connected;
 798                         phy[i].get_link_speed = lxt972_get_link_speed;
 799                         phy[i].auto_negotiate = lxt972_auto_negotiate;
 800                         break;
 801                 case PHY_DP83848:
 802                         sprintf(phy[i].name, "DP83848 @ 0x%02x",
 803                                                 active_phy_addr[i]);
 804                         phy[i].init = dp83848_init_phy;
 805                         phy[i].is_phy_connected = dp83848_is_phy_connected;
 806                         phy[i].get_link_speed = dp83848_get_link_speed;
 807                         phy[i].auto_negotiate = dp83848_auto_negotiate;
 808                         break;
 809                 case PHY_ET1011C:
 810                         sprintf(phy[i].name, "ET1011C @ 0x%02x",
 811                                                 active_phy_addr[i]);
 812                         phy[i].init = gen_init_phy;
 813                         phy[i].is_phy_connected = gen_is_phy_connected;
 814                         phy[i].get_link_speed = et1011c_get_link_speed;
 815                         phy[i].auto_negotiate = gen_auto_negotiate;
 816                         break;
 817                 default:
 818                         sprintf(phy[i].name, "GENERIC @ 0x%02x",
 819                                                 active_phy_addr[i]);
 820                         phy[i].init = gen_init_phy;
 821                         phy[i].is_phy_connected = gen_is_phy_connected;
 822                         phy[i].get_link_speed = gen_get_link_speed;
 823                         phy[i].auto_negotiate = gen_auto_negotiate;
 824                 }
 825
 826                 debug("Ethernet PHY: %s\n", phy[i].name);
 827
 828                 miiphy_register(phy[i].name, davinci_mii_phy_read,
 829                                                 davinci_mii_phy_write);
 830         }
 831         return(1);
 832 }