drivers/net/e1000.c

   1 /**************************************************************************
   2 Intel Pro 1000 for ppcboot/das-u-boot
   3 Drivers are port from Intel's Linux driver e1000-4.3.15
   4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
   5 tested on both gig copper and gig fiber boards
   6 ***************************************************************************/
   7 /*******************************************************************************
   8
   9
  10   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  11
  12  * SPDX-License-Identifier:     GPL-2.0+
  13
  14   Contact Information:
  15   Linux NICS <linux.nics@intel.com>
  16   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  17
  18 *******************************************************************************/
  19 /*
  20  *  Copyright (C) Archway Digital Solutions.
  21  *
  22  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  23  *  2/9/2002
  24  *
  25  *  Copyright (C) Linux Networx.
  26  *  Massive upgrade to work with the new intel gigabit NICs.
  27  *  <ebiederman at lnxi dot com>
  28  *
  29  *  Copyright 2011 Freescale Semiconductor, Inc.
  30  */
  31
  32 #include "e1000.h"
  33
  34 #define TOUT_LOOP   100000
  35
  36 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  37 #define bus_to_phys(devno, a)   pci_mem_to_phys(devno, a)
  38
  39 #define E1000_DEFAULT_PCI_PBA   0x00000030
  40 #define E1000_DEFAULT_PCIE_PBA  0x000a0026
  41
  42 /* NIC specific static variables go here */
  43
  44 static char tx_pool[128 + 16];
  45 static char rx_pool[128 + 16];
  46 static char packet[2096];
  47
  48 static struct e1000_tx_desc *tx_base;
  49 static struct e1000_rx_desc *rx_base;
  50
  51 static int tx_tail;
  52 static int rx_tail, rx_last;
  53
  54 static struct pci_device_id e1000_supported[] = {
  55         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
  56         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
  57         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
  58         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
  59         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
  60         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
  61         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
  62         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
  63         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
  64         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
  65         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
  66         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
  67         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
  68         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
  69         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
  70         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
  71         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
  72         /* E1000 PCIe card */
  73         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
  74         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER      },
  75         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES     },
  76         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
  77         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
  78         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
  79         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
  80         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
  81         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
  82         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
  83         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
  84         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
  85         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
  86         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
  87         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
  88         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
  89         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
  90         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
  91         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
  92         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
  93         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
  94         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
  95         {}
  96 };
  97
  98 /* Function forward declarations */
  99 static int e1000_setup_link(struct eth_device *nic);
 100 static int e1000_setup_fiber_link(struct eth_device *nic);
 101 static int e1000_setup_copper_link(struct eth_device *nic);
 102 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
 103 static void e1000_config_collision_dist(struct e1000_hw *hw);
 104 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
 105 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
 106 static int e1000_check_for_link(struct eth_device *nic);
 107 static int e1000_wait_autoneg(struct e1000_hw *hw);
 108 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
 109                                        uint16_t * duplex);
 110 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 111                               uint16_t * phy_data);
 112 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 113                                uint16_t phy_data);
 114 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 115 static int e1000_phy_reset(struct e1000_hw *hw);
 116 static int e1000_detect_gig_phy(struct e1000_hw *hw);
 117 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 118 static void e1000_set_media_type(struct e1000_hw *hw);
 119
 120 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 121 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 122
 123 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 124                 uint16_t words,
 125                 uint16_t *data);
 126 /******************************************************************************
 127  * Raises the EEPROM's clock input.
 128  *
 129  * hw - Struct containing variables accessed by shared code
 130  * eecd - EECD's current value
 131  *****************************************************************************/
 132 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 133 {
 134         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 135          * wait 50 microseconds.
 136          */
 137         *eecd = *eecd | E1000_EECD_SK;
 138         E1000_WRITE_REG(hw, EECD, *eecd);
 139         E1000_WRITE_FLUSH(hw);
 140         udelay(50);
 141 }
 142
 143 /******************************************************************************
 144  * Lowers the EEPROM's clock input.
 145  *
 146  * hw - Struct containing variables accessed by shared code
 147  * eecd - EECD's current value
 148  *****************************************************************************/
 149 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 150 {
 151         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 152          * wait 50 microseconds.
 153          */
 154         *eecd = *eecd & ~E1000_EECD_SK;
 155         E1000_WRITE_REG(hw, EECD, *eecd);
 156         E1000_WRITE_FLUSH(hw);
 157         udelay(50);
 158 }
 159
 160 /******************************************************************************
 161  * Shift data bits out to the EEPROM.
 162  *
 163  * hw - Struct containing variables accessed by shared code
 164  * data - data to send to the EEPROM
 165  * count - number of bits to shift out
 166  *****************************************************************************/
 167 static void
 168 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
 169 {
 170         uint32_t eecd;
 171         uint32_t mask;
 172
 173         /* We need to shift "count" bits out to the EEPROM. So, value in the
 174          * "data" parameter will be shifted out to the EEPROM one bit at a time.
 175          * In order to do this, "data" must be broken down into bits.
 176          */
 177         mask = 0x01 << (count - 1);
 178         eecd = E1000_READ_REG(hw, EECD);
 179         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 180         do {
 181                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 182                  * and then raising and then lowering the clock (the SK bit controls
 183                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 184                  * by setting "DI" to "0" and then raising and then lowering the clock.
 185                  */
 186                 eecd &= ~E1000_EECD_DI;
 187
 188                 if (data & mask)
 189                         eecd |= E1000_EECD_DI;
 190
 191                 E1000_WRITE_REG(hw, EECD, eecd);
 192                 E1000_WRITE_FLUSH(hw);
 193
 194                 udelay(50);
 195
 196                 e1000_raise_ee_clk(hw, &eecd);
 197                 e1000_lower_ee_clk(hw, &eecd);
 198
 199                 mask = mask >> 1;
 200
 201         } while (mask);
 202
 203         /* We leave the "DI" bit set to "0" when we leave this routine. */
 204         eecd &= ~E1000_EECD_DI;
 205         E1000_WRITE_REG(hw, EECD, eecd);
 206 }
 207
 208 /******************************************************************************
 209  * Shift data bits in from the EEPROM
 210  *
 211  * hw - Struct containing variables accessed by shared code
 212  *****************************************************************************/
 213 static uint16_t
 214 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
 215 {
 216         uint32_t eecd;
 217         uint32_t i;
 218         uint16_t data;
 219
 220         /* In order to read a register from the EEPROM, we need to shift 'count'
 221          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 222          * input to the EEPROM (setting the SK bit), and then reading the
 223          * value of the "DO" bit.  During this "shifting in" process the
 224          * "DI" bit should always be clear.
 225          */
 226
 227         eecd = E1000_READ_REG(hw, EECD);
 228
 229         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 230         data = 0;
 231
 232         for (i = 0; i < count; i++) {
 233                 data = data << 1;
 234                 e1000_raise_ee_clk(hw, &eecd);
 235
 236                 eecd = E1000_READ_REG(hw, EECD);
 237
 238                 eecd &= ~(E1000_EECD_DI);
 239                 if (eecd & E1000_EECD_DO)
 240                         data |= 1;
 241
 242                 e1000_lower_ee_clk(hw, &eecd);
 243         }
 244
 245         return data;
 246 }
 247
 248 /******************************************************************************
 249  * Returns EEPROM to a "standby" state
 250  *
 251  * hw - Struct containing variables accessed by shared code
 252  *****************************************************************************/
 253 void e1000_standby_eeprom(struct e1000_hw *hw)
 254 {
 255         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 256         uint32_t eecd;
 257
 258         eecd = E1000_READ_REG(hw, EECD);
 259
 260         if (eeprom->type == e1000_eeprom_microwire) {
 261                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 262                 E1000_WRITE_REG(hw, EECD, eecd);
 263                 E1000_WRITE_FLUSH(hw);
 264                 udelay(eeprom->delay_usec);
 265
 266                 /* Clock high */
 267                 eecd |= E1000_EECD_SK;
 268                 E1000_WRITE_REG(hw, EECD, eecd);
 269                 E1000_WRITE_FLUSH(hw);
 270                 udelay(eeprom->delay_usec);
 271
 272                 /* Select EEPROM */
 273                 eecd |= E1000_EECD_CS;
 274                 E1000_WRITE_REG(hw, EECD, eecd);
 275                 E1000_WRITE_FLUSH(hw);
 276                 udelay(eeprom->delay_usec);
 277
 278                 /* Clock low */
 279                 eecd &= ~E1000_EECD_SK;
 280                 E1000_WRITE_REG(hw, EECD, eecd);
 281                 E1000_WRITE_FLUSH(hw);
 282                 udelay(eeprom->delay_usec);
 283         } else if (eeprom->type == e1000_eeprom_spi) {
 284                 /* Toggle CS to flush commands */
 285                 eecd |= E1000_EECD_CS;
 286                 E1000_WRITE_REG(hw, EECD, eecd);
 287                 E1000_WRITE_FLUSH(hw);
 288                 udelay(eeprom->delay_usec);
 289                 eecd &= ~E1000_EECD_CS;
 290                 E1000_WRITE_REG(hw, EECD, eecd);
 291                 E1000_WRITE_FLUSH(hw);
 292                 udelay(eeprom->delay_usec);
 293         }
 294 }
 295
 296 /***************************************************************************
 297 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
 298 *
 299 * hw - Struct containing variables accessed by shared code
 300 ****************************************************************************/
 301 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 302 {
 303         uint32_t eecd = 0;
 304
 305         DEBUGFUNC();
 306
 307         if (hw->mac_type == e1000_ich8lan)
 308                 return false;
 309
 310         if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
 311                 eecd = E1000_READ_REG(hw, EECD);
 312
 313                 /* Isolate bits 15 & 16 */
 314                 eecd = ((eecd >> 15) & 0x03);
 315
 316                 /* If both bits are set, device is Flash type */
 317                 if (eecd == 0x03)
 318                         return false;
 319         }
 320         return true;
 321 }
 322
 323 /******************************************************************************
 324  * Prepares EEPROM for access
 325  *
 326  * hw - Struct containing variables accessed by shared code
 327  *
 328  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 329  * function should be called before issuing a command to the EEPROM.
 330  *****************************************************************************/
 331 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
 332 {
 333         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 334         uint32_t eecd, i = 0;
 335
 336         DEBUGFUNC();
 337
 338         if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 339                 return -E1000_ERR_SWFW_SYNC;
 340         eecd = E1000_READ_REG(hw, EECD);
 341
 342         if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) {
 343                 /* Request EEPROM Access */
 344                 if (hw->mac_type > e1000_82544) {
 345                         eecd |= E1000_EECD_REQ;
 346                         E1000_WRITE_REG(hw, EECD, eecd);
 347                         eecd = E1000_READ_REG(hw, EECD);
 348                         while ((!(eecd & E1000_EECD_GNT)) &&
 349                                 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
 350                                 i++;
 351                                 udelay(5);
 352                                 eecd = E1000_READ_REG(hw, EECD);
 353                         }
 354                         if (!(eecd & E1000_EECD_GNT)) {
 355                                 eecd &= ~E1000_EECD_REQ;
 356                                 E1000_WRITE_REG(hw, EECD, eecd);
 357                                 DEBUGOUT("Could not acquire EEPROM grant\n");
 358                                 return -E1000_ERR_EEPROM;
 359                         }
 360                 }
 361         }
 362
 363         /* Setup EEPROM for Read/Write */
 364
 365         if (eeprom->type == e1000_eeprom_microwire) {
 366                 /* Clear SK and DI */
 367                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 368                 E1000_WRITE_REG(hw, EECD, eecd);
 369
 370                 /* Set CS */
 371                 eecd |= E1000_EECD_CS;
 372                 E1000_WRITE_REG(hw, EECD, eecd);
 373         } else if (eeprom->type == e1000_eeprom_spi) {
 374                 /* Clear SK and CS */
 375                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 376                 E1000_WRITE_REG(hw, EECD, eecd);
 377                 udelay(1);
 378         }
 379
 380         return E1000_SUCCESS;
 381 }
 382
 383 /******************************************************************************
 384  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 385  * is configured.  Additionally, if this is ICH8, the flash controller GbE
 386  * registers must be mapped, or this will crash.
 387  *
 388  * hw - Struct containing variables accessed by shared code
 389  *****************************************************************************/
 390 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 391 {
 392         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 393         uint32_t eecd = E1000_READ_REG(hw, EECD);
 394         int32_t ret_val = E1000_SUCCESS;
 395         uint16_t eeprom_size;
 396
 397         DEBUGFUNC();
 398
 399         switch (hw->mac_type) {
 400         case e1000_82542_rev2_0:
 401         case e1000_82542_rev2_1:
 402         case e1000_82543:
 403         case e1000_82544:
 404                 eeprom->type = e1000_eeprom_microwire;
 405                 eeprom->word_size = 64;
 406                 eeprom->opcode_bits = 3;
 407                 eeprom->address_bits = 6;
 408                 eeprom->delay_usec = 50;
 409                 eeprom->use_eerd = false;
 410                 eeprom->use_eewr = false;
 411         break;
 412         case e1000_82540:
 413         case e1000_82545:
 414         case e1000_82545_rev_3:
 415         case e1000_82546:
 416         case e1000_82546_rev_3:
 417                 eeprom->type = e1000_eeprom_microwire;
 418                 eeprom->opcode_bits = 3;
 419                 eeprom->delay_usec = 50;
 420                 if (eecd & E1000_EECD_SIZE) {
 421                         eeprom->word_size = 256;
 422                         eeprom->address_bits = 8;
 423                 } else {
 424                         eeprom->word_size = 64;
 425                         eeprom->address_bits = 6;
 426                 }
 427                 eeprom->use_eerd = false;
 428                 eeprom->use_eewr = false;
 429                 break;
 430         case e1000_82541:
 431         case e1000_82541_rev_2:
 432         case e1000_82547:
 433         case e1000_82547_rev_2:
 434                 if (eecd & E1000_EECD_TYPE) {
 435                         eeprom->type = e1000_eeprom_spi;
 436                         eeprom->opcode_bits = 8;
 437                         eeprom->delay_usec = 1;
 438                         if (eecd & E1000_EECD_ADDR_BITS) {
 439                                 eeprom->page_size = 32;
 440                                 eeprom->address_bits = 16;
 441                         } else {
 442                                 eeprom->page_size = 8;
 443                                 eeprom->address_bits = 8;
 444                         }
 445                 } else {
 446                         eeprom->type = e1000_eeprom_microwire;
 447                         eeprom->opcode_bits = 3;
 448                         eeprom->delay_usec = 50;
 449                         if (eecd & E1000_EECD_ADDR_BITS) {
 450                                 eeprom->word_size = 256;
 451                                 eeprom->address_bits = 8;
 452                         } else {
 453                                 eeprom->word_size = 64;
 454                                 eeprom->address_bits = 6;
 455                         }
 456                 }
 457                 eeprom->use_eerd = false;
 458                 eeprom->use_eewr = false;
 459                 break;
 460         case e1000_82571:
 461         case e1000_82572:
 462                 eeprom->type = e1000_eeprom_spi;
 463                 eeprom->opcode_bits = 8;
 464                 eeprom->delay_usec = 1;
 465                 if (eecd & E1000_EECD_ADDR_BITS) {
 466                         eeprom->page_size = 32;
 467                         eeprom->address_bits = 16;
 468                 } else {
 469                         eeprom->page_size = 8;
 470                         eeprom->address_bits = 8;
 471                 }
 472                 eeprom->use_eerd = false;
 473                 eeprom->use_eewr = false;
 474                 break;
 475         case e1000_82573:
 476         case e1000_82574:
 477                 eeprom->type = e1000_eeprom_spi;
 478                 eeprom->opcode_bits = 8;
 479                 eeprom->delay_usec = 1;
 480                 if (eecd & E1000_EECD_ADDR_BITS) {
 481                         eeprom->page_size = 32;
 482                         eeprom->address_bits = 16;
 483                 } else {
 484                         eeprom->page_size = 8;
 485                         eeprom->address_bits = 8;
 486                 }
 487                 eeprom->use_eerd = true;
 488                 eeprom->use_eewr = true;
 489                 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
 490                         eeprom->type = e1000_eeprom_flash;
 491                         eeprom->word_size = 2048;
 492
 493                 /* Ensure that the Autonomous FLASH update bit is cleared due to
 494                  * Flash update issue on parts which use a FLASH for NVM. */
 495                         eecd &= ~E1000_EECD_AUPDEN;
 496                         E1000_WRITE_REG(hw, EECD, eecd);
 497                 }
 498                 break;
 499         case e1000_80003es2lan:
 500                 eeprom->type = e1000_eeprom_spi;
 501                 eeprom->opcode_bits = 8;
 502                 eeprom->delay_usec = 1;
 503                 if (eecd & E1000_EECD_ADDR_BITS) {
 504                         eeprom->page_size = 32;
 505                         eeprom->address_bits = 16;
 506                 } else {
 507                         eeprom->page_size = 8;
 508                         eeprom->address_bits = 8;
 509                 }
 510                 eeprom->use_eerd = true;
 511                 eeprom->use_eewr = false;
 512                 break;
 513
 514         /* ich8lan does not support currently. if needed, please
 515          * add corresponding code and functions.
 516          */
 517 #if 0
 518         case e1000_ich8lan:
 519                 {
 520                 int32_t  i = 0;
 521
 522                 eeprom->type = e1000_eeprom_ich8;
 523                 eeprom->use_eerd = false;
 524                 eeprom->use_eewr = false;
 525                 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
 526                 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
 527                                 ICH_FLASH_GFPREG);
 528                 /* Zero the shadow RAM structure. But don't load it from NVM
 529                  * so as to save time for driver init */
 530                 if (hw->eeprom_shadow_ram != NULL) {
 531                         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
 532                                 hw->eeprom_shadow_ram[i].modified = false;
 533                                 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
 534                         }
 535                 }
 536
 537                 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
 538                                 ICH_FLASH_SECTOR_SIZE;
 539
 540                 hw->flash_bank_size = ((flash_size >> 16)
 541                                 & ICH_GFPREG_BASE_MASK) + 1;
 542                 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
 543
 544                 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
 545
 546                 hw->flash_bank_size /= 2 * sizeof(uint16_t);
 547                 break;
 548                 }
 549 #endif
 550         default:
 551                 break;
 552         }
 553
 554         if (eeprom->type == e1000_eeprom_spi) {
 555                 /* eeprom_size will be an enum [0..8] that maps
 556                  * to eeprom sizes 128B to
 557                  * 32KB (incremented by powers of 2).
 558                  */
 559                 if (hw->mac_type <= e1000_82547_rev_2) {
 560                         /* Set to default value for initial eeprom read. */
 561                         eeprom->word_size = 64;
 562                         ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
 563                                         &eeprom_size);
 564                         if (ret_val)
 565                                 return ret_val;
 566                         eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
 567                                 >> EEPROM_SIZE_SHIFT;
 568                         /* 256B eeprom size was not supported in earlier
 569                          * hardware, so we bump eeprom_size up one to
 570                          * ensure that "1" (which maps to 256B) is never
 571                          * the result used in the shifting logic below. */
 572                         if (eeprom_size)
 573                                 eeprom_size++;
 574                 } else {
 575                         eeprom_size = (uint16_t)((eecd &
 576                                 E1000_EECD_SIZE_EX_MASK) >>
 577                                 E1000_EECD_SIZE_EX_SHIFT);
 578                 }
 579
 580                 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 581         }
 582         return ret_val;
 583 }
 584
 585 /******************************************************************************
 586  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 587  *
 588  * hw - Struct containing variables accessed by shared code
 589  *****************************************************************************/
 590 static int32_t
 591 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 592 {
 593         uint32_t attempts = 100000;
 594         uint32_t i, reg = 0;
 595         int32_t done = E1000_ERR_EEPROM;
 596
 597         for (i = 0; i < attempts; i++) {
 598                 if (eerd == E1000_EEPROM_POLL_READ)
 599                         reg = E1000_READ_REG(hw, EERD);
 600                 else
 601                         reg = E1000_READ_REG(hw, EEWR);
 602
 603                 if (reg & E1000_EEPROM_RW_REG_DONE) {
 604                         done = E1000_SUCCESS;
 605                         break;
 606                 }
 607                 udelay(5);
 608         }
 609
 610         return done;
 611 }
 612
 613 /******************************************************************************
 614  * Reads a 16 bit word from the EEPROM using the EERD register.
 615  *
 616  * hw - Struct containing variables accessed by shared code
 617  * offset - offset of  word in the EEPROM to read
 618  * data - word read from the EEPROM
 619  * words - number of words to read
 620  *****************************************************************************/
 621 static int32_t
 622 e1000_read_eeprom_eerd(struct e1000_hw *hw,
 623                         uint16_t offset,
 624                         uint16_t words,
 625                         uint16_t *data)
 626 {
 627         uint32_t i, eerd = 0;
 628         int32_t error = 0;
 629
 630         for (i = 0; i < words; i++) {
 631                 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
 632                         E1000_EEPROM_RW_REG_START;
 633
 634                 E1000_WRITE_REG(hw, EERD, eerd);
 635                 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 636
 637                 if (error)
 638                         break;
 639                 data[i] = (E1000_READ_REG(hw, EERD) >>
 640                                 E1000_EEPROM_RW_REG_DATA);
 641
 642         }
 643
 644         return error;
 645 }
 646
 647 void e1000_release_eeprom(struct e1000_hw *hw)
 648 {
 649         uint32_t eecd;
 650
 651         DEBUGFUNC();
 652
 653         eecd = E1000_READ_REG(hw, EECD);
 654
 655         if (hw->eeprom.type == e1000_eeprom_spi) {
 656                 eecd |= E1000_EECD_CS;  /* Pull CS high */
 657                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
 658
 659                 E1000_WRITE_REG(hw, EECD, eecd);
 660
 661                 udelay(hw->eeprom.delay_usec);
 662         } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 663                 /* cleanup eeprom */
 664
 665                 /* CS on Microwire is active-high */
 666                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 667
 668                 E1000_WRITE_REG(hw, EECD, eecd);
 669
 670                 /* Rising edge of clock */
 671                 eecd |= E1000_EECD_SK;
 672                 E1000_WRITE_REG(hw, EECD, eecd);
 673                 E1000_WRITE_FLUSH(hw);
 674                 udelay(hw->eeprom.delay_usec);
 675
 676                 /* Falling edge of clock */
 677                 eecd &= ~E1000_EECD_SK;
 678                 E1000_WRITE_REG(hw, EECD, eecd);
 679                 E1000_WRITE_FLUSH(hw);
 680                 udelay(hw->eeprom.delay_usec);
 681         }
 682
 683         /* Stop requesting EEPROM access */
 684         if (hw->mac_type > e1000_82544) {
 685                 eecd &= ~E1000_EECD_REQ;
 686                 E1000_WRITE_REG(hw, EECD, eecd);
 687         }
 688 }
 689 /******************************************************************************
 690  * Reads a 16 bit word from the EEPROM.
 691  *
 692  * hw - Struct containing variables accessed by shared code
 693  *****************************************************************************/
 694 static int32_t
 695 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 696 {
 697         uint16_t retry_count = 0;
 698         uint8_t spi_stat_reg;
 699
 700         DEBUGFUNC();
 701
 702         /* Read "Status Register" repeatedly until the LSB is cleared.  The
 703          * EEPROM will signal that the command has been completed by clearing
 704          * bit 0 of the internal status register.  If it's not cleared within
 705          * 5 milliseconds, then error out.
 706          */
 707         retry_count = 0;
 708         do {
 709                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
 710                         hw->eeprom.opcode_bits);
 711                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
 712                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 713                         break;
 714
 715                 udelay(5);
 716                 retry_count += 5;
 717
 718                 e1000_standby_eeprom(hw);
 719         } while (retry_count < EEPROM_MAX_RETRY_SPI);
 720
 721         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 722          * only 0-5mSec on 5V devices)
 723          */
 724         if (retry_count >= EEPROM_MAX_RETRY_SPI) {
 725                 DEBUGOUT("SPI EEPROM Status error\n");
 726                 return -E1000_ERR_EEPROM;
 727         }
 728
 729         return E1000_SUCCESS;
 730 }
 731
 732 /******************************************************************************
 733  * Reads a 16 bit word from the EEPROM.
 734  *
 735  * hw - Struct containing variables accessed by shared code
 736  * offset - offset of  word in the EEPROM to read
 737  * data - word read from the EEPROM
 738  *****************************************************************************/
 739 static int32_t
 740 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 741                 uint16_t words, uint16_t *data)
 742 {
 743         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 744         uint32_t i = 0;
 745
 746         DEBUGFUNC();
 747
 748         /* If eeprom is not yet detected, do so now */
 749         if (eeprom->word_size == 0)
 750                 e1000_init_eeprom_params(hw);
 751
 752         /* A check for invalid values:  offset too large, too many words,
 753          * and not enough words.
 754          */
 755         if ((offset >= eeprom->word_size) ||
 756                 (words > eeprom->word_size - offset) ||
 757                 (words == 0)) {
 758                 DEBUGOUT("\"words\" parameter out of bounds."
 759                         "Words = %d, size = %d\n", offset, eeprom->word_size);
 760                 return -E1000_ERR_EEPROM;
 761         }
 762
 763         /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 764          * directly. In this case, we need to acquire the EEPROM so that
 765          * FW or other port software does not interrupt.
 766          */
 767         if (e1000_is_onboard_nvm_eeprom(hw) == true &&
 768                 hw->eeprom.use_eerd == false) {
 769
 770                 /* Prepare the EEPROM for bit-bang reading */
 771                 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
 772                         return -E1000_ERR_EEPROM;
 773         }
 774
 775         /* Eerd register EEPROM access requires no eeprom aquire/release */
 776         if (eeprom->use_eerd == true)
 777                 return e1000_read_eeprom_eerd(hw, offset, words, data);
 778
 779         /* ich8lan does not support currently. if needed, please
 780          * add corresponding code and functions.
 781          */
 782 #if 0
 783         /* ICH EEPROM access is done via the ICH flash controller */
 784         if (eeprom->type == e1000_eeprom_ich8)
 785                 return e1000_read_eeprom_ich8(hw, offset, words, data);
 786 #endif
 787         /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 788          * acquired the EEPROM at this point, so any returns should relase it */
 789         if (eeprom->type == e1000_eeprom_spi) {
 790                 uint16_t word_in;
 791                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 792
 793                 if (e1000_spi_eeprom_ready(hw)) {
 794                         e1000_release_eeprom(hw);
 795                         return -E1000_ERR_EEPROM;
 796                 }
 797
 798                 e1000_standby_eeprom(hw);
 799
 800                 /* Some SPI eeproms use the 8th address bit embedded in
 801                  * the opcode */
 802                 if ((eeprom->address_bits == 8) && (offset >= 128))
 803                         read_opcode |= EEPROM_A8_OPCODE_SPI;
 804
 805                 /* Send the READ command (opcode + addr)  */
 806                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
 807                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
 808                                 eeprom->address_bits);
 809
 810                 /* Read the data.  The address of the eeprom internally
 811                  * increments with each byte (spi) being read, saving on the
 812                  * overhead of eeprom setup and tear-down.  The address
 813                  * counter will roll over if reading beyond the size of
 814                  * the eeprom, thus allowing the entire memory to be read
 815                  * starting from any offset. */
 816                 for (i = 0; i < words; i++) {
 817                         word_in = e1000_shift_in_ee_bits(hw, 16);
 818                         data[i] = (word_in >> 8) | (word_in << 8);
 819                 }
 820         } else if (eeprom->type == e1000_eeprom_microwire) {
 821                 for (i = 0; i < words; i++) {
 822                         /* Send the READ command (opcode + addr)  */
 823                         e1000_shift_out_ee_bits(hw,
 824                                 EEPROM_READ_OPCODE_MICROWIRE,
 825                                 eeprom->opcode_bits);
 826                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
 827                                 eeprom->address_bits);
 828
 829                         /* Read the data.  For microwire, each word requires
 830                          * the overhead of eeprom setup and tear-down. */
 831                         data[i] = e1000_shift_in_ee_bits(hw, 16);
 832                         e1000_standby_eeprom(hw);
 833                 }
 834         }
 835
 836         /* End this read operation */
 837         e1000_release_eeprom(hw);
 838
 839         return E1000_SUCCESS;
 840 }
 841
 842 /******************************************************************************
 843  * Verifies that the EEPROM has a valid checksum
 844  *
 845  * hw - Struct containing variables accessed by shared code
 846  *
 847  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
 848  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
 849  * valid.
 850  *****************************************************************************/
 851 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 852 {
 853         uint16_t i, checksum, checksum_reg, *buf;
 854
 855         DEBUGFUNC();
 856
 857         /* Allocate a temporary buffer */
 858         buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
 859         if (!buf) {
 860                 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
 861                 return -E1000_ERR_EEPROM;
 862         }
 863
 864         /* Read the EEPROM */
 865         if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
 866                 E1000_ERR(hw->nic, "Unable to read EEPROM!\n");
 867                 return -E1000_ERR_EEPROM;
 868         }
 869
 870         /* Compute the checksum */
 871         checksum = 0;
 872         for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
 873                 checksum += buf[i];
 874         checksum = ((uint16_t)EEPROM_SUM) - checksum;
 875         checksum_reg = buf[i];
 876
 877         /* Verify it! */
 878         if (checksum == checksum_reg)
 879                 return 0;
 880
 881         /* Hrm, verification failed, print an error */
 882         E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
 883         E1000_ERR(hw->nic, "  ...register was 0x%04hx, calculated 0x%04hx\n",
 884                         checksum_reg, checksum);
 885
 886         return -E1000_ERR_EEPROM;
 887 }
 888
 889 /*****************************************************************************
 890  * Set PHY to class A mode
 891  * Assumes the following operations will follow to enable the new class mode.
 892  *  1. Do a PHY soft reset
 893  *  2. Restart auto-negotiation or force link.
 894  *
 895  * hw - Struct containing variables accessed by shared code
 896  ****************************************************************************/
 897 static int32_t
 898 e1000_set_phy_mode(struct e1000_hw *hw)
 899 {
 900         int32_t ret_val;
 901         uint16_t eeprom_data;
 902
 903         DEBUGFUNC();
 904
 905         if ((hw->mac_type == e1000_82545_rev_3) &&
 906                 (hw->media_type == e1000_media_type_copper)) {
 907                 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
 908                                 1, &eeprom_data);
 909                 if (ret_val)
 910                         return ret_val;
 911
 912                 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
 913                         (eeprom_data & EEPROM_PHY_CLASS_A)) {
 914                         ret_val = e1000_write_phy_reg(hw,
 915                                         M88E1000_PHY_PAGE_SELECT, 0x000B);
 916                         if (ret_val)
 917                                 return ret_val;
 918                         ret_val = e1000_write_phy_reg(hw,
 919                                         M88E1000_PHY_GEN_CONTROL, 0x8104);
 920                         if (ret_val)
 921                                 return ret_val;
 922
 923                         hw->phy_reset_disable = false;
 924                 }
 925         }
 926
 927         return E1000_SUCCESS;
 928 }
 929
 930 /***************************************************************************
 931  *
 932  * Obtaining software semaphore bit (SMBI) before resetting PHY.
 933  *
 934  * hw: Struct containing variables accessed by shared code
 935  *
 936  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
 937  *            E1000_SUCCESS at any other case.
 938  *
 939  ***************************************************************************/
 940 static int32_t
 941 e1000_get_software_semaphore(struct e1000_hw *hw)
 942 {
 943          int32_t timeout = hw->eeprom.word_size + 1;
 944          uint32_t swsm;
 945
 946         DEBUGFUNC();
 947
 948         if (hw->mac_type != e1000_80003es2lan)
 949                 return E1000_SUCCESS;
 950
 951         while (timeout) {
 952                 swsm = E1000_READ_REG(hw, SWSM);
 953                 /* If SMBI bit cleared, it is now set and we hold
 954                  * the semaphore */
 955                 if (!(swsm & E1000_SWSM_SMBI))
 956                         break;
 957                 mdelay(1);
 958                 timeout--;
 959         }
 960
 961         if (!timeout) {
 962                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 963                 return -E1000_ERR_RESET;
 964         }
 965
 966         return E1000_SUCCESS;
 967 }
 968
 969 /***************************************************************************
 970  * This function clears HW semaphore bits.
 971  *
 972  * hw: Struct containing variables accessed by shared code
 973  *
 974  * returns: - None.
 975  *
 976  ***************************************************************************/
 977 static void
 978 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
 979 {
 980          uint32_t swsm;
 981
 982         DEBUGFUNC();
 983
 984         if (!hw->eeprom_semaphore_present)
 985                 return;
 986
 987         swsm = E1000_READ_REG(hw, SWSM);
 988         if (hw->mac_type == e1000_80003es2lan) {
 989                 /* Release both semaphores. */
 990                 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 991         } else
 992                 swsm &= ~(E1000_SWSM_SWESMBI);
 993         E1000_WRITE_REG(hw, SWSM, swsm);
 994 }
 995
 996 /***************************************************************************
 997  *
 998  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
 999  * adapter or Eeprom access.
1000  *
1001  * hw: Struct containing variables accessed by shared code
1002  *
1003  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1004  *            E1000_SUCCESS at any other case.
1005  *
1006  ***************************************************************************/
1007 static int32_t
1008 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1009 {
1010         int32_t timeout;
1011         uint32_t swsm;
1012
1013         DEBUGFUNC();
1014
1015         if (!hw->eeprom_semaphore_present)
1016                 return E1000_SUCCESS;
1017
1018         if (hw->mac_type == e1000_80003es2lan) {
1019                 /* Get the SW semaphore. */
1020                 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1021                         return -E1000_ERR_EEPROM;
1022         }
1023
1024         /* Get the FW semaphore. */
1025         timeout = hw->eeprom.word_size + 1;
1026         while (timeout) {
1027                 swsm = E1000_READ_REG(hw, SWSM);
1028                 swsm |= E1000_SWSM_SWESMBI;
1029                 E1000_WRITE_REG(hw, SWSM, swsm);
1030                 /* if we managed to set the bit we got the semaphore. */
1031                 swsm = E1000_READ_REG(hw, SWSM);
1032                 if (swsm & E1000_SWSM_SWESMBI)
1033                         break;
1034
1035                 udelay(50);
1036                 timeout--;
1037         }
1038
1039         if (!timeout) {
1040                 /* Release semaphores */
1041                 e1000_put_hw_eeprom_semaphore(hw);
1042                 DEBUGOUT("Driver can't access the Eeprom - "
1043                                 "SWESMBI bit is set.\n");
1044                 return -E1000_ERR_EEPROM;
1045         }
1046
1047         return E1000_SUCCESS;
1048 }
1049
1050 static int32_t
1051 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1052 {
1053         uint32_t swfw_sync = 0;
1054         uint32_t swmask = mask;
1055         uint32_t fwmask = mask << 16;
1056         int32_t timeout = 200;
1057
1058         DEBUGFUNC();
1059         while (timeout) {
1060                 if (e1000_get_hw_eeprom_semaphore(hw))
1061                         return -E1000_ERR_SWFW_SYNC;
1062
1063                 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1064                 if (!(swfw_sync & (fwmask | swmask)))
1065                         break;
1066
1067                 /* firmware currently using resource (fwmask) */
1068                 /* or other software thread currently using resource (swmask) */
1069                 e1000_put_hw_eeprom_semaphore(hw);
1070                 mdelay(5);
1071                 timeout--;
1072         }
1073
1074         if (!timeout) {
1075                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1076                 return -E1000_ERR_SWFW_SYNC;
1077         }
1078
1079         swfw_sync |= swmask;
1080         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1081
1082         e1000_put_hw_eeprom_semaphore(hw);
1083         return E1000_SUCCESS;
1084 }
1085
1086 static bool e1000_is_second_port(struct e1000_hw *hw)
1087 {
1088         switch (hw->mac_type) {
1089         case e1000_80003es2lan:
1090         case e1000_82546:
1091         case e1000_82571:
1092                 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1093                         return true;
1094                 /* Fallthrough */
1095         default:
1096                 return false;
1097         }
1098 }
1099
1100 /******************************************************************************
1101  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1102  * second function of dual function devices
1103  *
1104  * nic - Struct containing variables accessed by shared code
1105  *****************************************************************************/
1106 static int
1107 e1000_read_mac_addr(struct eth_device *nic)
1108 {
1109         struct e1000_hw *hw = nic->priv;
1110         uint16_t offset;
1111         uint16_t eeprom_data;
1112         int i;
1113
1114         DEBUGFUNC();
1115
1116         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1117                 offset = i >> 1;
1118                 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1119                         DEBUGOUT("EEPROM Read Error\n");
1120                         return -E1000_ERR_EEPROM;
1121                 }
1122                 nic->enetaddr[i] = eeprom_data & 0xff;
1123                 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1124         }
1125
1126         /* Invert the last bit if this is the second device */
1127         if (e1000_is_second_port(hw))
1128                 nic->enetaddr[5] ^= 1;
1129
1130 #ifdef CONFIG_E1000_FALLBACK_MAC
1131         if (!is_valid_ether_addr(nic->enetaddr)) {
1132                 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1133
1134                 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1135         }
1136 #endif
1137         return 0;
1138 }
1139
1140 /******************************************************************************
1141  * Initializes receive address filters.
1142  *
1143  * hw - Struct containing variables accessed by shared code
1144  *
1145  * Places the MAC address in receive address register 0 and clears the rest
1146  * of the receive addresss registers. Clears the multicast table. Assumes
1147  * the receiver is in reset when the routine is called.
1148  *****************************************************************************/
1149 static void
1150 e1000_init_rx_addrs(struct eth_device *nic)
1151 {
1152         struct e1000_hw *hw = nic->priv;
1153         uint32_t i;
1154         uint32_t addr_low;
1155         uint32_t addr_high;
1156
1157         DEBUGFUNC();
1158
1159         /* Setup the receive address. */
1160         DEBUGOUT("Programming MAC Address into RAR[0]\n");
1161         addr_low = (nic->enetaddr[0] |
1162                     (nic->enetaddr[1] << 8) |
1163                     (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1164
1165         addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1166
1167         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1168         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1169
1170         /* Zero out the other 15 receive addresses. */
1171         DEBUGOUT("Clearing RAR[1-15]\n");
1172         for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1173                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1174                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1175         }
1176 }
1177
1178 /******************************************************************************
1179  * Clears the VLAN filer table
1180  *
1181  * hw - Struct containing variables accessed by shared code
1182  *****************************************************************************/
1183 static void
1184 e1000_clear_vfta(struct e1000_hw *hw)
1185 {
1186         uint32_t offset;
1187
1188         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1189                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1190 }
1191
1192 /******************************************************************************
1193  * Set the mac type member in the hw struct.
1194  *
1195  * hw - Struct containing variables accessed by shared code
1196  *****************************************************************************/
1197 int32_t
1198 e1000_set_mac_type(struct e1000_hw *hw)
1199 {
1200         DEBUGFUNC();
1201
1202         switch (hw->device_id) {
1203         case E1000_DEV_ID_82542:
1204                 switch (hw->revision_id) {
1205                 case E1000_82542_2_0_REV_ID:
1206                         hw->mac_type = e1000_82542_rev2_0;
1207                         break;
1208                 case E1000_82542_2_1_REV_ID:
1209                         hw->mac_type = e1000_82542_rev2_1;
1210                         break;
1211                 default:
1212                         /* Invalid 82542 revision ID */
1213                         return -E1000_ERR_MAC_TYPE;
1214                 }
1215                 break;
1216         case E1000_DEV_ID_82543GC_FIBER:
1217         case E1000_DEV_ID_82543GC_COPPER:
1218                 hw->mac_type = e1000_82543;
1219                 break;
1220         case E1000_DEV_ID_82544EI_COPPER:
1221         case E1000_DEV_ID_82544EI_FIBER:
1222         case E1000_DEV_ID_82544GC_COPPER:
1223         case E1000_DEV_ID_82544GC_LOM:
1224                 hw->mac_type = e1000_82544;
1225                 break;
1226         case E1000_DEV_ID_82540EM:
1227         case E1000_DEV_ID_82540EM_LOM:
1228         case E1000_DEV_ID_82540EP:
1229         case E1000_DEV_ID_82540EP_LOM:
1230         case E1000_DEV_ID_82540EP_LP:
1231                 hw->mac_type = e1000_82540;
1232                 break;
1233         case E1000_DEV_ID_82545EM_COPPER:
1234         case E1000_DEV_ID_82545EM_FIBER:
1235                 hw->mac_type = e1000_82545;
1236                 break;
1237         case E1000_DEV_ID_82545GM_COPPER:
1238         case E1000_DEV_ID_82545GM_FIBER:
1239         case E1000_DEV_ID_82545GM_SERDES:
1240                 hw->mac_type = e1000_82545_rev_3;
1241                 break;
1242         case E1000_DEV_ID_82546EB_COPPER:
1243         case E1000_DEV_ID_82546EB_FIBER:
1244         case E1000_DEV_ID_82546EB_QUAD_COPPER:
1245                 hw->mac_type = e1000_82546;
1246                 break;
1247         case E1000_DEV_ID_82546GB_COPPER:
1248         case E1000_DEV_ID_82546GB_FIBER:
1249         case E1000_DEV_ID_82546GB_SERDES:
1250         case E1000_DEV_ID_82546GB_PCIE:
1251         case E1000_DEV_ID_82546GB_QUAD_COPPER:
1252         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1253                 hw->mac_type = e1000_82546_rev_3;
1254                 break;
1255         case E1000_DEV_ID_82541EI:
1256         case E1000_DEV_ID_82541EI_MOBILE:
1257         case E1000_DEV_ID_82541ER_LOM:
1258                 hw->mac_type = e1000_82541;
1259                 break;
1260         case E1000_DEV_ID_82541ER:
1261         case E1000_DEV_ID_82541GI:
1262         case E1000_DEV_ID_82541GI_LF:
1263         case E1000_DEV_ID_82541GI_MOBILE:
1264                 hw->mac_type = e1000_82541_rev_2;
1265                 break;
1266         case E1000_DEV_ID_82547EI:
1267         case E1000_DEV_ID_82547EI_MOBILE:
1268                 hw->mac_type = e1000_82547;
1269                 break;
1270         case E1000_DEV_ID_82547GI:
1271                 hw->mac_type = e1000_82547_rev_2;
1272                 break;
1273         case E1000_DEV_ID_82571EB_COPPER:
1274         case E1000_DEV_ID_82571EB_FIBER:
1275         case E1000_DEV_ID_82571EB_SERDES:
1276         case E1000_DEV_ID_82571EB_SERDES_DUAL:
1277         case E1000_DEV_ID_82571EB_SERDES_QUAD:
1278         case E1000_DEV_ID_82571EB_QUAD_COPPER:
1279         case E1000_DEV_ID_82571PT_QUAD_COPPER:
1280         case E1000_DEV_ID_82571EB_QUAD_FIBER:
1281         case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1282                 hw->mac_type = e1000_82571;
1283                 break;
1284         case E1000_DEV_ID_82572EI_COPPER:
1285         case E1000_DEV_ID_82572EI_FIBER:
1286         case E1000_DEV_ID_82572EI_SERDES:
1287         case E1000_DEV_ID_82572EI:
1288                 hw->mac_type = e1000_82572;
1289                 break;
1290         case E1000_DEV_ID_82573E:
1291         case E1000_DEV_ID_82573E_IAMT:
1292         case E1000_DEV_ID_82573L:
1293                 hw->mac_type = e1000_82573;
1294                 break;
1295         case E1000_DEV_ID_82574L:
1296                 hw->mac_type = e1000_82574;
1297                 break;
1298         case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1299         case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1300         case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1301         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1302                 hw->mac_type = e1000_80003es2lan;
1303                 break;
1304         case E1000_DEV_ID_ICH8_IGP_M_AMT:
1305         case E1000_DEV_ID_ICH8_IGP_AMT:
1306         case E1000_DEV_ID_ICH8_IGP_C:
1307         case E1000_DEV_ID_ICH8_IFE:
1308         case E1000_DEV_ID_ICH8_IFE_GT:
1309         case E1000_DEV_ID_ICH8_IFE_G:
1310         case E1000_DEV_ID_ICH8_IGP_M:
1311                 hw->mac_type = e1000_ich8lan;
1312                 break;
1313         default:
1314                 /* Should never have loaded on this device */
1315                 return -E1000_ERR_MAC_TYPE;
1316         }
1317         return E1000_SUCCESS;
1318 }
1319
1320 /******************************************************************************
1321  * Reset the transmit and receive units; mask and clear all interrupts.
1322  *
1323  * hw - Struct containing variables accessed by shared code
1324  *****************************************************************************/
1325 void
1326 e1000_reset_hw(struct e1000_hw *hw)
1327 {
1328         uint32_t ctrl;
1329         uint32_t ctrl_ext;
1330         uint32_t manc;
1331         uint32_t pba = 0;
1332
1333         DEBUGFUNC();
1334
1335         /* get the correct pba value for both PCI and PCIe*/
1336         if (hw->mac_type <  e1000_82571)
1337                 pba = E1000_DEFAULT_PCI_PBA;
1338         else
1339                 pba = E1000_DEFAULT_PCIE_PBA;
1340
1341         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1342         if (hw->mac_type == e1000_82542_rev2_0) {
1343                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1344                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1345                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1346         }
1347
1348         /* Clear interrupt mask to stop board from generating interrupts */
1349         DEBUGOUT("Masking off all interrupts\n");
1350         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1351
1352         /* Disable the Transmit and Receive units.  Then delay to allow
1353          * any pending transactions to complete before we hit the MAC with
1354          * the global reset.
1355          */
1356         E1000_WRITE_REG(hw, RCTL, 0);
1357         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1358         E1000_WRITE_FLUSH(hw);
1359
1360         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1361         hw->tbi_compatibility_on = false;
1362
1363         /* Delay to allow any outstanding PCI transactions to complete before
1364          * resetting the device
1365          */
1366         mdelay(10);
1367
1368         /* Issue a global reset to the MAC.  This will reset the chip's
1369          * transmit, receive, DMA, and link units.  It will not effect
1370          * the current PCI configuration.  The global reset bit is self-
1371          * clearing, and should clear within a microsecond.
1372          */
1373         DEBUGOUT("Issuing a global reset to MAC\n");
1374         ctrl = E1000_READ_REG(hw, CTRL);
1375
1376         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1377
1378         /* Force a reload from the EEPROM if necessary */
1379         if (hw->mac_type < e1000_82540) {
1380                 /* Wait for reset to complete */
1381                 udelay(10);
1382                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1383                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1384                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1385                 E1000_WRITE_FLUSH(hw);
1386                 /* Wait for EEPROM reload */
1387                 mdelay(2);
1388         } else {
1389                 /* Wait for EEPROM reload (it happens automatically) */
1390                 mdelay(4);
1391                 /* Dissable HW ARPs on ASF enabled adapters */
1392                 manc = E1000_READ_REG(hw, MANC);
1393                 manc &= ~(E1000_MANC_ARP_EN);
1394                 E1000_WRITE_REG(hw, MANC, manc);
1395         }
1396
1397         /* Clear interrupt mask to stop board from generating interrupts */
1398         DEBUGOUT("Masking off all interrupts\n");
1399         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1400
1401         /* Clear any pending interrupt events. */
1402         E1000_READ_REG(hw, ICR);
1403
1404         /* If MWI was previously enabled, reenable it. */
1405         if (hw->mac_type == e1000_82542_rev2_0) {
1406                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1407         }
1408         E1000_WRITE_REG(hw, PBA, pba);
1409 }
1410
1411 /******************************************************************************
1412  *
1413  * Initialize a number of hardware-dependent bits
1414  *
1415  * hw: Struct containing variables accessed by shared code
1416  *
1417  * This function contains hardware limitation workarounds for PCI-E adapters
1418  *
1419  *****************************************************************************/
1420 static void
1421 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1422 {
1423         if ((hw->mac_type >= e1000_82571) &&
1424                         (!hw->initialize_hw_bits_disable)) {
1425                 /* Settings common to all PCI-express silicon */
1426                 uint32_t reg_ctrl, reg_ctrl_ext;
1427                 uint32_t reg_tarc0, reg_tarc1;
1428                 uint32_t reg_tctl;
1429                 uint32_t reg_txdctl, reg_txdctl1;
1430
1431                 /* link autonegotiation/sync workarounds */
1432                 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1433                 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1434
1435                 /* Enable not-done TX descriptor counting */
1436                 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1437                 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1438                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1439
1440                 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1441                 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1442                 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1443
1444                 switch (hw->mac_type) {
1445                 case e1000_82571:
1446                 case e1000_82572:
1447                         /* Clear PHY TX compatible mode bits */
1448                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1449                         reg_tarc1 &= ~((1 << 30)|(1 << 29));
1450
1451                         /* link autonegotiation/sync workarounds */
1452                         reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1453
1454                         /* TX ring control fixes */
1455                         reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1456
1457                         /* Multiple read bit is reversed polarity */
1458                         reg_tctl = E1000_READ_REG(hw, TCTL);
1459                         if (reg_tctl & E1000_TCTL_MULR)
1460                                 reg_tarc1 &= ~(1 << 28);
1461                         else
1462                                 reg_tarc1 |= (1 << 28);
1463
1464                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1465                         break;
1466                 case e1000_82573:
1467                 case e1000_82574:
1468                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1469                         reg_ctrl_ext &= ~(1 << 23);
1470                         reg_ctrl_ext |= (1 << 22);
1471
1472                         /* TX byte count fix */
1473                         reg_ctrl = E1000_READ_REG(hw, CTRL);
1474                         reg_ctrl &= ~(1 << 29);
1475
1476                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1477                         E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1478                         break;
1479                 case e1000_80003es2lan:
1480         /* improve small packet performace for fiber/serdes */
1481                         if ((hw->media_type == e1000_media_type_fiber)
1482                         || (hw->media_type ==
1483                                 e1000_media_type_internal_serdes)) {
1484                                 reg_tarc0 &= ~(1 << 20);
1485                         }
1486
1487                 /* Multiple read bit is reversed polarity */
1488                         reg_tctl = E1000_READ_REG(hw, TCTL);
1489                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1490                         if (reg_tctl & E1000_TCTL_MULR)
1491                                 reg_tarc1 &= ~(1 << 28);
1492                         else
1493                                 reg_tarc1 |= (1 << 28);
1494
1495                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1496                         break;
1497                 case e1000_ich8lan:
1498                         /* Reduce concurrent DMA requests to 3 from 4 */
1499                         if ((hw->revision_id < 3) ||
1500                         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1501                                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1502                                 reg_tarc0 |= ((1 << 29)|(1 << 28));
1503
1504                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1505                         reg_ctrl_ext |= (1 << 22);
1506                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1507
1508                         /* workaround TX hang with TSO=on */
1509                         reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1510
1511                         /* Multiple read bit is reversed polarity */
1512                         reg_tctl = E1000_READ_REG(hw, TCTL);
1513                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1514                         if (reg_tctl & E1000_TCTL_MULR)
1515                                 reg_tarc1 &= ~(1 << 28);
1516                         else
1517                                 reg_tarc1 |= (1 << 28);
1518
1519                         /* workaround TX hang with TSO=on */
1520                         reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1521
1522                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1523                         break;
1524                 default:
1525                         break;
1526                 }
1527
1528                 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1529         }
1530 }
1531
1532 /******************************************************************************
1533  * Performs basic configuration of the adapter.
1534  *
1535  * hw - Struct containing variables accessed by shared code
1536  *
1537  * Assumes that the controller has previously been reset and is in a
1538  * post-reset uninitialized state. Initializes the receive address registers,
1539  * multicast table, and VLAN filter table. Calls routines to setup link
1540  * configuration and flow control settings. Clears all on-chip counters. Leaves
1541  * the transmit and receive units disabled and uninitialized.
1542  *****************************************************************************/
1543 static int
1544 e1000_init_hw(struct eth_device *nic)
1545 {
1546         struct e1000_hw *hw = nic->priv;
1547         uint32_t ctrl;
1548         uint32_t i;
1549         int32_t ret_val;
1550         uint16_t pcix_cmd_word;
1551         uint16_t pcix_stat_hi_word;
1552         uint16_t cmd_mmrbc;
1553         uint16_t stat_mmrbc;
1554         uint32_t mta_size;
1555         uint32_t reg_data;
1556         uint32_t ctrl_ext;
1557         DEBUGFUNC();
1558         /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1559         if ((hw->mac_type == e1000_ich8lan) &&
1560                 ((hw->revision_id < 3) ||
1561                 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1562                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1563                         reg_data = E1000_READ_REG(hw, STATUS);
1564                         reg_data &= ~0x80000000;
1565                         E1000_WRITE_REG(hw, STATUS, reg_data);
1566         }
1567         /* Do not need initialize Identification LED */
1568
1569         /* Set the media type and TBI compatibility */
1570         e1000_set_media_type(hw);
1571
1572         /* Must be called after e1000_set_media_type
1573          * because media_type is used */
1574         e1000_initialize_hardware_bits(hw);
1575
1576         /* Disabling VLAN filtering. */
1577         DEBUGOUT("Initializing the IEEE VLAN\n");
1578         /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1579         if (hw->mac_type != e1000_ich8lan) {
1580                 if (hw->mac_type < e1000_82545_rev_3)
1581                         E1000_WRITE_REG(hw, VET, 0);
1582                 e1000_clear_vfta(hw);
1583         }
1584
1585         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1586         if (hw->mac_type == e1000_82542_rev2_0) {
1587                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1588                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1589                                       hw->
1590                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1591                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1592                 E1000_WRITE_FLUSH(hw);
1593                 mdelay(5);
1594         }
1595
1596         /* Setup the receive address. This involves initializing all of the Receive
1597          * Address Registers (RARs 0 - 15).
1598          */
1599         e1000_init_rx_addrs(nic);
1600
1601         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1602         if (hw->mac_type == e1000_82542_rev2_0) {
1603                 E1000_WRITE_REG(hw, RCTL, 0);
1604                 E1000_WRITE_FLUSH(hw);
1605                 mdelay(1);
1606                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1607         }
1608
1609         /* Zero out the Multicast HASH table */
1610         DEBUGOUT("Zeroing the MTA\n");
1611         mta_size = E1000_MC_TBL_SIZE;
1612         if (hw->mac_type == e1000_ich8lan)
1613                 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1614         for (i = 0; i < mta_size; i++) {
1615                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1616                 /* use write flush to prevent Memory Write Block (MWB) from
1617                  * occuring when accessing our register space */
1618                 E1000_WRITE_FLUSH(hw);
1619         }
1620 #if 0
1621         /* Set the PCI priority bit correctly in the CTRL register.  This
1622          * determines if the adapter gives priority to receives, or if it
1623          * gives equal priority to transmits and receives.  Valid only on
1624          * 82542 and 82543 silicon.
1625          */
1626         if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1627                 ctrl = E1000_READ_REG(hw, CTRL);
1628                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1629         }
1630 #endif
1631         switch (hw->mac_type) {
1632         case e1000_82545_rev_3:
1633         case e1000_82546_rev_3:
1634                 break;
1635         default:
1636         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1637         if (hw->bus_type == e1000_bus_type_pcix) {
1638                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1639                                      &pcix_cmd_word);
1640                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1641                                      &pcix_stat_hi_word);
1642                 cmd_mmrbc =
1643                     (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1644                     PCIX_COMMAND_MMRBC_SHIFT;
1645                 stat_mmrbc =
1646                     (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1647                     PCIX_STATUS_HI_MMRBC_SHIFT;
1648                 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1649                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1650                 if (cmd_mmrbc > stat_mmrbc) {
1651                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1652                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1653                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1654                                               pcix_cmd_word);
1655                 }
1656         }
1657                 break;
1658         }
1659
1660         /* More time needed for PHY to initialize */
1661         if (hw->mac_type == e1000_ich8lan)
1662                 mdelay(15);
1663
1664         /* Call a subroutine to configure the link and setup flow control. */
1665         ret_val = e1000_setup_link(nic);
1666
1667         /* Set the transmit descriptor write-back policy */
1668         if (hw->mac_type > e1000_82544) {
1669                 ctrl = E1000_READ_REG(hw, TXDCTL);
1670                 ctrl =
1671                     (ctrl & ~E1000_TXDCTL_WTHRESH) |
1672                     E1000_TXDCTL_FULL_TX_DESC_WB;
1673                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1674         }
1675
1676         /* Set the receive descriptor write back policy */
1677
1678         if (hw->mac_type >= e1000_82571) {
1679                 ctrl = E1000_READ_REG(hw, RXDCTL);
1680                 ctrl =
1681                     (ctrl & ~E1000_RXDCTL_WTHRESH) |
1682                     E1000_RXDCTL_FULL_RX_DESC_WB;
1683                 E1000_WRITE_REG(hw, RXDCTL, ctrl);
1684         }
1685
1686         switch (hw->mac_type) {
1687         default:
1688                 break;
1689         case e1000_80003es2lan:
1690                 /* Enable retransmit on late collisions */
1691                 reg_data = E1000_READ_REG(hw, TCTL);
1692                 reg_data |= E1000_TCTL_RTLC;
1693                 E1000_WRITE_REG(hw, TCTL, reg_data);
1694
1695                 /* Configure Gigabit Carry Extend Padding */
1696                 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1697                 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1698                 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1699                 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1700
1701                 /* Configure Transmit Inter-Packet Gap */
1702                 reg_data = E1000_READ_REG(hw, TIPG);
1703                 reg_data &= ~E1000_TIPG_IPGT_MASK;
1704                 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1705                 E1000_WRITE_REG(hw, TIPG, reg_data);
1706
1707                 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1708                 reg_data &= ~0x00100000;
1709                 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1710                 /* Fall through */
1711         case e1000_82571:
1712         case e1000_82572:
1713         case e1000_ich8lan:
1714                 ctrl = E1000_READ_REG(hw, TXDCTL1);
1715                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1716                         | E1000_TXDCTL_FULL_TX_DESC_WB;
1717                 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1718                 break;
1719         case e1000_82573:
1720         case e1000_82574:
1721                 reg_data = E1000_READ_REG(hw, GCR);
1722                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1723                 E1000_WRITE_REG(hw, GCR, reg_data);
1724         }
1725
1726 #if 0
1727         /* Clear all of the statistics registers (clear on read).  It is
1728          * important that we do this after we have tried to establish link
1729          * because the symbol error count will increment wildly if there
1730          * is no link.
1731          */
1732         e1000_clear_hw_cntrs(hw);
1733
1734         /* ICH8 No-snoop bits are opposite polarity.
1735          * Set to snoop by default after reset. */
1736         if (hw->mac_type == e1000_ich8lan)
1737                 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1738 #endif
1739
1740         if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1741                 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1742                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1743                 /* Relaxed ordering must be disabled to avoid a parity
1744                  * error crash in a PCI slot. */
1745                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1746                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1747         }
1748
1749         return ret_val;
1750 }
1751
1752 /******************************************************************************
1753  * Configures flow control and link settings.
1754  *
1755  * hw - Struct containing variables accessed by shared code
1756  *
1757  * Determines which flow control settings to use. Calls the apropriate media-
1758  * specific link configuration function. Configures the flow control settings.
1759  * Assuming the adapter has a valid link partner, a valid link should be
1760  * established. Assumes the hardware has previously been reset and the
1761  * transmitter and receiver are not enabled.
1762  *****************************************************************************/
1763 static int
1764 e1000_setup_link(struct eth_device *nic)
1765 {
1766         struct e1000_hw *hw = nic->priv;
1767         uint32_t ctrl_ext;
1768         int32_t ret_val;
1769         uint16_t eeprom_data;
1770
1771         DEBUGFUNC();
1772
1773         /* In the case of the phy reset being blocked, we already have a link.
1774          * We do not have to set it up again. */
1775         if (e1000_check_phy_reset_block(hw))
1776                 return E1000_SUCCESS;
1777
1778         /* Read and store word 0x0F of the EEPROM. This word contains bits
1779          * that determine the hardware's default PAUSE (flow control) mode,
1780          * a bit that determines whether the HW defaults to enabling or
1781          * disabling auto-negotiation, and the direction of the
1782          * SW defined pins. If there is no SW over-ride of the flow
1783          * control setting, then the variable hw->fc will
1784          * be initialized based on a value in the EEPROM.
1785          */
1786         if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1787                                 &eeprom_data) < 0) {
1788                 DEBUGOUT("EEPROM Read Error\n");
1789                 return -E1000_ERR_EEPROM;
1790         }
1791
1792         if (hw->fc == e1000_fc_default) {
1793                 switch (hw->mac_type) {
1794                 case e1000_ich8lan:
1795                 case e1000_82573:
1796                 case e1000_82574:
1797                         hw->fc = e1000_fc_full;
1798                         break;
1799                 default:
1800                         ret_val = e1000_read_eeprom(hw,
1801                                 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1802                         if (ret_val) {
1803                                 DEBUGOUT("EEPROM Read Error\n");
1804                                 return -E1000_ERR_EEPROM;
1805                         }
1806                         if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1807                                 hw->fc = e1000_fc_none;
1808                         else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1809                                     EEPROM_WORD0F_ASM_DIR)
1810                                 hw->fc = e1000_fc_tx_pause;
1811                         else
1812                                 hw->fc = e1000_fc_full;
1813                         break;
1814                 }
1815         }
1816
1817         /* We want to save off the original Flow Control configuration just
1818          * in case we get disconnected and then reconnected into a different
1819          * hub or switch with different Flow Control capabilities.
1820          */
1821         if (hw->mac_type == e1000_82542_rev2_0)
1822                 hw->fc &= (~e1000_fc_tx_pause);
1823
1824         if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1825                 hw->fc &= (~e1000_fc_rx_pause);
1826
1827         hw->original_fc = hw->fc;
1828
1829         DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1830
1831         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1832          * polarity value for the SW controlled pins, and setup the
1833          * Extended Device Control reg with that info.
1834          * This is needed because one of the SW controlled pins is used for
1835          * signal detection.  So this should be done before e1000_setup_pcs_link()
1836          * or e1000_phy_setup() is called.
1837          */
1838         if (hw->mac_type == e1000_82543) {
1839                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1840                             SWDPIO__EXT_SHIFT);
1841                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1842         }
1843
1844         /* Call the necessary subroutine to configure the link. */
1845         ret_val = (hw->media_type == e1000_media_type_fiber) ?
1846             e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1847         if (ret_val < 0) {
1848                 return ret_val;
1849         }
1850
1851         /* Initialize the flow control address, type, and PAUSE timer
1852          * registers to their default values.  This is done even if flow
1853          * control is disabled, because it does not hurt anything to
1854          * initialize these registers.
1855          */
1856         DEBUGOUT("Initializing the Flow Control address, type"
1857                         "and timer regs\n");
1858
1859         /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1860         if (hw->mac_type != e1000_ich8lan) {
1861                 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1862                 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1863                 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1864         }
1865
1866         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1867
1868         /* Set the flow control receive threshold registers.  Normally,
1869          * these registers will be set to a default threshold that may be
1870          * adjusted later by the driver's runtime code.  However, if the
1871          * ability to transmit pause frames in not enabled, then these
1872          * registers will be set to 0.
1873          */
1874         if (!(hw->fc & e1000_fc_tx_pause)) {
1875                 E1000_WRITE_REG(hw, FCRTL, 0);
1876                 E1000_WRITE_REG(hw, FCRTH, 0);
1877         } else {
1878                 /* We need to set up the Receive Threshold high and low water marks
1879                  * as well as (optionally) enabling the transmission of XON frames.
1880                  */
1881                 if (hw->fc_send_xon) {
1882                         E1000_WRITE_REG(hw, FCRTL,
1883                                         (hw->fc_low_water | E1000_FCRTL_XONE));
1884                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1885                 } else {
1886                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1887                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1888                 }
1889         }
1890         return ret_val;
1891 }
1892
1893 /******************************************************************************
1894  * Sets up link for a fiber based adapter
1895  *
1896  * hw - Struct containing variables accessed by shared code
1897  *
1898  * Manipulates Physical Coding Sublayer functions in order to configure
1899  * link. Assumes the hardware has been previously reset and the transmitter
1900  * and receiver are not enabled.
1901  *****************************************************************************/
1902 static int
1903 e1000_setup_fiber_link(struct eth_device *nic)
1904 {
1905         struct e1000_hw *hw = nic->priv;
1906         uint32_t ctrl;
1907         uint32_t status;
1908         uint32_t txcw = 0;
1909         uint32_t i;
1910         uint32_t signal;
1911         int32_t ret_val;
1912
1913         DEBUGFUNC();
1914         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1915          * set when the optics detect a signal. On older adapters, it will be
1916          * cleared when there is a signal
1917          */
1918         ctrl = E1000_READ_REG(hw, CTRL);
1919         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1920                 signal = E1000_CTRL_SWDPIN1;
1921         else
1922                 signal = 0;
1923
1924         printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
1925                ctrl);
1926         /* Take the link out of reset */
1927         ctrl &= ~(E1000_CTRL_LRST);
1928
1929         e1000_config_collision_dist(hw);
1930
1931         /* Check for a software override of the flow control settings, and setup
1932          * the device accordingly.  If auto-negotiation is enabled, then software
1933          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1934          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
1935          * auto-negotiation is disabled, then software will have to manually
1936          * configure the two flow control enable bits in the CTRL register.
1937          *
1938          * The possible values of the "fc" parameter are:
1939          *      0:  Flow control is completely disabled
1940          *      1:  Rx flow control is enabled (we can receive pause frames, but
1941          *          not send pause frames).
1942          *      2:  Tx flow control is enabled (we can send pause frames but we do
1943          *          not support receiving pause frames).
1944          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1945          */
1946         switch (hw->fc) {
1947         case e1000_fc_none:
1948                 /* Flow control is completely disabled by a software over-ride. */
1949                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1950                 break;
1951         case e1000_fc_rx_pause:
1952                 /* RX Flow control is enabled and TX Flow control is disabled by a
1953                  * software over-ride. Since there really isn't a way to advertise
1954                  * that we are capable of RX Pause ONLY, we will advertise that we
1955                  * support both symmetric and asymmetric RX PAUSE. Later, we will
1956                  *  disable the adapter's ability to send PAUSE frames.
1957                  */
1958                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1959                 break;
1960         case e1000_fc_tx_pause:
1961                 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1962                  * software over-ride.
1963                  */
1964                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1965                 break;
1966         case e1000_fc_full:
1967                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1968                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1969                 break;
1970         default:
1971                 DEBUGOUT("Flow control param set incorrectly\n");
1972                 return -E1000_ERR_CONFIG;
1973                 break;
1974         }
1975
1976         /* Since auto-negotiation is enabled, take the link out of reset (the link
1977          * will be in reset, because we previously reset the chip). This will
1978          * restart auto-negotiation.  If auto-neogtiation is successful then the
1979          * link-up status bit will be set and the flow control enable bits (RFCE
1980          * and TFCE) will be set according to their negotiated value.
1981          */
1982         DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
1983
1984         E1000_WRITE_REG(hw, TXCW, txcw);
1985         E1000_WRITE_REG(hw, CTRL, ctrl);
1986         E1000_WRITE_FLUSH(hw);
1987
1988         hw->txcw = txcw;
1989         mdelay(1);
1990
1991         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1992          * indication in the Device Status Register.  Time-out if a link isn't
1993          * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1994          * less than 500 milliseconds even if the other end is doing it in SW).
1995          */
1996         if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1997                 DEBUGOUT("Looking for Link\n");
1998                 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1999                         mdelay(10);
2000                         status = E1000_READ_REG(hw, STATUS);
2001                         if (status & E1000_STATUS_LU)
2002                                 break;
2003                 }
2004                 if (i == (LINK_UP_TIMEOUT / 10)) {
2005                         /* AutoNeg failed to achieve a link, so we'll call
2006                          * e1000_check_for_link. This routine will force the link up if we
2007                          * detect a signal. This will allow us to communicate with
2008                          * non-autonegotiating link partners.
2009                          */
2010                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2011                         hw->autoneg_failed = 1;
2012                         ret_val = e1000_check_for_link(nic);
2013                         if (ret_val < 0) {
2014                                 DEBUGOUT("Error while checking for link\n");
2015                                 return ret_val;
2016                         }
2017                         hw->autoneg_failed = 0;
2018                 } else {
2019                         hw->autoneg_failed = 0;
2020                         DEBUGOUT("Valid Link Found\n");
2021                 }
2022         } else {
2023                 DEBUGOUT("No Signal Detected\n");
2024                 return -E1000_ERR_NOLINK;
2025         }
2026         return 0;
2027 }
2028
2029 /******************************************************************************
2030 * Make sure we have a valid PHY and change PHY mode before link setup.
2031 *
2032 * hw - Struct containing variables accessed by shared code
2033 ******************************************************************************/
2034 static int32_t
2035 e1000_copper_link_preconfig(struct e1000_hw *hw)
2036 {
2037         uint32_t ctrl;
2038         int32_t ret_val;
2039         uint16_t phy_data;
2040
2041         DEBUGFUNC();
2042
2043         ctrl = E1000_READ_REG(hw, CTRL);
2044         /* With 82543, we need to force speed and duplex on the MAC equal to what
2045          * the PHY speed and duplex configuration is. In addition, we need to
2046          * perform a hardware reset on the PHY to take it out of reset.
2047          */
2048         if (hw->mac_type > e1000_82543) {
2049                 ctrl |= E1000_CTRL_SLU;
2050                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2051                 E1000_WRITE_REG(hw, CTRL, ctrl);
2052         } else {
2053                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2054                                 | E1000_CTRL_SLU);
2055                 E1000_WRITE_REG(hw, CTRL, ctrl);
2056                 ret_val = e1000_phy_hw_reset(hw);
2057                 if (ret_val)
2058                         return ret_val;
2059         }
2060
2061         /* Make sure we have a valid PHY */
2062         ret_val = e1000_detect_gig_phy(hw);
2063         if (ret_val) {
2064                 DEBUGOUT("Error, did not detect valid phy.\n");
2065                 return ret_val;
2066         }
2067         DEBUGOUT("Phy ID = %x \n", hw->phy_id);
2068
2069         /* Set PHY to class A mode (if necessary) */
2070         ret_val = e1000_set_phy_mode(hw);
2071         if (ret_val)
2072                 return ret_val;
2073         if ((hw->mac_type == e1000_82545_rev_3) ||
2074                 (hw->mac_type == e1000_82546_rev_3)) {
2075                 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2076                                 &phy_data);
2077                 phy_data |= 0x00000008;
2078                 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2079                                 phy_data);
2080         }
2081
2082         if (hw->mac_type <= e1000_82543 ||
2083                 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2084                 hw->mac_type == e1000_82541_rev_2
2085                 || hw->mac_type == e1000_82547_rev_2)
2086                         hw->phy_reset_disable = false;
2087
2088         return E1000_SUCCESS;
2089 }
2090
2091 /*****************************************************************************
2092  *
2093  * This function sets the lplu state according to the active flag.  When
2094  * activating lplu this function also disables smart speed and vise versa.
2095  * lplu will not be activated unless the device autonegotiation advertisment
2096  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2097  * hw: Struct containing variables accessed by shared code
2098  * active - true to enable lplu false to disable lplu.
2099  *
2100  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2101  *            E1000_SUCCESS at any other case.
2102  *
2103  ****************************************************************************/
2104
2105 static int32_t
2106 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2107 {
2108         uint32_t phy_ctrl = 0;
2109         int32_t ret_val;
2110         uint16_t phy_data;
2111         DEBUGFUNC();
2112
2113         if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2114             && hw->phy_type != e1000_phy_igp_3)
2115                 return E1000_SUCCESS;
2116
2117         /* During driver activity LPLU should not be used or it will attain link
2118          * from the lowest speeds starting from 10Mbps. The capability is used
2119          * for Dx transitions and states */
2120         if (hw->mac_type == e1000_82541_rev_2
2121                         || hw->mac_type == e1000_82547_rev_2) {
2122                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2123                                 &phy_data);
2124                 if (ret_val)
2125                         return ret_val;
2126         } else if (hw->mac_type == e1000_ich8lan) {
2127                 /* MAC writes into PHY register based on the state transition
2128                  * and start auto-negotiation. SW driver can overwrite the
2129                  * settings in CSR PHY power control E1000_PHY_CTRL register. */
2130                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2131         } else {
2132                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2133                                 &phy_data);
2134                 if (ret_val)
2135                         return ret_val;
2136         }
2137
2138         if (!active) {
2139                 if (hw->mac_type == e1000_82541_rev_2 ||
2140                         hw->mac_type == e1000_82547_rev_2) {
2141                         phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2142                         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2143                                         phy_data);
2144                         if (ret_val)
2145                                 return ret_val;
2146                 } else {
2147                         if (hw->mac_type == e1000_ich8lan) {
2148                                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2149                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2150                         } else {
2151                                 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2152                                 ret_val = e1000_write_phy_reg(hw,
2153                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2154                                 if (ret_val)
2155                                         return ret_val;
2156                         }
2157                 }
2158
2159         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2160          * Dx states where the power conservation is most important.  During
2161          * driver activity we should enable SmartSpeed, so performance is
2162          * maintained. */
2163                 if (hw->smart_speed == e1000_smart_speed_on) {
2164                         ret_val = e1000_read_phy_reg(hw,
2165                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2166                         if (ret_val)
2167                                 return ret_val;
2168
2169                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2170                         ret_val = e1000_write_phy_reg(hw,
2171                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2172                         if (ret_val)
2173                                 return ret_val;
2174                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2175                         ret_val = e1000_read_phy_reg(hw,
2176                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2177                         if (ret_val)
2178                                 return ret_val;
2179
2180                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2181                         ret_val = e1000_write_phy_reg(hw,
2182                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2183                         if (ret_val)
2184                                 return ret_val;
2185                 }
2186
2187         } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2188                 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2189                 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2190
2191                 if (hw->mac_type == e1000_82541_rev_2 ||
2192                     hw->mac_type == e1000_82547_rev_2) {
2193                         phy_data |= IGP01E1000_GMII_FLEX_SPD;
2194                         ret_val = e1000_write_phy_reg(hw,
2195                                         IGP01E1000_GMII_FIFO, phy_data);
2196                         if (ret_val)
2197                                 return ret_val;
2198                 } else {
2199                         if (hw->mac_type == e1000_ich8lan) {
2200                                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2201                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2202                         } else {
2203                                 phy_data |= IGP02E1000_PM_D3_LPLU;
2204                                 ret_val = e1000_write_phy_reg(hw,
2205                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2206                                 if (ret_val)
2207                                         return ret_val;
2208                         }
2209                 }
2210
2211                 /* When LPLU is enabled we should disable SmartSpeed */
2212                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2213                                 &phy_data);
2214                 if (ret_val)
2215                         return ret_val;
2216
2217                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2218                 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2219                                 phy_data);
2220                 if (ret_val)
2221                         return ret_val;
2222         }
2223         return E1000_SUCCESS;
2224 }
2225
2226 /*****************************************************************************
2227  *
2228  * This function sets the lplu d0 state according to the active flag.  When
2229  * activating lplu this function also disables smart speed and vise versa.
2230  * lplu will not be activated unless the device autonegotiation advertisment
2231  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2232  * hw: Struct containing variables accessed by shared code
2233  * active - true to enable lplu false to disable lplu.
2234  *
2235  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2236  *            E1000_SUCCESS at any other case.
2237  *
2238  ****************************************************************************/
2239
2240 static int32_t
2241 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2242 {
2243         uint32_t phy_ctrl = 0;
2244         int32_t ret_val;
2245         uint16_t phy_data;
2246         DEBUGFUNC();
2247
2248         if (hw->mac_type <= e1000_82547_rev_2)
2249                 return E1000_SUCCESS;
2250
2251         if (hw->mac_type == e1000_ich8lan) {
2252                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2253         } else {
2254                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2255                                 &phy_data);
2256                 if (ret_val)
2257                         return ret_val;
2258         }
2259
2260         if (!active) {
2261                 if (hw->mac_type == e1000_ich8lan) {
2262                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2263                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2264                 } else {
2265                         phy_data &= ~IGP02E1000_PM_D0_LPLU;
2266                         ret_val = e1000_write_phy_reg(hw,
2267                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2268                         if (ret_val)
2269                                 return ret_val;
2270                 }
2271
2272         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2273          * Dx states where the power conservation is most important.  During
2274          * driver activity we should enable SmartSpeed, so performance is
2275          * maintained. */
2276                 if (hw->smart_speed == e1000_smart_speed_on) {
2277                         ret_val = e1000_read_phy_reg(hw,
2278                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2279                         if (ret_val)
2280                                 return ret_val;
2281
2282                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2283                         ret_val = e1000_write_phy_reg(hw,
2284                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2285                         if (ret_val)
2286                                 return ret_val;
2287                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2288                         ret_val = e1000_read_phy_reg(hw,
2289                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2290                         if (ret_val)
2291                                 return ret_val;
2292
2293                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2294                         ret_val = e1000_write_phy_reg(hw,
2295                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2296                         if (ret_val)
2297                                 return ret_val;
2298                 }
2299
2300
2301         } else {
2302
2303                 if (hw->mac_type == e1000_ich8lan) {
2304                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2305                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2306                 } else {
2307                         phy_data |= IGP02E1000_PM_D0_LPLU;
2308                         ret_val = e1000_write_phy_reg(hw,
2309                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2310                         if (ret_val)
2311                                 return ret_val;
2312                 }
2313
2314                 /* When LPLU is enabled we should disable SmartSpeed */
2315                 ret_val = e1000_read_phy_reg(hw,
2316                                 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2317                 if (ret_val)
2318                         return ret_val;
2319
2320                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2321                 ret_val = e1000_write_phy_reg(hw,
2322                                 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2323                 if (ret_val)
2324                         return ret_val;
2325
2326         }
2327         return E1000_SUCCESS;
2328 }
2329
2330 /********************************************************************
2331 * Copper link setup for e1000_phy_igp series.
2332 *
2333 * hw - Struct containing variables accessed by shared code
2334 *********************************************************************/
2335 static int32_t
2336 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2337 {
2338         uint32_t led_ctrl;
2339         int32_t ret_val;
2340         uint16_t phy_data;
2341
2342         DEBUGFUNC();
2343
2344         if (hw->phy_reset_disable)
2345                 return E1000_SUCCESS;
2346
2347         ret_val = e1000_phy_reset(hw);
2348         if (ret_val) {
2349                 DEBUGOUT("Error Resetting the PHY\n");
2350                 return ret_val;
2351         }
2352
2353         /* Wait 15ms for MAC to configure PHY from eeprom settings */
2354         mdelay(15);
2355         if (hw->mac_type != e1000_ich8lan) {
2356                 /* Configure activity LED after PHY reset */
2357                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2358                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2359                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2360                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2361         }
2362
2363         /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2364         if (hw->phy_type == e1000_phy_igp) {
2365                 /* disable lplu d3 during driver init */
2366                 ret_val = e1000_set_d3_lplu_state(hw, false);
2367                 if (ret_val) {
2368                         DEBUGOUT("Error Disabling LPLU D3\n");
2369                         return ret_val;
2370                 }
2371         }
2372
2373         /* disable lplu d0 during driver init */
2374         ret_val = e1000_set_d0_lplu_state(hw, false);
2375         if (ret_val) {
2376                 DEBUGOUT("Error Disabling LPLU D0\n");
2377                 return ret_val;
2378         }
2379         /* Configure mdi-mdix settings */
2380         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2381         if (ret_val)
2382                 return ret_val;
2383
2384         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2385                 hw->dsp_config_state = e1000_dsp_config_disabled;
2386                 /* Force MDI for earlier revs of the IGP PHY */
2387                 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2388                                 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2389                 hw->mdix = 1;
2390
2391         } else {
2392                 hw->dsp_config_state = e1000_dsp_config_enabled;
2393                 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2394
2395                 switch (hw->mdix) {
2396                 case 1:
2397                         phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2398                         break;
2399                 case 2:
2400                         phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2401                         break;
2402                 case 0:
2403                 default:
2404                         phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2405                         break;
2406                 }
2407         }
2408         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2409         if (ret_val)
2410                 return ret_val;
2411
2412         /* set auto-master slave resolution settings */
2413         if (hw->autoneg) {
2414                 e1000_ms_type phy_ms_setting = hw->master_slave;
2415
2416                 if (hw->ffe_config_state == e1000_ffe_config_active)
2417                         hw->ffe_config_state = e1000_ffe_config_enabled;
2418
2419                 if (hw->dsp_config_state == e1000_dsp_config_activated)
2420                         hw->dsp_config_state = e1000_dsp_config_enabled;
2421
2422                 /* when autonegotiation advertisment is only 1000Mbps then we
2423                   * should disable SmartSpeed and enable Auto MasterSlave
2424                   * resolution as hardware default. */
2425                 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2426                         /* Disable SmartSpeed */
2427                         ret_val = e1000_read_phy_reg(hw,
2428                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2429                         if (ret_val)
2430                                 return ret_val;
2431                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2432                         ret_val = e1000_write_phy_reg(hw,
2433                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2434                         if (ret_val)
2435                                 return ret_val;
2436                         /* Set auto Master/Slave resolution process */
2437                         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2438                                         &phy_data);
2439                         if (ret_val)
2440                                 return ret_val;
2441                         phy_data &= ~CR_1000T_MS_ENABLE;
2442                         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2443                                         phy_data);
2444                         if (ret_val)
2445                                 return ret_val;
2446                 }
2447
2448                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2449                 if (ret_val)
2450                         return ret_val;
2451
2452                 /* load defaults for future use */
2453                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2454                                 ((phy_data & CR_1000T_MS_VALUE) ?
2455                                 e1000_ms_force_master :
2456                                 e1000_ms_force_slave) :
2457                                 e1000_ms_auto;
2458
2459                 switch (phy_ms_setting) {
2460                 case e1000_ms_force_master:
2461                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2462                         break;
2463                 case e1000_ms_force_slave:
2464                         phy_data |= CR_1000T_MS_ENABLE;
2465                         phy_data &= ~(CR_1000T_MS_VALUE);
2466                         break;
2467                 case e1000_ms_auto:
2468                         phy_data &= ~CR_1000T_MS_ENABLE;
2469                 default:
2470                         break;
2471                 }
2472                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2473                 if (ret_val)
2474                         return ret_val;
2475         }
2476
2477         return E1000_SUCCESS;
2478 }
2479
2480 /*****************************************************************************
2481  * This function checks the mode of the firmware.
2482  *
2483  * returns  - true when the mode is IAMT or false.
2484  ****************************************************************************/
2485 bool
2486 e1000_check_mng_mode(struct e1000_hw *hw)
2487 {
2488         uint32_t fwsm;
2489         DEBUGFUNC();
2490
2491         fwsm = E1000_READ_REG(hw, FWSM);
2492
2493         if (hw->mac_type == e1000_ich8lan) {
2494                 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2495                     (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2496                         return true;
2497         } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2498                        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2499                         return true;
2500
2501         return false;
2502 }
2503
2504 static int32_t
2505 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2506 {
2507         uint16_t swfw = E1000_SWFW_PHY0_SM;
2508         uint32_t reg_val;
2509         DEBUGFUNC();
2510
2511         if (e1000_is_second_port(hw))
2512                 swfw = E1000_SWFW_PHY1_SM;
2513
2514         if (e1000_swfw_sync_acquire(hw, swfw))
2515                 return -E1000_ERR_SWFW_SYNC;
2516
2517         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2518                         & E1000_KUMCTRLSTA_OFFSET) | data;
2519         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2520         udelay(2);
2521
2522         return E1000_SUCCESS;
2523 }
2524
2525 static int32_t
2526 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2527 {
2528         uint16_t swfw = E1000_SWFW_PHY0_SM;
2529         uint32_t reg_val;
2530         DEBUGFUNC();
2531
2532         if (e1000_is_second_port(hw))
2533                 swfw = E1000_SWFW_PHY1_SM;
2534
2535         if (e1000_swfw_sync_acquire(hw, swfw))
2536                 return -E1000_ERR_SWFW_SYNC;
2537
2538         /* Write register address */
2539         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2540                         E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2541         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2542         udelay(2);
2543
2544         /* Read the data returned */
2545         reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2546         *data = (uint16_t)reg_val;
2547
2548         return E1000_SUCCESS;
2549 }
2550
2551 /********************************************************************
2552 * Copper link setup for e1000_phy_gg82563 series.
2553 *
2554 * hw - Struct containing variables accessed by shared code
2555 *********************************************************************/
2556 static int32_t
2557 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2558 {
2559         int32_t ret_val;
2560         uint16_t phy_data;
2561         uint32_t reg_data;
2562
2563         DEBUGFUNC();
2564
2565         if (!hw->phy_reset_disable) {
2566                 /* Enable CRS on TX for half-duplex operation. */
2567                 ret_val = e1000_read_phy_reg(hw,
2568                                 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2569                 if (ret_val)
2570                         return ret_val;
2571
2572                 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2573                 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2574                 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2575
2576                 ret_val = e1000_write_phy_reg(hw,
2577                                 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2578                 if (ret_val)
2579                         return ret_val;
2580
2581                 /* Options:
2582                  *   MDI/MDI-X = 0 (default)
2583                  *   0 - Auto for all speeds
2584                  *   1 - MDI mode
2585                  *   2 - MDI-X mode
2586                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2587                  */
2588                 ret_val = e1000_read_phy_reg(hw,
2589                                 GG82563_PHY_SPEC_CTRL, &phy_data);
2590                 if (ret_val)
2591                         return ret_val;
2592
2593                 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2594
2595                 switch (hw->mdix) {
2596                 case 1:
2597                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2598                         break;
2599                 case 2:
2600                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2601                         break;
2602                 case 0:
2603                 default:
2604                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2605                         break;
2606                 }
2607
2608                 /* Options:
2609                  *   disable_polarity_correction = 0 (default)
2610                  *       Automatic Correction for Reversed Cable Polarity
2611                  *   0 - Disabled
2612                  *   1 - Enabled
2613                  */
2614                 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2615                 ret_val = e1000_write_phy_reg(hw,
2616                                 GG82563_PHY_SPEC_CTRL, phy_data);
2617
2618                 if (ret_val)
2619                         return ret_val;
2620
2621                 /* SW Reset the PHY so all changes take effect */
2622                 ret_val = e1000_phy_reset(hw);
2623                 if (ret_val) {
2624                         DEBUGOUT("Error Resetting the PHY\n");
2625                         return ret_val;
2626                 }
2627         } /* phy_reset_disable */
2628
2629         if (hw->mac_type == e1000_80003es2lan) {
2630                 /* Bypass RX and TX FIFO's */
2631                 ret_val = e1000_write_kmrn_reg(hw,
2632                                 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2633                                 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2634                                 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2635                 if (ret_val)
2636                         return ret_val;
2637
2638                 ret_val = e1000_read_phy_reg(hw,
2639                                 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2640                 if (ret_val)
2641                         return ret_val;
2642
2643                 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2644                 ret_val = e1000_write_phy_reg(hw,
2645                                 GG82563_PHY_SPEC_CTRL_2, phy_data);
2646
2647                 if (ret_val)
2648                         return ret_val;
2649
2650                 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2651                 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2652                 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2653
2654                 ret_val = e1000_read_phy_reg(hw,
2655                                 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2656                 if (ret_val)
2657                         return ret_val;
2658
2659         /* Do not init these registers when the HW is in IAMT mode, since the
2660          * firmware will have already initialized them.  We only initialize
2661          * them if the HW is not in IAMT mode.
2662          */
2663                 if (e1000_check_mng_mode(hw) == false) {
2664                         /* Enable Electrical Idle on the PHY */
2665                         phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2666                         ret_val = e1000_write_phy_reg(hw,
2667                                         GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2668                         if (ret_val)
2669                                 return ret_val;
2670
2671                         ret_val = e1000_read_phy_reg(hw,
2672                                         GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2673                         if (ret_val)
2674                                 return ret_val;
2675
2676                         phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2677                         ret_val = e1000_write_phy_reg(hw,
2678                                         GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2679
2680                         if (ret_val)
2681                                 return ret_val;
2682                 }
2683
2684                 /* Workaround: Disable padding in Kumeran interface in the MAC
2685                  * and in the PHY to avoid CRC errors.
2686                  */
2687                 ret_val = e1000_read_phy_reg(hw,
2688                                 GG82563_PHY_INBAND_CTRL, &phy_data);
2689                 if (ret_val)
2690                         return ret_val;
2691                 phy_data |= GG82563_ICR_DIS_PADDING;
2692                 ret_val = e1000_write_phy_reg(hw,
2693                                 GG82563_PHY_INBAND_CTRL, phy_data);
2694                 if (ret_val)
2695                         return ret_val;
2696         }
2697         return E1000_SUCCESS;
2698 }
2699
2700 /********************************************************************
2701 * Copper link setup for e1000_phy_m88 series.
2702 *
2703 * hw - Struct containing variables accessed by shared code
2704 *********************************************************************/
2705 static int32_t
2706 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2707 {
2708         int32_t ret_val;
2709         uint16_t phy_data;
2710
2711         DEBUGFUNC();
2712
2713         if (hw->phy_reset_disable)
2714                 return E1000_SUCCESS;
2715
2716         /* Enable CRS on TX. This must be set for half-duplex operation. */
2717         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2718         if (ret_val)
2719                 return ret_val;
2720
2721         phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2722
2723         /* Options:
2724          *   MDI/MDI-X = 0 (default)
2725          *   0 - Auto for all speeds
2726          *   1 - MDI mode
2727          *   2 - MDI-X mode
2728          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2729          */
2730         phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2731
2732         switch (hw->mdix) {
2733         case 1:
2734                 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2735                 break;
2736         case 2:
2737                 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2738                 break;
2739         case 3:
2740                 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2741                 break;
2742         case 0:
2743         default:
2744                 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2745                 break;
2746         }
2747
2748         /* Options:
2749          *   disable_polarity_correction = 0 (default)
2750          *       Automatic Correction for Reversed Cable Polarity
2751          *   0 - Disabled
2752          *   1 - Enabled
2753          */
2754         phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2755         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2756         if (ret_val)
2757                 return ret_val;
2758
2759         if (hw->phy_revision < M88E1011_I_REV_4) {
2760                 /* Force TX_CLK in the Extended PHY Specific Control Register
2761                  * to 25MHz clock.
2762                  */
2763                 ret_val = e1000_read_phy_reg(hw,
2764                                 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2765                 if (ret_val)
2766                         return ret_val;
2767
2768                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2769
2770                 if ((hw->phy_revision == E1000_REVISION_2) &&
2771                         (hw->phy_id == M88E1111_I_PHY_ID)) {
2772                         /* Vidalia Phy, set the downshift counter to 5x */
2773                         phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2774                         phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2775                         ret_val = e1000_write_phy_reg(hw,
2776                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2777                         if (ret_val)
2778                                 return ret_val;
2779                 } else {
2780                         /* Configure Master and Slave downshift values */
2781                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2782                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2783                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2784                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2785                         ret_val = e1000_write_phy_reg(hw,
2786                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2787                         if (ret_val)
2788                                 return ret_val;
2789                 }
2790         }
2791
2792         /* SW Reset the PHY so all changes take effect */
2793         ret_val = e1000_phy_reset(hw);
2794         if (ret_val) {
2795                 DEBUGOUT("Error Resetting the PHY\n");
2796                 return ret_val;
2797         }
2798
2799         return E1000_SUCCESS;
2800 }
2801
2802 /********************************************************************
2803 * Setup auto-negotiation and flow control advertisements,
2804 * and then perform auto-negotiation.
2805 *
2806 * hw - Struct containing variables accessed by shared code
2807 *********************************************************************/
2808 static int32_t
2809 e1000_copper_link_autoneg(struct e1000_hw *hw)
2810 {
2811         int32_t ret_val;
2812         uint16_t phy_data;
2813
2814         DEBUGFUNC();
2815
2816         /* Perform some bounds checking on the hw->autoneg_advertised
2817          * parameter.  If this variable is zero, then set it to the default.
2818          */
2819         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2820
2821         /* If autoneg_advertised is zero, we assume it was not defaulted
2822          * by the calling code so we set to advertise full capability.
2823          */
2824         if (hw->autoneg_advertised == 0)
2825                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2826
2827         /* IFE phy only supports 10/100 */
2828         if (hw->phy_type == e1000_phy_ife)
2829                 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2830
2831         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2832         ret_val = e1000_phy_setup_autoneg(hw);
2833         if (ret_val) {
2834                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2835                 return ret_val;
2836         }
2837         DEBUGOUT("Restarting Auto-Neg\n");
2838
2839         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2840          * the Auto Neg Restart bit in the PHY control register.
2841          */
2842         ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2843         if (ret_val)
2844                 return ret_val;
2845
2846         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2847         ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2848         if (ret_val)
2849                 return ret_val;
2850
2851         /* Does the user want to wait for Auto-Neg to complete here, or
2852          * check at a later time (for example, callback routine).
2853          */
2854         /* If we do not wait for autonegtation to complete I
2855          * do not see a valid link status.
2856          * wait_autoneg_complete = 1 .
2857          */
2858         if (hw->wait_autoneg_complete) {
2859                 ret_val = e1000_wait_autoneg(hw);
2860                 if (ret_val) {
2861                         DEBUGOUT("Error while waiting for autoneg"
2862                                         "to complete\n");
2863                         return ret_val;
2864                 }
2865         }
2866
2867         hw->get_link_status = true;
2868
2869         return E1000_SUCCESS;
2870 }
2871
2872 /******************************************************************************
2873 * Config the MAC and the PHY after link is up.
2874 *   1) Set up the MAC to the current PHY speed/duplex
2875 *      if we are on 82543.  If we
2876 *      are on newer silicon, we only need to configure
2877 *      collision distance in the Transmit Control Register.
2878 *   2) Set up flow control on the MAC to that established with
2879 *      the link partner.
2880 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
2881 *
2882 * hw - Struct containing variables accessed by shared code
2883 ******************************************************************************/
2884 static int32_t
2885 e1000_copper_link_postconfig(struct e1000_hw *hw)
2886 {
2887         int32_t ret_val;
2888         DEBUGFUNC();
2889
2890         if (hw->mac_type >= e1000_82544) {
2891                 e1000_config_collision_dist(hw);
2892         } else {
2893                 ret_val = e1000_config_mac_to_phy(hw);
2894                 if (ret_val) {
2895                         DEBUGOUT("Error configuring MAC to PHY settings\n");
2896                         return ret_val;
2897                 }
2898         }
2899         ret_val = e1000_config_fc_after_link_up(hw);
2900         if (ret_val) {
2901                 DEBUGOUT("Error Configuring Flow Control\n");
2902                 return ret_val;
2903         }
2904         return E1000_SUCCESS;
2905 }
2906
2907 /******************************************************************************
2908 * Detects which PHY is present and setup the speed and duplex
2909 *
2910 * hw - Struct containing variables accessed by shared code
2911 ******************************************************************************/
2912 static int
2913 e1000_setup_copper_link(struct eth_device *nic)
2914 {
2915         struct e1000_hw *hw = nic->priv;
2916         int32_t ret_val;
2917         uint16_t i;
2918         uint16_t phy_data;
2919         uint16_t reg_data;
2920
2921         DEBUGFUNC();
2922
2923         switch (hw->mac_type) {
2924         case e1000_80003es2lan:
2925         case e1000_ich8lan:
2926                 /* Set the mac to wait the maximum time between each
2927                  * iteration and increase the max iterations when
2928                  * polling the phy; this fixes erroneous timeouts at 10Mbps. */
2929                 ret_val = e1000_write_kmrn_reg(hw,
2930                                 GG82563_REG(0x34, 4), 0xFFFF);
2931                 if (ret_val)
2932                         return ret_val;
2933                 ret_val = e1000_read_kmrn_reg(hw,
2934                                 GG82563_REG(0x34, 9), &reg_data);
2935                 if (ret_val)
2936                         return ret_val;
2937                 reg_data |= 0x3F;
2938                 ret_val = e1000_write_kmrn_reg(hw,
2939                                 GG82563_REG(0x34, 9), reg_data);
2940                 if (ret_val)
2941                         return ret_val;
2942         default:
2943                 break;
2944         }
2945
2946         /* Check if it is a valid PHY and set PHY mode if necessary. */
2947         ret_val = e1000_copper_link_preconfig(hw);
2948         if (ret_val)
2949                 return ret_val;
2950         switch (hw->mac_type) {
2951         case e1000_80003es2lan:
2952                 /* Kumeran registers are written-only */
2953                 reg_data =
2954                 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
2955                 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
2956                 ret_val = e1000_write_kmrn_reg(hw,
2957                                 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
2958                 if (ret_val)
2959                         return ret_val;
2960                 break;
2961         default:
2962                 break;
2963         }
2964
2965         if (hw->phy_type == e1000_phy_igp ||
2966                 hw->phy_type == e1000_phy_igp_3 ||
2967                 hw->phy_type == e1000_phy_igp_2) {
2968                 ret_val = e1000_copper_link_igp_setup(hw);
2969                 if (ret_val)
2970                         return ret_val;
2971         } else if (hw->phy_type == e1000_phy_m88) {
2972                 ret_val = e1000_copper_link_mgp_setup(hw);
2973                 if (ret_val)
2974                         return ret_val;
2975         } else if (hw->phy_type == e1000_phy_gg82563) {
2976                 ret_val = e1000_copper_link_ggp_setup(hw);
2977                 if (ret_val)
2978                         return ret_val;
2979         }
2980
2981         /* always auto */
2982         /* Setup autoneg and flow control advertisement
2983           * and perform autonegotiation */
2984         ret_val = e1000_copper_link_autoneg(hw);
2985         if (ret_val)
2986                 return ret_val;
2987
2988         /* Check link status. Wait up to 100 microseconds for link to become
2989          * valid.
2990          */
2991         for (i = 0; i < 10; i++) {
2992                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2993                 if (ret_val)
2994                         return ret_val;
2995                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2996                 if (ret_val)
2997                         return ret_val;
2998
2999                 if (phy_data & MII_SR_LINK_STATUS) {
3000                         /* Config the MAC and PHY after link is up */
3001                         ret_val = e1000_copper_link_postconfig(hw);
3002                         if (ret_val)
3003                                 return ret_val;
3004
3005                         DEBUGOUT("Valid link established!!!\n");
3006                         return E1000_SUCCESS;
3007                 }
3008                 udelay(10);
3009         }
3010
3011         DEBUGOUT("Unable to establish link!!!\n");
3012         return E1000_SUCCESS;
3013 }
3014
3015 /******************************************************************************
3016 * Configures PHY autoneg and flow control advertisement settings
3017 *
3018 * hw - Struct containing variables accessed by shared code
3019 ******************************************************************************/
3020 int32_t
3021 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3022 {
3023         int32_t ret_val;
3024         uint16_t mii_autoneg_adv_reg;
3025         uint16_t mii_1000t_ctrl_reg;
3026
3027         DEBUGFUNC();
3028
3029         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3030         ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3031         if (ret_val)
3032                 return ret_val;
3033
3034         if (hw->phy_type != e1000_phy_ife) {
3035                 /* Read the MII 1000Base-T Control Register (Address 9). */
3036                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3037                                 &mii_1000t_ctrl_reg);
3038                 if (ret_val)
3039                         return ret_val;
3040         } else
3041                 mii_1000t_ctrl_reg = 0;
3042
3043         /* Need to parse both autoneg_advertised and fc and set up
3044          * the appropriate PHY registers.  First we will parse for
3045          * autoneg_advertised software override.  Since we can advertise
3046          * a plethora of combinations, we need to check each bit
3047          * individually.
3048          */
3049
3050         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3051          * Advertisement Register (Address 4) and the 1000 mb speed bits in
3052          * the  1000Base-T Control Register (Address 9).
3053          */
3054         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3055         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3056
3057         DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3058
3059         /* Do we want to advertise 10 Mb Half Duplex? */
3060         if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3061                 DEBUGOUT("Advertise 10mb Half duplex\n");
3062                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3063         }
3064
3065         /* Do we want to advertise 10 Mb Full Duplex? */
3066         if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3067                 DEBUGOUT("Advertise 10mb Full duplex\n");
3068                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3069         }
3070
3071         /* Do we want to advertise 100 Mb Half Duplex? */
3072         if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3073                 DEBUGOUT("Advertise 100mb Half duplex\n");
3074                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3075         }
3076
3077         /* Do we want to advertise 100 Mb Full Duplex? */
3078         if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3079                 DEBUGOUT("Advertise 100mb Full duplex\n");
3080                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3081         }
3082
3083         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3084         if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3085                 DEBUGOUT
3086                     ("Advertise 1000mb Half duplex requested, request denied!\n");
3087         }
3088
3089         /* Do we want to advertise 1000 Mb Full Duplex? */
3090         if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3091                 DEBUGOUT("Advertise 1000mb Full duplex\n");
3092                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3093         }
3094
3095         /* Check for a software override of the flow control settings, and
3096          * setup the PHY advertisement registers accordingly.  If
3097          * auto-negotiation is enabled, then software will have to set the
3098          * "PAUSE" bits to the correct value in the Auto-Negotiation
3099          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3100          *
3101          * The possible values of the "fc" parameter are:
3102          *      0:  Flow control is completely disabled
3103          *      1:  Rx flow control is enabled (we can receive pause frames
3104          *          but not send pause frames).
3105          *      2:  Tx flow control is enabled (we can send pause frames
3106          *          but we do not support receiving pause frames).
3107          *      3:  Both Rx and TX flow control (symmetric) are enabled.
3108          *  other:  No software override.  The flow control configuration
3109          *          in the EEPROM is used.
3110          */
3111         switch (hw->fc) {
3112         case e1000_fc_none:     /* 0 */
3113                 /* Flow control (RX & TX) is completely disabled by a
3114                  * software over-ride.
3115                  */
3116                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3117                 break;
3118         case e1000_fc_rx_pause: /* 1 */
3119                 /* RX Flow control is enabled, and TX Flow control is
3120                  * disabled, by a software over-ride.
3121                  */
3122                 /* Since there really isn't a way to advertise that we are
3123                  * capable of RX Pause ONLY, we will advertise that we
3124                  * support both symmetric and asymmetric RX PAUSE.  Later
3125                  * (in e1000_config_fc_after_link_up) we will disable the
3126                  *hw's ability to send PAUSE frames.
3127                  */
3128                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3129                 break;
3130         case e1000_fc_tx_pause: /* 2 */
3131                 /* TX Flow control is enabled, and RX Flow control is
3132                  * disabled, by a software over-ride.
3133                  */
3134                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3135                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3136                 break;
3137         case e1000_fc_full:     /* 3 */
3138                 /* Flow control (both RX and TX) is enabled by a software
3139                  * over-ride.
3140                  */
3141                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3142                 break;
3143         default:
3144                 DEBUGOUT("Flow control param set incorrectly\n");
3145                 return -E1000_ERR_CONFIG;
3146         }
3147
3148         ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3149         if (ret_val)
3150                 return ret_val;
3151
3152         DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3153
3154         if (hw->phy_type != e1000_phy_ife) {
3155                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3156                                 mii_1000t_ctrl_reg);
3157                 if (ret_val)
3158                         return ret_val;
3159         }
3160
3161         return E1000_SUCCESS;
3162 }
3163
3164 /******************************************************************************
3165 * Sets the collision distance in the Transmit Control register
3166 *
3167 * hw - Struct containing variables accessed by shared code
3168 *
3169 * Link should have been established previously. Reads the speed and duplex
3170 * information from the Device Status register.
3171 ******************************************************************************/
3172 static void
3173 e1000_config_collision_dist(struct e1000_hw *hw)
3174 {
3175         uint32_t tctl, coll_dist;
3176
3177         DEBUGFUNC();
3178
3179         if (hw->mac_type < e1000_82543)
3180                 coll_dist = E1000_COLLISION_DISTANCE_82542;
3181         else
3182                 coll_dist = E1000_COLLISION_DISTANCE;
3183
3184         tctl = E1000_READ_REG(hw, TCTL);
3185
3186         tctl &= ~E1000_TCTL_COLD;
3187         tctl |= coll_dist << E1000_COLD_SHIFT;
3188
3189         E1000_WRITE_REG(hw, TCTL, tctl);
3190         E1000_WRITE_FLUSH(hw);
3191 }
3192
3193 /******************************************************************************
3194 * Sets MAC speed and duplex settings to reflect the those in the PHY
3195 *
3196 * hw - Struct containing variables accessed by shared code
3197 * mii_reg - data to write to the MII control register
3198 *
3199 * The contents of the PHY register containing the needed information need to
3200 * be passed in.
3201 ******************************************************************************/
3202 static int
3203 e1000_config_mac_to_phy(struct e1000_hw *hw)
3204 {
3205         uint32_t ctrl;
3206         uint16_t phy_data;
3207
3208         DEBUGFUNC();
3209
3210         /* Read the Device Control Register and set the bits to Force Speed
3211          * and Duplex.
3212          */
3213         ctrl = E1000_READ_REG(hw, CTRL);
3214         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3215         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
3216
3217         /* Set up duplex in the Device Control and Transmit Control
3218          * registers depending on negotiated values.
3219          */
3220         if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3221                 DEBUGOUT("PHY Read Error\n");
3222                 return -E1000_ERR_PHY;
3223         }
3224         if (phy_data & M88E1000_PSSR_DPLX)
3225                 ctrl |= E1000_CTRL_FD;
3226         else
3227                 ctrl &= ~E1000_CTRL_FD;
3228
3229         e1000_config_collision_dist(hw);
3230
3231         /* Set up speed in the Device Control register depending on
3232          * negotiated values.
3233          */
3234         if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3235                 ctrl |= E1000_CTRL_SPD_1000;
3236         else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3237                 ctrl |= E1000_CTRL_SPD_100;
3238         /* Write the configured values back to the Device Control Reg. */
3239         E1000_WRITE_REG(hw, CTRL, ctrl);
3240         return 0;
3241 }
3242
3243 /******************************************************************************
3244  * Forces the MAC's flow control settings.
3245  *
3246  * hw - Struct containing variables accessed by shared code
3247  *
3248  * Sets the TFCE and RFCE bits in the device control register to reflect
3249  * the adapter settings. TFCE and RFCE need to be explicitly set by
3250  * software when a Copper PHY is used because autonegotiation is managed
3251  * by the PHY rather than the MAC. Software must also configure these
3252  * bits when link is forced on a fiber connection.
3253  *****************************************************************************/
3254 static int
3255 e1000_force_mac_fc(struct e1000_hw *hw)
3256 {
3257         uint32_t ctrl;
3258
3259         DEBUGFUNC();
3260
3261         /* Get the current configuration of the Device Control Register */
3262         ctrl = E1000_READ_REG(hw, CTRL);
3263
3264         /* Because we didn't get link via the internal auto-negotiation
3265          * mechanism (we either forced link or we got link via PHY
3266          * auto-neg), we have to manually enable/disable transmit an
3267          * receive flow control.
3268          *
3269          * The "Case" statement below enables/disable flow control
3270          * according to the "hw->fc" parameter.
3271          *
3272          * The possible values of the "fc" parameter are:
3273          *      0:  Flow control is completely disabled
3274          *      1:  Rx flow control is enabled (we can receive pause
3275          *          frames but not send pause frames).
3276          *      2:  Tx flow control is enabled (we can send pause frames
3277          *          frames but we do not receive pause frames).
3278          *      3:  Both Rx and TX flow control (symmetric) is enabled.
3279          *  other:  No other values should be possible at this point.
3280          */
3281
3282         switch (hw->fc) {
3283         case e1000_fc_none:
3284                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3285                 break;
3286         case e1000_fc_rx_pause:
3287                 ctrl &= (~E1000_CTRL_TFCE);
3288                 ctrl |= E1000_CTRL_RFCE;
3289                 break;
3290         case e1000_fc_tx_pause:
3291                 ctrl &= (~E1000_CTRL_RFCE);
3292                 ctrl |= E1000_CTRL_TFCE;
3293                 break;
3294         case e1000_fc_full:
3295                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3296                 break;
3297         default:
3298                 DEBUGOUT("Flow control param set incorrectly\n");
3299                 return -E1000_ERR_CONFIG;
3300         }
3301
3302         /* Disable TX Flow Control for 82542 (rev 2.0) */
3303         if (hw->mac_type == e1000_82542_rev2_0)
3304                 ctrl &= (~E1000_CTRL_TFCE);
3305
3306         E1000_WRITE_REG(hw, CTRL, ctrl);
3307         return 0;
3308 }
3309
3310 /******************************************************************************
3311  * Configures flow control settings after link is established
3312  *
3313  * hw - Struct containing variables accessed by shared code
3314  *
3315  * Should be called immediately after a valid link has been established.
3316  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3317  * and autonegotiation is enabled, the MAC flow control settings will be set
3318  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3319  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3320  *****************************************************************************/
3321 static int32_t
3322 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3323 {
3324         int32_t ret_val;
3325         uint16_t mii_status_reg;
3326         uint16_t mii_nway_adv_reg;
3327         uint16_t mii_nway_lp_ability_reg;
3328         uint16_t speed;
3329         uint16_t duplex;
3330
3331         DEBUGFUNC();
3332
3333         /* Check for the case where we have fiber media and auto-neg failed
3334          * so we had to force link.  In this case, we need to force the
3335          * configuration of the MAC to match the "fc" parameter.
3336          */
3337         if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3338                 || ((hw->media_type == e1000_media_type_internal_serdes)
3339                 && (hw->autoneg_failed))
3340                 || ((hw->media_type == e1000_media_type_copper)
3341                 && (!hw->autoneg))) {
3342                 ret_val = e1000_force_mac_fc(hw);
3343                 if (ret_val < 0) {
3344                         DEBUGOUT("Error forcing flow control settings\n");
3345                         return ret_val;
3346                 }
3347         }
3348
3349         /* Check for the case where we have copper media and auto-neg is
3350          * enabled.  In this case, we need to check and see if Auto-Neg
3351          * has completed, and if so, how the PHY and link partner has
3352          * flow control configured.
3353          */
3354         if (hw->media_type == e1000_media_type_copper) {
3355                 /* Read the MII Status Register and check to see if AutoNeg
3356                  * has completed.  We read this twice because this reg has
3357                  * some "sticky" (latched) bits.
3358                  */
3359                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3360                         DEBUGOUT("PHY Read Error \n");
3361                         return -E1000_ERR_PHY;
3362                 }
3363                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3364                         DEBUGOUT("PHY Read Error \n");
3365                         return -E1000_ERR_PHY;
3366                 }
3367
3368                 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3369                         /* The AutoNeg process has completed, so we now need to
3370                          * read both the Auto Negotiation Advertisement Register
3371                          * (Address 4) and the Auto_Negotiation Base Page Ability
3372                          * Register (Address 5) to determine how flow control was
3373                          * negotiated.
3374                          */
3375                         if (e1000_read_phy_reg
3376                             (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3377                                 DEBUGOUT("PHY Read Error\n");
3378                                 return -E1000_ERR_PHY;
3379                         }
3380                         if (e1000_read_phy_reg
3381                             (hw, PHY_LP_ABILITY,
3382                              &mii_nway_lp_ability_reg) < 0) {
3383                                 DEBUGOUT("PHY Read Error\n");
3384                                 return -E1000_ERR_PHY;
3385                         }
3386
3387                         /* Two bits in the Auto Negotiation Advertisement Register
3388                          * (Address 4) and two bits in the Auto Negotiation Base
3389                          * Page Ability Register (Address 5) determine flow control
3390                          * for both the PHY and the link partner.  The following
3391                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3392                          * 1999, describes these PAUSE resolution bits and how flow
3393                          * control is determined based upon these settings.
3394                          * NOTE:  DC = Don't Care
3395                          *
3396                          *   LOCAL DEVICE  |   LINK PARTNER
3397                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3398                          *-------|---------|-------|---------|--------------------
3399                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
3400                          *   0   |    1    |   0   |   DC    | e1000_fc_none
3401                          *   0   |    1    |   1   |    0    | e1000_fc_none
3402                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3403                          *   1   |    0    |   0   |   DC    | e1000_fc_none
3404                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3405                          *   1   |    1    |   0   |    0    | e1000_fc_none
3406                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3407                          *
3408                          */
3409                         /* Are both PAUSE bits set to 1?  If so, this implies
3410                          * Symmetric Flow Control is enabled at both ends.  The
3411                          * ASM_DIR bits are irrelevant per the spec.
3412                          *
3413                          * For Symmetric Flow Control:
3414                          *
3415                          *   LOCAL DEVICE  |   LINK PARTNER
3416                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3417                          *-------|---------|-------|---------|--------------------
3418                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3419                          *
3420                          */
3421                         if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3422                             (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3423                                 /* Now we need to check if the user selected RX ONLY
3424                                  * of pause frames.  In this case, we had to advertise
3425                                  * FULL flow control because we could not advertise RX
3426                                  * ONLY. Hence, we must now check to see if we need to
3427                                  * turn OFF  the TRANSMISSION of PAUSE frames.
3428                                  */
3429                                 if (hw->original_fc == e1000_fc_full) {
3430                                         hw->fc = e1000_fc_full;
3431                                         DEBUGOUT("Flow Control = FULL.\r\n");
3432                                 } else {
3433                                         hw->fc = e1000_fc_rx_pause;
3434                                         DEBUGOUT
3435                                             ("Flow Control = RX PAUSE frames only.\r\n");
3436                                 }
3437                         }
3438                         /* For receiving PAUSE frames ONLY.
3439                          *
3440                          *   LOCAL DEVICE  |   LINK PARTNER
3441                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3442                          *-------|---------|-------|---------|--------------------
3443                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3444                          *
3445                          */
3446                         else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3447                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3448                                  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3449                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3450                         {
3451                                 hw->fc = e1000_fc_tx_pause;
3452                                 DEBUGOUT
3453                                     ("Flow Control = TX PAUSE frames only.\r\n");
3454                         }
3455                         /* For transmitting PAUSE frames ONLY.
3456                          *
3457                          *   LOCAL DEVICE  |   LINK PARTNER
3458                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3459                          *-------|---------|-------|---------|--------------------
3460                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3461                          *
3462                          */
3463                         else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3464                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3465                                  !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3466                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3467                         {
3468                                 hw->fc = e1000_fc_rx_pause;
3469                                 DEBUGOUT
3470                                     ("Flow Control = RX PAUSE frames only.\r\n");
3471                         }
3472                         /* Per the IEEE spec, at this point flow control should be
3473                          * disabled.  However, we want to consider that we could
3474                          * be connected to a legacy switch that doesn't advertise
3475                          * desired flow control, but can be forced on the link
3476                          * partner.  So if we advertised no flow control, that is
3477                          * what we will resolve to.  If we advertised some kind of
3478                          * receive capability (Rx Pause Only or Full Flow Control)
3479                          * and the link partner advertised none, we will configure
3480                          * ourselves to enable Rx Flow Control only.  We can do
3481                          * this safely for two reasons:  If the link partner really
3482                          * didn't want flow control enabled, and we enable Rx, no
3483                          * harm done since we won't be receiving any PAUSE frames
3484                          * anyway.  If the intent on the link partner was to have
3485                          * flow control enabled, then by us enabling RX only, we
3486                          * can at least receive pause frames and process them.
3487                          * This is a good idea because in most cases, since we are
3488                          * predominantly a server NIC, more times than not we will
3489                          * be asked to delay transmission of packets than asking
3490                          * our link partner to pause transmission of frames.
3491                          */
3492                         else if (hw->original_fc == e1000_fc_none ||
3493                                  hw->original_fc == e1000_fc_tx_pause) {
3494                                 hw->fc = e1000_fc_none;
3495                                 DEBUGOUT("Flow Control = NONE.\r\n");
3496                         } else {
3497                                 hw->fc = e1000_fc_rx_pause;
3498                                 DEBUGOUT
3499                                     ("Flow Control = RX PAUSE frames only.\r\n");
3500                         }
3501
3502                         /* Now we need to do one last check...  If we auto-
3503                          * negotiated to HALF DUPLEX, flow control should not be
3504                          * enabled per IEEE 802.3 spec.
3505                          */
3506                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
3507
3508                         if (duplex == HALF_DUPLEX)
3509                                 hw->fc = e1000_fc_none;
3510
3511                         /* Now we call a subroutine to actually force the MAC
3512                          * controller to use the correct flow control settings.
3513                          */
3514                         ret_val = e1000_force_mac_fc(hw);
3515                         if (ret_val < 0) {
3516                                 DEBUGOUT
3517                                     ("Error forcing flow control settings\n");
3518                                 return ret_val;
3519                         }
3520                 } else {
3521                         DEBUGOUT
3522                             ("Copper PHY and Auto Neg has not completed.\r\n");
3523                 }
3524         }
3525         return E1000_SUCCESS;
3526 }
3527
3528 /******************************************************************************
3529  * Checks to see if the link status of the hardware has changed.
3530  *
3531  * hw - Struct containing variables accessed by shared code
3532  *
3533  * Called by any function that needs to check the link status of the adapter.
3534  *****************************************************************************/
3535 static int
3536 e1000_check_for_link(struct eth_device *nic)
3537 {
3538         struct e1000_hw *hw = nic->priv;
3539         uint32_t rxcw;
3540         uint32_t ctrl;
3541         uint32_t status;
3542         uint32_t rctl;
3543         uint32_t signal;
3544         int32_t ret_val;
3545         uint16_t phy_data;
3546         uint16_t lp_capability;
3547
3548         DEBUGFUNC();
3549
3550         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3551          * set when the optics detect a signal. On older adapters, it will be
3552          * cleared when there is a signal
3553          */
3554         ctrl = E1000_READ_REG(hw, CTRL);
3555         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3556                 signal = E1000_CTRL_SWDPIN1;
3557         else
3558                 signal = 0;
3559
3560         status = E1000_READ_REG(hw, STATUS);
3561         rxcw = E1000_READ_REG(hw, RXCW);
3562         DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3563
3564         /* If we have a copper PHY then we only want to go out to the PHY
3565          * registers to see if Auto-Neg has completed and/or if our link
3566          * status has changed.  The get_link_status flag will be set if we
3567          * receive a Link Status Change interrupt or we have Rx Sequence
3568          * Errors.
3569          */
3570         if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3571                 /* First we want to see if the MII Status Register reports
3572                  * link.  If so, then we want to get the current speed/duplex
3573                  * of the PHY.
3574                  * Read the register twice since the link bit is sticky.
3575                  */
3576                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3577                         DEBUGOUT("PHY Read Error\n");
3578                         return -E1000_ERR_PHY;
3579                 }
3580                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3581                         DEBUGOUT("PHY Read Error\n");
3582                         return -E1000_ERR_PHY;
3583                 }
3584
3585                 if (phy_data & MII_SR_LINK_STATUS) {
3586                         hw->get_link_status = false;
3587                 } else {
3588                         /* No link detected */
3589                         return -E1000_ERR_NOLINK;
3590                 }
3591
3592                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3593                  * have Si on board that is 82544 or newer, Auto
3594                  * Speed Detection takes care of MAC speed/duplex
3595                  * configuration.  So we only need to configure Collision
3596                  * Distance in the MAC.  Otherwise, we need to force
3597                  * speed/duplex on the MAC to the current PHY speed/duplex
3598                  * settings.
3599                  */
3600                 if (hw->mac_type >= e1000_82544)
3601                         e1000_config_collision_dist(hw);
3602                 else {
3603                         ret_val = e1000_config_mac_to_phy(hw);
3604                         if (ret_val < 0) {
3605                                 DEBUGOUT
3606                                     ("Error configuring MAC to PHY settings\n");
3607                                 return ret_val;
3608                         }
3609                 }
3610
3611                 /* Configure Flow Control now that Auto-Neg has completed. First, we
3612                  * need to restore the desired flow control settings because we may
3613                  * have had to re-autoneg with a different link partner.
3614                  */
3615                 ret_val = e1000_config_fc_after_link_up(hw);
3616                 if (ret_val < 0) {
3617                         DEBUGOUT("Error configuring flow control\n");
3618                         return ret_val;
3619                 }
3620
3621                 /* At this point we know that we are on copper and we have
3622                  * auto-negotiated link.  These are conditions for checking the link
3623                  * parter capability register.  We use the link partner capability to
3624                  * determine if TBI Compatibility needs to be turned on or off.  If
3625                  * the link partner advertises any speed in addition to Gigabit, then
3626                  * we assume that they are GMII-based, and TBI compatibility is not
3627                  * needed. If no other speeds are advertised, we assume the link
3628                  * partner is TBI-based, and we turn on TBI Compatibility.
3629                  */
3630                 if (hw->tbi_compatibility_en) {
3631                         if (e1000_read_phy_reg
3632                             (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3633                                 DEBUGOUT("PHY Read Error\n");
3634                                 return -E1000_ERR_PHY;
3635                         }
3636                         if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3637                                              NWAY_LPAR_10T_FD_CAPS |
3638                                              NWAY_LPAR_100TX_HD_CAPS |
3639                                              NWAY_LPAR_100TX_FD_CAPS |
3640                                              NWAY_LPAR_100T4_CAPS)) {
3641                                 /* If our link partner advertises anything in addition to
3642                                  * gigabit, we do not need to enable TBI compatibility.
3643                                  */
3644                                 if (hw->tbi_compatibility_on) {
3645                                         /* If we previously were in the mode, turn it off. */
3646                                         rctl = E1000_READ_REG(hw, RCTL);
3647                                         rctl &= ~E1000_RCTL_SBP;
3648                                         E1000_WRITE_REG(hw, RCTL, rctl);
3649                                         hw->tbi_compatibility_on = false;
3650                                 }
3651                         } else {
3652                                 /* If TBI compatibility is was previously off, turn it on. For
3653                                  * compatibility with a TBI link partner, we will store bad
3654                                  * packets. Some frames have an additional byte on the end and
3655                                  * will look like CRC errors to to the hardware.
3656                                  */
3657                                 if (!hw->tbi_compatibility_on) {
3658                                         hw->tbi_compatibility_on = true;
3659                                         rctl = E1000_READ_REG(hw, RCTL);
3660                                         rctl |= E1000_RCTL_SBP;
3661                                         E1000_WRITE_REG(hw, RCTL, rctl);
3662                                 }
3663                         }
3664                 }
3665         }
3666         /* If we don't have link (auto-negotiation failed or link partner cannot
3667          * auto-negotiate), the cable is plugged in (we have signal), and our
3668          * link partner is not trying to auto-negotiate with us (we are receiving
3669          * idles or data), we need to force link up. We also need to give
3670          * auto-negotiation time to complete, in case the cable was just plugged
3671          * in. The autoneg_failed flag does this.
3672          */
3673         else if ((hw->media_type == e1000_media_type_fiber) &&
3674                  (!(status & E1000_STATUS_LU)) &&
3675                  ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3676                  (!(rxcw & E1000_RXCW_C))) {
3677                 if (hw->autoneg_failed == 0) {
3678                         hw->autoneg_failed = 1;
3679                         return 0;
3680                 }
3681                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3682
3683                 /* Disable auto-negotiation in the TXCW register */
3684                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3685
3686                 /* Force link-up and also force full-duplex. */
3687                 ctrl = E1000_READ_REG(hw, CTRL);
3688                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3689                 E1000_WRITE_REG(hw, CTRL, ctrl);
3690
3691                 /* Configure Flow Control after forcing link up. */
3692                 ret_val = e1000_config_fc_after_link_up(hw);
3693                 if (ret_val < 0) {
3694                         DEBUGOUT("Error configuring flow control\n");
3695                         return ret_val;
3696                 }
3697         }
3698         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3699          * auto-negotiation in the TXCW register and disable forced link in the
3700          * Device Control register in an attempt to auto-negotiate with our link
3701          * partner.
3702          */
3703         else if ((hw->media_type == e1000_media_type_fiber) &&
3704                  (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3705                 DEBUGOUT
3706                     ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3707                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3708                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3709         }
3710         return 0;
3711 }
3712
3713 /******************************************************************************
3714 * Configure the MAC-to-PHY interface for 10/100Mbps
3715 *
3716 * hw - Struct containing variables accessed by shared code
3717 ******************************************************************************/
3718 static int32_t
3719 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3720 {
3721         int32_t ret_val = E1000_SUCCESS;
3722         uint32_t tipg;
3723         uint16_t reg_data;
3724
3725         DEBUGFUNC();
3726
3727         reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3728         ret_val = e1000_write_kmrn_reg(hw,
3729                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3730         if (ret_val)
3731                 return ret_val;
3732
3733         /* Configure Transmit Inter-Packet Gap */
3734         tipg = E1000_READ_REG(hw, TIPG);
3735         tipg &= ~E1000_TIPG_IPGT_MASK;
3736         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3737         E1000_WRITE_REG(hw, TIPG, tipg);
3738
3739         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3740
3741         if (ret_val)
3742                 return ret_val;
3743
3744         if (duplex == HALF_DUPLEX)
3745                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3746         else
3747                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3748
3749         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3750
3751         return ret_val;
3752 }
3753
3754 static int32_t
3755 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3756 {
3757         int32_t ret_val = E1000_SUCCESS;
3758         uint16_t reg_data;
3759         uint32_t tipg;
3760
3761         DEBUGFUNC();
3762
3763         reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3764         ret_val = e1000_write_kmrn_reg(hw,
3765                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3766         if (ret_val)
3767                 return ret_val;
3768
3769         /* Configure Transmit Inter-Packet Gap */
3770         tipg = E1000_READ_REG(hw, TIPG);
3771         tipg &= ~E1000_TIPG_IPGT_MASK;
3772         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3773         E1000_WRITE_REG(hw, TIPG, tipg);
3774
3775         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3776
3777         if (ret_val)
3778                 return ret_val;
3779
3780         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3781         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3782
3783         return ret_val;
3784 }
3785
3786 /******************************************************************************
3787  * Detects the current speed and duplex settings of the hardware.
3788  *
3789  * hw - Struct containing variables accessed by shared code
3790  * speed - Speed of the connection
3791  * duplex - Duplex setting of the connection
3792  *****************************************************************************/
3793 static int
3794 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3795                 uint16_t *duplex)
3796 {
3797         uint32_t status;
3798         int32_t ret_val;
3799         uint16_t phy_data;
3800
3801         DEBUGFUNC();
3802
3803         if (hw->mac_type >= e1000_82543) {
3804                 status = E1000_READ_REG(hw, STATUS);
3805                 if (status & E1000_STATUS_SPEED_1000) {
3806                         *speed = SPEED_1000;
3807                         DEBUGOUT("1000 Mbs, ");
3808                 } else if (status & E1000_STATUS_SPEED_100) {
3809                         *speed = SPEED_100;
3810                         DEBUGOUT("100 Mbs, ");
3811                 } else {
3812                         *speed = SPEED_10;
3813                         DEBUGOUT("10 Mbs, ");
3814                 }
3815
3816                 if (status & E1000_STATUS_FD) {
3817                         *duplex = FULL_DUPLEX;
3818                         DEBUGOUT("Full Duplex\r\n");
3819                 } else {
3820                         *duplex = HALF_DUPLEX;
3821                         DEBUGOUT(" Half Duplex\r\n");
3822                 }
3823         } else {
3824                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3825                 *speed = SPEED_1000;
3826                 *duplex = FULL_DUPLEX;
3827         }
3828
3829         /* IGP01 PHY may advertise full duplex operation after speed downgrade
3830          * even if it is operating at half duplex.  Here we set the duplex
3831          * settings to match the duplex in the link partner's capabilities.
3832          */
3833         if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3834                 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3835                 if (ret_val)
3836                         return ret_val;
3837
3838                 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3839                         *duplex = HALF_DUPLEX;
3840                 else {
3841                         ret_val = e1000_read_phy_reg(hw,
3842                                         PHY_LP_ABILITY, &phy_data);
3843                         if (ret_val)
3844                                 return ret_val;
3845                         if ((*speed == SPEED_100 &&
3846                                 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3847                                 || (*speed == SPEED_10
3848                                 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3849                                 *duplex = HALF_DUPLEX;
3850                 }
3851         }
3852
3853         if ((hw->mac_type == e1000_80003es2lan) &&
3854                 (hw->media_type == e1000_media_type_copper)) {
3855                 if (*speed == SPEED_1000)
3856                         ret_val = e1000_configure_kmrn_for_1000(hw);
3857                 else
3858                         ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3859                 if (ret_val)
3860                         return ret_val;
3861         }
3862         return E1000_SUCCESS;
3863 }
3864
3865 /******************************************************************************
3866 * Blocks until autoneg completes or times out (~4.5 seconds)
3867 *
3868 * hw - Struct containing variables accessed by shared code
3869 ******************************************************************************/
3870 static int
3871 e1000_wait_autoneg(struct e1000_hw *hw)
3872 {
3873         uint16_t i;
3874         uint16_t phy_data;
3875
3876         DEBUGFUNC();
3877         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3878
3879         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3880         for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3881                 /* Read the MII Status Register and wait for Auto-Neg
3882                  * Complete bit to be set.
3883                  */
3884                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3885                         DEBUGOUT("PHY Read Error\n");
3886                         return -E1000_ERR_PHY;
3887                 }
3888                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3889                         DEBUGOUT("PHY Read Error\n");
3890                         return -E1000_ERR_PHY;
3891                 }
3892                 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3893                         DEBUGOUT("Auto-Neg complete.\n");
3894                         return 0;
3895                 }
3896                 mdelay(100);
3897         }
3898         DEBUGOUT("Auto-Neg timedout.\n");
3899         return -E1000_ERR_TIMEOUT;
3900 }
3901
3902 /******************************************************************************
3903 * Raises the Management Data Clock
3904 *
3905 * hw - Struct containing variables accessed by shared code
3906 * ctrl - Device control register's current value
3907 ******************************************************************************/
3908 static void
3909 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3910 {
3911         /* Raise the clock input to the Management Data Clock (by setting the MDC
3912          * bit), and then delay 2 microseconds.
3913          */
3914         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3915         E1000_WRITE_FLUSH(hw);
3916         udelay(2);
3917 }
3918
3919 /******************************************************************************
3920 * Lowers the Management Data Clock
3921 *
3922 * hw - Struct containing variables accessed by shared code
3923 * ctrl - Device control register's current value
3924 ******************************************************************************/
3925 static void
3926 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3927 {
3928         /* Lower the clock input to the Management Data Clock (by clearing the MDC
3929          * bit), and then delay 2 microseconds.
3930          */
3931         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3932         E1000_WRITE_FLUSH(hw);
3933         udelay(2);
3934 }
3935
3936 /******************************************************************************
3937 * Shifts data bits out to the PHY
3938 *
3939 * hw - Struct containing variables accessed by shared code
3940 * data - Data to send out to the PHY
3941 * count - Number of bits to shift out
3942 *
3943 * Bits are shifted out in MSB to LSB order.
3944 ******************************************************************************/
3945 static void
3946 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
3947 {
3948         uint32_t ctrl;
3949         uint32_t mask;
3950
3951         /* We need to shift "count" number of bits out to the PHY. So, the value
3952          * in the "data" parameter will be shifted out to the PHY one bit at a
3953          * time. In order to do this, "data" must be broken down into bits.
3954          */
3955         mask = 0x01;
3956         mask <<= (count - 1);
3957
3958         ctrl = E1000_READ_REG(hw, CTRL);
3959
3960         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3961         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3962
3963         while (mask) {
3964                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3965                  * then raising and lowering the Management Data Clock. A "0" is
3966                  * shifted out to the PHY by setting the MDIO bit to "0" and then
3967                  * raising and lowering the clock.
3968                  */
3969                 if (data & mask)
3970                         ctrl |= E1000_CTRL_MDIO;
3971                 else
3972                         ctrl &= ~E1000_CTRL_MDIO;
3973
3974                 E1000_WRITE_REG(hw, CTRL, ctrl);
3975                 E1000_WRITE_FLUSH(hw);
3976
3977                 udelay(2);
3978
3979                 e1000_raise_mdi_clk(hw, &ctrl);
3980                 e1000_lower_mdi_clk(hw, &ctrl);
3981
3982                 mask = mask >> 1;
3983         }
3984 }
3985
3986 /******************************************************************************
3987 * Shifts data bits in from the PHY
3988 *
3989 * hw - Struct containing variables accessed by shared code
3990 *
3991 * Bits are shifted in in MSB to LSB order.
3992 ******************************************************************************/
3993 static uint16_t
3994 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3995 {
3996         uint32_t ctrl;
3997         uint16_t data = 0;
3998         uint8_t i;
3999
4000         /* In order to read a register from the PHY, we need to shift in a total
4001          * of 18 bits from the PHY. The first two bit (turnaround) times are used
4002          * to avoid contention on the MDIO pin when a read operation is performed.
4003          * These two bits are ignored by us and thrown away. Bits are "shifted in"
4004          * by raising the input to the Management Data Clock (setting the MDC bit),
4005          * and then reading the value of the MDIO bit.
4006          */
4007         ctrl = E1000_READ_REG(hw, CTRL);
4008
4009         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4010         ctrl &= ~E1000_CTRL_MDIO_DIR;
4011         ctrl &= ~E1000_CTRL_MDIO;
4012
4013         E1000_WRITE_REG(hw, CTRL, ctrl);
4014         E1000_WRITE_FLUSH(hw);
4015
4016         /* Raise and Lower the clock before reading in the data. This accounts for
4017          * the turnaround bits. The first clock occurred when we clocked out the
4018          * last bit of the Register Address.
4019          */
4020         e1000_raise_mdi_clk(hw, &ctrl);
4021         e1000_lower_mdi_clk(hw, &ctrl);
4022
4023         for (data = 0, i = 0; i < 16; i++) {
4024                 data = data << 1;
4025                 e1000_raise_mdi_clk(hw, &ctrl);
4026                 ctrl = E1000_READ_REG(hw, CTRL);
4027                 /* Check to see if we shifted in a "1". */
4028                 if (ctrl & E1000_CTRL_MDIO)
4029                         data |= 1;
4030                 e1000_lower_mdi_clk(hw, &ctrl);
4031         }
4032
4033         e1000_raise_mdi_clk(hw, &ctrl);
4034         e1000_lower_mdi_clk(hw, &ctrl);
4035
4036         return data;
4037 }
4038
4039 /*****************************************************************************
4040 * Reads the value from a PHY register
4041 *
4042 * hw - Struct containing variables accessed by shared code
4043 * reg_addr - address of the PHY register to read
4044 ******************************************************************************/
4045 static int
4046 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4047 {
4048         uint32_t i;
4049         uint32_t mdic = 0;
4050         const uint32_t phy_addr = 1;
4051
4052         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4053                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4054                 return -E1000_ERR_PARAM;
4055         }
4056
4057         if (hw->mac_type > e1000_82543) {
4058                 /* Set up Op-code, Phy Address, and register address in the MDI
4059                  * Control register.  The MAC will take care of interfacing with the
4060                  * PHY to retrieve the desired data.
4061                  */
4062                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4063                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4064                         (E1000_MDIC_OP_READ));
4065
4066                 E1000_WRITE_REG(hw, MDIC, mdic);
4067
4068                 /* Poll the ready bit to see if the MDI read completed */
4069                 for (i = 0; i < 64; i++) {
4070                         udelay(10);
4071                         mdic = E1000_READ_REG(hw, MDIC);
4072                         if (mdic & E1000_MDIC_READY)
4073                                 break;
4074                 }
4075                 if (!(mdic & E1000_MDIC_READY)) {
4076                         DEBUGOUT("MDI Read did not complete\n");
4077                         return -E1000_ERR_PHY;
4078                 }
4079                 if (mdic & E1000_MDIC_ERROR) {
4080                         DEBUGOUT("MDI Error\n");
4081                         return -E1000_ERR_PHY;
4082                 }
4083                 *phy_data = (uint16_t) mdic;
4084         } else {
4085                 /* We must first send a preamble through the MDIO pin to signal the
4086                  * beginning of an MII instruction.  This is done by sending 32
4087                  * consecutive "1" bits.
4088                  */
4089                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4090
4091                 /* Now combine the next few fields that are required for a read
4092                  * operation.  We use this method instead of calling the
4093                  * e1000_shift_out_mdi_bits routine five different times. The format of
4094                  * a MII read instruction consists of a shift out of 14 bits and is
4095                  * defined as follows:
4096                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4097                  * followed by a shift in of 18 bits.  This first two bits shifted in
4098                  * are TurnAround bits used to avoid contention on the MDIO pin when a
4099                  * READ operation is performed.  These two bits are thrown away
4100                  * followed by a shift in of 16 bits which contains the desired data.
4101                  */
4102                 mdic = ((reg_addr) | (phy_addr << 5) |
4103                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
4104
4105                 e1000_shift_out_mdi_bits(hw, mdic, 14);
4106
4107                 /* Now that we've shifted out the read command to the MII, we need to
4108                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
4109                  * register address.
4110                  */
4111                 *phy_data = e1000_shift_in_mdi_bits(hw);
4112         }
4113         return 0;
4114 }
4115
4116 /******************************************************************************
4117 * Writes a value to a PHY register
4118 *
4119 * hw - Struct containing variables accessed by shared code
4120 * reg_addr - address of the PHY register to write
4121 * data - data to write to the PHY
4122 ******************************************************************************/
4123 static int
4124 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4125 {
4126         uint32_t i;
4127         uint32_t mdic = 0;
4128         const uint32_t phy_addr = 1;
4129
4130         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4131                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4132                 return -E1000_ERR_PARAM;
4133         }
4134
4135         if (hw->mac_type > e1000_82543) {
4136                 /* Set up Op-code, Phy Address, register address, and data intended
4137                  * for the PHY register in the MDI Control register.  The MAC will take
4138                  * care of interfacing with the PHY to send the desired data.
4139                  */
4140                 mdic = (((uint32_t) phy_data) |
4141                         (reg_addr << E1000_MDIC_REG_SHIFT) |
4142                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4143                         (E1000_MDIC_OP_WRITE));
4144
4145                 E1000_WRITE_REG(hw, MDIC, mdic);
4146
4147                 /* Poll the ready bit to see if the MDI read completed */
4148                 for (i = 0; i < 64; i++) {
4149                         udelay(10);
4150                         mdic = E1000_READ_REG(hw, MDIC);
4151                         if (mdic & E1000_MDIC_READY)
4152                                 break;
4153                 }
4154                 if (!(mdic & E1000_MDIC_READY)) {
4155                         DEBUGOUT("MDI Write did not complete\n");
4156                         return -E1000_ERR_PHY;
4157                 }
4158         } else {
4159                 /* We'll need to use the SW defined pins to shift the write command
4160                  * out to the PHY. We first send a preamble to the PHY to signal the
4161                  * beginning of the MII instruction.  This is done by sending 32
4162                  * consecutive "1" bits.
4163                  */
4164                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4165
4166                 /* Now combine the remaining required fields that will indicate a
4167                  * write operation. We use this method instead of calling the
4168                  * e1000_shift_out_mdi_bits routine for each field in the command. The
4169                  * format of a MII write instruction is as follows:
4170                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4171                  */
4172                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4173                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4174                 mdic <<= 16;
4175                 mdic |= (uint32_t) phy_data;
4176
4177                 e1000_shift_out_mdi_bits(hw, mdic, 32);
4178         }
4179         return 0;
4180 }
4181
4182 /******************************************************************************
4183  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4184  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4185  * the caller to figure out how to deal with it.
4186  *
4187  * hw - Struct containing variables accessed by shared code
4188  *
4189  * returns: - E1000_BLK_PHY_RESET
4190  *            E1000_SUCCESS
4191  *
4192  *****************************************************************************/
4193 int32_t
4194 e1000_check_phy_reset_block(struct e1000_hw *hw)
4195 {
4196         uint32_t manc = 0;
4197         uint32_t fwsm = 0;
4198
4199         if (hw->mac_type == e1000_ich8lan) {
4200                 fwsm = E1000_READ_REG(hw, FWSM);
4201                 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4202                                                 : E1000_BLK_PHY_RESET;
4203         }
4204
4205         if (hw->mac_type > e1000_82547_rev_2)
4206                 manc = E1000_READ_REG(hw, MANC);
4207         return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4208                 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4209 }
4210
4211 /***************************************************************************
4212  * Checks if the PHY configuration is done
4213  *
4214  * hw: Struct containing variables accessed by shared code
4215  *
4216  * returns: - E1000_ERR_RESET if fail to reset MAC
4217  *            E1000_SUCCESS at any other case.
4218  *
4219  ***************************************************************************/
4220 static int32_t
4221 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4222 {
4223         int32_t timeout = PHY_CFG_TIMEOUT;
4224         uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4225
4226         DEBUGFUNC();
4227
4228         switch (hw->mac_type) {
4229         default:
4230                 mdelay(10);
4231                 break;
4232
4233         case e1000_80003es2lan:
4234                 /* Separate *_CFG_DONE_* bit for each port */
4235                 if (e1000_is_second_port(hw))
4236                         cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4237                 /* Fall Through */
4238
4239         case e1000_82571:
4240         case e1000_82572:
4241                 while (timeout) {
4242                         if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4243                                 break;
4244                         else
4245                                 mdelay(1);
4246                         timeout--;
4247                 }
4248                 if (!timeout) {
4249                         DEBUGOUT("MNG configuration cycle has not "
4250                                         "completed.\n");
4251                         return -E1000_ERR_RESET;
4252                 }
4253                 break;
4254         }
4255
4256         return E1000_SUCCESS;
4257 }
4258
4259 /******************************************************************************
4260 * Returns the PHY to the power-on reset state
4261 *
4262 * hw - Struct containing variables accessed by shared code
4263 ******************************************************************************/
4264 int32_t
4265 e1000_phy_hw_reset(struct e1000_hw *hw)
4266 {
4267         uint16_t swfw = E1000_SWFW_PHY0_SM;
4268         uint32_t ctrl, ctrl_ext;
4269         uint32_t led_ctrl;
4270         int32_t ret_val;
4271
4272         DEBUGFUNC();
4273
4274         /* In the case of the phy reset being blocked, it's not an error, we
4275          * simply return success without performing the reset. */
4276         ret_val = e1000_check_phy_reset_block(hw);
4277         if (ret_val)
4278                 return E1000_SUCCESS;
4279
4280         DEBUGOUT("Resetting Phy...\n");
4281
4282         if (hw->mac_type > e1000_82543) {
4283                 if (e1000_is_second_port(hw))
4284                         swfw = E1000_SWFW_PHY1_SM;
4285
4286                 if (e1000_swfw_sync_acquire(hw, swfw)) {
4287                         DEBUGOUT("Unable to acquire swfw sync\n");
4288                         return -E1000_ERR_SWFW_SYNC;
4289                 }
4290
4291                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4292                  * bit. Then, take it out of reset.
4293                  */
4294                 ctrl = E1000_READ_REG(hw, CTRL);
4295                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4296                 E1000_WRITE_FLUSH(hw);
4297
4298                 if (hw->mac_type < e1000_82571)
4299                         udelay(10);
4300                 else
4301                         udelay(100);
4302
4303                 E1000_WRITE_REG(hw, CTRL, ctrl);
4304                 E1000_WRITE_FLUSH(hw);
4305
4306                 if (hw->mac_type >= e1000_82571)
4307                         mdelay(10);
4308
4309         } else {
4310                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4311                  * bit to put the PHY into reset. Then, take it out of reset.
4312                  */
4313                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4314                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4315                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4316                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4317                 E1000_WRITE_FLUSH(hw);
4318                 mdelay(10);
4319                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4320                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4321                 E1000_WRITE_FLUSH(hw);
4322         }
4323         udelay(150);
4324
4325         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4326                 /* Configure activity LED after PHY reset */
4327                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4328                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4329                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4330                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4331         }
4332
4333         /* Wait for FW to finish PHY configuration. */
4334         ret_val = e1000_get_phy_cfg_done(hw);
4335         if (ret_val != E1000_SUCCESS)
4336                 return ret_val;
4337
4338         return ret_val;
4339 }
4340
4341 /******************************************************************************
4342  * IGP phy init script - initializes the GbE PHY
4343  *
4344  * hw - Struct containing variables accessed by shared code
4345  *****************************************************************************/
4346 static void
4347 e1000_phy_init_script(struct e1000_hw *hw)
4348 {
4349         uint32_t ret_val;
4350         uint16_t phy_saved_data;
4351         DEBUGFUNC();
4352
4353         if (hw->phy_init_script) {
4354                 mdelay(20);
4355
4356                 /* Save off the current value of register 0x2F5B to be
4357                  * restored at the end of this routine. */
4358                 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4359
4360                 /* Disabled the PHY transmitter */
4361                 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4362
4363                 mdelay(20);
4364
4365                 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4366
4367                 mdelay(5);
4368
4369                 switch (hw->mac_type) {
4370                 case e1000_82541:
4371                 case e1000_82547:
4372                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4373
4374                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4375
4376                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4377
4378                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4379
4380                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4381
4382                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4383
4384                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4385
4386                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4387
4388                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
4389                         break;
4390
4391                 case e1000_82541_rev_2:
4392                 case e1000_82547_rev_2:
4393                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4394                         break;
4395                 default:
4396                         break;
4397                 }
4398
4399                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4400
4401                 mdelay(20);
4402
4403                 /* Now enable the transmitter */
4404                 if (!ret_val)
4405                         e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4406
4407                 if (hw->mac_type == e1000_82547) {
4408                         uint16_t fused, fine, coarse;
4409
4410                         /* Move to analog registers page */
4411                         e1000_read_phy_reg(hw,
4412                                 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4413
4414                         if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4415                                 e1000_read_phy_reg(hw,
4416                                         IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4417
4418                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4419                                 coarse = fused
4420                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4421
4422                                 if (coarse >
4423                                         IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4424                                         coarse -=
4425                                         IGP01E1000_ANALOG_FUSE_COARSE_10;
4426                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4427                                 } else if (coarse
4428                                         == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4429                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4430
4431                                 fused = (fused
4432                                         & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4433                                         (fine
4434                                         & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4435                                         (coarse
4436                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4437
4438                                 e1000_write_phy_reg(hw,
4439                                         IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4440                                 e1000_write_phy_reg(hw,
4441                                         IGP01E1000_ANALOG_FUSE_BYPASS,
4442                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4443                         }
4444                 }
4445         }
4446 }
4447
4448 /******************************************************************************
4449 * Resets the PHY
4450 *
4451 * hw - Struct containing variables accessed by shared code
4452 *
4453 * Sets bit 15 of the MII Control register
4454 ******************************************************************************/
4455 int32_t
4456 e1000_phy_reset(struct e1000_hw *hw)
4457 {
4458         int32_t ret_val;
4459         uint16_t phy_data;
4460
4461         DEBUGFUNC();
4462
4463         /* In the case of the phy reset being blocked, it's not an error, we
4464          * simply return success without performing the reset. */
4465         ret_val = e1000_check_phy_reset_block(hw);
4466         if (ret_val)
4467                 return E1000_SUCCESS;
4468
4469         switch (hw->phy_type) {
4470         case e1000_phy_igp:
4471         case e1000_phy_igp_2:
4472         case e1000_phy_igp_3:
4473         case e1000_phy_ife:
4474                 ret_val = e1000_phy_hw_reset(hw);
4475                 if (ret_val)
4476                         return ret_val;
4477                 break;
4478         default:
4479                 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4480                 if (ret_val)
4481                         return ret_val;
4482
4483                 phy_data |= MII_CR_RESET;
4484                 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4485                 if (ret_val)
4486                         return ret_val;
4487
4488                 udelay(1);
4489                 break;
4490         }
4491
4492         if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4493                 e1000_phy_init_script(hw);
4494
4495         return E1000_SUCCESS;
4496 }
4497
4498 static int e1000_set_phy_type (struct e1000_hw *hw)
4499 {
4500         DEBUGFUNC ();
4501
4502         if (hw->mac_type == e1000_undefined)
4503                 return -E1000_ERR_PHY_TYPE;
4504
4505         switch (hw->phy_id) {
4506         case M88E1000_E_PHY_ID:
4507         case M88E1000_I_PHY_ID:
4508         case M88E1011_I_PHY_ID:
4509         case M88E1111_I_PHY_ID:
4510                 hw->phy_type = e1000_phy_m88;
4511                 break;
4512         case IGP01E1000_I_PHY_ID:
4513                 if (hw->mac_type == e1000_82541 ||
4514                         hw->mac_type == e1000_82541_rev_2 ||
4515                         hw->mac_type == e1000_82547 ||
4516                         hw->mac_type == e1000_82547_rev_2) {
4517                         hw->phy_type = e1000_phy_igp;
4518                         hw->phy_type = e1000_phy_igp;
4519                         break;
4520                 }
4521         case IGP03E1000_E_PHY_ID:
4522                 hw->phy_type = e1000_phy_igp_3;
4523                 break;
4524         case IFE_E_PHY_ID:
4525         case IFE_PLUS_E_PHY_ID:
4526         case IFE_C_E_PHY_ID:
4527                 hw->phy_type = e1000_phy_ife;
4528                 break;
4529         case GG82563_E_PHY_ID:
4530                 if (hw->mac_type == e1000_80003es2lan) {
4531                         hw->phy_type = e1000_phy_gg82563;
4532                         break;
4533                 }
4534         case BME1000_E_PHY_ID:
4535                 hw->phy_type = e1000_phy_bm;
4536                 break;
4537                 /* Fall Through */
4538         default:
4539                 /* Should never have loaded on this device */
4540                 hw->phy_type = e1000_phy_undefined;
4541                 return -E1000_ERR_PHY_TYPE;
4542         }
4543
4544         return E1000_SUCCESS;
4545 }
4546
4547 /******************************************************************************
4548 * Probes the expected PHY address for known PHY IDs
4549 *
4550 * hw - Struct containing variables accessed by shared code
4551 ******************************************************************************/
4552 static int32_t
4553 e1000_detect_gig_phy(struct e1000_hw *hw)
4554 {
4555         int32_t phy_init_status, ret_val;
4556         uint16_t phy_id_high, phy_id_low;
4557         bool match = false;
4558
4559         DEBUGFUNC();
4560
4561         /* The 82571 firmware may still be configuring the PHY.  In this
4562          * case, we cannot access the PHY until the configuration is done.  So
4563          * we explicitly set the PHY values. */
4564         if (hw->mac_type == e1000_82571 ||
4565                 hw->mac_type == e1000_82572) {
4566                 hw->phy_id = IGP01E1000_I_PHY_ID;
4567                 hw->phy_type = e1000_phy_igp_2;
4568                 return E1000_SUCCESS;
4569         }
4570
4571         /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4572          * work- around that forces PHY page 0 to be set or the reads fail.
4573          * The rest of the code in this routine uses e1000_read_phy_reg to
4574          * read the PHY ID.  So for ESB-2 we need to have this set so our
4575          * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4576          * the routines below will figure this out as well. */
4577         if (hw->mac_type == e1000_80003es2lan)
4578                 hw->phy_type = e1000_phy_gg82563;
4579
4580         /* Read the PHY ID Registers to identify which PHY is onboard. */
4581         ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4582         if (ret_val)
4583                 return ret_val;
4584
4585         hw->phy_id = (uint32_t) (phy_id_high << 16);
4586         udelay(20);
4587         ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4588         if (ret_val)
4589                 return ret_val;
4590
4591         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4592         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4593
4594         switch (hw->mac_type) {
4595         case e1000_82543:
4596                 if (hw->phy_id == M88E1000_E_PHY_ID)
4597                         match = true;
4598                 break;
4599         case e1000_82544:
4600                 if (hw->phy_id == M88E1000_I_PHY_ID)
4601                         match = true;
4602                 break;
4603         case e1000_82540:
4604         case e1000_82545:
4605         case e1000_82545_rev_3:
4606         case e1000_82546:
4607         case e1000_82546_rev_3:
4608                 if (hw->phy_id == M88E1011_I_PHY_ID)
4609                         match = true;
4610                 break;
4611         case e1000_82541:
4612         case e1000_82541_rev_2:
4613         case e1000_82547:
4614         case e1000_82547_rev_2:
4615                 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4616                         match = true;
4617
4618                 break;
4619         case e1000_82573:
4620                 if (hw->phy_id == M88E1111_I_PHY_ID)
4621                         match = true;
4622                 break;
4623         case e1000_82574:
4624                 if (hw->phy_id == BME1000_E_PHY_ID)
4625                         match = true;
4626                 break;
4627         case e1000_80003es2lan:
4628                 if (hw->phy_id == GG82563_E_PHY_ID)
4629                         match = true;
4630                 break;
4631         case e1000_ich8lan:
4632                 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4633                         match = true;
4634                 if (hw->phy_id == IFE_E_PHY_ID)
4635                         match = true;
4636                 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4637                         match = true;
4638                 if (hw->phy_id == IFE_C_E_PHY_ID)
4639                         match = true;
4640                 break;
4641         default:
4642                 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4643                 return -E1000_ERR_CONFIG;
4644         }
4645
4646         phy_init_status = e1000_set_phy_type(hw);
4647
4648         if ((match) && (phy_init_status == E1000_SUCCESS)) {
4649                 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4650                 return 0;
4651         }
4652         DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4653         return -E1000_ERR_PHY;
4654 }
4655
4656 /*****************************************************************************
4657  * Set media type and TBI compatibility.
4658  *
4659  * hw - Struct containing variables accessed by shared code
4660  * **************************************************************************/
4661 void
4662 e1000_set_media_type(struct e1000_hw *hw)
4663 {
4664         uint32_t status;
4665
4666         DEBUGFUNC();
4667
4668         if (hw->mac_type != e1000_82543) {
4669                 /* tbi_compatibility is only valid on 82543 */
4670                 hw->tbi_compatibility_en = false;
4671         }
4672
4673         switch (hw->device_id) {
4674         case E1000_DEV_ID_82545GM_SERDES:
4675         case E1000_DEV_ID_82546GB_SERDES:
4676         case E1000_DEV_ID_82571EB_SERDES:
4677         case E1000_DEV_ID_82571EB_SERDES_DUAL:
4678         case E1000_DEV_ID_82571EB_SERDES_QUAD:
4679         case E1000_DEV_ID_82572EI_SERDES:
4680         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4681                 hw->media_type = e1000_media_type_internal_serdes;
4682                 break;
4683         default:
4684                 switch (hw->mac_type) {
4685                 case e1000_82542_rev2_0:
4686                 case e1000_82542_rev2_1:
4687                         hw->media_type = e1000_media_type_fiber;
4688                         break;
4689                 case e1000_ich8lan:
4690                 case e1000_82573:
4691                 case e1000_82574:
4692                         /* The STATUS_TBIMODE bit is reserved or reused
4693                          * for the this device.
4694                          */
4695                         hw->media_type = e1000_media_type_copper;
4696                         break;
4697                 default:
4698                         status = E1000_READ_REG(hw, STATUS);
4699                         if (status & E1000_STATUS_TBIMODE) {
4700                                 hw->media_type = e1000_media_type_fiber;
4701                                 /* tbi_compatibility not valid on fiber */
4702                                 hw->tbi_compatibility_en = false;
4703                         } else {
4704                                 hw->media_type = e1000_media_type_copper;
4705                         }
4706                         break;
4707                 }
4708         }
4709 }
4710
4711 /**
4712  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4713  *
4714  * e1000_sw_init initializes the Adapter private data structure.
4715  * Fields are initialized based on PCI device information and
4716  * OS network device settings (MTU size).
4717  **/
4718
4719 static int
4720 e1000_sw_init(struct eth_device *nic)
4721 {
4722         struct e1000_hw *hw = (typeof(hw)) nic->priv;
4723         int result;
4724
4725         /* PCI config space info */
4726         pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4727         pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4728         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4729                              &hw->subsystem_vendor_id);
4730         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4731
4732         pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4733         pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4734
4735         /* identify the MAC */
4736         result = e1000_set_mac_type(hw);
4737         if (result) {
4738                 E1000_ERR(hw->nic, "Unknown MAC Type\n");
4739                 return result;
4740         }
4741
4742         switch (hw->mac_type) {
4743         default:
4744                 break;
4745         case e1000_82541:
4746         case e1000_82547:
4747         case e1000_82541_rev_2:
4748         case e1000_82547_rev_2:
4749                 hw->phy_init_script = 1;
4750                 break;
4751         }
4752
4753         /* flow control settings */
4754         hw->fc_high_water = E1000_FC_HIGH_THRESH;
4755         hw->fc_low_water = E1000_FC_LOW_THRESH;
4756         hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4757         hw->fc_send_xon = 1;
4758
4759         /* Media type - copper or fiber */
4760         e1000_set_media_type(hw);
4761
4762         if (hw->mac_type >= e1000_82543) {
4763                 uint32_t status = E1000_READ_REG(hw, STATUS);
4764
4765                 if (status & E1000_STATUS_TBIMODE) {
4766                         DEBUGOUT("fiber interface\n");
4767                         hw->media_type = e1000_media_type_fiber;
4768                 } else {
4769                         DEBUGOUT("copper interface\n");
4770                         hw->media_type = e1000_media_type_copper;
4771                 }
4772         } else {
4773                 hw->media_type = e1000_media_type_fiber;
4774         }
4775
4776         hw->tbi_compatibility_en = true;
4777         hw->wait_autoneg_complete = true;
4778         if (hw->mac_type < e1000_82543)
4779                 hw->report_tx_early = 0;
4780         else
4781                 hw->report_tx_early = 1;
4782
4783         return E1000_SUCCESS;
4784 }
4785
4786 void
4787 fill_rx(struct e1000_hw *hw)
4788 {
4789         struct e1000_rx_desc *rd;
4790
4791         rx_last = rx_tail;
4792         rd = rx_base + rx_tail;
4793         rx_tail = (rx_tail + 1) % 8;
4794         memset(rd, 0, 16);
4795         rd->buffer_addr = cpu_to_le64((u32) & packet);
4796         E1000_WRITE_REG(hw, RDT, rx_tail);
4797 }
4798
4799 /**
4800  * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4801  * @adapter: board private structure
4802  *
4803  * Configure the Tx unit of the MAC after a reset.
4804  **/
4805
4806 static void
4807 e1000_configure_tx(struct e1000_hw *hw)
4808 {
4809         unsigned long ptr;
4810         unsigned long tctl;
4811         unsigned long tipg, tarc;
4812         uint32_t ipgr1, ipgr2;
4813
4814         ptr = (u32) tx_pool;
4815         if (ptr & 0xf)
4816                 ptr = (ptr + 0x10) & (~0xf);
4817
4818         tx_base = (typeof(tx_base)) ptr;
4819
4820         E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
4821         E1000_WRITE_REG(hw, TDBAH, 0);
4822
4823         E1000_WRITE_REG(hw, TDLEN, 128);
4824
4825         /* Setup the HW Tx Head and Tail descriptor pointers */
4826         E1000_WRITE_REG(hw, TDH, 0);
4827         E1000_WRITE_REG(hw, TDT, 0);
4828         tx_tail = 0;
4829
4830         /* Set the default values for the Tx Inter Packet Gap timer */
4831         if (hw->mac_type <= e1000_82547_rev_2 &&
4832             (hw->media_type == e1000_media_type_fiber ||
4833              hw->media_type == e1000_media_type_internal_serdes))
4834                 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4835         else
4836                 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4837
4838         /* Set the default values for the Tx Inter Packet Gap timer */
4839         switch (hw->mac_type) {
4840         case e1000_82542_rev2_0:
4841         case e1000_82542_rev2_1:
4842                 tipg = DEFAULT_82542_TIPG_IPGT;
4843                 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4844                 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4845                 break;
4846         case e1000_80003es2lan:
4847                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4848                 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
4849                 break;
4850         default:
4851                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4852                 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
4853                 break;
4854         }
4855         tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
4856         tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
4857         E1000_WRITE_REG(hw, TIPG, tipg);
4858         /* Program the Transmit Control Register */
4859         tctl = E1000_READ_REG(hw, TCTL);
4860         tctl &= ~E1000_TCTL_CT;
4861         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
4862             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4863
4864         if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
4865                 tarc = E1000_READ_REG(hw, TARC0);
4866                 /* set the speed mode bit, we'll clear it if we're not at
4867                  * gigabit link later */
4868                 /* git bit can be set to 1*/
4869         } else if (hw->mac_type == e1000_80003es2lan) {
4870                 tarc = E1000_READ_REG(hw, TARC0);
4871                 tarc |= 1;
4872                 E1000_WRITE_REG(hw, TARC0, tarc);
4873                 tarc = E1000_READ_REG(hw, TARC1);
4874                 tarc |= 1;
4875                 E1000_WRITE_REG(hw, TARC1, tarc);
4876         }
4877
4878
4879         e1000_config_collision_dist(hw);
4880         /* Setup Transmit Descriptor Settings for eop descriptor */
4881         hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
4882
4883         /* Need to set up RS bit */
4884         if (hw->mac_type < e1000_82543)
4885                 hw->txd_cmd |= E1000_TXD_CMD_RPS;
4886         else
4887                 hw->txd_cmd |= E1000_TXD_CMD_RS;
4888         E1000_WRITE_REG(hw, TCTL, tctl);
4889 }
4890
4891 /**
4892  * e1000_setup_rctl - configure the receive control register
4893  * @adapter: Board private structure
4894  **/
4895 static void
4896 e1000_setup_rctl(struct e1000_hw *hw)
4897 {
4898         uint32_t rctl;
4899
4900         rctl = E1000_READ_REG(hw, RCTL);
4901
4902         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4903
4904         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
4905                 | E1000_RCTL_RDMTS_HALF;        /* |
4906                         (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
4907
4908         if (hw->tbi_compatibility_on == 1)
4909                 rctl |= E1000_RCTL_SBP;
4910         else
4911                 rctl &= ~E1000_RCTL_SBP;
4912
4913         rctl &= ~(E1000_RCTL_SZ_4096);
4914                 rctl |= E1000_RCTL_SZ_2048;
4915                 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
4916         E1000_WRITE_REG(hw, RCTL, rctl);
4917 }
4918
4919 /**
4920  * e1000_configure_rx - Configure 8254x Receive Unit after Reset
4921  * @adapter: board private structure
4922  *
4923  * Configure the Rx unit of the MAC after a reset.
4924  **/
4925 static void
4926 e1000_configure_rx(struct e1000_hw *hw)
4927 {
4928         unsigned long ptr;
4929         unsigned long rctl, ctrl_ext;
4930         rx_tail = 0;
4931         /* make sure receives are disabled while setting up the descriptors */
4932         rctl = E1000_READ_REG(hw, RCTL);
4933         E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
4934         if (hw->mac_type >= e1000_82540) {
4935                 /* Set the interrupt throttling rate.  Value is calculated
4936                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
4937 #define MAX_INTS_PER_SEC        8000
4938 #define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
4939                 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
4940         }
4941
4942         if (hw->mac_type >= e1000_82571) {
4943                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4944                 /* Reset delay timers after every interrupt */
4945                 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
4946                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4947                 E1000_WRITE_FLUSH(hw);
4948         }
4949         /* Setup the Base and Length of the Rx Descriptor Ring */
4950         ptr = (u32) rx_pool;
4951         if (ptr & 0xf)
4952                 ptr = (ptr + 0x10) & (~0xf);
4953         rx_base = (typeof(rx_base)) ptr;
4954         E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
4955         E1000_WRITE_REG(hw, RDBAH, 0);
4956
4957         E1000_WRITE_REG(hw, RDLEN, 128);
4958
4959         /* Setup the HW Rx Head and Tail Descriptor Pointers */
4960         E1000_WRITE_REG(hw, RDH, 0);
4961         E1000_WRITE_REG(hw, RDT, 0);
4962         /* Enable Receives */
4963
4964         E1000_WRITE_REG(hw, RCTL, rctl);
4965         fill_rx(hw);
4966 }
4967
4968 /**************************************************************************
4969 POLL - Wait for a frame
4970 ***************************************************************************/
4971 static int
4972 e1000_poll(struct eth_device *nic)
4973 {
4974         struct e1000_hw *hw = nic->priv;
4975         struct e1000_rx_desc *rd;
4976         /* return true if there's an ethernet packet ready to read */
4977         rd = rx_base + rx_last;
4978         if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
4979                 return 0;
4980         /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
4981         NetReceive((uchar *)packet, le32_to_cpu(rd->length));
4982         fill_rx(hw);
4983         return 1;
4984 }
4985
4986 /**************************************************************************
4987 TRANSMIT - Transmit a frame
4988 ***************************************************************************/
4989 static int e1000_transmit(struct eth_device *nic, void *packet, int length)
4990 {
4991         void *nv_packet = (void *)packet;
4992         struct e1000_hw *hw = nic->priv;
4993         struct e1000_tx_desc *txp;
4994         int i = 0;
4995
4996         txp = tx_base + tx_tail;
4997         tx_tail = (tx_tail + 1) % 8;
4998
4999         txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5000         txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5001         txp->upper.data = 0;
5002         E1000_WRITE_REG(hw, TDT, tx_tail);
5003
5004         E1000_WRITE_FLUSH(hw);
5005         while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
5006                 if (i++ > TOUT_LOOP) {
5007                         DEBUGOUT("e1000: tx timeout\n");
5008                         return 0;
5009                 }
5010                 udelay(10);     /* give the nic a chance to write to the register */
5011         }
5012         return 1;
5013 }
5014
5015 /*reset function*/
5016 static inline int
5017 e1000_reset(struct eth_device *nic)
5018 {
5019         struct e1000_hw *hw = nic->priv;
5020
5021         e1000_reset_hw(hw);
5022         if (hw->mac_type >= e1000_82544) {
5023                 E1000_WRITE_REG(hw, WUC, 0);
5024         }
5025         return e1000_init_hw(nic);
5026 }
5027
5028 /**************************************************************************
5029 DISABLE - Turn off ethernet interface
5030 ***************************************************************************/
5031 static void
5032 e1000_disable(struct eth_device *nic)
5033 {
5034         struct e1000_hw *hw = nic->priv;
5035
5036         /* Turn off the ethernet interface */
5037         E1000_WRITE_REG(hw, RCTL, 0);
5038         E1000_WRITE_REG(hw, TCTL, 0);
5039
5040         /* Clear the transmit ring */
5041         E1000_WRITE_REG(hw, TDH, 0);
5042         E1000_WRITE_REG(hw, TDT, 0);
5043
5044         /* Clear the receive ring */
5045         E1000_WRITE_REG(hw, RDH, 0);
5046         E1000_WRITE_REG(hw, RDT, 0);
5047
5048         /* put the card in its initial state */
5049 #if 0
5050         E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5051 #endif
5052         mdelay(10);
5053
5054 }
5055
5056 /**************************************************************************
5057 INIT - set up ethernet interface(s)
5058 ***************************************************************************/
5059 static int
5060 e1000_init(struct eth_device *nic, bd_t * bis)
5061 {
5062         struct e1000_hw *hw = nic->priv;
5063         int ret_val = 0;
5064
5065         ret_val = e1000_reset(nic);
5066         if (ret_val < 0) {
5067                 if ((ret_val == -E1000_ERR_NOLINK) ||
5068                     (ret_val == -E1000_ERR_TIMEOUT)) {
5069                         E1000_ERR(hw->nic, "Valid Link not detected\n");
5070                 } else {
5071                         E1000_ERR(hw->nic, "Hardware Initialization Failed\n");
5072                 }
5073                 return 0;
5074         }
5075         e1000_configure_tx(hw);
5076         e1000_setup_rctl(hw);
5077         e1000_configure_rx(hw);
5078         return 1;
5079 }
5080
5081 /******************************************************************************
5082  * Gets the current PCI bus type of hardware
5083  *
5084  * hw - Struct containing variables accessed by shared code
5085  *****************************************************************************/
5086 void e1000_get_bus_type(struct e1000_hw *hw)
5087 {
5088         uint32_t status;
5089
5090         switch (hw->mac_type) {
5091         case e1000_82542_rev2_0:
5092         case e1000_82542_rev2_1:
5093                 hw->bus_type = e1000_bus_type_pci;
5094                 break;
5095         case e1000_82571:
5096         case e1000_82572:
5097         case e1000_82573:
5098         case e1000_82574:
5099         case e1000_80003es2lan:
5100                 hw->bus_type = e1000_bus_type_pci_express;
5101                 break;
5102         case e1000_ich8lan:
5103                 hw->bus_type = e1000_bus_type_pci_express;
5104                 break;
5105         default:
5106                 status = E1000_READ_REG(hw, STATUS);
5107                 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5108                                 e1000_bus_type_pcix : e1000_bus_type_pci;
5109                 break;
5110         }
5111 }
5112
5113 /* A list of all registered e1000 devices */
5114 static LIST_HEAD(e1000_hw_list);
5115
5116 /**************************************************************************
5117 PROBE - Look for an adapter, this routine's visible to the outside
5118 You should omit the last argument struct pci_device * for a non-PCI NIC
5119 ***************************************************************************/
5120 int
5121 e1000_initialize(bd_t * bis)
5122 {
5123         unsigned int i;
5124         pci_dev_t devno;
5125
5126         DEBUGFUNC();
5127
5128         /* Find and probe all the matching PCI devices */
5129         for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5130                 u32 val;
5131
5132                 /*
5133                  * These will never get freed due to errors, this allows us to
5134                  * perform SPI EEPROM programming from U-boot, for example.
5135                  */
5136                 struct eth_device *nic = malloc(sizeof(*nic));
5137                 struct e1000_hw *hw = malloc(sizeof(*hw));
5138                 if (!nic || !hw) {
5139                         printf("e1000#%u: Out of Memory!\n", i);
5140                         free(nic);
5141                         free(hw);
5142                         continue;
5143                 }
5144
5145                 /* Make sure all of the fields are initially zeroed */
5146                 memset(nic, 0, sizeof(*nic));
5147                 memset(hw, 0, sizeof(*hw));
5148
5149                 /* Assign the passed-in values */
5150                 hw->cardnum = i;
5151                 hw->pdev = devno;
5152                 hw->nic = nic;
5153                 nic->priv = hw;
5154
5155                 /* Generate a card name */
5156                 sprintf(nic->name, "e1000#%u", hw->cardnum);
5157
5158                 /* Print a debug message with the IO base address */
5159                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5160                 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0);
5161
5162                 /* Try to enable I/O accesses and bus-mastering */
5163                 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5164                 pci_write_config_dword(devno, PCI_COMMAND, val);
5165
5166                 /* Make sure it worked */
5167                 pci_read_config_dword(devno, PCI_COMMAND, &val);
5168                 if (!(val & PCI_COMMAND_MEMORY)) {
5169                         E1000_ERR(nic, "Can't enable I/O memory\n");
5170                         continue;
5171                 }
5172                 if (!(val & PCI_COMMAND_MASTER)) {
5173                         E1000_ERR(nic, "Can't enable bus-mastering\n");
5174                         continue;
5175                 }
5176
5177                 /* Are these variables needed? */
5178                 hw->fc = e1000_fc_default;
5179                 hw->original_fc = e1000_fc_default;
5180                 hw->autoneg_failed = 0;
5181                 hw->autoneg = 1;
5182                 hw->get_link_status = true;
5183                 hw->hw_addr = pci_map_bar(devno,        PCI_BASE_ADDRESS_0,
5184                                                         PCI_REGION_MEM);
5185                 hw->mac_type = e1000_undefined;
5186
5187                 /* MAC and Phy settings */
5188                 if (e1000_sw_init(nic) < 0) {
5189                         E1000_ERR(nic, "Software init failed\n");
5190                         continue;
5191                 }
5192                 if (e1000_check_phy_reset_block(hw))
5193                         E1000_ERR(nic, "PHY Reset is blocked!\n");
5194
5195                 /* Basic init was OK, reset the hardware and allow SPI access */
5196                 e1000_reset_hw(hw);
5197                 list_add_tail(&hw->list_node, &e1000_hw_list);
5198
5199                 /* Validate the EEPROM and get chipset information */
5200 #if !defined(CONFIG_MVBC_1G)
5201                 if (e1000_init_eeprom_params(hw)) {
5202                         E1000_ERR(nic, "EEPROM is invalid!\n");
5203                         continue;
5204                 }
5205                 if (e1000_validate_eeprom_checksum(hw))
5206                         continue;
5207 #endif
5208                 e1000_read_mac_addr(nic);
5209                 e1000_get_bus_type(hw);
5210
5211                 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n       ",
5212                        nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5213                        nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5214
5215                 /* Set up the function pointers and register the device */
5216                 nic->init = e1000_init;
5217                 nic->recv = e1000_poll;
5218                 nic->send = e1000_transmit;
5219                 nic->halt = e1000_disable;
5220                 eth_register(nic);
5221         }
5222
5223         return i;
5224 }
5225
5226 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5227 {
5228         struct e1000_hw *hw;
5229
5230         list_for_each_entry(hw, &e1000_hw_list, list_node)
5231                 if (hw->cardnum == cardnum)
5232                         return hw;
5233
5234         return NULL;
5235 }
5236
5237 #ifdef CONFIG_CMD_E1000
5238 static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5239                 int argc, char * const argv[])
5240 {
5241         struct e1000_hw *hw;
5242
5243         if (argc < 3) {
5244                 cmd_usage(cmdtp);
5245                 return 1;
5246         }
5247
5248         /* Make sure we can find the requested e1000 card */
5249         hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10));
5250         if (!hw) {
5251                 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5252                 return 1;
5253         }
5254
5255         if (!strcmp(argv[2], "print-mac-address")) {
5256                 unsigned char *mac = hw->nic->enetaddr;
5257                 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5258                         mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5259                 return 0;
5260         }
5261
5262 #ifdef CONFIG_E1000_SPI
5263         /* Handle the "SPI" subcommand */
5264         if (!strcmp(argv[2], "spi"))
5265                 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5266 #endif
5267
5268         cmd_usage(cmdtp);
5269         return 1;
5270 }
5271
5272 U_BOOT_CMD(
5273         e1000, 7, 0, do_e1000,
5274         "Intel e1000 controller management",
5275         /*  */"<card#> print-mac-address\n"
5276 #ifdef CONFIG_E1000_SPI
5277         "e1000 <card#> spi show [<offset> [<length>]]\n"
5278         "e1000 <card#> spi dump <addr> <offset> <length>\n"
5279         "e1000 <card#> spi program <addr> <offset> <length>\n"
5280         "e1000 <card#> spi checksum [update]\n"
5281 #endif
5282         "       - Manage the Intel E1000 PCI device"
5283 );
5284 #endif /* not CONFIG_CMD_E1000 */