1 /******************************************************************************
4 * Project: GEnesis, PCI Gigabit Ethernet Adapter
7 * Purpose: Contains functions to initialize the GE HW
9 ******************************************************************************/
11 /******************************************************************************
13 * (C)Copyright 1998-2003 SysKonnect GmbH.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * The information in this file is provided "AS IS" without warranty.
22 ******************************************************************************/
24 /******************************************************************************
29 * Revision 1.1.3.1 2011-02-28 14:53:19 lothar
30 * imported Ka-Ro specific additions to U-Boot 2009.08 for TX28
32 * Revision 1.85 2003/02/05 15:30:33 rschmidt
33 * Corrected setting of GIHstClkFact (Host Clock Factor) and
34 * GIPollTimerVal (Descr. Poll Timer Init Value) for YUKON.
37 * Revision 1.84 2003/01/28 09:57:25 rschmidt
38 * Added detection of YUKON-Lite Rev. A0 (stored in GIYukonLite).
39 * Disabled Rx GMAC FIFO Flush for YUKON-Lite Rev. A0.
40 * Added support for CLK_RUN (YUKON-Lite).
41 * Added additional check of PME from D3cold for setting GIVauxAvail.
44 * Revision 1.83 2002/12/17 16:15:41 rschmidt
45 * Added default setting of PhyType (Copper) for YUKON.
46 * Added define around check for HW self test results.
49 * Revision 1.82 2002/12/05 13:40:21 rschmidt
50 * Added setting of Rx GMAC FIFO Flush Mask register.
51 * Corrected PhyType with new define SK_PHY_MARV_FIBER when
52 * YUKON Fiber board was found.
55 * Revision 1.81 2002/11/15 12:48:35 rschmidt
56 * Replaced message SKERR_HWI_E018 with SKERR_HWI_E024 for Rx queue error
58 * Added init for pAC->GIni.GIGenesis with SK_FALSE in YUKON-branch.
61 * Revision 1.80 2002/11/12 17:28:30 rschmidt
62 * Initialized GIPciSlot64 and GIPciClock66 in SkGeInit1().
63 * Reduced PCI FIFO watermarks for 32bit/33MHz bus in SkGeInitBmu().
66 * Revision 1.79 2002/10/21 09:31:02 mkarl
67 * Changed SkGeInitAssignRamToQueues(), removed call to
68 * SkGeInitAssignRamToQueues in SkGeInit1 and fixed compiler warning in
71 * Revision 1.78 2002/10/16 15:55:07 mkarl
72 * Fixed a bug in SkGeInitAssignRamToQueues.
74 * Revision 1.77 2002/10/14 15:07:22 rschmidt
75 * Corrected timeout handling for Rx queue in SkGeStopPort() (#10748)
78 * Revision 1.76 2002/10/11 09:24:38 mkarl
79 * Added check for HW self test results.
81 * Revision 1.75 2002/10/09 16:56:44 mkarl
82 * Now call SkGeInitAssignRamToQueues() in Init Level 1 in order to assign
83 * the adapter memory to the queues. This default assignment is not suitable
86 * Revision 1.74 2002/09/12 08:45:06 rwahl
87 * Set defaults for PMSCap, PLinkSpeed & PLinkSpeedCap dependent on PHY.
89 * Revision 1.73 2002/08/16 15:19:45 rschmidt
90 * Corrected check for Tx queues in SkGeCheckQSize().
91 * Added init for new entry GIGenesis and GICopperType
92 * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis.
93 * Replaced wrong 1st para pAC with IoC in SK_IN/OUT macros.
95 * Revision 1.72 2002/08/12 13:38:55 rschmidt
96 * Added check if VAUX is available (stored in GIVauxAvail)
97 * Initialized PLinkSpeedCap in Port struct with SK_LSPEED_CAP_1000MBPS
100 * Revision 1.71 2002/08/08 16:32:58 rschmidt
101 * Added check for Tx queues in SkGeCheckQSize().
102 * Added start of Time Stamp Timer (YUKON) in SkGeInit2().
105 * Revision 1.70 2002/07/23 16:04:26 rschmidt
106 * Added init for GIWolOffs (HW-Bug in YUKON 1st rev.)
109 * Revision 1.69 2002/07/17 17:07:08 rwahl
110 * - SkGeInit1(): fixed PHY type debug output; corrected init of GIFunc
112 * - Editorial changes.
114 * Revision 1.68 2002/07/15 18:38:31 rwahl
115 * Added initialization for MAC type dependent function table.
117 * Revision 1.67 2002/07/15 15:45:39 rschmidt
118 * Added Tx Store & Forward for YUKON (GMAC Tx FIFO is only 1 kB)
119 * Replaced SK_PHY_MARV by SK_PHY_MARV_COPPER
122 * Revision 1.66 2002/06/10 09:35:08 rschmidt
123 * Replaced C++ comments (//)
126 * Revision 1.65 2002/06/05 08:33:37 rschmidt
127 * Changed GIRamSize and Reset sequence for YUKON.
128 * SkMacInit() replaced by SkXmInitMac() resp. SkGmInitMac()
130 * Revision 1.64 2002/04/25 13:03:20 rschmidt
131 * Changes for handling YUKON.
132 * Removed reference to xmac_ii.h (not necessary).
133 * Moved all defines into header file.
134 * Replaced all SkXm...() functions with SkMac...() to handle also
136 * Added handling for GMAC FIFO in SkGeInitMacFifo(), SkGeStopPort().
137 * Removed 'goto'-directive from SkGeCfgSync(), SkGeCheckQSize().
138 * Replaced all XMAC-access macros by functions: SkMacRxTxDisable(),
139 * SkMacFlushTxFifo().
140 * Optimized timeout handling in SkGeStopPort().
141 * Initialized PLinkSpeed in Port struct with SK_LSPEED_AUTO.
142 * Release of GMAC Link Control reset in SkGeInit1().
143 * Initialized GIChipId and GIChipRev in GE Init structure.
144 * Added GIRamSize and PhyType values for YUKON.
145 * Removed use of PRxCmd to setup XMAC.
146 * Moved setting of XM_RX_DIS_CEXT to SkXmInitMac().
147 * Use of SkGeXmitLED() only for GENESIS.
148 * Changes for V-CPU support.
151 * Revision 1.63 2001/04/05 11:02:09 rassmann
152 * Stop Port check of the STOP bit did not take 2/18 sec as wanted.
154 * Revision 1.62 2001/02/07 07:54:21 rassmann
155 * Corrected copyright.
157 * Revision 1.61 2001/01/31 15:31:40 gklug
158 * fix: problem with autosensing an SR8800 switch
160 * Revision 1.60 2000/10/18 12:22:21 cgoos
161 * Added workaround for half duplex hangup.
163 * Revision 1.59 2000/10/10 11:22:06 gklug
164 * add: in manual half duplex mode ignore carrier extension errors
166 * Revision 1.58 2000/10/02 14:10:27 rassmann
167 * Reading BCOM PHY after releasing reset until it returns a valid value.
169 * Revision 1.57 2000/08/03 14:55:28 rassmann
170 * Waiting for I2C to be ready before de-initializing adapter
171 * (prevents sensors from hanging up).
173 * Revision 1.56 2000/07/27 12:16:48 gklug
174 * fix: Stop Port check of the STOP bit does now take 2/18 sec as wanted
176 * Revision 1.55 1999/11/22 13:32:26 cgoos
177 * Changed license header to GPL.
179 * Revision 1.54 1999/10/26 07:32:54 malthoff
180 * Initialize PHWLinkUp with SK_FALSE. Required for Diagnostics.
182 * Revision 1.53 1999/08/12 19:13:50 malthoff
183 * Fix for 1000BT. Do not owerwrite XM_MMU_CMD when
184 * disabling receiver and transmitter. Other bits
187 * Revision 1.52 1999/07/01 09:29:54 gklug
188 * fix: DoInitRamQueue needs pAC
190 * Revision 1.51 1999/07/01 08:42:21 gklug
191 * chg: use Store & forward for RAM buffer when Jumbos are used
193 * Revision 1.50 1999/05/27 13:19:38 cgoos
194 * Added Tx PCI watermark initialization.
195 * Removed Tx RAM queue Store & Forward setting.
197 * Revision 1.49 1999/05/20 14:32:45 malthoff
198 * SkGeLinkLED() is completly removed now.
200 * Revision 1.48 1999/05/19 07:28:24 cgoos
201 * SkGeLinkLED no more available for drivers.
202 * Changes for 1000Base-T.
204 * Revision 1.47 1999/04/08 13:57:45 gklug
205 * add: Init of new port struct fiels PLinkResCt
206 * chg: StopPort Timer check
208 * Revision 1.46 1999/03/25 07:42:15 malthoff
209 * SkGeStopPort(): Add workaround for cache incoherency.
210 * Create error log entry, disable port, and
211 * exit loop if it does not terminate.
212 * Add XM_RX_LENERR_OK to the default value for the
213 * XMAC receive command register.
215 * Revision 1.45 1999/03/12 16:24:47 malthoff
216 * Remove PPollRxD and PPollTxD.
217 * Add check for GIPollTimerVal.
219 * Revision 1.44 1999/03/12 13:40:23 malthoff
220 * Fix: SkGeXmitLED(), SK_LED_TST mode does not work.
221 * Add: Jumbo frame support.
222 * Chg: Resolution of parameter IntTime in SkGeCfgSync().
224 * Revision 1.43 1999/02/09 10:29:46 malthoff
225 * Bugfix: The previous modification again also for the second location.
227 * Revision 1.42 1999/02/09 09:35:16 malthoff
228 * Bugfix: The bits '66 MHz Capable' and 'NEWCAP are reset while
229 * clearing the error bits in the PCI status register.
231 * Revision 1.41 1999/01/18 13:07:02 malthoff
232 * Bugfix: Do not use CFG cycles after during Init- or Runtime, because
233 * they may not be available after Boottime.
235 * Revision 1.40 1999/01/11 12:40:49 malthoff
236 * Bug fix: PCI_STATUS: clearing error bits sets the UDF bit.
238 * Revision 1.39 1998/12/11 15:17:33 gklug
239 * chg: Init LipaAutoNeg with Unknown
241 * Revision 1.38 1998/12/10 11:02:57 malthoff
242 * Disable Error Log Message when calling SkGeInit(level 2)
245 * Revision 1.37 1998/12/07 12:18:25 gklug
246 * add: refinement of autosense mode: take into account the autoneg cap of LiPa
248 * Revision 1.36 1998/12/07 07:10:39 gklug
249 * fix: init values of LinkBroken/ Capabilities for management
251 * Revision 1.35 1998/12/02 10:56:20 gklug
252 * fix: do NOT init LoinkSync Counter.
254 * Revision 1.34 1998/12/01 10:53:21 gklug
255 * add: init of additional Counters for workaround
257 * Revision 1.33 1998/12/01 10:00:49 gklug
258 * add: init PIsave var in Port struct
260 * Revision 1.32 1998/11/26 14:50:40 gklug
261 * chg: Default is autosensing with AUTOFULL mode
263 * Revision 1.31 1998/11/25 15:36:16 gklug
264 * fix: do NOT stop LED Timer when port should be stopped
266 * Revision 1.30 1998/11/24 13:15:28 gklug
267 * add: Init PCkeckPar struct member
269 * Revision 1.29 1998/11/18 13:19:27 malthoff
270 * Disable packet arbiter timeouts on receive side.
271 * Use maximum timeout value for packet arbiter
273 * Add TestStopBit() function to handle stop RX/TX
274 * problem with active descriptor poll timers.
275 * Bug Fix: Descriptor Poll Timer not started, because
276 * GIPollTimerVal was initialized with 0.
278 * Revision 1.28 1998/11/13 14:24:26 malthoff
279 * Bug Fix: SkGeStopPort() may hang if a Packet Arbiter Timout
280 * is pending or occurs while waiting for TX_STOP and RX_STOP.
281 * The PA timeout is cleared now while waiting for TX- or RX_STOP.
283 * Revision 1.27 1998/11/02 11:04:36 malthoff
286 * Revision 1.26 1998/11/02 10:37:03 malthoff
287 * Fix: SkGePollTxD() enables always the synchronounous poll timer.
289 * Revision 1.25 1998/10/28 07:12:43 cgoos
290 * Fixed "LED_STOP" in SkGeLnkSyncCnt, "== SK_INIT_IO" in SkGeInit.
291 * Removed: Reset of RAM Interface in SkGeStopPort.
293 * Revision 1.24 1998/10/27 08:13:12 malthoff
294 * Remove temporary code.
296 * Revision 1.23 1998/10/26 07:45:03 malthoff
297 * Add Address Calculation Workaround: If the EPROM byte
298 * Id is 3, the address offset is 512 kB.
299 * Initialize default values for PLinkMode and PFlowCtrlMode.
301 * Revision 1.22 1998/10/22 09:46:47 gklug
302 * fix SysKonnectFileId typo
304 * Revision 1.21 1998/10/20 12:11:56 malthoff
305 * Don't dendy the Queue config if the size of the unused
308 * Revision 1.20 1998/10/19 07:27:58 malthoff
309 * SkGeInitRamIface() is public to be called by diagnostics.
311 * Revision 1.19 1998/10/16 13:33:45 malthoff
312 * Fix: enabling descriptor polling is not allowed until
313 * the descriptor addresses are set. Descriptor polling
314 * must be handled by the driver.
316 * Revision 1.18 1998/10/16 10:58:27 malthoff
317 * Remove temp. code for Diag prototype.
318 * Remove lint warning for dummy reads.
319 * Call SkGeLoadLnkSyncCnt() during SkGeInitPort().
321 * Revision 1.17 1998/10/14 09:16:06 malthoff
322 * Change parameter LimCount and programming of
323 * the limit counter in SkGeCfgSync().
325 * Revision 1.16 1998/10/13 09:21:16 malthoff
326 * Don't set XM_RX_SELF_RX in RxCmd Reg, because it's
327 * like a Loopback Mode in half duplex.
329 * Revision 1.15 1998/10/09 06:47:40 malthoff
330 * SkGeInitMacArb(): set recovery counters init value
331 * to zero although this counters are not uesd.
332 * Bug fix in Rx Upper/Lower Pause Threshold calculation.
333 * Add XM_RX_SELF_RX to RxCmd.
335 * Revision 1.14 1998/10/06 15:15:53 malthoff
336 * Make sure no pending IRQ is cleared in SkGeLoadLnkSyncCnt().
338 * Revision 1.13 1998/10/06 14:09:36 malthoff
339 * Add SkGeLoadLnkSyncCnt(). Modify
340 * the 'port stopped' condition according
341 * to the current problem report.
343 * Revision 1.12 1998/10/05 08:17:21 malthoff
344 * Add functions: SkGePollRxD(), SkGePollTxD(),
345 * DoCalcAddr(), SkGeCheckQSize(),
346 * DoInitRamQueue(), and SkGeCfgSync().
347 * Add coding for SkGeInitMacArb(), SkGeInitPktArb(),
348 * SkGeInitMacFifo(), SkGeInitRamBufs(),
349 * SkGeInitRamIface(), and SkGeInitBmu().
351 * Revision 1.11 1998/09/29 08:26:29 malthoff
352 * bug fix: SkGeInit0() 'i' should be increment.
354 * Revision 1.10 1998/09/28 13:19:01 malthoff
355 * Coding time: Save the done work.
356 * Modify SkGeLinkLED(), add SkGeXmitLED(),
357 * define SkGeCheckQSize(), SkGeInitMacArb(),
358 * SkGeInitPktArb(), SkGeInitMacFifo(),
359 * SkGeInitRamBufs(), SkGeInitRamIface(),
360 * and SkGeInitBmu(). Do coding for SkGeStopPort(),
361 * SkGeInit1(), SkGeInit2(), and SkGeInit3().
362 * Do coding for SkGeDinit() and SkGeInitPort().
364 * Revision 1.9 1998/09/16 14:29:05 malthoff
365 * Some minor changes.
367 * Revision 1.8 1998/09/11 05:29:14 gklug
368 * add: init state of a port
370 * Revision 1.7 1998/09/04 09:26:25 malthoff
371 * Short temporary modification.
373 * Revision 1.6 1998/09/04 08:27:59 malthoff
374 * Remark the do-while in StopPort() because it never ends
375 * without a GE adapter.
377 * Revision 1.5 1998/09/03 14:05:45 malthoff
378 * Change comment for SkGeInitPort(). Do not
379 * repair the queue sizes if invalid.
381 * Revision 1.4 1998/09/03 10:03:19 malthoff
382 * Implement the new interface according to the
383 * reviewed interface specification.
385 * Revision 1.3 1998/08/19 09:11:25 gklug
386 * fix: struct are removed from c-source (see CCC)
388 * Revision 1.2 1998/07/28 12:33:58 malthoff
389 * Add 'IoC' parameter in function declaration and SK IO macros.
391 * Revision 1.1 1998/07/23 09:48:57 malthoff
392 * Creation. First dummy 'C' file.
393 * SkGeInit(Level 0) is card_start for GE.
394 * SkGeDeInit() is card_stop for GE.
397 ******************************************************************************/
401 #include "h/skdrv1st.h"
402 #include "h/skdrv2nd.h"
404 /* global variables ***********************************************************/
406 /* local variables ************************************************************/
408 static const char SysKonnectFileId[] =
412 int RxQOff; /* Receive Queue Address Offset */
413 int XsQOff; /* Sync Tx Queue Address Offset */
414 int XaQOff; /* Async Tx Queue Address Offset */
416 static struct s_QOffTab QOffTab[] = {
417 {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2}
421 /******************************************************************************
423 * SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring
426 * Enable or disable the descriptor polling of the receive descriptor
427 * ring (RxD) for port 'Port'.
428 * The new configuration is *not* saved over any SkGeStopPort() and
429 * SkGeInitPort() calls.
435 SK_AC *pAC, /* adapter context */
436 SK_IOC IoC, /* IO context */
437 int Port, /* Port Index (MAC_1 + n) */
438 SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
442 pPrt = &pAC->GIni.GP[Port];
444 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (PollRxD) ?
445 CSR_ENA_POL : CSR_DIS_POL);
449 /******************************************************************************
451 * SkGePollTxD() - Enable / Disable Descriptor Polling of TxD Rings
454 * Enable or disable the descriptor polling of the transmit descriptor
455 * ring(s) (TxD) for port 'Port'.
456 * The new configuration is *not* saved over any SkGeStopPort() and
457 * SkGeInitPort() calls.
463 SK_AC *pAC, /* adapter context */
464 SK_IOC IoC, /* IO context */
465 int Port, /* Port Index (MAC_1 + n) */
466 SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
471 pPrt = &pAC->GIni.GP[Port];
473 DWord = (PollTxD) ? CSR_ENA_POL : CSR_DIS_POL;
475 if (pPrt->PXSQSize != 0) {
476 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord);
479 if (pPrt->PXAQSize != 0) {
480 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord);
485 /******************************************************************************
487 * SkGeYellowLED() - Switch the yellow LED on or off.
490 * Switch the yellow LED on or off.
493 * This function may be called any time after SkGeInit(Level 1).
499 SK_AC *pAC, /* adapter context */
500 SK_IOC IoC, /* IO context */
501 int State) /* yellow LED state, 0 = OFF, 0 != ON */
504 /* Switch yellow LED OFF */
505 SK_OUT8(IoC, B0_LED, LED_STAT_OFF);
508 /* Switch yellow LED ON */
509 SK_OUT8(IoC, B0_LED, LED_STAT_ON);
511 } /* SkGeYellowLED */
514 /******************************************************************************
516 * SkGeXmitLED() - Modify the Operational Mode of a transmission LED.
519 * The Rx or Tx LED which is specified by 'Led' will be
520 * enabled, disabled or switched on in test mode.
523 * 'Led' must contain the address offset of the LEDs INI register.
526 * SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
532 SK_AC *pAC, /* adapter context */
533 SK_IOC IoC, /* IO context */
534 int Led, /* offset to the LED Init Value register */
535 int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */
541 LedIni = SK_XMIT_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
542 SK_OUT32(IoC, Led + XMIT_LED_INI, LedIni);
543 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START);
546 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_ON);
547 SK_OUT32(IoC, Led + XMIT_LED_CNT, 100);
548 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START);
553 * Do NOT stop the LED Timer here. The LED might be
554 * in on state. But it needs to go off.
556 SK_OUT32(IoC, Led + XMIT_LED_CNT, 0);
557 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF);
562 * 1000BT: The Transmit LED is driven by the PHY.
563 * But the default LED configuration is used for
564 * Level One and Broadcom PHYs.
565 * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.)
566 * (In this case it has to be added here. But we will see. XXX)
571 /******************************************************************************
573 * DoCalcAddr() - Calculates the start and the end address of a queue.
576 * This function calculates the start and the end address of a queue.
577 * Afterwards the 'StartVal' is incremented to the next start position.
578 * If the port is already initialized the calculated values
579 * will be checked against the configured values and an
580 * error will be returned, if they are not equal.
581 * If the port is not initialized the values will be written to
582 * *StartAdr and *EndAddr.
586 * 1: configuration error
588 static int DoCalcAddr(
589 SK_AC *pAC, /* adapter context */
590 SK_GEPORT *pPrt, /* port index */
591 int QuSize, /* size of the queue to configure in kB */
592 SK_U32 *StartVal, /* start value for address calculation */
593 SK_U32 *QuStartAddr, /* start addr to calculate */
594 SK_U32 *QuEndAddr) /* end address to calculate */
606 EndVal = *StartVal + ((SK_U32)QuSize * 1024) - 1;
607 NextStart = EndVal + 1;
610 if (pPrt->PState >= SK_PRT_INIT) {
611 if (*StartVal != *QuStartAddr || EndVal != *QuEndAddr) {
616 *QuStartAddr = *StartVal;
620 *StartVal = NextStart;
624 /******************************************************************************
626 * SkGeInitAssignRamToQueues() - allocate default queue sizes
629 * This function assigns the memory to the different queues and ports.
630 * When DualNet is set to SK_TRUE all ports get the same amount of memory.
631 * Otherwise the first port gets most of the memory and all the
632 * other ports just the required minimum.
633 * This function can only be called when pAC->GIni.GIRamSize and
634 * pAC->GIni.GIMacsFound have been initialized, usually this happens
639 * 1 - invalid input values
640 * 2 - not enough memory
643 int SkGeInitAssignRamToQueues(
644 SK_AC *pAC, /* Adapter context */
645 int ActivePort, /* Active Port in RLMT mode */
646 SK_BOOL DualNet) /* adapter context */
649 int UsedKilobytes; /* memory already assigned */
650 int ActivePortKilobytes; /* memory available for active port */
655 if (ActivePort >= pAC->GIni.GIMacsFound) {
656 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
657 ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n",
661 if (((pAC->GIni.GIMacsFound * (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE)) +
662 ((RAM_QUOTA_SYNC == 0) ? 0 : SK_MIN_TXQ_SIZE)) > pAC->GIni.GIRamSize) {
663 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
664 ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n",
665 pAC->GIni.GIRamSize));
671 /* every port gets the same amount of memory */
672 ActivePortKilobytes = pAC->GIni.GIRamSize / pAC->GIni.GIMacsFound;
673 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
675 pGePort = &pAC->GIni.GP[i];
677 /* take away the minimum memory for active queues */
678 ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
680 /* receive queue gets the minimum + 80% of the rest */
681 pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((
682 ActivePortKilobytes * (unsigned long) RAM_QUOTA_RX) / 100))
685 ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
687 /* synchronous transmit queue */
688 pGePort->PXSQSize = 0;
690 /* asynchronous transmit queue */
691 pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes +
696 /* Rlmt Mode or single link adapter */
698 /* Set standby queue size defaults for all standby ports */
699 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
701 if (i != ActivePort) {
702 pGePort = &pAC->GIni.GP[i];
704 pGePort->PRxQSize = SK_MIN_RXQ_SIZE;
705 pGePort->PXAQSize = SK_MIN_TXQ_SIZE;
706 pGePort->PXSQSize = 0;
709 UsedKilobytes += pGePort->PRxQSize + pGePort->PXAQSize;
713 ActivePortKilobytes = pAC->GIni.GIRamSize - UsedKilobytes;
715 /* assign it to the active port */
716 /* first take away the minimum memory */
717 ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
718 pGePort = &pAC->GIni.GP[ActivePort];
720 /* receive queue get's the minimum + 80% of the rest */
721 pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes *
722 (unsigned long) RAM_QUOTA_RX) / 100)) + SK_MIN_RXQ_SIZE;
724 ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
726 /* synchronous transmit queue */
727 pGePort->PXSQSize = 0;
729 /* asynchronous transmit queue */
730 pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes) +
734 VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n",
735 pGePort->PRxQSize, pGePort->PXSQSize, pGePort->PXAQSize);
739 } /* SkGeInitAssignRamToQueues */
741 /******************************************************************************
743 * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration
746 * This function verifies the Queue Size Configuration specified
747 * in the variables PRxQSize, PXSQSize, and PXAQSize of all
749 * This requirements must be fullfilled to have a valid configuration:
750 * - The size of all queues must not exceed GIRamSize.
751 * - The queue sizes must be specified in units of 8 kB.
752 * - The size of Rx queues of available ports must not be
753 * smaller than 16 kB.
754 * - The size of at least one Tx queue (synch. or asynch.)
755 * of available ports must not be smaller than 16 kB
756 * when Jumbo Frames are used.
757 * - The RAM start and end addresses must not be changed
758 * for ports which are already initialized.
759 * Furthermore SkGeCheckQSize() defines the Start and End Addresses
760 * of all ports and stores them into the HWAC port structure.
763 * 0: Queue Size Configuration valid
764 * 1: Queue Size Configuration invalid
766 static int SkGeCheckQSize(
767 SK_AC *pAC, /* adapter context */
768 int Port) /* port index */
771 int UsedMem; /* total memory used (max. found ports) */
779 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
780 pPrt = &pAC->GIni.GP[i];
782 if ((pPrt->PRxQSize & QZ_UNITS) != 0 ||
783 (pPrt->PXSQSize & QZ_UNITS) != 0 ||
784 (pPrt->PXAQSize & QZ_UNITS) != 0) {
786 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
790 if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
791 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG);
796 * the size of at least one Tx queue (synch. or asynch.) has to be > 0.
797 * if Jumbo Frames are used, this size has to be >= 16 kB.
799 if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) ||
800 (pAC->GIni.GIPortUsage == SK_JUMBO_LINK &&
801 ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
802 (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) {
803 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG);
807 UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize;
810 if (UsedMem > pAC->GIni.GIRamSize) {
811 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
815 /* Now start address calculation */
816 StartAddr = pAC->GIni.GIRamOffs;
817 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
818 pPrt = &pAC->GIni.GP[i];
820 /* Calculate/Check values for the receive queue */
821 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr,
822 &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd);
825 /* Calculate/Check values for the synchronous Tx queue */
826 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXSQSize, &StartAddr,
827 &pPrt->PXsQRamStart, &pPrt->PXsQRamEnd);
830 /* Calculate/Check values for the asynchronous Tx queue */
831 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXAQSize, &StartAddr,
832 &pPrt->PXaQRamStart, &pPrt->PXaQRamEnd);
836 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E013, SKERR_HWI_E013MSG);
842 } /* SkGeCheckQSize */
845 /******************************************************************************
847 * SkGeInitMacArb() - Initialize the MAC Arbiter
850 * This function initializes the MAC Arbiter.
851 * It must not be called if there is still an
852 * initialized or active port.
857 static void SkGeInitMacArb(
858 SK_AC *pAC, /* adapter context */
859 SK_IOC IoC) /* IO context */
861 /* release local reset */
862 SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR);
864 /* configure timeout values */
865 SK_OUT8(IoC, B3_MA_TOINI_RX1, SK_MAC_TO_53);
866 SK_OUT8(IoC, B3_MA_TOINI_RX2, SK_MAC_TO_53);
867 SK_OUT8(IoC, B3_MA_TOINI_TX1, SK_MAC_TO_53);
868 SK_OUT8(IoC, B3_MA_TOINI_TX2, SK_MAC_TO_53);
870 SK_OUT8(IoC, B3_MA_RCINI_RX1, 0);
871 SK_OUT8(IoC, B3_MA_RCINI_RX2, 0);
872 SK_OUT8(IoC, B3_MA_RCINI_TX1, 0);
873 SK_OUT8(IoC, B3_MA_RCINI_TX2, 0);
875 /* recovery values are needed for XMAC II Rev. B2 only */
876 /* Fast Output Enable Mode was intended to use with Rev. B2, but now? */
879 * There is no start or enable button to push, therefore
880 * the MAC arbiter is configured and enabled now.
882 } /* SkGeInitMacArb */
885 /******************************************************************************
887 * SkGeInitPktArb() - Initialize the Packet Arbiter
890 * This function initializes the Packet Arbiter.
891 * It must not be called if there is still an
892 * initialized or active port.
897 static void SkGeInitPktArb(
898 SK_AC *pAC, /* adapter context */
899 SK_IOC IoC) /* IO context */
901 /* release local reset */
902 SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR);
904 /* configure timeout values */
905 SK_OUT16(IoC, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
906 SK_OUT16(IoC, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
907 SK_OUT16(IoC, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
908 SK_OUT16(IoC, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
911 * enable timeout timers if jumbo frames not used
912 * NOTE: the packet arbiter timeout interrupt is needed for
913 * half duplex hangup workaround
915 if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) {
916 if (pAC->GIni.GIMacsFound == 1) {
917 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1);
920 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1 | PA_ENA_TO_TX2);
923 } /* SkGeInitPktArb */
926 /******************************************************************************
928 * SkGeInitMacFifo() - Initialize the MAC FIFOs
931 * Initialize all MAC FIFOs of the specified port
936 static void SkGeInitMacFifo(
937 SK_AC *pAC, /* adapter context */
938 SK_IOC IoC, /* IO context */
939 int Port) /* Port Index (MAC_1 + n) */
947 * - release local reset
948 * - use default value for MAC FIFO size
949 * - setup defaults for the control register
953 Word = GMF_RX_CTRL_DEF;
955 if (pAC->GIni.GIGenesis) {
956 /* Configure Rx MAC FIFO */
957 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR);
958 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF);
959 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
961 /* Configure Tx MAC FIFO */
962 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR);
963 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
964 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
966 /* Enable frame flushing if jumbo frames used */
967 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
968 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
972 /* set Rx GMAC FIFO Flush Mask */
973 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK);
975 if (pAC->GIni.GIYukonLite && pAC->GIni.GIChipId == CHIP_ID_YUKON) {
977 Word &= ~GMF_RX_F_FL_ON;
980 /* Configure Rx MAC FIFO */
981 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
982 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word);
984 /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */
985 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
987 /* Configure Tx MAC FIFO */
988 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
989 SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF);
992 SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord);
993 SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord);
996 /* set Tx GMAC FIFO Almost Empty Threshold */
997 /* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */
999 } /* SkGeInitMacFifo */
1002 /******************************************************************************
1004 * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting
1007 * This function starts the Link Sync Counter of the specified
1008 * port and enables the generation of an Link Sync IRQ.
1009 * The Link Sync Counter may be used to detect an active link,
1010 * if autonegotiation is not used.
1013 * o To ensure receiving the Link Sync Event the LinkSyncCounter
1014 * should be initialized BEFORE clearing the XMAC's reset!
1015 * o Enable IS_LNK_SYNC_M1 and IS_LNK_SYNC_M2 after calling this
1021 void SkGeLoadLnkSyncCnt(
1022 SK_AC *pAC, /* adapter context */
1023 SK_IOC IoC, /* IO context */
1024 int Port, /* Port Index (MAC_1 + n) */
1025 SK_U32 CntVal) /* Counter value */
1033 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP);
1037 * Each time starting the Link Sync Counter an IRQ is generated
1038 * by the adapter. See problem report entry from 21.07.98
1040 * Workaround: Disable Link Sync IRQ and clear the unexpeced IRQ
1041 * if no IRQ is already pending.
1044 SK_IN32(IoC, B0_ISRC, &ISrc);
1045 SK_IN32(IoC, B0_IMSK, &OrgIMsk);
1046 if (Port == MAC_1) {
1047 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1;
1048 if ((ISrc & IS_LNK_SYNC_M1) != 0) {
1053 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M2;
1054 if ((ISrc & IS_LNK_SYNC_M2) != 0) {
1059 SK_OUT32(IoC, B0_IMSK, NewIMsk);
1063 SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal);
1066 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START);
1069 /* clear the unexpected IRQ, and restore the interrupt mask */
1070 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ);
1071 SK_OUT32(IoC, B0_IMSK, OrgIMsk);
1073 } /* SkGeLoadLnkSyncCnt*/
1076 /******************************************************************************
1078 * SkGeCfgSync() - Configure synchronous bandwidth for this port.
1081 * This function may be used to configure synchronous bandwidth
1082 * to the specified port. This may be done any time after
1083 * initializing the port. The configuration values are NOT saved
1084 * in the HWAC port structure and will be overwritten any
1085 * time when stopping and starting the port.
1086 * Any values for the synchronous configuration will be ignored
1087 * if the size of the synchronous queue is zero!
1089 * The default configuration for the synchronous service is
1090 * TXA_ENA_FSYNC. This means if the size of
1091 * the synchronous queue is unequal zero but no specific
1092 * synchronous bandwidth is configured, the synchronous queue
1093 * will always have the 'unlimited' transmit priority!
1095 * This mode will be restored if the synchronous bandwidth is
1096 * deallocated ('IntTime' = 0 and 'LimCount' = 0).
1100 * 1: parameter configuration error
1101 * 2: try to configure quality of service although no
1102 * synchronous queue is configured
1105 SK_AC *pAC, /* adapter context */
1106 SK_IOC IoC, /* IO context */
1107 int Port, /* Port Index (MAC_1 + n) */
1108 SK_U32 IntTime, /* Interval Timer Value in units of 8ns */
1109 SK_U32 LimCount, /* Number of bytes to transfer during IntTime */
1110 int SyncMode) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */
1116 /* check the parameters */
1117 if (LimCount > IntTime ||
1118 (LimCount == 0 && IntTime != 0) ||
1119 (LimCount != 0 && IntTime == 0)) {
1121 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
1125 if (pAC->GIni.GP[Port].PXSQSize == 0) {
1126 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG);
1130 /* calculate register values */
1131 IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100;
1132 LimCount = LimCount / 8;
1134 if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) {
1135 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
1140 * - Enable 'Force Sync' to ensure the synchronous queue
1141 * has the priority while configuring the new values.
1142 * - Also 'disable alloc' to ensure the settings complies
1143 * to the SyncMode parameter.
1144 * - Disable 'Rate Control' to configure the new values.
1145 * - write IntTime and LimCount
1146 * - start 'Rate Control' and disable 'Force Sync'
1147 * if Interval Timer or Limit Counter not zero.
1149 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
1150 TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1152 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime);
1153 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount);
1155 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
1156 (SK_U8)(SyncMode & (TXA_ENA_ALLOC | TXA_DIS_ALLOC)));
1158 if (IntTime != 0 || LimCount != 0) {
1159 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_START_RC);
1166 /******************************************************************************
1168 * DoInitRamQueue() - Initialize the RAM Buffer Address of a single Queue
1171 * If the queue is used, enable and initialize it.
1172 * Make sure the queue is still reset, if it is not used.
1177 static void DoInitRamQueue(
1178 SK_AC *pAC, /* adapter context */
1179 SK_IOC IoC, /* IO context */
1180 int QuIoOffs, /* Queue IO Address Offset */
1181 SK_U32 QuStartAddr, /* Queue Start Address */
1182 SK_U32 QuEndAddr, /* Queue End Address */
1183 int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */
1185 SK_U32 RxUpThresVal;
1186 SK_U32 RxLoThresVal;
1188 if (QuStartAddr != QuEndAddr) {
1189 /* calculate thresholds, assume we have a big Rx queue */
1190 RxUpThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_ULPP) / 8;
1191 RxLoThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_LLPP_B)/8;
1193 /* build HW address format */
1194 QuStartAddr = QuStartAddr / 8;
1195 QuEndAddr = QuEndAddr / 8;
1197 /* release local reset */
1198 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_CLR);
1200 /* configure addresses */
1201 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_START), QuStartAddr);
1202 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_END), QuEndAddr);
1203 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_WP), QuStartAddr);
1204 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RP), QuStartAddr);
1208 /* configure threshold for small Rx Queue */
1209 RxLoThresVal += (SK_RB_LLPP_B - SK_RB_LLPP_S) / 8;
1211 /* continue with SK_RX_BRAM_Q */
1213 /* write threshold for Rx Queue */
1215 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal);
1216 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal);
1218 /* the high priority threshold not used */
1222 * Do NOT use Store & Forward under normal operation due to
1223 * performance optimization (GENESIS only).
1224 * But if Jumbo Frames are configured (XMAC Tx FIFO is only 4 kB)
1225 * or YUKON is used ((GMAC Tx FIFO is only 1 kB)
1226 * we NEED Store & Forward of the RAM buffer.
1228 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK ||
1229 !pAC->GIni.GIGenesis) {
1230 /* enable Store & Forward Mode for the Tx Side */
1231 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD);
1236 /* set queue operational */
1237 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_OP_MD);
1240 /* ensure the queue is still disabled */
1241 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_SET);
1243 } /* DoInitRamQueue */
1246 /******************************************************************************
1248 * SkGeInitRamBufs() - Initialize the RAM Buffer Queues
1251 * Initialize all RAM Buffer Queues of the specified port
1256 static void SkGeInitRamBufs(
1257 SK_AC *pAC, /* adapter context */
1258 SK_IOC IoC, /* IO context */
1259 int Port) /* Port Index (MAC_1 + n) */
1264 pPrt = &pAC->GIni.GP[Port];
1266 if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) {
1267 RxQType = SK_RX_SRAM_Q; /* small Rx Queue */
1269 RxQType = SK_RX_BRAM_Q; /* big Rx Queue */
1272 DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart,
1273 pPrt->PRxQRamEnd, RxQType);
1275 DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart,
1276 pPrt->PXsQRamEnd, SK_TX_RAM_Q);
1278 DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart,
1279 pPrt->PXaQRamEnd, SK_TX_RAM_Q);
1281 } /* SkGeInitRamBufs */
1284 /******************************************************************************
1286 * SkGeInitRamIface() - Initialize the RAM Interface
1289 * This function initializes the Adapters RAM Interface.
1292 * This function is used in the diagnostics.
1297 void SkGeInitRamIface(
1298 SK_AC *pAC, /* adapter context */
1299 SK_IOC IoC) /* IO context */
1301 /* release local reset */
1302 SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR);
1304 /* configure timeout values */
1305 SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53);
1306 SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53);
1307 SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53);
1308 SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53);
1309 SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53);
1310 SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53);
1311 SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53);
1312 SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53);
1313 SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53);
1314 SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53);
1315 SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53);
1316 SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53);
1318 } /* SkGeInitRamIface */
1321 /******************************************************************************
1323 * SkGeInitBmu() - Initialize the BMU state machines
1326 * Initialize all BMU state machines of the specified port
1331 static void SkGeInitBmu(
1332 SK_AC *pAC, /* adapter context */
1333 SK_IOC IoC, /* IO context */
1334 int Port) /* Port Index (MAC_1 + n) */
1340 pPrt = &pAC->GIni.GP[Port];
1342 RxWm = SK_BMU_RX_WM;
1343 TxWm = SK_BMU_TX_WM;
1345 if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
1346 /* for better performance */
1351 /* Rx Queue: Release all local resets and set the watermark */
1352 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
1353 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm);
1356 * Tx Queue: Release all local resets if the queue is used !
1359 if (pPrt->PXSQSize != 0) {
1360 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
1361 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
1364 if (pPrt->PXAQSize != 0) {
1365 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
1366 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
1369 * Do NOT enable the descriptor poll timers here, because
1370 * the descriptor addresses are not specified yet.
1375 /******************************************************************************
1377 * TestStopBit() - Test the stop bit of the queue
1380 * Stopping a queue is not as simple as it seems to be.
1381 * If descriptor polling is enabled, it may happen
1382 * that RX/TX stop is done and SV idle is NOT set.
1383 * In this case we have to issue another stop command.
1386 * The queues control status register
1388 static SK_U32 TestStopBit(
1389 SK_AC *pAC, /* Adapter Context */
1390 SK_IOC IoC, /* IO Context */
1391 int QuIoOffs) /* Queue IO Address Offset */
1393 SK_U32 QuCsr; /* CSR contents */
1395 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
1397 if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
1398 /* Stop Descriptor overridden by start command */
1399 SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
1401 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
1408 /******************************************************************************
1410 * SkGeStopPort() - Stop the Rx/Tx activity of the port 'Port'.
1413 * After calling this function the descriptor rings and Rx and Tx
1414 * queues of this port may be reconfigured.
1416 * It is possible to stop the receive and transmit path separate or
1419 * Dir = SK_STOP_TX Stops the transmit path only and resets the MAC.
1420 * The receive queue is still active and
1421 * the pending Rx frames may be still transferred
1423 * SK_STOP_RX Stop the receive path. The tansmit path
1424 * has to be stopped once before.
1425 * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX
1427 * RstMode = SK_SOFT_RST Resets the MAC. The PHY is still alive.
1428 * SK_HARD_RST Resets the MAC and the PHY.
1431 * 1) A Link Down event was signaled for a port. Therefore the activity
1432 * of this port should be stopped and a hardware reset should be issued
1433 * to enable the workaround of XMAC errata #2. But the received frames
1434 * should not be discarded.
1436 * SkGeStopPort(pAC, IoC, Port, SK_STOP_TX, SK_HARD_RST);
1437 * (transfer all pending Rx frames)
1438 * SkGeStopPort(pAC, IoC, Port, SK_STOP_RX, SK_HARD_RST);
1441 * 2) An event was issued which request the driver to switch
1442 * the 'virtual active' link to an other already active port
1443 * as soon as possible. The frames in the receive queue of this
1444 * port may be lost. But the PHY must not be reset during this
1447 * SkGeStopPort(pAC, IoC, Port, SK_STOP_ALL, SK_SOFT_RST);
1450 * Extended Description:
1451 * If SK_STOP_TX is set,
1452 * o disable the MAC's receive and transmitter to prevent
1453 * from sending incomplete frames
1454 * o stop the port's transmit queues before terminating the
1455 * BMUs to prevent from performing incomplete PCI cycles
1457 * - The network Rx and Tx activity and PCI Tx transfer is
1459 * o reset the MAC depending on the RstMode
1460 * o Stop Interval Timer and Limit Counter of Tx Arbiter,
1461 * also disable Force Sync bit and Enable Alloc bit.
1462 * o perform a local reset of the port's Tx path
1463 * - reset the PCI FIFO of the async Tx queue
1464 * - reset the PCI FIFO of the sync Tx queue
1465 * - reset the RAM Buffer async Tx queue
1466 * - reset the RAM Buffer sync Tx queue
1467 * - reset the MAC Tx FIFO
1468 * o switch Link and Tx LED off, stop the LED counters
1470 * If SK_STOP_RX is set,
1471 * o stop the port's receive queue
1472 * - The path data transfer activity is fully stopped now.
1473 * o perform a local reset of the port's Rx path
1474 * - reset the PCI FIFO of the Rx queue
1475 * - reset the RAM Buffer receive queue
1476 * - reset the MAC Rx FIFO
1477 * o switch Rx LED off, stop the LED counter
1479 * If all ports are stopped,
1480 * o reset the RAM Interface.
1483 * o This function may be called during the driver states RESET_PORT and
1487 SK_AC *pAC, /* adapter context */
1488 SK_IOC IoC, /* I/O context */
1489 int Port, /* port to stop (MAC_1 + n) */
1490 int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
1491 int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
1495 #endif /* !SK_DIAG */
1504 pPrt = &pAC->GIni.GP[Port];
1506 if ((Dir & SK_STOP_TX) != 0) {
1507 /* disable receiver and transmitter */
1508 SkMacRxTxDisable(pAC, IoC, Port);
1510 /* stop both transmit queues */
1512 * If the BMU is in the reset state CSR_STOP will terminate
1515 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP);
1516 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP);
1518 ToutStart = SkOsGetTime(pAC);
1522 * Clear packet arbiter timeout to make sure
1523 * this loop will terminate.
1525 SK_OUT16(IoC, B3_PA_CTRL, (Port == MAC_1) ? PA_CLR_TO_TX1 :
1529 * If the transfer stucks at the MAC the STOP command will not
1530 * terminate if we don't flush the XMAC's transmit FIFO !
1532 SkMacFlushTxFifo(pAC, IoC, Port);
1534 XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
1535 XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
1537 if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) {
1539 * Timeout of 1/18 second reached.
1540 * This needs to be checked at 1/18 sec only.
1544 /* Might be a problem when the driver event handler
1545 * calls StopPort again. XXX.
1548 /* Fatal Error, Loop aborted */
1549 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E018,
1553 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
1554 #endif /* !SK_DIAG */
1558 * Cache incoherency workaround: Assume a start command
1559 * has been lost while sending the frame.
1561 ToutStart = SkOsGetTime(pAC);
1563 if ((XsCsr & CSR_STOP) != 0) {
1564 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START);
1566 if ((XaCsr & CSR_STOP) != 0) {
1567 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START);
1572 * Because of the ASIC problem report entry from 21.08.1998 it is
1573 * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
1575 } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE ||
1576 (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
1578 /* Reset the MAC depending on the RstMode */
1579 if (RstMode == SK_SOFT_RST) {
1580 SkMacSoftRst(pAC, IoC, Port);
1583 SkMacHardRst(pAC, IoC, Port);
1586 /* Disable Force Sync bit and Enable Alloc bit */
1587 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
1588 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1590 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1591 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L);
1592 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L);
1594 /* Perform a local reset of the port's Tx path */
1596 /* Reset the PCI FIFO of the async Tx queue */
1597 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
1598 /* Reset the PCI FIFO of the sync Tx queue */
1599 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
1600 /* Reset the RAM Buffer async Tx queue */
1601 SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET);
1602 /* Reset the RAM Buffer sync Tx queue */
1603 SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET);
1605 /* Reset Tx MAC FIFO */
1606 if (pAC->GIni.GIGenesis) {
1607 /* Note: MFF_RST_SET does NOT reset the XMAC ! */
1608 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_SET);
1610 /* switch Link and Tx LED off, stop the LED counters */
1611 /* Link LED is switched off by the RLMT and the Diag itself */
1612 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS);
1615 /* Reset TX MAC FIFO */
1616 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
1620 if ((Dir & SK_STOP_RX) != 0) {
1622 * The RX Stop Command will not terminate if no buffers
1623 * are queued in the RxD ring. But it will always reach
1624 * the Idle state. Therefore we can use this feature to
1625 * stop the transfer of received packets.
1627 /* stop the port's receive queue */
1628 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP);
1633 * Clear packet arbiter timeout to make sure
1634 * this loop will terminate
1636 SK_OUT16(IoC, B3_PA_CTRL, (Port == MAC_1) ? PA_CLR_TO_RX1 :
1639 DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff);
1641 /* timeout if i==0 (bug fix for #10748) */
1643 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
1648 * because of the ASIC problem report entry from 21.08.98
1649 * it is required to wait until CSR_STOP is reset and
1650 * CSR_SV_IDLE is set.
1652 } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
1654 /* The path data transfer activity is fully stopped now */
1656 /* Perform a local reset of the port's Rx path */
1658 /* Reset the PCI FIFO of the Rx queue */
1659 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
1660 /* Reset the RAM Buffer receive queue */
1661 SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET);
1663 /* Reset Rx MAC FIFO */
1664 if (pAC->GIni.GIGenesis) {
1666 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET);
1668 /* switch Rx LED off, stop the LED counter */
1669 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS);
1672 /* Reset Rx MAC FIFO */
1673 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
1676 } /* SkGeStopPort */
1679 /******************************************************************************
1681 * SkGeInit0() - Level 0 Initialization
1684 * - Initialize the BMU address offsets
1689 static void SkGeInit0(
1690 SK_AC *pAC, /* adapter context */
1691 SK_IOC IoC) /* IO context */
1696 for (i = 0; i < SK_MAX_MACS; i++) {
1697 pPrt = &pAC->GIni.GP[i];
1699 pPrt->PState = SK_PRT_RESET;
1700 pPrt->PRxQOff = QOffTab[i].RxQOff;
1701 pPrt->PXsQOff = QOffTab[i].XsQOff;
1702 pPrt->PXaQOff = QOffTab[i].XaQOff;
1703 pPrt->PCheckPar = SK_FALSE;
1705 pPrt->PPrevShorts = 0;
1706 pPrt->PLinkResCt = 0;
1707 pPrt->PAutoNegTOCt = 0;
1710 pPrt->PRxLim = SK_DEF_RX_WA_LIM;
1711 pPrt->PLinkMode = SK_LMODE_AUTOFULL;
1712 pPrt->PLinkSpeedCap = SK_LSPEED_CAP_1000MBPS;
1713 pPrt->PLinkSpeed = SK_LSPEED_1000MBPS;
1714 pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_UNKNOWN;
1715 pPrt->PLinkModeConf = SK_LMODE_AUTOSENSE;
1716 pPrt->PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM;
1717 pPrt->PLinkBroken = SK_TRUE; /* See WA code */
1718 pPrt->PLinkCap = (SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL |
1719 SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL);
1720 pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN;
1721 pPrt->PFlowCtrlCap = SK_FLOW_MODE_SYM_OR_REM;
1722 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
1724 pPrt->PMSMode = SK_MS_MODE_AUTO;
1725 pPrt->PMSStatus = SK_MS_STAT_UNSET;
1726 pPrt->PAutoNegFail = SK_FALSE;
1727 pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
1728 pPrt->PHWLinkUp = SK_FALSE;
1731 pAC->GIni.GIPortUsage = SK_RED_LINK;
1737 /******************************************************************************
1739 * SkGePciReset() - Reset PCI interface
1742 * o Read PCI configuration.
1743 * o Change power state to 3.
1744 * o Change power state to 0.
1745 * o Restore PCI configuration.
1749 * 1: Power state could not be changed to 3.
1751 static int SkGePciReset(
1752 SK_AC *pAC, /* adapter context */
1753 SK_IOC IoC) /* IO context */
1762 SK_U8 ConfigSpace[PCI_CFG_SIZE];
1765 * Note: Switching to D3 state is like a software reset.
1766 * Switching from D3 to D0 is a hardware reset.
1767 * We have to save and restore the configuration space.
1769 for (i = 0; i < PCI_CFG_SIZE; i++) {
1770 SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]);
1773 /* We know the RAM Interface Arbiter is enabled. */
1774 SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3);
1775 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
1777 if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) {
1781 /* Return to D0 state. */
1782 SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0);
1784 /* Check for D0 state. */
1785 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
1787 if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) {
1791 /* Check PCI Config Registers. */
1792 SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd);
1793 SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls);
1794 SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);
1795 SkPciReadCfgDWord(pAC, PCI_BASE_2ND, &Bp2);
1796 SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat);
1798 if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 ||
1803 /* Restore PCI Config Space. */
1804 for (i = 0; i < PCI_CFG_SIZE; i++) {
1805 SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]);
1809 } /* SkGePciReset */
1811 #endif /* SK_PCI_RESET */
1813 /******************************************************************************
1815 * SkGeInit1() - Level 1 Initialization
1818 * o Do a software reset.
1819 * o Clear all reset bits.
1820 * o Verify that the detected hardware is present.
1821 * Return an error if not.
1822 * o Get the hardware configuration
1823 * + Read the number of MACs/Ports.
1824 * + Read the RAM size.
1825 * + Read the PCI Revision Id.
1826 * + Find out the adapters host clock speed
1827 * + Read and check the PHY type
1831 * 5: Unexpected PHY type detected
1832 * 6: HW self test failed
1834 static int SkGeInit1(
1835 SK_AC *pAC, /* adapter context */
1836 SK_IOC IoC) /* IO context */
1847 /* save CLK_RUN bits (YUKON-Lite) */
1848 SK_IN16(IoC, B0_CTST, &CtrlStat);
1851 (void)SkGePciReset(pAC, IoC);
1852 #endif /* SK_PCI_RESET */
1854 /* do the SW-reset */
1855 SK_OUT8(IoC, B0_CTST, CS_RST_SET);
1857 /* release the SW-reset */
1858 SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
1860 /* reset all error bits in the PCI STATUS register */
1862 * Note: PCI Cfg cycles cannot be used, because they are not
1863 * available on some platforms after 'boot time'.
1865 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
1867 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1868 SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
1869 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1871 /* release Master Reset */
1872 SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);
1875 CtrlStat |= CS_CLK_RUN_ENA;
1876 #endif /* CLK_RUN */
1878 /* restore CLK_RUN bits */
1879 SK_OUT16(IoC, B0_CTST, CtrlStat &
1880 (CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA));
1882 /* read Chip Identification Number */
1883 SK_IN8(IoC, B2_CHIP_ID, &Byte);
1884 pAC->GIni.GIChipId = Byte;
1886 /* read number of MACs */
1887 SK_IN8(IoC, B2_MAC_CFG, &Byte);
1888 pAC->GIni.GIMacsFound = (Byte & CONFIG_SYS_SNG_MAC) ? 1 : 2;
1890 /* get Chip Revision Number */
1891 pAC->GIni.GIChipRev = (SK_U8)((Byte & CONFIG_SYS_CHIP_R_MSK) >> 4);
1893 /* get diff. PCI parameters */
1894 SK_IN16(IoC, B0_CTST, &CtrlStat);
1896 /* read the adapters RAM size */
1897 SK_IN8(IoC, B2_E_0, &Byte);
1899 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
1901 pAC->GIni.GIGenesis = SK_TRUE;
1904 /* special case: 4 x 64k x 36, offset = 0x80000 */
1905 pAC->GIni.GIRamSize = 1024;
1906 pAC->GIni.GIRamOffs = (SK_U32)512 * 1024;
1909 pAC->GIni.GIRamSize = (int)Byte * 512;
1910 pAC->GIni.GIRamOffs = 0;
1912 /* all GE adapters work with 53.125 MHz host clock */
1913 pAC->GIni.GIHstClkFact = SK_FACT_53;
1915 /* set Descr. Poll Timer Init Value to 250 ms */
1916 pAC->GIni.GIPollTimerVal =
1917 SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100;
1920 pAC->GIni.GIGenesis = SK_FALSE;
1923 pAC->GIni.GIRamSize = (Byte == 0) ? 128 : (int)Byte * 4;
1925 pAC->GIni.GIRamSize = 128;
1927 pAC->GIni.GIRamOffs = 0;
1929 /* WA for chip Rev. A */
1930 pAC->GIni.GIWolOffs = (pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0;
1932 /* get PM Capabilities of PCI config space */
1933 SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word);
1935 /* check if VAUX is available */
1936 if (((CtrlStat & CS_VAUX_AVAIL) != 0) &&
1937 /* check also if PME from D3cold is set */
1938 ((Word & PCI_PME_D3C_SUP) != 0)) {
1939 /* set entry in GE init struct */
1940 pAC->GIni.GIVauxAvail = SK_TRUE;
1943 /* save Flash-Address Register */
1944 SK_IN32(IoC, B2_FAR, &FlashAddr);
1946 /* test Flash-Address Register */
1947 SK_OUT8(IoC, B2_FAR + 3, 0xff);
1948 SK_IN8(IoC, B2_FAR + 3, &Byte);
1950 pAC->GIni.GIYukonLite = (SK_BOOL)(Byte != 0);
1952 /* restore Flash-Address Register */
1953 SK_OUT32(IoC, B2_FAR, FlashAddr);
1955 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
1956 /* set GMAC Link Control reset */
1957 SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET);
1959 /* clear GMAC Link Control reset */
1960 SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
1962 /* all YU chips work with 78.125 MHz host clock */
1963 pAC->GIni.GIHstClkFact = SK_FACT_78;
1965 pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */
1968 /* check if 64-bit PCI Slot is present */
1969 pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
1971 /* check if 66 MHz PCI Clock is active */
1972 pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
1974 /* read PCI HW Revision Id. */
1975 SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte);
1976 pAC->GIni.GIPciHwRev = Byte;
1978 /* read the PMD type */
1979 SK_IN8(IoC, B2_PMD_TYP, &Byte);
1980 pAC->GIni.GICopperType = (SK_U8)(Byte == 'T');
1982 /* read the PHY type */
1983 SK_IN8(IoC, B2_E_1, &Byte);
1985 Byte &= 0x0f; /* the PHY type is stored in the lower nibble */
1986 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
1988 if (pAC->GIni.GIGenesis) {
1991 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC;
1994 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM;
1995 pAC->GIni.GP[i].PMSCap =
1996 SK_MS_CAP_AUTO | SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE;
2000 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE;
2003 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT;
2005 #endif /* OTHER_PHY */
2007 /* ERROR: unexpected PHY type detected */
2014 /* if this field is not initialized */
2015 Byte = SK_PHY_MARV_COPPER;
2016 pAC->GIni.GICopperType = SK_TRUE;
2018 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV;
2020 if (pAC->GIni.GICopperType) {
2021 pAC->GIni.GP[i].PLinkSpeedCap = SK_LSPEED_CAP_AUTO |
2022 SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS |
2023 SK_LSPEED_CAP_1000MBPS;
2024 pAC->GIni.GP[i].PLinkSpeed = SK_LSPEED_AUTO;
2025 pAC->GIni.GP[i].PMSCap =
2026 SK_MS_CAP_AUTO | SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE;
2029 Byte = SK_PHY_MARV_FIBER;
2033 pAC->GIni.GP[i].PhyType = Byte;
2035 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
2036 ("PHY type: %d PHY addr: %04x\n", Byte,
2037 pAC->GIni.GP[i].PhyAddr));
2040 /* get Mac Type & set function pointers dependent on */
2041 if (pAC->GIni.GIGenesis) {
2042 pAC->GIni.GIMacType = SK_MAC_XMAC;
2044 pAC->GIni.GIFunc.pFnMacUpdateStats = SkXmUpdateStats;
2045 pAC->GIni.GIFunc.pFnMacStatistic = SkXmMacStatistic;
2046 pAC->GIni.GIFunc.pFnMacResetCounter = SkXmResetCounter;
2047 pAC->GIni.GIFunc.pFnMacOverflow = SkXmOverflowStatus;
2050 pAC->GIni.GIMacType = SK_MAC_GMAC;
2052 pAC->GIni.GIFunc.pFnMacUpdateStats = SkGmUpdateStats;
2053 pAC->GIni.GIFunc.pFnMacStatistic = SkGmMacStatistic;
2054 pAC->GIni.GIFunc.pFnMacResetCounter = SkGmResetCounter;
2055 pAC->GIni.GIFunc.pFnMacOverflow = SkGmOverflowStatus;
2057 #ifdef SPECIAL_HANDLING
2058 if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
2059 /* check HW self test result */
2060 SK_IN8(IoC, B2_E_3, &Byte);
2061 if ((Byte & B2_E3_RES_MASK) != 0) {
2071 /******************************************************************************
2073 * SkGeInit2() - Level 2 Initialization
2076 * - start the Blink Source Counter
2077 * - start the Descriptor Poll Timer
2078 * - configure the MAC-Arbiter
2079 * - configure the Packet-Arbiter
2080 * - enable the Tx Arbiters
2081 * - enable the RAM Interface Arbiter
2086 static void SkGeInit2(
2087 SK_AC *pAC, /* adapter context */
2088 SK_IOC IoC) /* IO context */
2093 /* start the Descriptor Poll Timer */
2094 if (pAC->GIni.GIPollTimerVal != 0) {
2095 if (pAC->GIni.GIPollTimerVal > SK_DPOLL_MAX) {
2096 pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX;
2098 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG);
2100 SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal);
2101 SK_OUT8(IoC, B28_DPT_CTRL, DPT_START);
2104 if (pAC->GIni.GIGenesis) {
2105 /* start the Blink Source Counter */
2106 DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
2108 SK_OUT32(IoC, B2_BSC_INI, DWord);
2109 SK_OUT8(IoC, B2_BSC_CTRL, BSC_START);
2112 * Configure the MAC Arbiter and the Packet Arbiter.
2113 * They will be started once and never be stopped.
2115 SkGeInitMacArb(pAC, IoC);
2117 SkGeInitPktArb(pAC, IoC);
2120 /* start Time Stamp Timer */
2121 SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_START);
2124 /* enable the Tx Arbiters */
2125 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
2126 SK_OUT8(IoC, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB);
2129 /* enable the RAM Interface Arbiter */
2130 SkGeInitRamIface(pAC, IoC);
2134 /******************************************************************************
2136 * SkGeInit() - Initialize the GE Adapter with the specified level.
2139 * Level 0: Initialize the Module structures.
2140 * Level 1: Generic Hardware Initialization. The IOP/MemBase pointer has
2141 * to be set before calling this level.
2143 * o Do a software reset.
2144 * o Clear all reset bits.
2145 * o Verify that the detected hardware is present.
2146 * Return an error if not.
2147 * o Get the hardware configuration
2148 * + Set GIMacsFound with the number of MACs.
2149 * + Store the RAM size in GIRamSize.
2150 * + Save the PCI Revision ID in GIPciHwRev.
2152 * if Number of MACs > SK_MAX_MACS
2154 * After returning from Level 0 the adapter
2155 * may be accessed with IO operations.
2157 * Level 2: start the Blink Source Counter
2161 * 1: Number of MACs exceeds SK_MAX_MACS (after level 1)
2162 * 2: Adapter not present or not accessible
2163 * 3: Illegal initialization level
2164 * 4: Initialization Level 1 Call missing
2165 * 5: Unexpected PHY type detected
2166 * 6: HW self test failed
2169 SK_AC *pAC, /* adapter context */
2170 SK_IOC IoC, /* IO context */
2171 int Level) /* initialization level */
2173 int RetVal; /* return value */
2177 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
2178 ("SkGeInit(Level %d)\n", Level));
2182 /* Initialization Level 0 */
2183 SkGeInit0(pAC, IoC);
2184 pAC->GIni.GILevel = SK_INIT_DATA;
2188 /* Initialization Level 1 */
2189 RetVal = SkGeInit1(pAC, IoC);
2194 /* check if the adapter seems to be accessible */
2195 SK_OUT32(IoC, B2_IRQM_INI, 0x11335577L);
2196 SK_IN32(IoC, B2_IRQM_INI, &DWord);
2197 SK_OUT32(IoC, B2_IRQM_INI, 0L);
2199 if (DWord != 0x11335577L) {
2204 /* check if the number of GIMacsFound matches SK_MAX_MACS */
2205 if (pAC->GIni.GIMacsFound > SK_MAX_MACS) {
2210 /* Level 1 successfully passed */
2211 pAC->GIni.GILevel = SK_INIT_IO;
2215 /* Initialization Level 2 */
2216 if (pAC->GIni.GILevel != SK_INIT_IO) {
2218 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E002, SKERR_HWI_E002MSG);
2219 #endif /* !SK_DIAG */
2223 SkGeInit2(pAC, IoC);
2225 /* Level 2 successfully passed */
2226 pAC->GIni.GILevel = SK_INIT_RUN;
2230 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG);
2239 /******************************************************************************
2241 * SkGeDeInit() - Deinitialize the adapter
2244 * All ports of the adapter will be stopped if not already done.
2245 * Do a software reset and switch off all LEDs.
2251 SK_AC *pAC, /* adapter context */
2252 SK_IOC IoC) /* IO context */
2258 /* ensure I2C is ready */
2259 SkI2cWaitIrq(pAC, IoC);
2262 /* stop all current transfer activity */
2263 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
2264 if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
2265 pAC->GIni.GP[i].PState != SK_PRT_RESET) {
2267 SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
2271 /* Reset all bits in the PCI STATUS register */
2273 * Note: PCI Cfg cycles cannot be used, because they are not
2274 * available on some platforms after 'boot time'.
2276 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
2278 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2279 SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
2280 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2282 /* do the reset, all LEDs are switched off now */
2283 SK_OUT8(IoC, B0_CTST, CS_RST_SET);
2287 /******************************************************************************
2289 * SkGeInitPort() Initialize the specified port.
2292 * PRxQSize, PXSQSize, and PXAQSize has to be
2293 * configured for the specified port before calling this function.
2294 * The descriptor rings has to be initialized too.
2296 * o (Re)configure queues of the specified port.
2297 * o configure the MAC of the specified port.
2298 * o put ASIC and MAC(s) in operational mode.
2299 * o initialize Rx/Tx and Sync LED
2300 * o initialize RAM Buffers and MAC FIFOs
2302 * The port is ready to connect when returning.
2305 * The MAC's Rx and Tx state machine is still disabled when returning.
2309 * 1: Queue size initialization error. The configured values
2310 * for PRxQSize, PXSQSize, or PXAQSize are invalid for one
2311 * or more queues. The specified port was NOT initialized.
2312 * An error log entry was generated.
2313 * 2: The port has to be stopped before it can be initialized again.
2316 SK_AC *pAC, /* adapter context */
2317 SK_IOC IoC, /* IO context */
2318 int Port) /* Port to configure */
2322 pPrt = &pAC->GIni.GP[Port];
2324 if (SkGeCheckQSize(pAC, Port) != 0) {
2325 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG);
2329 if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) {
2330 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG);
2334 /* configuration ok, initialize the Port now */
2336 if (pAC->GIni.GIGenesis) {
2337 /* initialize Rx, Tx and Link LED */
2339 * If 1000BT Phy needs LED initialization than swap
2340 * LED and XMAC initialization order
2342 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
2343 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA);
2344 /* The Link LED is initialized by RLMT or Diagnostics itself */
2346 SkXmInitMac(pAC, IoC, Port);
2350 SkGmInitMac(pAC, IoC, Port);
2353 /* do NOT initialize the Link Sync Counter */
2355 SkGeInitMacFifo(pAC, IoC, Port);
2357 SkGeInitRamBufs(pAC, IoC, Port);
2359 if (pPrt->PXSQSize != 0) {
2360 /* enable Force Sync bit if synchronous queue available */
2361 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC);
2364 SkGeInitBmu(pAC, IoC, Port);
2366 /* mark port as initialized */
2367 pPrt->PState = SK_PRT_INIT;
2370 } /* SkGeInitPort */