drivers/net/tsec.c

   1 /*
   2  * Freescale Three Speed Ethernet Controller driver
   3  *
   4  * This software may be used and distributed according to the
   5  * terms of the GNU Public License, Version 2, incorporated
   6  * herein by reference.
   7  *
   8  * Copyright 2004-2009 Freescale Semiconductor, Inc.
   9  * (C) Copyright 2003, Motorola, Inc.
  10  * author Andy Fleming
  11  *
  12  */
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <command.h>
  19 #include <tsec.h>
  20 #include <asm/errno.h>
  21
  22 #include "miiphy.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define TX_BUF_CNT              2
  27
  28 static uint rxIdx;              /* index of the current RX buffer */
  29 static uint txIdx;              /* index of the current TX buffer */
  30
  31 typedef volatile struct rtxbd {
  32         txbd8_t txbd[TX_BUF_CNT];
  33         rxbd8_t rxbd[PKTBUFSRX];
  34 } RTXBD;
  35
  36 #define MAXCONTROLLERS  (8)
  37
  38 static struct tsec_private *privlist[MAXCONTROLLERS];
  39 static int num_tsecs = 0;
  40
  41 #ifdef __GNUC__
  42 static RTXBD rtx __attribute__ ((aligned(8)));
  43 #else
  44 #error "rtx must be 64-bit aligned"
  45 #endif
  46
  47 static int tsec_send(struct eth_device *dev,
  48                      volatile void *packet, int length);
  49 static int tsec_recv(struct eth_device *dev);
  50 static int tsec_init(struct eth_device *dev, bd_t * bd);
  51 static void tsec_halt(struct eth_device *dev);
  52 static void init_registers(volatile tsec_t * regs);
  53 static void startup_tsec(struct eth_device *dev);
  54 static int init_phy(struct eth_device *dev);
  55 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
  56 uint read_phy_reg(struct tsec_private *priv, uint regnum);
  57 struct phy_info *get_phy_info(struct eth_device *dev);
  58 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
  59 static void adjust_link(struct eth_device *dev);
  60 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
  61         && !defined(BITBANGMII)
  62 static int tsec_miiphy_write(char *devname, unsigned char addr,
  63                              unsigned char reg, unsigned short value);
  64 static int tsec_miiphy_read(char *devname, unsigned char addr,
  65                             unsigned char reg, unsigned short *value);
  66 #endif
  67 #ifdef CONFIG_MCAST_TFTP
  68 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
  69 #endif
  70
  71 /* Default initializations for TSEC controllers. */
  72
  73 static struct tsec_info_struct tsec_info[] = {
  74 #ifdef CONFIG_TSEC1
  75         STD_TSEC_INFO(1),       /* TSEC1 */
  76 #endif
  77 #ifdef CONFIG_TSEC2
  78         STD_TSEC_INFO(2),       /* TSEC2 */
  79 #endif
  80 #ifdef CONFIG_MPC85XX_FEC
  81         {
  82                 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
  83                 .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR),
  84                 .devname = CONFIG_MPC85XX_FEC_NAME,
  85                 .phyaddr = FEC_PHY_ADDR,
  86                 .flags = FEC_FLAGS
  87         },                      /* FEC */
  88 #endif
  89 #ifdef CONFIG_TSEC3
  90         STD_TSEC_INFO(3),       /* TSEC3 */
  91 #endif
  92 #ifdef CONFIG_TSEC4
  93         STD_TSEC_INFO(4),       /* TSEC4 */
  94 #endif
  95 };
  96
  97 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
  98 {
  99         int i;
 100
 101         for (i = 0; i < num; i++)
 102                 tsec_initialize(bis, &tsecs[i]);
 103
 104         return 0;
 105 }
 106
 107 int tsec_standard_init(bd_t *bis)
 108 {
 109         return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
 110 }
 111
 112 /* Initialize device structure. Returns success if PHY
 113  * initialization succeeded (i.e. if it recognizes the PHY)
 114  */
 115 int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info)
 116 {
 117         struct eth_device *dev;
 118         int i;
 119         struct tsec_private *priv;
 120
 121         dev = (struct eth_device *)malloc(sizeof *dev);
 122
 123         if (NULL == dev)
 124                 return 0;
 125
 126         memset(dev, 0, sizeof *dev);
 127
 128         priv = (struct tsec_private *)malloc(sizeof(*priv));
 129
 130         if (NULL == priv)
 131                 return 0;
 132
 133         privlist[num_tsecs++] = priv;
 134         priv->regs = tsec_info->regs;
 135         priv->phyregs = tsec_info->miiregs;
 136         priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
 137
 138         priv->phyaddr = tsec_info->phyaddr;
 139         priv->flags = tsec_info->flags;
 140
 141         sprintf(dev->name, tsec_info->devname);
 142         dev->iobase = 0;
 143         dev->priv = priv;
 144         dev->init = tsec_init;
 145         dev->halt = tsec_halt;
 146         dev->send = tsec_send;
 147         dev->recv = tsec_recv;
 148 #ifdef CONFIG_MCAST_TFTP
 149         dev->mcast = tsec_mcast_addr;
 150 #endif
 151
 152         /* Tell u-boot to get the addr from the env */
 153         for (i = 0; i < 6; i++)
 154                 dev->enetaddr[i] = 0;
 155
 156         eth_register(dev);
 157
 158         /* Reset the MAC */
 159         priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
 160         udelay(2);  /* Soft Reset must be asserted for 3 TX clocks */
 161         priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
 162
 163 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
 164         && !defined(BITBANGMII)
 165         miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
 166 #endif
 167
 168         /* Try to initialize PHY here, and return */
 169         return init_phy(dev);
 170 }
 171
 172 /* Initializes data structures and registers for the controller,
 173  * and brings the interface up.  Returns the link status, meaning
 174  * that it returns success if the link is up, failure otherwise.
 175  * This allows u-boot to find the first active controller.
 176  */
 177 int tsec_init(struct eth_device *dev, bd_t * bd)
 178 {
 179         uint tempval;
 180         char tmpbuf[MAC_ADDR_LEN];
 181         int i;
 182         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 183         volatile tsec_t *regs = priv->regs;
 184
 185         /* Make sure the controller is stopped */
 186         tsec_halt(dev);
 187
 188         /* Init MACCFG2.  Defaults to GMII */
 189         regs->maccfg2 = MACCFG2_INIT_SETTINGS;
 190
 191         /* Init ECNTRL */
 192         regs->ecntrl = ECNTRL_INIT_SETTINGS;
 193
 194         /* Copy the station address into the address registers.
 195          * Backwards, because little endian MACS are dumb */
 196         for (i = 0; i < MAC_ADDR_LEN; i++) {
 197                 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
 198         }
 199         tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
 200                   tmpbuf[3];
 201
 202         regs->macstnaddr1 = tempval;
 203
 204         tempval = *((uint *) (tmpbuf + 4));
 205
 206         regs->macstnaddr2 = tempval;
 207
 208         /* reset the indices to zero */
 209         rxIdx = 0;
 210         txIdx = 0;
 211
 212         /* Clear out (for the most part) the other registers */
 213         init_registers(regs);
 214
 215         /* Ready the device for tx/rx */
 216         startup_tsec(dev);
 217
 218         /* If there's no link, fail */
 219         return (priv->link ? 0 : -1);
 220 }
 221
 222 /* Writes the given phy's reg with value, using the specified MDIO regs */
 223 static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr,
 224                 uint reg, uint value)
 225 {
 226         int timeout = 1000000;
 227
 228         phyregs->miimadd = (addr << 8) | reg;
 229         phyregs->miimcon = value;
 230         asm("sync");
 231
 232         timeout = 1000000;
 233         while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
 234 }
 235
 236
 237 /* Provide the default behavior of writing the PHY of this ethernet device */
 238 #define write_phy_reg(priv, regnum, value) tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
 239
 240 /* Reads register regnum on the device's PHY through the
 241  * specified registers.  It lowers and raises the read
 242  * command, and waits for the data to become valid (miimind
 243  * notvalid bit cleared), and the bus to cease activity (miimind
 244  * busy bit cleared), and then returns the value
 245  */
 246 uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, uint phyid, uint regnum)
 247 {
 248         uint value;
 249
 250         /* Put the address of the phy, and the register
 251          * number into MIIMADD */
 252         phyregs->miimadd = (phyid << 8) | regnum;
 253
 254         /* Clear the command register, and wait */
 255         phyregs->miimcom = 0;
 256         asm("sync");
 257
 258         /* Initiate a read command, and wait */
 259         phyregs->miimcom = MIIM_READ_COMMAND;
 260         asm("sync");
 261
 262         /* Wait for the the indication that the read is done */
 263         while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
 264
 265         /* Grab the value read from the PHY */
 266         value = phyregs->miimstat;
 267
 268         return value;
 269 }
 270
 271 /* #define to provide old read_phy_reg functionality without duplicating code */
 272 #define read_phy_reg(priv,regnum) tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
 273
 274 #define TBIANA_SETTINGS ( \
 275                 TBIANA_ASYMMETRIC_PAUSE \
 276                 | TBIANA_SYMMETRIC_PAUSE \
 277                 | TBIANA_FULL_DUPLEX \
 278                 )
 279
 280 #define TBICR_SETTINGS ( \
 281                 TBICR_PHY_RESET \
 282                 | TBICR_ANEG_ENABLE \
 283                 | TBICR_FULL_DUPLEX \
 284                 | TBICR_SPEED1_SET \
 285                 )
 286 /* Configure the TBI for SGMII operation */
 287 static void tsec_configure_serdes(struct tsec_private *priv)
 288 {
 289         /* Access TBI PHY registers at given TSEC register offset as opposed to the
 290          * register offset used for external PHY accesses */
 291         tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA,
 292                         TBIANA_SETTINGS);
 293         tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON,
 294                         TBICON_CLK_SELECT);
 295         tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
 296                         TBICR_SETTINGS);
 297 }
 298
 299 /* Discover which PHY is attached to the device, and configure it
 300  * properly.  If the PHY is not recognized, then return 0
 301  * (failure).  Otherwise, return 1
 302  */
 303 static int init_phy(struct eth_device *dev)
 304 {
 305         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 306         struct phy_info *curphy;
 307         volatile tsec_t *regs = priv->regs;
 308
 309         /* Assign a Physical address to the TBI */
 310         regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
 311         asm("sync");
 312
 313         /* Reset MII (due to new addresses) */
 314         priv->phyregs->miimcfg = MIIMCFG_RESET;
 315         asm("sync");
 316         priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
 317         asm("sync");
 318         while (priv->phyregs->miimind & MIIMIND_BUSY) ;
 319
 320         /* Get the cmd structure corresponding to the attached
 321          * PHY */
 322         curphy = get_phy_info(dev);
 323
 324         if (curphy == NULL) {
 325                 priv->phyinfo = NULL;
 326                 printf("%s: No PHY found\n", dev->name);
 327
 328                 return 0;
 329         }
 330
 331         if (regs->ecntrl & ECNTRL_SGMII_MODE)
 332                 tsec_configure_serdes(priv);
 333
 334         priv->phyinfo = curphy;
 335
 336         phy_run_commands(priv, priv->phyinfo->config);
 337
 338         return 1;
 339 }
 340
 341 /*
 342  * Returns which value to write to the control register.
 343  * For 10/100, the value is slightly different
 344  */
 345 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
 346 {
 347         if (priv->flags & TSEC_GIGABIT)
 348                 return MIIM_CONTROL_INIT;
 349         else
 350                 return MIIM_CR_INIT;
 351 }
 352
 353 /*
 354  * Wait for auto-negotiation to complete, then determine link
 355  */
 356 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 357 {
 358         /*
 359          * Wait if the link is up, and autonegotiation is in progress
 360          * (ie - we're capable and it's not done)
 361          */
 362         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 363         if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
 364                 int i = 0;
 365
 366                 puts("Waiting for PHY auto negotiation to complete");
 367                 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
 368                         /*
 369                          * Timeout reached ?
 370                          */
 371                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 372                                 puts(" TIMEOUT !\n");
 373                                 priv->link = 0;
 374                                 return 0;
 375                         }
 376
 377                         if (ctrlc()) {
 378                                 puts("user interrupt!\n");
 379                                 priv->link = 0;
 380                                 return -EINTR;
 381                         }
 382
 383                         if ((i++ % 1000) == 0) {
 384                                 putc('.');
 385                         }
 386                         udelay(1000);   /* 1 ms */
 387                         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 388                 }
 389                 puts(" done\n");
 390
 391                 /* Link status bit is latched low, read it again */
 392                 mii_reg = read_phy_reg(priv, MIIM_STATUS);
 393
 394                 udelay(500000); /* another 500 ms (results in faster booting) */
 395         }
 396
 397         priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0;
 398
 399         return 0;
 400 }
 401
 402 /* Generic function which updates the speed and duplex.  If
 403  * autonegotiation is enabled, it uses the AND of the link
 404  * partner's advertised capabilities and our advertised
 405  * capabilities.  If autonegotiation is disabled, we use the
 406  * appropriate bits in the control register.
 407  *
 408  * Stolen from Linux's mii.c and phy_device.c
 409  */
 410 uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
 411 {
 412         /* We're using autonegotiation */
 413         if (mii_reg & PHY_BMSR_AUTN_ABLE) {
 414                 uint lpa = 0;
 415                 uint gblpa = 0;
 416
 417                 /* Check for gigabit capability */
 418                 if (mii_reg & PHY_BMSR_EXT) {
 419                         /* We want a list of states supported by
 420                          * both PHYs in the link
 421                          */
 422                         gblpa = read_phy_reg(priv, PHY_1000BTSR);
 423                         gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
 424                 }
 425
 426                 /* Set the baseline so we only have to set them
 427                  * if they're different
 428                  */
 429                 priv->speed = 10;
 430                 priv->duplexity = 0;
 431
 432                 /* Check the gigabit fields */
 433                 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
 434                         priv->speed = 1000;
 435
 436                         if (gblpa & PHY_1000BTSR_1000FD)
 437                                 priv->duplexity = 1;
 438
 439                         /* We're done! */
 440                         return 0;
 441                 }
 442
 443                 lpa = read_phy_reg(priv, PHY_ANAR);
 444                 lpa &= read_phy_reg(priv, PHY_ANLPAR);
 445
 446                 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
 447                         priv->speed = 100;
 448
 449                         if (lpa & PHY_ANLPAR_TXFD)
 450                                 priv->duplexity = 1;
 451
 452                 } else if (lpa & PHY_ANLPAR_10FD)
 453                         priv->duplexity = 1;
 454         } else {
 455                 uint bmcr = read_phy_reg(priv, PHY_BMCR);
 456
 457                 priv->speed = 10;
 458                 priv->duplexity = 0;
 459
 460                 if (bmcr & PHY_BMCR_DPLX)
 461                         priv->duplexity = 1;
 462
 463                 if (bmcr & PHY_BMCR_1000_MBPS)
 464                         priv->speed = 1000;
 465                 else if (bmcr & PHY_BMCR_100_MBPS)
 466                         priv->speed = 100;
 467         }
 468
 469         return 0;
 470 }
 471
 472 /*
 473  * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
 474  * circumstances.  eg a gigabit TSEC connected to a gigabit switch with
 475  * a 4-wire ethernet cable.  Both ends advertise gigabit, but can't
 476  * link.  "Ethernet@Wirespeed" reduces advertised speed until link
 477  * can be achieved.
 478  */
 479 uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv)
 480 {
 481         return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010;
 482 }
 483
 484 /*
 485  * Parse the BCM54xx status register for speed and duplex information.
 486  * The linux sungem_phy has this information, but in a table format.
 487  */
 488 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
 489 {
 490
 491         switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
 492
 493                 case 1:
 494                         printf("Enet starting in 10BT/HD\n");
 495                         priv->duplexity = 0;
 496                         priv->speed = 10;
 497                         break;
 498
 499                 case 2:
 500                         printf("Enet starting in 10BT/FD\n");
 501                         priv->duplexity = 1;
 502                         priv->speed = 10;
 503                         break;
 504
 505                 case 3:
 506                         printf("Enet starting in 100BT/HD\n");
 507                         priv->duplexity = 0;
 508                         priv->speed = 100;
 509                         break;
 510
 511                 case 5:
 512                         printf("Enet starting in 100BT/FD\n");
 513                         priv->duplexity = 1;
 514                         priv->speed = 100;
 515                         break;
 516
 517                 case 6:
 518                         printf("Enet starting in 1000BT/HD\n");
 519                         priv->duplexity = 0;
 520                         priv->speed = 1000;
 521                         break;
 522
 523                 case 7:
 524                         printf("Enet starting in 1000BT/FD\n");
 525                         priv->duplexity = 1;
 526                         priv->speed = 1000;
 527                         break;
 528
 529                 default:
 530                         printf("Auto-neg error, defaulting to 10BT/HD\n");
 531                         priv->duplexity = 0;
 532                         priv->speed = 10;
 533                         break;
 534         }
 535
 536         return 0;
 537
 538 }
 539 /* Parse the 88E1011's status register for speed and duplex
 540  * information
 541  */
 542 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
 543 {
 544         uint speed;
 545
 546         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 547
 548         if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
 549                 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
 550                 int i = 0;
 551
 552                 puts("Waiting for PHY realtime link");
 553                 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
 554                         /* Timeout reached ? */
 555                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 556                                 puts(" TIMEOUT !\n");
 557                                 priv->link = 0;
 558                                 break;
 559                         }
 560
 561                         if ((i++ % 1000) == 0) {
 562                                 putc('.');
 563                         }
 564                         udelay(1000);   /* 1 ms */
 565                         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 566                 }
 567                 puts(" done\n");
 568                 udelay(500000); /* another 500 ms (results in faster booting) */
 569         } else {
 570                 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
 571                         priv->link = 1;
 572                 else
 573                         priv->link = 0;
 574         }
 575
 576         if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
 577                 priv->duplexity = 1;
 578         else
 579                 priv->duplexity = 0;
 580
 581         speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
 582
 583         switch (speed) {
 584         case MIIM_88E1011_PHYSTAT_GBIT:
 585                 priv->speed = 1000;
 586                 break;
 587         case MIIM_88E1011_PHYSTAT_100:
 588                 priv->speed = 100;
 589                 break;
 590         default:
 591                 priv->speed = 10;
 592         }
 593
 594         return 0;
 595 }
 596
 597 /* Parse the RTL8211B's status register for speed and duplex
 598  * information
 599  */
 600 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv)
 601 {
 602         uint speed;
 603
 604         mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
 605         if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
 606                 int i = 0;
 607
 608                 /* in case of timeout ->link is cleared */
 609                 priv->link = 1;
 610                 puts("Waiting for PHY realtime link");
 611                 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
 612                         /* Timeout reached ? */
 613                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 614                                 puts(" TIMEOUT !\n");
 615                                 priv->link = 0;
 616                                 break;
 617                         }
 618
 619                         if ((i++ % 1000) == 0) {
 620                                 putc('.');
 621                         }
 622                         udelay(1000);   /* 1 ms */
 623                         mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
 624                 }
 625                 puts(" done\n");
 626                 udelay(500000); /* another 500 ms (results in faster booting) */
 627         } else {
 628                 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK)
 629                         priv->link = 1;
 630                 else
 631                         priv->link = 0;
 632         }
 633
 634         if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX)
 635                 priv->duplexity = 1;
 636         else
 637                 priv->duplexity = 0;
 638
 639         speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED);
 640
 641         switch (speed) {
 642         case MIIM_RTL8211B_PHYSTAT_GBIT:
 643                 priv->speed = 1000;
 644                 break;
 645         case MIIM_RTL8211B_PHYSTAT_100:
 646                 priv->speed = 100;
 647                 break;
 648         default:
 649                 priv->speed = 10;
 650         }
 651
 652         return 0;
 653 }
 654
 655 /* Parse the cis8201's status register for speed and duplex
 656  * information
 657  */
 658 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
 659 {
 660         uint speed;
 661
 662         if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
 663                 priv->duplexity = 1;
 664         else
 665                 priv->duplexity = 0;
 666
 667         speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
 668         switch (speed) {
 669         case MIIM_CIS8201_AUXCONSTAT_GBIT:
 670                 priv->speed = 1000;
 671                 break;
 672         case MIIM_CIS8201_AUXCONSTAT_100:
 673                 priv->speed = 100;
 674                 break;
 675         default:
 676                 priv->speed = 10;
 677                 break;
 678         }
 679
 680         return 0;
 681 }
 682
 683 /* Parse the vsc8244's status register for speed and duplex
 684  * information
 685  */
 686 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
 687 {
 688         uint speed;
 689
 690         if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
 691                 priv->duplexity = 1;
 692         else
 693                 priv->duplexity = 0;
 694
 695         speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
 696         switch (speed) {
 697         case MIIM_VSC8244_AUXCONSTAT_GBIT:
 698                 priv->speed = 1000;
 699                 break;
 700         case MIIM_VSC8244_AUXCONSTAT_100:
 701                 priv->speed = 100;
 702                 break;
 703         default:
 704                 priv->speed = 10;
 705                 break;
 706         }
 707
 708         return 0;
 709 }
 710
 711 /* Parse the DM9161's status register for speed and duplex
 712  * information
 713  */
 714 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
 715 {
 716         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
 717                 priv->speed = 100;
 718         else
 719                 priv->speed = 10;
 720
 721         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
 722                 priv->duplexity = 1;
 723         else
 724                 priv->duplexity = 0;
 725
 726         return 0;
 727 }
 728
 729 /*
 730  * Hack to write all 4 PHYs with the LED values
 731  */
 732 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
 733 {
 734         uint phyid;
 735         volatile tsec_mdio_t *regbase = priv->phyregs;
 736         int timeout = 1000000;
 737
 738         for (phyid = 0; phyid < 4; phyid++) {
 739                 regbase->miimadd = (phyid << 8) | mii_reg;
 740                 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
 741                 asm("sync");
 742
 743                 timeout = 1000000;
 744                 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 745         }
 746
 747         return MIIM_CIS8204_SLEDCON_INIT;
 748 }
 749
 750 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
 751 {
 752         if (priv->flags & TSEC_REDUCED)
 753                 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
 754         else
 755                 return MIIM_CIS8204_EPHYCON_INIT;
 756 }
 757
 758 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
 759 {
 760         uint mii_data = read_phy_reg(priv, mii_reg);
 761
 762         if (priv->flags & TSEC_REDUCED)
 763                 mii_data = (mii_data & 0xfff0) | 0x000b;
 764         return mii_data;
 765 }
 766
 767 /* Initialized required registers to appropriate values, zeroing
 768  * those we don't care about (unless zero is bad, in which case,
 769  * choose a more appropriate value)
 770  */
 771 static void init_registers(volatile tsec_t * regs)
 772 {
 773         /* Clear IEVENT */
 774         regs->ievent = IEVENT_INIT_CLEAR;
 775
 776         regs->imask = IMASK_INIT_CLEAR;
 777
 778         regs->hash.iaddr0 = 0;
 779         regs->hash.iaddr1 = 0;
 780         regs->hash.iaddr2 = 0;
 781         regs->hash.iaddr3 = 0;
 782         regs->hash.iaddr4 = 0;
 783         regs->hash.iaddr5 = 0;
 784         regs->hash.iaddr6 = 0;
 785         regs->hash.iaddr7 = 0;
 786
 787         regs->hash.gaddr0 = 0;
 788         regs->hash.gaddr1 = 0;
 789         regs->hash.gaddr2 = 0;
 790         regs->hash.gaddr3 = 0;
 791         regs->hash.gaddr4 = 0;
 792         regs->hash.gaddr5 = 0;
 793         regs->hash.gaddr6 = 0;
 794         regs->hash.gaddr7 = 0;
 795
 796         regs->rctrl = 0x00000000;
 797
 798         /* Init RMON mib registers */
 799         memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
 800
 801         regs->rmon.cam1 = 0xffffffff;
 802         regs->rmon.cam2 = 0xffffffff;
 803
 804         regs->mrblr = MRBLR_INIT_SETTINGS;
 805
 806         regs->minflr = MINFLR_INIT_SETTINGS;
 807
 808         regs->attr = ATTR_INIT_SETTINGS;
 809         regs->attreli = ATTRELI_INIT_SETTINGS;
 810
 811 }
 812
 813 /* Configure maccfg2 based on negotiated speed and duplex
 814  * reported by PHY handling code
 815  */
 816 static void adjust_link(struct eth_device *dev)
 817 {
 818         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 819         volatile tsec_t *regs = priv->regs;
 820
 821         if (priv->link) {
 822                 if (priv->duplexity != 0)
 823                         regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
 824                 else
 825                         regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
 826
 827                 switch (priv->speed) {
 828                 case 1000:
 829                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 830                                          | MACCFG2_GMII);
 831                         break;
 832                 case 100:
 833                 case 10:
 834                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 835                                          | MACCFG2_MII);
 836
 837                         /* Set R100 bit in all modes although
 838                          * it is only used in RGMII mode
 839                          */
 840                         if (priv->speed == 100)
 841                                 regs->ecntrl |= ECNTRL_R100;
 842                         else
 843                                 regs->ecntrl &= ~(ECNTRL_R100);
 844                         break;
 845                 default:
 846                         printf("%s: Speed was bad\n", dev->name);
 847                         break;
 848                 }
 849
 850                 printf("Speed: %d, %s duplex\n", priv->speed,
 851                        (priv->duplexity) ? "full" : "half");
 852
 853         } else {
 854                 printf("%s: No link.\n", dev->name);
 855         }
 856 }
 857
 858 /* Set up the buffers and their descriptors, and bring up the
 859  * interface
 860  */
 861 static void startup_tsec(struct eth_device *dev)
 862 {
 863         int i;
 864         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 865         volatile tsec_t *regs = priv->regs;
 866
 867         /* Point to the buffer descriptors */
 868         regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
 869         regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
 870
 871         /* Initialize the Rx Buffer descriptors */
 872         for (i = 0; i < PKTBUFSRX; i++) {
 873                 rtx.rxbd[i].status = RXBD_EMPTY;
 874                 rtx.rxbd[i].length = 0;
 875                 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
 876         }
 877         rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
 878
 879         /* Initialize the TX Buffer Descriptors */
 880         for (i = 0; i < TX_BUF_CNT; i++) {
 881                 rtx.txbd[i].status = 0;
 882                 rtx.txbd[i].length = 0;
 883                 rtx.txbd[i].bufPtr = 0;
 884         }
 885         rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
 886
 887         /* Start up the PHY */
 888         if(priv->phyinfo)
 889                 phy_run_commands(priv, priv->phyinfo->startup);
 890
 891         adjust_link(dev);
 892
 893         /* Enable Transmit and Receive */
 894         regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 895
 896         /* Tell the DMA it is clear to go */
 897         regs->dmactrl |= DMACTRL_INIT_SETTINGS;
 898         regs->tstat = TSTAT_CLEAR_THALT;
 899         regs->rstat = RSTAT_CLEAR_RHALT;
 900         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 901 }
 902
 903 /* This returns the status bits of the device.  The return value
 904  * is never checked, and this is what the 8260 driver did, so we
 905  * do the same.  Presumably, this would be zero if there were no
 906  * errors
 907  */
 908 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
 909 {
 910         int i;
 911         int result = 0;
 912         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 913         volatile tsec_t *regs = priv->regs;
 914
 915         /* Find an empty buffer descriptor */
 916         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 917                 if (i >= TOUT_LOOP) {
 918                         debug("%s: tsec: tx buffers full\n", dev->name);
 919                         return result;
 920                 }
 921         }
 922
 923         rtx.txbd[txIdx].bufPtr = (uint) packet;
 924         rtx.txbd[txIdx].length = length;
 925         rtx.txbd[txIdx].status |=
 926             (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
 927
 928         /* Tell the DMA to go */
 929         regs->tstat = TSTAT_CLEAR_THALT;
 930
 931         /* Wait for buffer to be transmitted */
 932         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 933                 if (i >= TOUT_LOOP) {
 934                         debug("%s: tsec: tx error\n", dev->name);
 935                         return result;
 936                 }
 937         }
 938
 939         txIdx = (txIdx + 1) % TX_BUF_CNT;
 940         result = rtx.txbd[txIdx].status & TXBD_STATS;
 941
 942         return result;
 943 }
 944
 945 static int tsec_recv(struct eth_device *dev)
 946 {
 947         int length;
 948         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 949         volatile tsec_t *regs = priv->regs;
 950
 951         while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
 952
 953                 length = rtx.rxbd[rxIdx].length;
 954
 955                 /* Send the packet up if there were no errors */
 956                 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
 957                         NetReceive(NetRxPackets[rxIdx], length - 4);
 958                 } else {
 959                         printf("Got error %x\n",
 960                                (rtx.rxbd[rxIdx].status & RXBD_STATS));
 961                 }
 962
 963                 rtx.rxbd[rxIdx].length = 0;
 964
 965                 /* Set the wrap bit if this is the last element in the list */
 966                 rtx.rxbd[rxIdx].status =
 967                     RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
 968
 969                 rxIdx = (rxIdx + 1) % PKTBUFSRX;
 970         }
 971
 972         if (regs->ievent & IEVENT_BSY) {
 973                 regs->ievent = IEVENT_BSY;
 974                 regs->rstat = RSTAT_CLEAR_RHALT;
 975         }
 976
 977         return -1;
 978
 979 }
 980
 981 /* Stop the interface */
 982 static void tsec_halt(struct eth_device *dev)
 983 {
 984         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 985         volatile tsec_t *regs = priv->regs;
 986
 987         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 988         regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
 989
 990         while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
 991
 992         regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
 993
 994         /* Shut down the PHY, as needed */
 995         if(priv->phyinfo)
 996                 phy_run_commands(priv, priv->phyinfo->shutdown);
 997 }
 998
 999 struct phy_info phy_info_M88E1149S = {
1000         0x1410ca,
1001         "Marvell 88E1149S",
1002         4,
1003         (struct phy_cmd[]){     /* config */
1004                 /* Reset and configure the PHY */
1005                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1006                 {0x1d, 0x1f, NULL},
1007                 {0x1e, 0x200c, NULL},
1008                 {0x1d, 0x5, NULL},
1009                 {0x1e, 0x0, NULL},
1010                 {0x1e, 0x100, NULL},
1011                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1012                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1013                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1014                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1015                 {miim_end,}
1016         },
1017         (struct phy_cmd[]){     /* startup */
1018                 /* Status is read once to clear old link state */
1019                 {MIIM_STATUS, miim_read, NULL},
1020                 /* Auto-negotiate */
1021                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1022                 /* Read the status */
1023                 {MIIM_88E1011_PHY_STATUS, miim_read,
1024                  &mii_parse_88E1011_psr},
1025                 {miim_end,}
1026         },
1027         (struct phy_cmd[]){     /* shutdown */
1028                 {miim_end,}
1029         },
1030 };
1031
1032 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
1033 struct phy_info phy_info_BCM5461S = {
1034         0x02060c1,      /* 5461 ID */
1035         "Broadcom BCM5461S",
1036         0, /* not clear to me what minor revisions we can shift away */
1037         (struct phy_cmd[]) { /* config */
1038                 /* Reset and configure the PHY */
1039                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1040                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1041                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1042                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1043                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1044                 {miim_end,}
1045         },
1046         (struct phy_cmd[]) { /* startup */
1047                 /* Status is read once to clear old link state */
1048                 {MIIM_STATUS, miim_read, NULL},
1049                 /* Auto-negotiate */
1050                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1051                 /* Read the status */
1052                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1053                 {miim_end,}
1054         },
1055         (struct phy_cmd[]) { /* shutdown */
1056                 {miim_end,}
1057         },
1058 };
1059
1060 struct phy_info phy_info_BCM5464S = {
1061         0x02060b1,      /* 5464 ID */
1062         "Broadcom BCM5464S",
1063         0, /* not clear to me what minor revisions we can shift away */
1064         (struct phy_cmd[]) { /* config */
1065                 /* Reset and configure the PHY */
1066                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1067                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1068                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1069                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1070                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1071                 {miim_end,}
1072         },
1073         (struct phy_cmd[]) { /* startup */
1074                 /* Status is read once to clear old link state */
1075                 {MIIM_STATUS, miim_read, NULL},
1076                 /* Auto-negotiate */
1077                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1078                 /* Read the status */
1079                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1080                 {miim_end,}
1081         },
1082         (struct phy_cmd[]) { /* shutdown */
1083                 {miim_end,}
1084         },
1085 };
1086
1087 struct phy_info phy_info_BCM5482S =  {
1088         0x0143bcb,
1089         "Broadcom BCM5482S",
1090         4,
1091         (struct phy_cmd[]) { /* config */
1092                 /* Reset and configure the PHY */
1093                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1094                 /* Setup read from auxilary control shadow register 7 */
1095                 {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL},
1096                 /* Read Misc Control register and or in Ethernet@Wirespeed */
1097                 {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed},
1098                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1099                 {miim_end,}
1100         },
1101         (struct phy_cmd[]) { /* startup */
1102                 /* Status is read once to clear old link state */
1103                 {MIIM_STATUS, miim_read, NULL},
1104                 /* Auto-negotiate */
1105                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1106                 /* Read the status */
1107                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1108                 {miim_end,}
1109         },
1110         (struct phy_cmd[]) { /* shutdown */
1111                 {miim_end,}
1112         },
1113 };
1114
1115 struct phy_info phy_info_M88E1011S = {
1116         0x01410c6,
1117         "Marvell 88E1011S",
1118         4,
1119         (struct phy_cmd[]){     /* config */
1120                            /* Reset and configure the PHY */
1121                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1122                            {0x1d, 0x1f, NULL},
1123                            {0x1e, 0x200c, NULL},
1124                            {0x1d, 0x5, NULL},
1125                            {0x1e, 0x0, NULL},
1126                            {0x1e, 0x100, NULL},
1127                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1128                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1129                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1130                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1131                            {miim_end,}
1132                            },
1133         (struct phy_cmd[]){     /* startup */
1134                            /* Status is read once to clear old link state */
1135                            {MIIM_STATUS, miim_read, NULL},
1136                            /* Auto-negotiate */
1137                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1138                            /* Read the status */
1139                            {MIIM_88E1011_PHY_STATUS, miim_read,
1140                             &mii_parse_88E1011_psr},
1141                            {miim_end,}
1142                            },
1143         (struct phy_cmd[]){     /* shutdown */
1144                            {miim_end,}
1145                            },
1146 };
1147
1148 struct phy_info phy_info_M88E1111S = {
1149         0x01410cc,
1150         "Marvell 88E1111S",
1151         4,
1152         (struct phy_cmd[]){     /* config */
1153                            /* Reset and configure the PHY */
1154                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1155                            {0x1b, 0x848f, &mii_m88e1111s_setmode},
1156                            {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
1157                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1158                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1159                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1160                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1161                            {miim_end,}
1162                            },
1163         (struct phy_cmd[]){     /* startup */
1164                            /* Status is read once to clear old link state */
1165                            {MIIM_STATUS, miim_read, NULL},
1166                            /* Auto-negotiate */
1167                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1168                            /* Read the status */
1169                            {MIIM_88E1011_PHY_STATUS, miim_read,
1170                             &mii_parse_88E1011_psr},
1171                            {miim_end,}
1172                            },
1173         (struct phy_cmd[]){     /* shutdown */
1174                            {miim_end,}
1175                            },
1176 };
1177
1178 struct phy_info phy_info_M88E1118 = {
1179         0x01410e1,
1180         "Marvell 88E1118",
1181         4,
1182         (struct phy_cmd[]){     /* config */
1183                 /* Reset and configure the PHY */
1184                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1185                 {0x16, 0x0002, NULL}, /* Change Page Number */
1186                 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */
1187                 {0x16, 0x0003, NULL}, /* Change Page Number */
1188                 {0x10, 0x021e, NULL}, /* Adjust LED control */
1189                 {0x16, 0x0000, NULL}, /* Change Page Number */
1190                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1191                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1192                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1193                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1194                 {miim_end,}
1195                 },
1196         (struct phy_cmd[]){     /* startup */
1197                 {0x16, 0x0000, NULL}, /* Change Page Number */
1198                 /* Status is read once to clear old link state */
1199                 {MIIM_STATUS, miim_read, NULL},
1200                 /* Auto-negotiate */
1201                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1202                 /* Read the status */
1203                 {MIIM_88E1011_PHY_STATUS, miim_read,
1204                  &mii_parse_88E1011_psr},
1205                 {miim_end,}
1206                 },
1207         (struct phy_cmd[]){     /* shutdown */
1208                 {miim_end,}
1209                 },
1210 };
1211
1212 /*
1213  *  Since to access LED register we need do switch the page, we
1214  * do LED configuring in the miim_read-like function as follows
1215  */
1216 uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
1217 {
1218         uint pg;
1219
1220         /* Switch the page to access the led register */
1221         pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
1222         write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
1223
1224         /* Configure leds */
1225         write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
1226                       MIIM_88E1121_PHY_LED_DEF);
1227
1228         /* Restore the page pointer */
1229         write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
1230         return 0;
1231 }
1232
1233 struct phy_info phy_info_M88E1121R = {
1234         0x01410cb,
1235         "Marvell 88E1121R",
1236         4,
1237         (struct phy_cmd[]){     /* config */
1238                            /* Reset and configure the PHY */
1239                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1240                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1241                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1242                            /* Configure leds */
1243                            {MIIM_88E1121_PHY_LED_CTRL, miim_read,
1244                             &mii_88E1121_set_led},
1245                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1246                            /* Disable IRQs and de-assert interrupt */
1247                            {MIIM_88E1121_PHY_IRQ_EN, 0, NULL},
1248                            {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL},
1249                            {miim_end,}
1250                            },
1251         (struct phy_cmd[]){     /* startup */
1252                            /* Status is read once to clear old link state */
1253                            {MIIM_STATUS, miim_read, NULL},
1254                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1255                            {MIIM_STATUS, miim_read, &mii_parse_link},
1256                            {miim_end,}
1257                            },
1258         (struct phy_cmd[]){     /* shutdown */
1259                            {miim_end,}
1260                            },
1261 };
1262
1263 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1264 {
1265         uint mii_data = read_phy_reg(priv, mii_reg);
1266
1267         /* Setting MIIM_88E1145_PHY_EXT_CR */
1268         if (priv->flags & TSEC_REDUCED)
1269                 return mii_data |
1270                     MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1271         else
1272                 return mii_data;
1273 }
1274
1275 static struct phy_info phy_info_M88E1145 = {
1276         0x01410cd,
1277         "Marvell 88E1145",
1278         4,
1279         (struct phy_cmd[]){     /* config */
1280                            /* Reset the PHY */
1281                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1282
1283                            /* Errata E0, E1 */
1284                            {29, 0x001b, NULL},
1285                            {30, 0x418f, NULL},
1286                            {29, 0x0016, NULL},
1287                            {30, 0xa2da, NULL},
1288
1289                            /* Configure the PHY */
1290                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1291                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1292                            {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
1293                             NULL},
1294                            {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1295                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1296                            {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1297                            {miim_end,}
1298                            },
1299         (struct phy_cmd[]){     /* startup */
1300                            /* Status is read once to clear old link state */
1301                            {MIIM_STATUS, miim_read, NULL},
1302                            /* Auto-negotiate */
1303                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1304                            {MIIM_88E1111_PHY_LED_CONTROL,
1305                             MIIM_88E1111_PHY_LED_DIRECT, NULL},
1306                            /* Read the Status */
1307                            {MIIM_88E1011_PHY_STATUS, miim_read,
1308                             &mii_parse_88E1011_psr},
1309                            {miim_end,}
1310                            },
1311         (struct phy_cmd[]){     /* shutdown */
1312                            {miim_end,}
1313                            },
1314 };
1315
1316 struct phy_info phy_info_cis8204 = {
1317         0x3f11,
1318         "Cicada Cis8204",
1319         6,
1320         (struct phy_cmd[]){     /* config */
1321                            /* Override PHY config settings */
1322                            {MIIM_CIS8201_AUX_CONSTAT,
1323                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1324                            /* Configure some basic stuff */
1325                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1326                            {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1327                             &mii_cis8204_fixled},
1328                            {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1329                             &mii_cis8204_setmode},
1330                            {miim_end,}
1331                            },
1332         (struct phy_cmd[]){     /* startup */
1333                            /* Read the Status (2x to make sure link is right) */
1334                            {MIIM_STATUS, miim_read, NULL},
1335                            /* Auto-negotiate */
1336                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1337                            /* Read the status */
1338                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1339                             &mii_parse_cis8201},
1340                            {miim_end,}
1341                            },
1342         (struct phy_cmd[]){     /* shutdown */
1343                            {miim_end,}
1344                            },
1345 };
1346
1347 /* Cicada 8201 */
1348 struct phy_info phy_info_cis8201 = {
1349         0xfc41,
1350         "CIS8201",
1351         4,
1352         (struct phy_cmd[]){     /* config */
1353                            /* Override PHY config settings */
1354                            {MIIM_CIS8201_AUX_CONSTAT,
1355                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1356                            /* Set up the interface mode */
1357                            {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1358                             NULL},
1359                            /* Configure some basic stuff */
1360                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1361                            {miim_end,}
1362                            },
1363         (struct phy_cmd[]){     /* startup */
1364                            /* Read the Status (2x to make sure link is right) */
1365                            {MIIM_STATUS, miim_read, NULL},
1366                            /* Auto-negotiate */
1367                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1368                            /* Read the status */
1369                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1370                             &mii_parse_cis8201},
1371                            {miim_end,}
1372                            },
1373         (struct phy_cmd[]){     /* shutdown */
1374                            {miim_end,}
1375                            },
1376 };
1377 struct phy_info phy_info_VSC8211 = {
1378         0xfc4b,
1379         "Vitesse VSC8211",
1380         4,
1381         (struct phy_cmd[]) { /* config */
1382                            /* Override PHY config settings */
1383                            {MIIM_CIS8201_AUX_CONSTAT,
1384                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1385                            /* Set up the interface mode */
1386                            {MIIM_CIS8201_EXT_CON1,
1387                             MIIM_CIS8201_EXTCON1_INIT, NULL},
1388                            /* Configure some basic stuff */
1389                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1390                            {miim_end,}
1391                            },
1392         (struct phy_cmd[]) { /* startup */
1393                            /* Read the Status (2x to make sure link is right) */
1394                            {MIIM_STATUS, miim_read, NULL},
1395                            /* Auto-negotiate */
1396                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1397                            /* Read the status */
1398                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1399                             &mii_parse_cis8201},
1400                            {miim_end,}
1401                            },
1402         (struct phy_cmd[]) { /* shutdown */
1403                            {miim_end,}
1404         },
1405 };
1406 struct phy_info phy_info_VSC8244 = {
1407         0x3f1b,
1408         "Vitesse VSC8244",
1409         6,
1410         (struct phy_cmd[]){     /* config */
1411                            /* Override PHY config settings */
1412                            /* Configure some basic stuff */
1413                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1414                            {miim_end,}
1415                            },
1416         (struct phy_cmd[]){     /* startup */
1417                            /* Read the Status (2x to make sure link is right) */
1418                            {MIIM_STATUS, miim_read, NULL},
1419                            /* Auto-negotiate */
1420                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1421                            /* Read the status */
1422                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1423                             &mii_parse_vsc8244},
1424                            {miim_end,}
1425                            },
1426         (struct phy_cmd[]){     /* shutdown */
1427                            {miim_end,}
1428                            },
1429 };
1430
1431 struct phy_info phy_info_VSC8641 = {
1432         0x7043,
1433         "Vitesse VSC8641",
1434         4,
1435         (struct phy_cmd[]){     /* config */
1436                            /* Configure some basic stuff */
1437                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1438                            {miim_end,}
1439                            },
1440         (struct phy_cmd[]){     /* startup */
1441                            /* Read the Status (2x to make sure link is right) */
1442                            {MIIM_STATUS, miim_read, NULL},
1443                            /* Auto-negotiate */
1444                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1445                            /* Read the status */
1446                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1447                             &mii_parse_vsc8244},
1448                            {miim_end,}
1449                            },
1450         (struct phy_cmd[]){     /* shutdown */
1451                            {miim_end,}
1452                            },
1453 };
1454
1455 struct phy_info phy_info_VSC8221 = {
1456         0xfc55,
1457         "Vitesse VSC8221",
1458         4,
1459         (struct phy_cmd[]){     /* config */
1460                            /* Configure some basic stuff */
1461                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1462                            {miim_end,}
1463                            },
1464         (struct phy_cmd[]){     /* startup */
1465                            /* Read the Status (2x to make sure link is right) */
1466                            {MIIM_STATUS, miim_read, NULL},
1467                            /* Auto-negotiate */
1468                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1469                            /* Read the status */
1470                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1471                             &mii_parse_vsc8244},
1472                            {miim_end,}
1473                            },
1474         (struct phy_cmd[]){     /* shutdown */
1475                            {miim_end,}
1476                            },
1477 };
1478
1479 struct phy_info phy_info_VSC8601 = {
1480                 0x00007042,
1481                 "Vitesse VSC8601",
1482                 4,
1483                 (struct phy_cmd[]){     /* config */
1484                                 /* Override PHY config settings */
1485                                 /* Configure some basic stuff */
1486                                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1487 #ifdef CONFIG_SYS_VSC8601_SKEWFIX
1488                                 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
1489 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
1490                                 {MIIM_EXT_PAGE_ACCESS,1,NULL},
1491 #define VSC8101_SKEW    (CONFIG_SYS_VSC8601_SKEW_TX<<14)|(CONFIG_SYS_VSC8601_SKEW_RX<<12)
1492                                 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
1493                                 {MIIM_EXT_PAGE_ACCESS,0,NULL},
1494 #endif
1495 #endif
1496                                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1497                                 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init},
1498                                 {miim_end,}
1499                                  },
1500                 (struct phy_cmd[]){     /* startup */
1501                                 /* Read the Status (2x to make sure link is right) */
1502                                 {MIIM_STATUS, miim_read, NULL},
1503                                 /* Auto-negotiate */
1504                                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1505                                 /* Read the status */
1506                                 {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1507                                                 &mii_parse_vsc8244},
1508                                 {miim_end,}
1509                                 },
1510                 (struct phy_cmd[]){     /* shutdown */
1511                                 {miim_end,}
1512                                 },
1513 };
1514
1515
1516 struct phy_info phy_info_dm9161 = {
1517         0x0181b88,
1518         "Davicom DM9161E",
1519         4,
1520         (struct phy_cmd[]){     /* config */
1521                            {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1522                            /* Do not bypass the scrambler/descrambler */
1523                            {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1524                            /* Clear 10BTCSR to default */
1525                            {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1526                             NULL},
1527                            /* Configure some basic stuff */
1528                            {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1529                            /* Restart Auto Negotiation */
1530                            {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1531                            {miim_end,}
1532                            },
1533         (struct phy_cmd[]){     /* startup */
1534                            /* Status is read once to clear old link state */
1535                            {MIIM_STATUS, miim_read, NULL},
1536                            /* Auto-negotiate */
1537                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1538                            /* Read the status */
1539                            {MIIM_DM9161_SCSR, miim_read,
1540                             &mii_parse_dm9161_scsr},
1541                            {miim_end,}
1542                            },
1543         (struct phy_cmd[]){     /* shutdown */
1544                            {miim_end,}
1545                            },
1546 };
1547 /* a generic flavor.  */
1548 struct phy_info phy_info_generic =  {
1549         0,
1550         "Unknown/Generic PHY",
1551         32,
1552         (struct phy_cmd[]) { /* config */
1553                 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1554                 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1555                 {miim_end,}
1556         },
1557         (struct phy_cmd[]) { /* startup */
1558                 {PHY_BMSR, miim_read, NULL},
1559                 {PHY_BMSR, miim_read, &mii_parse_sr},
1560                 {PHY_BMSR, miim_read, &mii_parse_link},
1561                 {miim_end,}
1562         },
1563         (struct phy_cmd[]) { /* shutdown */
1564                 {miim_end,}
1565         }
1566 };
1567
1568
1569 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1570 {
1571         unsigned int speed;
1572         if (priv->link) {
1573                 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1574
1575                 switch (speed) {
1576                 case MIIM_LXT971_SR2_10HDX:
1577                         priv->speed = 10;
1578                         priv->duplexity = 0;
1579                         break;
1580                 case MIIM_LXT971_SR2_10FDX:
1581                         priv->speed = 10;
1582                         priv->duplexity = 1;
1583                         break;
1584                 case MIIM_LXT971_SR2_100HDX:
1585                         priv->speed = 100;
1586                         priv->duplexity = 0;
1587                         break;
1588                 default:
1589                         priv->speed = 100;
1590                         priv->duplexity = 1;
1591                 }
1592         } else {
1593                 priv->speed = 0;
1594                 priv->duplexity = 0;
1595         }
1596
1597         return 0;
1598 }
1599
1600 static struct phy_info phy_info_lxt971 = {
1601         0x0001378e,
1602         "LXT971",
1603         4,
1604         (struct phy_cmd[]){     /* config */
1605                            {MIIM_CR, MIIM_CR_INIT, mii_cr_init},        /* autonegotiate */
1606                            {miim_end,}
1607                            },
1608         (struct phy_cmd[]){     /* startup - enable interrupts */
1609                            /* { 0x12, 0x00f2, NULL }, */
1610                            {MIIM_STATUS, miim_read, NULL},
1611                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1612                            {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1613                            {miim_end,}
1614                            },
1615         (struct phy_cmd[]){     /* shutdown - disable interrupts */
1616                            {miim_end,}
1617                            },
1618 };
1619
1620 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1621  * information
1622  */
1623 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1624 {
1625         switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1626
1627         case MIIM_DP83865_SPD_1000:
1628                 priv->speed = 1000;
1629                 break;
1630
1631         case MIIM_DP83865_SPD_100:
1632                 priv->speed = 100;
1633                 break;
1634
1635         default:
1636                 priv->speed = 10;
1637                 break;
1638
1639         }
1640
1641         if (mii_reg & MIIM_DP83865_DPX_FULL)
1642                 priv->duplexity = 1;
1643         else
1644                 priv->duplexity = 0;
1645
1646         return 0;
1647 }
1648
1649 struct phy_info phy_info_dp83865 = {
1650         0x20005c7,
1651         "NatSemi DP83865",
1652         4,
1653         (struct phy_cmd[]){     /* config */
1654                            {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1655                            {miim_end,}
1656                            },
1657         (struct phy_cmd[]){     /* startup */
1658                            /* Status is read once to clear old link state */
1659                            {MIIM_STATUS, miim_read, NULL},
1660                            /* Auto-negotiate */
1661                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1662                            /* Read the link and auto-neg status */
1663                            {MIIM_DP83865_LANR, miim_read,
1664                             &mii_parse_dp83865_lanr},
1665                            {miim_end,}
1666                            },
1667         (struct phy_cmd[]){     /* shutdown */
1668                            {miim_end,}
1669                            },
1670 };
1671
1672 struct phy_info phy_info_rtl8211b = {
1673         0x001cc91,
1674         "RealTek RTL8211B",
1675         4,
1676         (struct phy_cmd[]){     /* config */
1677                 /* Reset and configure the PHY */
1678                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1679                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1680                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1681                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1682                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1683                 {miim_end,}
1684         },
1685         (struct phy_cmd[]){     /* startup */
1686                 /* Status is read once to clear old link state */
1687                 {MIIM_STATUS, miim_read, NULL},
1688                 /* Auto-negotiate */
1689                 {MIIM_STATUS, miim_read, &mii_parse_sr},
1690                 /* Read the status */
1691                 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr},
1692                 {miim_end,}
1693         },
1694         (struct phy_cmd[]){     /* shutdown */
1695                 {miim_end,}
1696         },
1697 };
1698
1699 struct phy_info *phy_info[] = {
1700         &phy_info_cis8204,
1701         &phy_info_cis8201,
1702         &phy_info_BCM5461S,
1703         &phy_info_BCM5464S,
1704         &phy_info_BCM5482S,
1705         &phy_info_M88E1011S,
1706         &phy_info_M88E1111S,
1707         &phy_info_M88E1118,
1708         &phy_info_M88E1121R,
1709         &phy_info_M88E1145,
1710         &phy_info_M88E1149S,
1711         &phy_info_dm9161,
1712         &phy_info_lxt971,
1713         &phy_info_VSC8211,
1714         &phy_info_VSC8244,
1715         &phy_info_VSC8601,
1716         &phy_info_VSC8641,
1717         &phy_info_VSC8221,
1718         &phy_info_dp83865,
1719         &phy_info_rtl8211b,
1720         &phy_info_generic,      /* must be last; has ID 0 and 32 bit mask */
1721         NULL
1722 };
1723
1724 /* Grab the identifier of the device's PHY, and search through
1725  * all of the known PHYs to see if one matches.  If so, return
1726  * it, if not, return NULL
1727  */
1728 struct phy_info *get_phy_info(struct eth_device *dev)
1729 {
1730         struct tsec_private *priv = (struct tsec_private *)dev->priv;
1731         uint phy_reg, phy_ID;
1732         int i;
1733         struct phy_info *theInfo = NULL;
1734
1735         /* Grab the bits from PHYIR1, and put them in the upper half */
1736         phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1737         phy_ID = (phy_reg & 0xffff) << 16;
1738
1739         /* Grab the bits from PHYIR2, and put them in the lower half */
1740         phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1741         phy_ID |= (phy_reg & 0xffff);
1742
1743         /* loop through all the known PHY types, and find one that */
1744         /* matches the ID we read from the PHY. */
1745         for (i = 0; phy_info[i]; i++) {
1746                 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
1747                         theInfo = phy_info[i];
1748                         break;
1749                 }
1750         }
1751
1752         if (theInfo == &phy_info_generic) {
1753                 printf("%s: No support for PHY id %x; assuming generic\n", dev->name, phy_ID);
1754         } else {
1755                 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1756         }
1757
1758         return theInfo;
1759 }
1760
1761 /* Execute the given series of commands on the given device's
1762  * PHY, running functions as necessary
1763  */
1764 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1765 {
1766         int i;
1767         uint result;
1768         volatile tsec_mdio_t *phyregs = priv->phyregs;
1769
1770         phyregs->miimcfg = MIIMCFG_RESET;
1771
1772         phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1773
1774         while (phyregs->miimind & MIIMIND_BUSY) ;
1775
1776         for (i = 0; cmd->mii_reg != miim_end; i++) {
1777                 if (cmd->mii_data == miim_read) {
1778                         result = read_phy_reg(priv, cmd->mii_reg);
1779
1780                         if (cmd->funct != NULL)
1781                                 (*(cmd->funct)) (result, priv);
1782
1783                 } else {
1784                         if (cmd->funct != NULL)
1785                                 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1786                         else
1787                                 result = cmd->mii_data;
1788
1789                         write_phy_reg(priv, cmd->mii_reg, result);
1790
1791                 }
1792                 cmd++;
1793         }
1794 }
1795
1796 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1797         && !defined(BITBANGMII)
1798
1799 /*
1800  * Read a MII PHY register.
1801  *
1802  * Returns:
1803  *  0 on success
1804  */
1805 static int tsec_miiphy_read(char *devname, unsigned char addr,
1806                             unsigned char reg, unsigned short *value)
1807 {
1808         unsigned short ret;
1809         struct tsec_private *priv = privlist[0];
1810
1811         if (NULL == priv) {
1812                 printf("Can't read PHY at address %d\n", addr);
1813                 return -1;
1814         }
1815
1816         ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
1817         *value = ret;
1818
1819         return 0;
1820 }
1821
1822 /*
1823  * Write a MII PHY register.
1824  *
1825  * Returns:
1826  *  0 on success
1827  */
1828 static int tsec_miiphy_write(char *devname, unsigned char addr,
1829                              unsigned char reg, unsigned short value)
1830 {
1831         struct tsec_private *priv = privlist[0];
1832
1833         if (NULL == priv) {
1834                 printf("Can't write PHY at address %d\n", addr);
1835                 return -1;
1836         }
1837
1838         tsec_local_mdio_write(priv->phyregs, addr, reg, value);
1839
1840         return 0;
1841 }
1842
1843 #endif
1844
1845 #ifdef CONFIG_MCAST_TFTP
1846
1847 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1848
1849 /* Set the appropriate hash bit for the given addr */
1850
1851 /* The algorithm works like so:
1852  * 1) Take the Destination Address (ie the multicast address), and
1853  * do a CRC on it (little endian), and reverse the bits of the
1854  * result.
1855  * 2) Use the 8 most significant bits as a hash into a 256-entry
1856  * table.  The table is controlled through 8 32-bit registers:
1857  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1858  * gaddr7.  This means that the 3 most significant bits in the
1859  * hash index which gaddr register to use, and the 5 other bits
1860  * indicate which bit (assuming an IBM numbering scheme, which
1861  * for PowerPC (tm) is usually the case) in the tregister holds
1862  * the entry. */
1863 static int
1864 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
1865 {
1866  struct tsec_private *priv = privlist[1];
1867  volatile tsec_t *regs = priv->regs;
1868  volatile u32  *reg_array, value;
1869  u8 result, whichbit, whichreg;
1870
1871         result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
1872         whichbit = result & 0x1f;       /* the 5 LSB = which bit to set */
1873         whichreg = result >> 5;         /* the 3 MSB = which reg to set it in */
1874         value = (1 << (31-whichbit));
1875
1876         reg_array = &(regs->hash.gaddr0);
1877
1878         if (set) {
1879                 reg_array[whichreg] |= value;
1880         } else {
1881                 reg_array[whichreg] &= ~value;
1882         }
1883         return 0;
1884 }
1885 #endif /* Multicast TFTP ? */