drivers/pci.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * (C) Copyright 2002, 2003
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * PCI routines
  29  */
  30
  31 #include <common.h>
  32
  33 #ifdef CONFIG_PCI
  34
  35 #include <command.h>
  36 #include <asm/processor.h>
  37 #include <asm/io.h>
  38 #include <pci.h>
  39
  40 #ifdef DEBUG
  41 #define DEBUGF(x...) printf(x)
  42 #else
  43 #define DEBUGF(x...)
  44 #endif /* DEBUG */
  45
  46 /*
  47  *
  48  */
  49
  50 #define PCI_HOSE_OP(rw, size, type)                                     \
  51 int pci_hose_##rw##_config_##size(struct pci_controller *hose,          \
  52                                   pci_dev_t dev,                        \
  53                                   int offset, type value)               \
  54 {                                                                       \
  55         return hose->rw##_##size(hose, dev, offset, value);             \
  56 }
  57
  58 PCI_HOSE_OP(read, byte, u8 *)
  59 PCI_HOSE_OP(read, word, u16 *)
  60 PCI_HOSE_OP(read, dword, u32 *)
  61 PCI_HOSE_OP(write, byte, u8)
  62 PCI_HOSE_OP(write, word, u16)
  63 PCI_HOSE_OP(write, dword, u32)
  64
  65 #define PCI_OP(rw, size, type, error_code)                              \
  66 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)     \
  67 {                                                                       \
  68         struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));    \
  69                                                                         \
  70         if (!hose)                                                      \
  71         {                                                               \
  72                 error_code;                                             \
  73                 return -1;                                              \
  74         }                                                               \
  75                                                                         \
  76         return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  77 }
  78
  79 PCI_OP(read, byte, u8 *, *value = 0xff)
  80 PCI_OP(read, word, u16 *, *value = 0xffff)
  81 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  82 PCI_OP(write, byte, u8, )
  83 PCI_OP(write, word, u16, )
  84 PCI_OP(write, dword, u32, )
  85
  86 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                     \
  87 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  88                                         pci_dev_t dev,                  \
  89                                         int offset, type val)           \
  90 {                                                                       \
  91         u32 val32;                                                      \
  92                                                                         \
  93         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  94                 return -1;                                              \
  95                                                                         \
  96         *val = (val32 >> ((offset & (int)off_mask) * 8));               \
  97                                                                         \
  98         return 0;                                                       \
  99 }
 100
 101 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)          \
 102 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
 103                                              pci_dev_t dev,             \
 104                                              int offset, type val)      \
 105 {                                                                       \
 106         u32 val32, mask, ldata, shift;                                  \
 107                                                                         \
 108         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
 109                 return -1;                                              \
 110                                                                         \
 111         shift = ((offset & (int)off_mask) * 8);                         \
 112         ldata = (((unsigned long)val) & val_mask) << shift;             \
 113         mask = val_mask << shift;                                       \
 114         val32 = (val32 & ~mask) | ldata;                                \
 115                                                                         \
 116         if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
 117                 return -1;                                              \
 118                                                                         \
 119         return 0;                                                       \
 120 }
 121
 122 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
 123 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
 124 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
 125 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
 126
 127 /*
 128  *
 129  */
 130
 131 static struct pci_controller* hose_head = NULL;
 132
 133 void pci_register_hose(struct pci_controller* hose)
 134 {
 135         struct pci_controller **phose = &hose_head;
 136
 137         while(*phose)
 138                 phose = &(*phose)->next;
 139
 140         hose->next = NULL;
 141
 142         *phose = hose;
 143 }
 144
 145 struct pci_controller *pci_bus_to_hose (int bus)
 146 {
 147         struct pci_controller *hose;
 148
 149         for (hose = hose_head; hose; hose = hose->next)
 150                 if (bus >= hose->first_busno && bus <= hose->last_busno)
 151                         return hose;
 152
 153         return NULL;
 154 }
 155
 156 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 157 {
 158         struct pci_controller * hose;
 159         u16 vendor, device;
 160         u8 header_type;
 161         pci_dev_t bdf;
 162         int i, bus, found_multi = 0;
 163
 164         for (hose = hose_head; hose; hose = hose->next)
 165         {
 166 #ifdef CFG_SCSI_SCAN_BUS_REVERSE
 167                 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
 168 #else
 169                 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
 170 #endif
 171                         for (bdf = PCI_BDF(bus,0,0);
 172 #ifdef CONFIG_ELPPC
 173                              bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 174 #else
 175                              bdf < PCI_BDF(bus+1,0,0);
 176 #endif
 177                              bdf += PCI_BDF(0,0,1))
 178                         {
 179                                 if (!PCI_FUNC(bdf)) {
 180                                         pci_read_config_byte(bdf,
 181                                                              PCI_HEADER_TYPE,
 182                                                              &header_type);
 183
 184                                         found_multi = header_type & 0x80;
 185                                 } else {
 186                                         if (!found_multi)
 187                                                 continue;
 188                                 }
 189
 190                                 pci_read_config_word(bdf,
 191                                                      PCI_VENDOR_ID,
 192                                                      &vendor);
 193                                 pci_read_config_word(bdf,
 194                                                      PCI_DEVICE_ID,
 195                                                      &device);
 196
 197                                 for (i=0; ids[i].vendor != 0; i++)
 198                                         if (vendor == ids[i].vendor &&
 199                                             device == ids[i].device)
 200                                         {
 201                                                 if (index <= 0)
 202                                                         return bdf;
 203
 204                                                 index--;
 205                                         }
 206                         }
 207         }
 208
 209         return (-1);
 210 }
 211
 212 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 213 {
 214         static struct pci_device_id ids[2] = {{}, {0, 0}};
 215
 216         ids[0].vendor = vendor;
 217         ids[0].device = device;
 218
 219         return pci_find_devices(ids, index);
 220 }
 221
 222 /*
 223  *
 224  */
 225
 226 unsigned long pci_hose_phys_to_bus (struct pci_controller *hose,
 227                                     unsigned long phys_addr,
 228                                     unsigned long flags)
 229 {
 230         struct pci_region *res;
 231         unsigned long bus_addr;
 232         int i;
 233
 234         if (!hose) {
 235                 printf ("pci_hose_phys_to_bus: %s\n", "invalid hose");
 236                 goto Done;
 237         }
 238
 239         for (i = 0; i < hose->region_count; i++) {
 240                 res = &hose->regions[i];
 241
 242                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 243                         continue;
 244
 245                 bus_addr = phys_addr - res->phys_start + res->bus_start;
 246
 247                 if (bus_addr >= res->bus_start &&
 248                         bus_addr < res->bus_start + res->size) {
 249                         return bus_addr;
 250                 }
 251         }
 252
 253         printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address");
 254
 255 Done:
 256         return 0;
 257 }
 258
 259 unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
 260                                    unsigned long bus_addr,
 261                                    unsigned long flags)
 262 {
 263         struct pci_region *res;
 264         int i;
 265
 266         if (!hose) {
 267                 printf ("pci_hose_bus_to_phys: %s\n", "invalid hose");
 268                 goto Done;
 269         }
 270
 271         for (i = 0; i < hose->region_count; i++) {
 272                 res = &hose->regions[i];
 273
 274                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 275                         continue;
 276
 277                 if (bus_addr >= res->bus_start &&
 278                         bus_addr < res->bus_start + res->size) {
 279                         return bus_addr - res->bus_start + res->phys_start;
 280                 }
 281         }
 282
 283         printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address");
 284
 285 Done:
 286         return 0;
 287 }
 288
 289 /*
 290  *
 291  */
 292
 293 int pci_hose_config_device(struct pci_controller *hose,
 294                            pci_dev_t dev,
 295                            unsigned long io,
 296                            unsigned long mem,
 297                            unsigned long command)
 298 {
 299         unsigned int bar_response, bar_size, bar_value, old_command;
 300         unsigned char pin;
 301         int bar, found_mem64;
 302
 303         DEBUGF ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
 304                 io, mem, command);
 305
 306         pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
 307
 308         for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) {
 309                 pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
 310                 pci_hose_read_config_dword (hose, dev, bar, &bar_response);
 311
 312                 if (!bar_response)
 313                         continue;
 314
 315                 found_mem64 = 0;
 316
 317                 /* Check the BAR type and set our address mask */
 318                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 319                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
 320                         /* round up region base address to a multiple of size */
 321                         io = ((io - 1) | (bar_size - 1)) + 1;
 322                         bar_value = io;
 323                         /* compute new region base address */
 324                         io = io + bar_size;
 325                 } else {
 326                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 327                                 PCI_BASE_ADDRESS_MEM_TYPE_64)
 328                                 found_mem64 = 1;
 329
 330                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 331
 332                         /* round up region base address to multiple of size */
 333                         mem = ((mem - 1) | (bar_size - 1)) + 1;
 334                         bar_value = mem;
 335                         /* compute new region base address */
 336                         mem = mem + bar_size;
 337                 }
 338
 339                 /* Write it out and update our limit */
 340                 pci_hose_write_config_dword (hose, dev, bar, bar_value);
 341
 342                 if (found_mem64) {
 343                         bar += 4;
 344                         pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
 345                 }
 346         }
 347
 348         /* Configure Cache Line Size Register */
 349         pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 350
 351         /* Configure Latency Timer */
 352         pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
 353
 354         /* Disable interrupt line, if device says it wants to use interrupts */
 355         pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
 356         if (pin != 0) {
 357                 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
 358         }
 359
 360         pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
 361         pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
 362                                      (old_command & 0xffff0000) | command);
 363
 364         return 0;
 365 }
 366
 367 /*
 368  *
 369  */
 370
 371 struct pci_config_table *pci_find_config(struct pci_controller *hose,
 372                                          unsigned short class,
 373                                          unsigned int vendor,
 374                                          unsigned int device,
 375                                          unsigned int bus,
 376                                          unsigned int dev,
 377                                          unsigned int func)
 378 {
 379         struct pci_config_table *table;
 380
 381         for (table = hose->config_table; table && table->vendor; table++) {
 382                 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
 383                     (table->device == PCI_ANY_ID || table->device == device) &&
 384                     (table->class  == PCI_ANY_ID || table->class  == class)  &&
 385                     (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
 386                     (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
 387                     (table->func   == PCI_ANY_ID || table->func   == func)) {
 388                         return table;
 389                 }
 390         }
 391
 392         return NULL;
 393 }
 394
 395 void pci_cfgfunc_config_device(struct pci_controller *hose,
 396                                pci_dev_t dev,
 397                                struct pci_config_table *entry)
 398 {
 399         pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
 400 }
 401
 402 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
 403                             pci_dev_t dev, struct pci_config_table *entry)
 404 {
 405 }
 406
 407 /*
 408  *
 409  */
 410
 411 /* HJF: Changed this to return int. I think this is required
 412  * to get the correct result when scanning bridges
 413  */
 414 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 415 extern void pciauto_config_init(struct pci_controller *hose);
 416
 417 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 418 {
 419         unsigned int sub_bus, found_multi=0;
 420         unsigned short vendor, device, class;
 421         unsigned char header_type;
 422         struct pci_config_table *cfg;
 423         pci_dev_t dev;
 424
 425         sub_bus = bus;
 426
 427         for (dev =  PCI_BDF(bus,0,0);
 428              dev <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 429              dev += PCI_BDF(0,0,1))
 430         {
 431                 /* Skip our host bridge */
 432                 if ( dev == PCI_BDF(hose->first_busno,0,0) ) {
 433 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE)              /* don't skip host bridge */
 434                         /*
 435                          * Only skip hostbridge configuration if "pciconfighost" is not set
 436                          */
 437                         if (getenv("pciconfighost") == NULL) {
 438                                 continue; /* Skip our host bridge */
 439                         }
 440 #else
 441                         continue; /* Skip our host bridge */
 442 #endif
 443                 }
 444
 445                 if (PCI_FUNC(dev) && !found_multi)
 446                         continue;
 447
 448                 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 449
 450                 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
 451
 452                 if (vendor != 0xffff && vendor != 0x0000) {
 453
 454                         if (!PCI_FUNC(dev))
 455                                 found_multi = header_type & 0x80;
 456
 457                         DEBUGF("PCI Scan: Found Bus %d, Device %d, Function %d\n",
 458                             PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
 459
 460                         pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
 461                         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 462
 463                         cfg = pci_find_config(hose, class, vendor, device,
 464                                               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 465                         if (cfg) {
 466                                 cfg->config_device(hose, dev, cfg);
 467 #ifdef CONFIG_PCI_PNP
 468                         } else {
 469                                 int n = pciauto_config_device(hose, dev);
 470
 471                                 sub_bus = max(sub_bus, n);
 472 #endif
 473                         }
 474                         if (hose->fixup_irq)
 475                                 hose->fixup_irq(hose, dev);
 476
 477 #ifdef CONFIG_PCI_SCAN_SHOW
 478                         /* Skip our host bridge */
 479                         if ( dev != PCI_BDF(hose->first_busno,0,0) ) {
 480                             unsigned char int_line;
 481
 482                             pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE,
 483                                                       &int_line);
 484                             printf("        %02x  %02x  %04x  %04x  %04x  %02x\n",
 485                                    PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
 486                                    int_line);
 487                         }
 488 #endif
 489                 }
 490         }
 491
 492         return sub_bus;
 493 }
 494
 495 int pci_hose_scan(struct pci_controller *hose)
 496 {
 497 #ifdef CONFIG_PCI_PNP
 498         pciauto_config_init(hose);
 499 #endif
 500         return pci_hose_scan_bus(hose, hose->first_busno);
 501 }
 502
 503 void pci_init(void)
 504 {
 505 #if defined(CONFIG_PCI_BOOTDELAY)
 506         char *s;
 507         int i;
 508
 509         /* wait "pcidelay" ms (if defined)... */
 510         s = getenv ("pcidelay");
 511         if (s) {
 512                 int val = simple_strtoul (s, NULL, 10);
 513                 for (i=0; i<val; i++)
 514                         udelay (1000);
 515         }
 516 #endif /* CONFIG_PCI_BOOTDELAY */
 517
 518         /* now call board specific pci_init()... */
 519         pci_init_board();
 520 }
 521
 522 #endif /* CONFIG_PCI */