2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _COMPHY_HPIPE_H_
8 #define _COMPHY_HPIPE_H_
10 /* SerDes IP register */
11 #define SD_EXTERNAL_CONFIG0_REG 0
12 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
13 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \
14 (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
15 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
16 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \
17 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
18 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
19 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \
20 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
21 #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11
22 #define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \
23 (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
24 #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12
25 #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \
26 (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
27 #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
28 #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \
29 (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
30 #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15
31 #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \
32 (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
34 #define SD_EXTERNAL_CONFIG1_REG 0x4
35 #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
36 #define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
37 (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
38 #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4
39 #define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \
40 (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
41 #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5
42 #define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \
43 (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
44 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6
45 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \
46 (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
48 #define SD_EXTERNAL_CONFIG2_REG 0x8
49 #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
50 #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
51 (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
53 #define SD_EXTERNAL_STATUS0_REG 0x18
54 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
55 #define SD_EXTERNAL_STATUS0_PLL_TX_MASK \
56 (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
57 #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3
58 #define SD_EXTERNAL_STATUS0_PLL_RX_MASK \
59 (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
60 #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4
61 #define SD_EXTERNAL_STATUS0_RX_INIT_MASK \
62 (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
63 #define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6
64 #define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \
65 (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
68 #define HPIPE_PWR_PLL_REG 0x4
69 #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
70 #define HPIPE_PWR_PLL_REF_FREQ_MASK \
71 (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
72 #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5
73 #define HPIPE_PWR_PLL_PHY_MODE_MASK \
74 (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
76 #define HPIPE_KVCO_CALIB_CTRL_REG 0x8
77 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12
78 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \
79 (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
81 #define HPIPE_SQUELCH_FFE_SETTING_REG 0x018
83 #define HPIPE_DFE_REG0 0x01C
84 #define HPIPE_DFE_RES_FORCE_OFFSET 15
85 #define HPIPE_DFE_RES_FORCE_MASK \
86 (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
88 #define HPIPE_DFE_F3_F5_REG 0x028
89 #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14
90 #define HPIPE_DFE_F3_F5_DFE_EN_MASK \
91 (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
92 #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15
93 #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
94 (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
96 #define HPIPE_G1_SET_0_REG 0x034
97 #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
98 #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
99 (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
101 #define HPIPE_G1_SET_1_REG 0x038
102 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
103 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
104 (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
105 #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
106 #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
107 (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
108 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
109 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
110 (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
112 #define HPIPE_G2_SETTINGS_1_REG 0x040
114 #define HPIPE_G3_SETTINGS_1_REG 0x048
115 #define HPIPE_G3_RX_SELMUPI_OFFSET 0
116 #define HPIPE_G3_RX_SELMUPI_MASK \
117 (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET)
118 #define HPIPE_G3_RX_SELMUPF_OFFSET 3
119 #define HPIPE_G3_RX_SELMUPF_MASK \
120 (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET)
121 #define HPIPE_G3_SETTING_BIT_OFFSET 13
122 #define HPIPE_G3_SETTING_BIT_MASK \
123 (0x1 << HPIPE_G3_SETTING_BIT_OFFSET)
125 #define HPIPE_LOOPBACK_REG 0x08c
126 #define HPIPE_LOOPBACK_SEL_OFFSET 1
127 #define HPIPE_LOOPBACK_SEL_MASK \
128 (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
130 #define HPIPE_SYNC_PATTERN_REG 0x090
132 #define HPIPE_INTERFACE_REG 0x94
133 #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
134 #define HPIPE_INTERFACE_GEN_MAX_MASK \
135 (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
136 #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
137 #define HPIPE_INTERFACE_LINK_TRAIN_MASK \
138 (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
140 #define HPIPE_ISOLATE_MODE_REG 0x98
141 #define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0
142 #define HPIPE_ISOLATE_MODE_GEN_RX_MASK \
143 (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
144 #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4
145 #define HPIPE_ISOLATE_MODE_GEN_TX_MASK \
146 (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
148 #define HPIPE_VTHIMPCAL_CTRL_REG 0x104
150 #define HPIPE_PCIE_REG0 0x120
151 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
152 #define HPIPE_PCIE_IDLE_SYNC_MASK \
153 (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
154 #define HPIPE_PCIE_SEL_BITS_OFFSET 13
155 #define HPIPE_PCIE_SEL_BITS_MASK \
156 (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
158 #define HPIPE_LANE_ALIGN_REG 0x124
159 #define HPIPE_LANE_ALIGN_OFF_OFFSET 12
160 #define HPIPE_LANE_ALIGN_OFF_MASK \
161 (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
163 #define HPIPE_MISC_REG 0x13C
164 #define HPIPE_MISC_CLK100M_125M_OFFSET 4
165 #define HPIPE_MISC_CLK100M_125M_MASK \
166 (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
167 #define HPIPE_MISC_TXDCLK_2X_OFFSET 6
168 #define HPIPE_MISC_TXDCLK_2X_MASK \
169 (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
170 #define HPIPE_MISC_CLK500_EN_OFFSET 7
171 #define HPIPE_MISC_CLK500_EN_MASK \
172 (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
173 #define HPIPE_MISC_REFCLK_SEL_OFFSET 10
174 #define HPIPE_MISC_REFCLK_SEL_MASK \
175 (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
177 #define HPIPE_RX_CONTROL_1_REG 0x140
178 #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11
179 #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \
180 (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
181 #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12
182 #define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \
183 (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
185 #define HPIPE_PWR_CTR_REG 0x148
186 #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
187 #define HPIPE_PWR_CTR_RST_DFE_MASK \
188 (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
189 #define HPIPE_PWR_CTR_SFT_RST_OFFSET 10
190 #define HPIPE_PWR_CTR_SFT_RST_MASK \
191 (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
193 #define HPIPE_PLLINTP_REG1 0x150
195 #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
196 #define HPIPE_SMAPLER_OFFSET 12
197 #define HPIPE_SMAPLER_MASK \
198 (0x1 << HPIPE_SMAPLER_OFFSET)
200 #define HPIPE_PWR_CTR_DTL_REG 0x184
201 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
202 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
203 (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
205 #define HPIPE_RX_REG3 0x188
207 #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
208 #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
209 #define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
210 (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
212 #define HPIPE_TX_TRAIN_CTRL_REG 0x26C
213 #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
214 #define HPIPE_TX_TRAIN_CTRL_G1_MASK \
215 (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
216 #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1
217 #define HPIPE_TX_TRAIN_CTRL_GN1_MASK \
218 (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
219 #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2
220 #define HPIPE_TX_TRAIN_CTRL_G0_MASK \
221 (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
223 #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
224 #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
225 #define HPIPE_TRX_TRAIN_TIMER_MASK \
226 (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
228 #define HPIPE_PCIE_REG1 0x288
229 #define HPIPE_PCIE_REG3 0x290
231 #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
232 #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
233 #define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
234 (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
235 #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12
236 #define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \
237 (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
238 #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13
239 #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \
240 (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
241 #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14
242 #define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
243 (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
245 #define HPIPE_TX_TRAIN_REG 0x31C
246 #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
247 #define HPIPE_TX_TRAIN_CHK_INIT_MASK \
248 (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
249 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
250 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
251 (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
253 #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
254 #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
255 #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
256 (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
257 #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10
258 #define HPIPE_TX_NUM_OF_PRESET_MASK \
259 (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
260 #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15
261 #define HPIPE_TX_SWEEP_PRESET_EN_MASK \
262 (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
264 #define HPIPE_G1_SETTINGS_3_REG 0x440
266 #define HPIPE_G1_SETTINGS_4_REG 0x444
267 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
268 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \
269 (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
271 #define HPIPE_G2_SETTINGS_3_REG 0x448
272 #define HPIPE_G2_SETTINGS_4_REG 0x44C
274 #define HPIPE_G3_SETTING_3_REG 0x450
275 #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
276 #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
277 (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
278 #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14
279 #define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \
280 (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
282 #define HPIPE_G3_SETTING_4_REG 0x454
283 #define HPIPE_G3_DFE_RES_OFFSET 8
284 #define HPIPE_G3_DFE_RES_MASK \
285 (0x3 << HPIPE_G3_DFE_RES_OFFSET)
287 #define HPIPE_DFE_CTRL_28_REG 0x49C
288 #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
289 #define HPIPE_DFE_CTRL_28_PIPE4_MASK \
290 (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
292 #define HPIPE_LANE_CONFIG0_REG 0x600
293 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
294 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
295 (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
297 #define HPIPE_LANE_CONFIG1_REG 0x604
298 #define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9
299 #define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \
300 (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET)
301 #define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10
302 #define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \
303 (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET)
305 #define HPIPE_LANE_STATUS1_REG 0x60C
306 #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0
307 #define HPIPE_LANE_STATUS1_PCLK_EN_MASK \
308 (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
310 #define HPIPE_LANE_CFG4_REG 0x620
311 #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
312 #define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
313 (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
314 #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
315 #define HPIPE_LANE_CFG4_DFE_OVER_MASK \
316 (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
317 #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7
318 #define HPIPE_LANE_CFG4_SSC_CTRL_MASK \
319 (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
321 #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
322 #define HPIPE_CFG_PHY_RC_EP_OFFSET 12
323 #define HPIPE_CFG_PHY_RC_EP_MASK \
324 (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
326 #define HPIPE_LANE_EQ_CFG1_REG 0x6a0
327 #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12
328 #define HPIPE_CFG_UPDATE_POLARITY_MASK \
329 (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
331 #define HPIPE_RST_CLK_CTRL_REG 0x704
332 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
333 #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
334 (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
335 #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
336 #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \
337 (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
338 #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
339 #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \
340 (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
341 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
342 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \
343 (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
345 #define HPIPE_TST_MODE_CTRL_REG 0x708
346 #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2
347 #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \
348 (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
350 #define HPIPE_CLK_SRC_LO_REG 0x70c
351 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
352 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \
353 (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
354 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
355 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \
356 (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
357 #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
358 #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \
359 (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
361 #define HPIPE_CLK_SRC_HI_REG 0x710
362 #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
363 #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \
364 (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
365 #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
366 #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \
367 (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
368 #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
369 #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \
370 (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
371 #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
372 #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \
373 (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
375 #define HPIPE_GLOBAL_MISC_CTRL 0x718
376 #define HPIPE_GLOBAL_PM_CTRL 0x740
377 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
378 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \
379 (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
381 #endif /* _COMPHY_HPIPE_H_ */