1 /*------------------------------------------------------------------------
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
10 . Developed by Simple Network Magic Corporation (SNMC)
11 . Copyright (C) 1996 by Erik Stahlman (ES)
13 . This program is free software; you can redistribute it and/or modify
14 . it under the terms of the GNU General Public License as published by
15 . the Free Software Foundation; either version 2 of the License, or
16 . (at your option) any later version.
18 . This program is distributed in the hope that it will be useful,
19 . but WITHOUT ANY WARRANTY; without even the implied warranty of
20 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 . GNU General Public License for more details.
23 . You should have received a copy of the GNU General Public License
24 . along with this program; if not, write to the Free Software
25 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 . Information contained in this file was obtained from the LAN91C111
28 . manual from SMC. To get a copy, if you really want one, you can find
29 . information under www.smsc.com.
32 . "Features" of the SMC chip:
33 . Integrated PHY/MAC for 10/100BaseT Operation
34 . Supports internal and external MII
35 . Integrated 8K packet memory
36 . EEPROM interface for configuration
39 . io = for the base address
43 . Erik Stahlman ( erik@vt.edu )
44 . Daris A Nevil ( dnevil@snmc.com )
47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
50 . o SMSC LAN91C111 databook (www.smsc.com)
51 . o smc9194.c by Erik Stahlman
52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
55 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
56 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
57 . 07/25/01 Woojung Huh Modify for ADS Bitsy
58 . 04/25/01 Daris A Nevil Initial public release through SMSC
59 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
60 ----------------------------------------------------------------------------*/
68 #ifdef CONFIG_DRIVER_SMC91111
70 /* Use power-down feature of the chip */
78 static const char version[] =
79 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
82 /* Autonegotiation timeout in seconds */
83 #ifndef CONFIG_SMC_AUTONEG_TIMEOUT
84 #define CONFIG_SMC_AUTONEG_TIMEOUT 10
87 /*------------------------------------------------------------------------
89 . Configuration options, for the experienced user to change.
91 -------------------------------------------------------------------------*/
94 . Wait time for memory to be free. This probably shouldn't be
95 . tuned that much, as waiting for this means nothing else happens
98 #define MEMORY_WAIT_TIME 16
102 #define PRINTK3(args...) printf(args)
104 #define PRINTK3(args...)
108 #define PRINTK2(args...) printf(args)
110 #define PRINTK2(args...)
114 #define PRINTK(args...) printf(args)
116 #define PRINTK(args...)
120 /*------------------------------------------------------------------------
122 . The internal workings of the driver. If you are changing anything
123 . here with the SMC stuff, you should have the datasheet and know
124 . what you are doing.
126 -------------------------------------------------------------------------*/
127 #define CARDNAME "LAN91C111"
129 /* Memory sizing constant */
130 #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
132 #ifndef CONFIG_SMC91111_BASE
133 #define CONFIG_SMC91111_BASE 0x20000300
136 #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
138 #define SMC_DEV_NAME "SMC91111"
139 #define SMC_PHY_ADDR 0x0000
140 #define SMC_ALLOC_MAX_TRY 5
141 #define SMC_TX_TIMEOUT 30
143 #define SMC_PHY_CLOCK_DELAY 1000
147 #ifdef CONFIG_SMC_USE_32_BIT
152 /*-----------------------------------------------------------------
154 . The driver can be entered at any of the following entry points.
156 .------------------------------------------------------------------ */
158 extern int eth_init(bd_t *bd);
159 extern void eth_halt(void);
160 extern int eth_rx(void);
161 extern int eth_send(volatile void *packet, int length);
165 . This is called by register_netdev(). It is responsible for
166 . checking the portlist for the SMC9000 series chipset. If it finds
167 . one, then it will initialize the device, find the hardware information,
168 . and sets up the appropriate device parameters.
169 . NOTE: Interrupts are *OFF* when this procedure is called.
171 . NB:This shouldn't be static since it is referred to externally.
176 . This is called by unregister_netdev(). It is responsible for
177 . cleaning up before the driver is finally unregistered and discarded.
179 void smc_destructor(void);
182 . The kernel calls this function when someone wants to use the device,
183 . typically 'ifconfig ethX up'.
185 static int smc_open(bd_t *bd);
189 . This is called by the kernel in response to 'ifconfig ethX down'. It
190 . is responsible for cleaning up everything that the open routine
191 . does, and maybe putting the card into a powerdown state.
193 static int smc_close(void);
196 . Configures the PHY through the MII Management interface
198 #ifndef CONFIG_SMC91111_EXT_PHY
199 static void smc_phy_configure(void);
200 #endif /* !CONFIG_SMC91111_EXT_PHY */
203 . This is a separate procedure to handle the receipt of a packet, to
204 . leave the interrupt code looking slightly cleaner
206 static int smc_rcv(void);
208 /* See if a MAC address is defined in the current environment. If so use it. If not
209 . print a warning and set the environment and other globals with the default.
210 . If an EEPROM is present it really should be consulted.
212 int smc_get_ethaddr(bd_t *bd);
213 int get_rom_mac(uchar *v_rom_mac);
216 ------------------------------------------------------------
220 ------------------------------------------------------------
223 #ifdef CONFIG_SMC_USE_IOFUNCS
225 * input and output functions
227 * Implemented due to inx,outx macros accessing the device improperly
228 * and putting the device into an unkown state.
230 * For instance, on Sharp LPD7A400 SDK, affects were chip memory
231 * could not be free'd (hence the alloc failures), duplicate packets,
232 * packets being corrupt (shifted) on the wire, etc. Switching to the
233 * inx,outx functions fixed this problem.
235 static inline word SMC_inw(dword offset);
236 static inline void SMC_outw(word value, dword offset);
237 static inline byte SMC_inb(dword offset);
238 static inline void SMC_outb(byte value, dword offset);
239 static inline void SMC_insw(dword offset, volatile uchar* buf, dword len);
240 static inline void SMC_outsw(dword offset, uchar* buf, dword len);
242 #define barrier() __asm__ __volatile__("": : :"memory")
244 static inline word SMC_inw(dword offset)
247 v = *((volatile word*)(SMC_BASE_ADDRESS+offset));
248 barrier(); *(volatile u32*)(0xc0000000);
252 static inline void SMC_outw(word value, dword offset)
254 *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value;
255 barrier(); *(volatile u32*)(0xc0000000);
258 static inline byte SMC_inb(dword offset)
262 _w = SMC_inw(offset & ~((dword)1));
263 return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
266 static inline void SMC_outb(byte value, dword offset)
270 _w = SMC_inw(offset & ~((dword)1));
272 *((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff);
274 *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00);
277 static inline void SMC_insw(dword offset, volatile uchar* buf, dword len)
279 volatile word *p = (volatile word *)buf;
282 *p++ = SMC_inw(offset);
284 *((volatile u32*)(0xc0000000));
288 static inline void SMC_outsw(dword offset, uchar* buf, dword len)
290 volatile word *p = (volatile word *)buf;
293 SMC_outw(*p++, offset);
295 *(volatile u32*)(0xc0000000);
298 #endif /* CONFIG_SMC_USE_IOFUNCS */
300 static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
303 * This function must be called before smc_open() if you want to override
304 * the default mac address.
307 void smc_set_mac_addr(const unsigned char *addr) {
310 for (i=0; i < sizeof(smc_mac_addr); i++){
311 smc_mac_addr[i] = addr[i];
316 * smc_get_macaddr is no longer used. If you want to override the default
317 * mac address, call smc_get_mac_addr as a part of the board initialization.
321 void smc_get_macaddr( byte *addr ) {
322 /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
323 unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
327 for (i=0; i<6; i++) {
328 addr[0] = *(dnp1110_mac+0);
329 addr[1] = *(dnp1110_mac+1);
330 addr[2] = *(dnp1110_mac+2);
331 addr[3] = *(dnp1110_mac+3);
332 addr[4] = *(dnp1110_mac+4);
333 addr[5] = *(dnp1110_mac+5);
338 /***********************************************
339 * Show available memory *
340 ***********************************************/
341 void dump_memory_info(void)
346 old_bank = SMC_inw(BANK_SELECT)&0xF;
349 mem_info = SMC_inw( MIR_REG );
350 PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
352 SMC_SELECT_BANK(old_bank);
355 . A rather simple routine to print out a packet for debugging purposes.
358 static void print_packet( byte *, int );
361 #define tx_done(dev) 1
364 /* this does a soft reset on the device */
365 static void smc_reset( void );
367 /* Enable Interrupts, Receive, and Transmit */
368 static void smc_enable( void );
370 /* this puts the device in an inactive state */
371 static void smc_shutdown( void );
373 /* Routines to Read and Write the PHY Registers across the
374 MII Management Interface
377 #ifndef CONFIG_SMC91111_EXT_PHY
378 static word smc_read_phy_register(byte phyreg);
379 static void smc_write_phy_register(byte phyreg, word phydata);
380 #endif /* !CONFIG_SMC91111_EXT_PHY */
383 static int poll4int (byte mask, int timeout)
385 int tmo = get_timer (0) + timeout * CFG_HZ;
387 word old_bank = SMC_inw (BSR_REG);
389 PRINTK2 ("Polling...\n");
391 while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) {
392 if (get_timer (0) >= tmo) {
398 /* restore old bank selection */
399 SMC_SELECT_BANK (old_bank);
407 /* Only one release command at a time, please */
408 static inline void smc_wait_mmu_release_complete (void)
412 /* assume bank 2 selected */
413 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
414 udelay (1); /* Wait until not busy */
421 . Function: smc_reset( void )
423 . This sets the SMC91111 chip to its normal state, hopefully from whatever
424 . mess that any other DOS driver has put it in.
426 . Maybe I should reset more registers to defaults in here? SOFTRST should
430 . 1. send a SOFT RESET
431 . 2. wait for it to finish
432 . 3. enable autorelease mode
433 . 4. reset the memory management unit
434 . 5. clear all interrupts
437 static void smc_reset (void)
439 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
441 /* This resets the registers mostly to defaults, but doesn't
442 affect EEPROM. That seems unnecessary */
444 SMC_outw (RCR_SOFTRST, RCR_REG);
446 /* Setup the Configuration Register */
447 /* This is necessary because the CONFIG_REG is not affected */
448 /* by a soft reset */
451 #if defined(CONFIG_SMC91111_EXT_PHY)
452 SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
454 SMC_outw (CONFIG_DEFAULT, CONFIG_REG);
458 /* Release from possible power-down state */
459 /* Configuration register is not affected by Soft Reset */
460 SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG);
464 /* this should pause enough for the chip to be happy */
467 /* Disable transmit and receive functionality */
468 SMC_outw (RCR_CLEAR, RCR_REG);
469 SMC_outw (TCR_CLEAR, TCR_REG);
471 /* set the control register */
473 SMC_outw (CTL_DEFAULT, CTL_REG);
477 smc_wait_mmu_release_complete ();
478 SMC_outw (MC_RESET, MMU_CMD_REG);
479 while (SMC_inw (MMU_CMD_REG) & MC_BUSY)
480 udelay (1); /* Wait until not busy */
482 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
483 but this is a place where future chipsets _COULD_ break. Be wary
484 of issuing another MMU command right after this */
486 /* Disable all interrupts */
487 SMC_outb (0, IM_REG);
491 . Function: smc_enable
492 . Purpose: let the chip talk to the outside work
494 . 1. Enable the transmitter
495 . 2. Enable the receiver
496 . 3. Enable interrupts
498 static void smc_enable()
500 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
501 SMC_SELECT_BANK( 0 );
502 /* see the header file for options in TCR/RCR DEFAULT*/
503 SMC_outw( TCR_DEFAULT, TCR_REG );
504 SMC_outw( RCR_DEFAULT, RCR_REG );
507 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
511 . Function: smc_shutdown
512 . Purpose: closes down the SMC91xxx chip.
514 . 1. zero the interrupt mask
515 . 2. clear the enable receive flag
516 . 3. clear the enable xmit flags
519 . (1) maybe utilize power down mode.
520 . Why not yet? Because while the chip will go into power down mode,
521 . the manual says that it will wake up in response to any I/O requests
522 . in the register space. Empirical results do not show this working.
524 static void smc_shutdown()
526 PRINTK2(CARDNAME ": smc_shutdown\n");
528 /* no more interrupts for me */
529 SMC_SELECT_BANK( 2 );
530 SMC_outb( 0, IM_REG );
532 /* and tell the card to stay away from that nasty outside world */
533 SMC_SELECT_BANK( 0 );
534 SMC_outb( RCR_CLEAR, RCR_REG );
535 SMC_outb( TCR_CLEAR, TCR_REG );
540 . Function: smc_hardware_send_packet(struct net_device * )
542 . This sends the actual packet to the SMC9xxx chip.
545 . First, see if a saved_skb is available.
546 . ( this should NOT be called if there is no 'saved_skb'
547 . Now, find the packet number that the chip allocated
548 . Point the data pointers at it in memory
549 . Set the length word in the chip's memory
550 . Dump the packet to chip memory
551 . Check if a last byte is needed ( odd length packet )
552 . if so, set the control flag right
553 . Tell the card to send it
554 . Enable the transmit interrupt, so I know if it failed
555 . Free the kernel data if I actually sent it.
557 static int smc_send_packet (volatile void *packet, int packet_length)
560 unsigned long ioaddr;
570 /* save PTR and PNR registers before manipulation */
572 saved_pnr = SMC_inb( PN_REG );
573 saved_ptr = SMC_inw( PTR_REG );
575 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
577 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
580 ** The MMU wants the number of pages to be the number of 256 bytes
581 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
583 ** The 91C111 ignores the size bits, but the code is left intact
584 ** for backwards and future compatibility.
586 ** Pkt size for allocating is data length +6 (for additional status
587 ** words, length and ctl!)
589 ** If odd size then last byte is included in this header.
591 numPages = ((length & 0xfffe) + 6);
592 numPages >>= 8; /* Divide by 256 */
595 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
599 /* now, try to allocate the memory */
601 SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG);
603 /* FIXME: the ALLOC_INT bit never gets set *
604 * so the following will always give a *
605 * memory allocation error. *
606 * same code works in armboot though *
612 time_out = MEMORY_WAIT_TIME;
614 status = SMC_inb (SMC91111_INT_REG);
615 if (status & IM_ALLOC_INT) {
616 /* acknowledge the interrupt */
617 SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG);
620 } while (--time_out);
623 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
625 if (try < SMC_ALLOC_MAX_TRY)
631 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
634 /* I can send the packet now.. */
636 ioaddr = SMC_BASE_ADDRESS;
638 buf = (byte *) packet;
640 /* If I get here, I _know_ there is a packet slot waiting for me */
641 packet_no = SMC_inb (AR_REG);
642 if (packet_no & AR_FAILED) {
643 /* or isn't there? BAD CHIP! */
644 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
648 /* we have a packet address, so tell the card to use it */
649 #ifndef CONFIG_XAENIAX
650 SMC_outb (packet_no, PN_REG);
652 /* On Xaeniax board, we can't use SMC_outb here because that way
653 * the Allocate MMU command will end up written to the command register
654 * as well, which will lead to a problem.
656 SMC_outl (packet_no << 16, 0);
658 /* do not write new ptr value if Write data fifo not empty */
659 while ( saved_ptr & PTR_NOTEMPTY )
660 printf ("Write data fifo not empty!\n");
662 /* point to the beginning of the packet */
663 SMC_outw (PTR_AUTOINC, PTR_REG);
665 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
666 SMC_DEV_NAME, length);
669 printf ("Transmitting Packet\n");
670 print_packet (buf, length);
673 /* send the packet length ( +6 for status, length and ctl byte )
674 and the status word ( set to zeros ) */
676 SMC_outl ((length + 6) << 16, SMC91111_DATA_REG);
678 SMC_outw (0, SMC91111_DATA_REG);
679 /* send the packet length ( +6 for status words, length, and ctl */
680 SMC_outw ((length + 6), SMC91111_DATA_REG);
683 /* send the actual data
684 . I _think_ it's faster to send the longs first, and then
685 . mop up by sending the last word. It depends heavily
686 . on alignment, at least on the 486. Maybe it would be
687 . a good idea to check which is optimal? But that could take
688 . almost as much time as is saved?
691 SMC_outsl (SMC91111_DATA_REG, buf, length >> 2);
692 #ifndef CONFIG_XAENIAX
694 SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))),
697 /* On XANEIAX, we can only use 32-bit writes, so we need to handle
698 * unaligned tail part specially. The standard code doesn't work.
700 if ((length & 3) == 3) {
701 u16 * ptr = (u16*) &buf[length-3];
702 SMC_outl((*ptr) | ((0x2000 | buf[length-1]) << 16),
704 } else if ((length & 2) == 2) {
705 u16 * ptr = (u16*) &buf[length-2];
706 SMC_outl(*ptr, SMC91111_DATA_REG);
707 } else if (length & 1) {
708 SMC_outl((0x2000 | buf[length-1]), SMC91111_DATA_REG);
710 SMC_outl(0, SMC91111_DATA_REG);
714 SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1);
715 #endif /* USE_32_BIT */
717 #ifndef CONFIG_XAENIAX
718 /* Send the last byte, if there is one. */
719 if ((length & 1) == 0) {
720 SMC_outw (0, SMC91111_DATA_REG);
722 SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG);
726 /* and let the chipset deal with it */
727 SMC_outw (MC_ENQUEUE, MMU_CMD_REG);
729 /* poll for TX INT */
730 /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */
731 /* poll for TX_EMPTY INT - autorelease enabled */
732 if (poll4int(IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
734 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
737 /* no need to release, MMU does that now */
738 #ifdef CONFIG_XAENIAX
739 SMC_outw (MC_FREEPKT, MMU_CMD_REG);
742 /* wait for MMU getting ready (low) */
743 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
747 PRINTK2 ("MMU ready\n");
753 SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG);
754 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
755 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
759 /* no need to release, MMU does that now */
760 #ifdef CONFIG_XAENIAX
761 SMC_outw (MC_FREEPKT, MMU_CMD_REG);
764 /* wait for MMU getting ready (low) */
765 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
769 PRINTK2 ("MMU ready\n");
774 /* restore previously saved registers */
775 #ifndef CONFIG_XAENIAX
776 SMC_outb( saved_pnr, PN_REG );
778 /* On Xaeniax board, we can't use SMC_outb here because that way
779 * the Allocate MMU command will end up written to the command register
780 * as well, which will lead to a problem.
782 SMC_outl(saved_pnr << 16, 0);
784 SMC_outw( saved_ptr, PTR_REG );
789 /*-------------------------------------------------------------------------
791 | smc_destructor( struct net_device * dev )
793 | dev, pointer to the device structure
798 ---------------------------------------------------------------------------
800 void smc_destructor()
802 PRINTK2(CARDNAME ": smc_destructor\n");
807 * Open and Initialize the board
809 * Set up everything, reset the card, etc ..
812 static int smc_open (bd_t * bd)
816 PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME);
818 /* reset the hardware */
822 /* Configure the PHY */
823 #ifndef CONFIG_SMC91111_EXT_PHY
824 smc_phy_configure ();
827 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
828 /* SMC_SELECT_BANK(0); */
829 /* SMC_outw(0, RPC_REG); */
832 err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */
834 memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */
835 return (-1); /* upper code ignores this, but NOT bi_enetaddr */
838 for (i = 0; i < 6; i += 2) {
841 address = smc_mac_addr[i + 1] << 8;
842 address |= smc_mac_addr[i];
843 SMC_outw (address, (ADDR0_REG + i));
846 for (i = 0; i < 6; i++)
847 SMC_outb (smc_mac_addr[i], (ADDR0_REG + i));
853 /*-------------------------------------------------------------
855 . smc_rcv - receive a packet from the card
857 . There is ( at least ) a packet waiting to be read from
861 . o If an error, record it
862 . o otherwise, read in the packet
863 --------------------------------------------------------------
878 /* save PTR and PTR registers */
879 saved_pnr = SMC_inb( PN_REG );
880 saved_ptr = SMC_inw( PTR_REG );
882 packet_number = SMC_inw( RXFIFO_REG );
884 if ( packet_number & RXFIFO_REMPTY ) {
889 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
890 /* start reading from the start of the packet */
891 SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
893 /* First two words are status and packet_length */
895 stat_len = SMC_inl(SMC91111_DATA_REG);
896 status = stat_len & 0xffff;
897 packet_length = stat_len >> 16;
899 status = SMC_inw( SMC91111_DATA_REG );
900 packet_length = SMC_inw( SMC91111_DATA_REG );
903 packet_length &= 0x07ff; /* mask off top bits */
905 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
907 if ( !(status & RS_ERRORS ) ){
908 /* Adjust for having already read the first two words */
909 packet_length -= 4; /*4; */
912 /* set odd length for bug in LAN91C111, */
913 /* which never sets RS_ODDFRAME */
918 PRINTK3(" Reading %d dwords (and %d bytes) \n",
919 packet_length >> 2, packet_length & 3 );
920 /* QUESTION: Like in the TX routine, do I want
921 to send the DWORDs or the bytes first, or some
922 mixture. A mixture might improve already slow PIO
924 SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
925 /* read the left over bytes */
926 if (packet_length & 3) {
929 byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3));
930 dword leftover = SMC_inl(SMC91111_DATA_REG);
931 for (i=0; i<(packet_length & 3); i++)
932 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
935 PRINTK3(" Reading %d words and %d byte(s) \n",
936 (packet_length >> 1 ), packet_length & 1 );
937 SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
939 #endif /* USE_32_BIT */
942 printf("Receiving Packet\n");
943 print_packet( NetRxPackets[0], packet_length );
951 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
952 udelay(1); /* Wait until not busy */
954 /* error or good, tell the card to get rid of this packet */
955 SMC_outw( MC_RELEASE, MMU_CMD_REG );
957 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
958 udelay(1); /* Wait until not busy */
960 /* restore saved registers */
961 #ifndef CONFIG_XAENIAX
962 SMC_outb( saved_pnr, PN_REG );
964 /* On Xaeniax board, we can't use SMC_outb here because that way
965 * the Allocate MMU command will end up written to the command register
966 * as well, which will lead to a problem.
968 SMC_outl( saved_pnr << 16, 0);
970 SMC_outw( saved_ptr, PTR_REG );
973 /* Pass the packet up to the protocol layers. */
974 NetReceive(NetRxPackets[0], packet_length);
975 return packet_length;
983 /*----------------------------------------------------
986 . this makes the board clean up everything that it can
987 . and not talk to the outside world. Caused by
988 . an 'ifconfig ethX down'
990 -----------------------------------------------------*/
991 static int smc_close()
993 PRINTK2("%s: smc_close\n", SMC_DEV_NAME);
995 /* clear everything */
1003 /*------------------------------------------------------------
1004 . Modify a bit in the LAN91C111 register set
1005 .-------------------------------------------------------------*/
1006 static word smc_modify_regbit(int bank, int ioaddr, int reg,
1007 unsigned int bit, int val)
1011 SMC_SELECT_BANK( bank );
1013 regval = SMC_inw( reg );
1019 SMC_outw( regval, 0 );
1024 /*------------------------------------------------------------
1025 . Retrieve a bit in the LAN91C111 register set
1026 .-------------------------------------------------------------*/
1027 static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit)
1029 SMC_SELECT_BANK( bank );
1030 if ( SMC_inw( reg ) & bit)
1037 /*------------------------------------------------------------
1038 . Modify a LAN91C111 register (word access only)
1039 .-------------------------------------------------------------*/
1040 static void smc_modify_reg(int bank, int ioaddr, int reg, word val)
1042 SMC_SELECT_BANK( bank );
1043 SMC_outw( val, reg );
1047 /*------------------------------------------------------------
1048 . Retrieve a LAN91C111 register (word access only)
1049 .-------------------------------------------------------------*/
1050 static int smc_get_reg(int bank, int ioaddr, int reg)
1052 SMC_SELECT_BANK( bank );
1053 return(SMC_inw( reg ));
1058 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
1060 #if (SMC_DEBUG > 2 )
1062 /*------------------------------------------------------------
1063 . Debugging function for viewing MII Management serial bitstream
1064 .-------------------------------------------------------------*/
1065 static void smc_dump_mii_stream (byte * bits, int size)
1070 for (i = 0; i < size; ++i) {
1071 printf ("%d", i % 10);
1075 for (i = 0; i < size; ++i) {
1076 if (bits[i] & MII_MDOE)
1083 for (i = 0; i < size; ++i) {
1084 if (bits[i] & MII_MDO)
1091 for (i = 0; i < size; ++i) {
1092 if (bits[i] & MII_MDI)
1102 /*------------------------------------------------------------
1103 . Reads a register from the MII Management serial interface
1104 .-------------------------------------------------------------*/
1105 #ifndef CONFIG_SMC91111_EXT_PHY
1106 static word smc_read_phy_register (byte phyreg)
1116 byte phyaddr = SMC_PHY_ADDR;
1118 /* 32 consecutive ones on MDO to establish sync */
1119 for (i = 0; i < 32; ++i)
1120 bits[clk_idx++] = MII_MDOE | MII_MDO;
1122 /* Start code <01> */
1123 bits[clk_idx++] = MII_MDOE;
1124 bits[clk_idx++] = MII_MDOE | MII_MDO;
1126 /* Read command <10> */
1127 bits[clk_idx++] = MII_MDOE | MII_MDO;
1128 bits[clk_idx++] = MII_MDOE;
1130 /* Output the PHY address, msb first */
1132 for (i = 0; i < 5; ++i) {
1134 bits[clk_idx++] = MII_MDOE | MII_MDO;
1136 bits[clk_idx++] = MII_MDOE;
1138 /* Shift to next lowest bit */
1142 /* Output the phy register number, msb first */
1144 for (i = 0; i < 5; ++i) {
1146 bits[clk_idx++] = MII_MDOE | MII_MDO;
1148 bits[clk_idx++] = MII_MDOE;
1150 /* Shift to next lowest bit */
1154 /* Tristate and turnaround (2 bit times) */
1155 bits[clk_idx++] = 0;
1156 /*bits[clk_idx++] = 0; */
1158 /* Input starts at this bit time */
1159 input_idx = clk_idx;
1161 /* Will input 16 bits */
1162 for (i = 0; i < 16; ++i)
1163 bits[clk_idx++] = 0;
1165 /* Final clock bit */
1166 bits[clk_idx++] = 0;
1168 /* Save the current bank */
1169 oldBank = SMC_inw (BANK_SELECT);
1172 SMC_SELECT_BANK (3);
1174 /* Get the current MII register value */
1175 mii_reg = SMC_inw (MII_REG);
1177 /* Turn off all MII Interface bits */
1178 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
1180 /* Clock all 64 cycles */
1181 for (i = 0; i < sizeof bits; ++i) {
1182 /* Clock Low - output data */
1183 SMC_outw (mii_reg | bits[i], MII_REG);
1184 udelay (SMC_PHY_CLOCK_DELAY);
1187 /* Clock Hi - input data */
1188 SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
1189 udelay (SMC_PHY_CLOCK_DELAY);
1190 bits[i] |= SMC_inw (MII_REG) & MII_MDI;
1193 /* Return to idle state */
1194 /* Set clock to low, data to low, and output tristated */
1195 SMC_outw (mii_reg, MII_REG);
1196 udelay (SMC_PHY_CLOCK_DELAY);
1198 /* Restore original bank select */
1199 SMC_SELECT_BANK (oldBank);
1201 /* Recover input data */
1203 for (i = 0; i < 16; ++i) {
1206 if (bits[input_idx++] & MII_MDI)
1210 #if (SMC_DEBUG > 2 )
1211 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1212 phyaddr, phyreg, phydata);
1213 smc_dump_mii_stream (bits, sizeof bits);
1220 /*------------------------------------------------------------
1221 . Writes a register to the MII Management serial interface
1222 .-------------------------------------------------------------*/
1223 static void smc_write_phy_register (byte phyreg, word phydata)
1231 byte phyaddr = SMC_PHY_ADDR;
1233 /* 32 consecutive ones on MDO to establish sync */
1234 for (i = 0; i < 32; ++i)
1235 bits[clk_idx++] = MII_MDOE | MII_MDO;
1237 /* Start code <01> */
1238 bits[clk_idx++] = MII_MDOE;
1239 bits[clk_idx++] = MII_MDOE | MII_MDO;
1241 /* Write command <01> */
1242 bits[clk_idx++] = MII_MDOE;
1243 bits[clk_idx++] = MII_MDOE | MII_MDO;
1245 /* Output the PHY address, msb first */
1247 for (i = 0; i < 5; ++i) {
1249 bits[clk_idx++] = MII_MDOE | MII_MDO;
1251 bits[clk_idx++] = MII_MDOE;
1253 /* Shift to next lowest bit */
1257 /* Output the phy register number, msb first */
1259 for (i = 0; i < 5; ++i) {
1261 bits[clk_idx++] = MII_MDOE | MII_MDO;
1263 bits[clk_idx++] = MII_MDOE;
1265 /* Shift to next lowest bit */
1269 /* Tristate and turnaround (2 bit times) */
1270 bits[clk_idx++] = 0;
1271 bits[clk_idx++] = 0;
1273 /* Write out 16 bits of data, msb first */
1275 for (i = 0; i < 16; ++i) {
1277 bits[clk_idx++] = MII_MDOE | MII_MDO;
1279 bits[clk_idx++] = MII_MDOE;
1281 /* Shift to next lowest bit */
1285 /* Final clock bit (tristate) */
1286 bits[clk_idx++] = 0;
1288 /* Save the current bank */
1289 oldBank = SMC_inw (BANK_SELECT);
1292 SMC_SELECT_BANK (3);
1294 /* Get the current MII register value */
1295 mii_reg = SMC_inw (MII_REG);
1297 /* Turn off all MII Interface bits */
1298 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
1300 /* Clock all cycles */
1301 for (i = 0; i < sizeof bits; ++i) {
1302 /* Clock Low - output data */
1303 SMC_outw (mii_reg | bits[i], MII_REG);
1304 udelay (SMC_PHY_CLOCK_DELAY);
1307 /* Clock Hi - input data */
1308 SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
1309 udelay (SMC_PHY_CLOCK_DELAY);
1310 bits[i] |= SMC_inw (MII_REG) & MII_MDI;
1313 /* Return to idle state */
1314 /* Set clock to low, data to low, and output tristated */
1315 SMC_outw (mii_reg, MII_REG);
1316 udelay (SMC_PHY_CLOCK_DELAY);
1318 /* Restore original bank select */
1319 SMC_SELECT_BANK (oldBank);
1321 #if (SMC_DEBUG > 2 )
1322 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1323 phyaddr, phyreg, phydata);
1324 smc_dump_mii_stream (bits, sizeof bits);
1327 #endif /* !CONFIG_SMC91111_EXT_PHY */
1330 /*------------------------------------------------------------
1331 . Waits the specified number of milliseconds - kernel friendly
1332 .-------------------------------------------------------------*/
1333 #ifndef CONFIG_SMC91111_EXT_PHY
1334 static void smc_wait_ms(unsigned int ms)
1338 #endif /* !CONFIG_SMC91111_EXT_PHY */
1341 /*------------------------------------------------------------
1342 . Configures the specified PHY using Autonegotiation. Calls
1343 . smc_phy_fixed() if the user has requested a certain config.
1344 .-------------------------------------------------------------*/
1345 #ifndef CONFIG_SMC91111_EXT_PHY
1346 static void smc_phy_configure ()
1350 word my_phy_caps; /* My PHY capabilities */
1351 word my_ad_caps; /* My Advertised capabilities */
1352 word status = 0; /*;my status = 0 */
1355 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
1358 /* Get the detected phy address */
1359 phyaddr = SMC_PHY_ADDR;
1361 /* Reset the PHY, setting all other bits to zero */
1362 smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST);
1364 /* Wait for the reset to complete, or time out */
1365 timeout = 6; /* Wait up to 3 seconds */
1367 if (!(smc_read_phy_register (PHY_CNTL_REG)
1369 /* reset complete */
1373 smc_wait_ms (500); /* wait 500 millisecs */
1377 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
1378 goto smc_phy_configure_exit;
1381 /* Read PHY Register 18, Status Output */
1382 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1384 /* Enable PHY Interrupts (for register 18) */
1385 /* Interrupts listed here are disabled */
1386 smc_write_phy_register (PHY_MASK_REG, 0xffff);
1388 /* Configure the Receive/Phy Control register */
1389 SMC_SELECT_BANK (0);
1390 SMC_outw (RPC_DEFAULT, RPC_REG);
1392 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
1393 my_phy_caps = smc_read_phy_register (PHY_STAT_REG);
1394 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
1396 if (my_phy_caps & PHY_STAT_CAP_T4)
1397 my_ad_caps |= PHY_AD_T4;
1399 if (my_phy_caps & PHY_STAT_CAP_TXF)
1400 my_ad_caps |= PHY_AD_TX_FDX;
1402 if (my_phy_caps & PHY_STAT_CAP_TXH)
1403 my_ad_caps |= PHY_AD_TX_HDX;
1405 if (my_phy_caps & PHY_STAT_CAP_TF)
1406 my_ad_caps |= PHY_AD_10_FDX;
1408 if (my_phy_caps & PHY_STAT_CAP_TH)
1409 my_ad_caps |= PHY_AD_10_HDX;
1411 /* Update our Auto-Neg Advertisement Register */
1412 smc_write_phy_register (PHY_AD_REG, my_ad_caps);
1414 /* Read the register back. Without this, it appears that when */
1415 /* auto-negotiation is restarted, sometimes it isn't ready and */
1416 /* the link does not come up. */
1417 smc_read_phy_register(PHY_AD_REG);
1419 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1420 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
1422 /* Restart auto-negotiation process in order to advertise my caps */
1423 smc_write_phy_register (PHY_CNTL_REG,
1424 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
1426 /* Wait for the auto-negotiation to complete. This may take from */
1427 /* 2 to 3 seconds. */
1428 /* Wait for the reset to complete, or time out */
1429 timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
1432 status = smc_read_phy_register (PHY_STAT_REG);
1433 if (status & PHY_STAT_ANEG_ACK) {
1434 /* auto-negotiate complete */
1438 smc_wait_ms (500); /* wait 500 millisecs */
1440 /* Restart auto-negotiation if remote fault */
1441 if (status & PHY_STAT_REM_FLT) {
1442 printf ("%s: PHY remote fault detected\n",
1445 /* Restart auto-negotiation */
1446 printf ("%s: PHY restarting auto-negotiation\n",
1448 smc_write_phy_register (PHY_CNTL_REG,
1457 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
1461 /* Fail if we detected an auto-negotiate remote fault */
1462 if (status & PHY_STAT_REM_FLT) {
1463 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
1467 /* Re-Configure the Receive/Phy Control register */
1468 SMC_outw (RPC_DEFAULT, RPC_REG);
1470 smc_phy_configure_exit: ;
1473 #endif /* !CONFIG_SMC91111_EXT_PHY */
1477 static void print_packet( byte * buf, int length )
1483 printf("Packet of length %d \n", length );
1486 lines = length / 16;
1487 remainder = length % 16;
1489 for ( i = 0; i < lines ; i ++ ) {
1492 for ( cur = 0; cur < 8; cur ++ ) {
1497 printf("%02x%02x ", a, b );
1501 for ( i = 0; i < remainder/2 ; i++ ) {
1506 printf("%02x%02x ", a, b );
1513 int eth_init(bd_t *bd) {
1514 return (smc_open(bd));
1525 int eth_send(volatile void *packet, int length) {
1526 return smc_send_packet(packet, length);
1529 int smc_get_ethaddr (bd_t * bd)
1531 int env_size, rom_valid, env_present = 0, reg;
1532 char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66";
1534 uchar v_env_mac[6], v_rom_mac[6];
1536 env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac));
1537 if ((env_size > 0) && (env_size < sizeof (es))) { /* exit if env is bad */
1538 printf ("\n*** ERROR: ethaddr is not set properly!!\n");
1547 for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */
1548 v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0;
1550 s = (*e) ? e + 1 : e;
1553 rom_valid = get_rom_mac (v_rom_mac); /* get ROM mac value if any */
1555 if (!env_present) { /* if NO env */
1556 if (rom_valid) { /* but ROM is valid */
1557 v_mac = (char *)v_rom_mac;
1558 sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
1559 v_mac[0], v_mac[1], v_mac[2], v_mac[3],
1560 v_mac[4], v_mac[5]);
1561 setenv ("ethaddr", s_env_mac);
1562 } else { /* no env, bad ROM */
1563 printf ("\n*** ERROR: ethaddr is NOT set !!\n");
1566 } else { /* good env, don't care ROM */
1567 v_mac = (char *)v_env_mac; /* always use a good env over a ROM */
1570 if (env_present && rom_valid) { /* if both env and ROM are good */
1571 if (memcmp (v_env_mac, v_rom_mac, 6) != 0) {
1572 printf ("\nWarning: MAC addresses don't match:\n");
1573 printf ("\tHW MAC address: "
1574 "%02X:%02X:%02X:%02X:%02X:%02X\n",
1575 v_rom_mac[0], v_rom_mac[1],
1576 v_rom_mac[2], v_rom_mac[3],
1577 v_rom_mac[4], v_rom_mac[5] );
1578 printf ("\t\"ethaddr\" value: "
1579 "%02X:%02X:%02X:%02X:%02X:%02X\n",
1580 v_env_mac[0], v_env_mac[1],
1581 v_env_mac[2], v_env_mac[3],
1582 v_env_mac[4], v_env_mac[5]) ;
1583 debug ("### Set MAC addr from environment\n");
1586 memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */
1587 smc_set_mac_addr ((uchar *)v_mac); /* use old function to update smc default */
1588 PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1],
1589 v_mac[2], v_mac[3], v_mac[4], v_mac[5]);
1593 int get_rom_mac (uchar *v_rom_mac)
1595 #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
1596 char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
1598 memcpy (v_rom_mac, hw_mac_addr, 6);
1604 SMC_SELECT_BANK (1);
1607 v_rom_mac[i] = SMC_inb ((ADDR0_REG + i));
1608 valid_mac |= v_rom_mac[i];
1611 return (valid_mac ? 1 : 0);
1614 #endif /* CONFIG_DRIVER_SMC91111 */