drivers/spi/fsl_qspi.c

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * Freescale Quad Serial Peripheral Interface (QSPI) driver
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <spi.h>
  12 #include <asm/io.h>
  13 #include <linux/sizes.h>
  14 #include "fsl_qspi.h"
  15
  16 #define RX_BUFFER_SIZE          0x80
  17 #define TX_BUFFER_SIZE          0x40
  18
  19 #define OFFSET_BITS_MASK        0x00ffffff
  20
  21 #define FLASH_STATUS_WEL        0x02
  22
  23 /* SEQID */
  24 #define SEQID_WREN              1
  25 #define SEQID_FAST_READ         2
  26 #define SEQID_RDSR              3
  27 #define SEQID_SE                4
  28 #define SEQID_CHIP_ERASE        5
  29 #define SEQID_PP                6
  30 #define SEQID_RDID              7
  31
  32 /* Flash opcodes */
  33 #define OPCODE_PP               0x02    /* Page program (up to 256 bytes) */
  34 #define OPCODE_RDSR             0x05    /* Read status register */
  35 #define OPCODE_WREN             0x06    /* Write enable */
  36 #define OPCODE_FAST_READ        0x0b    /* Read data bytes (high frequency) */
  37 #define OPCODE_CHIP_ERASE       0xc7    /* Erase whole flash chip */
  38 #define OPCODE_SE               0xd8    /* Sector erase (usually 64KiB) */
  39 #define OPCODE_RDID             0x9f    /* Read JEDEC ID */
  40
  41 /* 4-byte address opcodes - used on Spansion and some Macronix flashes */
  42 #define OPCODE_FAST_READ_4B     0x0c    /* Read data bytes (high frequency) */
  43 #define OPCODE_PP_4B            0x12    /* Page program (up to 256 bytes) */
  44 #define OPCODE_SE_4B            0xdc    /* Sector erase (usually 64KiB) */
  45
  46 #ifdef CONFIG_SYS_FSL_QSPI_LE
  47 #define qspi_read32             in_le32
  48 #define qspi_write32            out_le32
  49 #elif defined(CONFIG_SYS_FSL_QSPI_BE)
  50 #define qspi_read32             in_be32
  51 #define qspi_write32            out_be32
  52 #endif
  53
  54 static unsigned long spi_bases[] = {
  55         QSPI0_BASE_ADDR,
  56 };
  57
  58 static unsigned long amba_bases[] = {
  59         QSPI0_AMBA_BASE,
  60 };
  61
  62 struct fsl_qspi {
  63         struct spi_slave slave;
  64         unsigned long reg_base;
  65         unsigned long amba_base;
  66         u32 sf_addr;
  67         u8 cur_seqid;
  68 };
  69
  70 /* QSPI support swapping the flash read/write data
  71  * in hardware for LS102xA, but not for VF610 */
  72 static inline u32 qspi_endian_xchg(u32 data)
  73 {
  74 #ifdef CONFIG_VF610
  75         return swab32(data);
  76 #else
  77         return data;
  78 #endif
  79 }
  80
  81 static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
  82 {
  83         return container_of(slave, struct fsl_qspi, slave);
  84 }
  85
  86 static void qspi_set_lut(struct fsl_qspi *qspi)
  87 {
  88         struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
  89         u32 lut_base;
  90
  91         /* Unlock the LUT */
  92         qspi_write32(&regs->lutkey, LUT_KEY_VALUE);
  93         qspi_write32(&regs->lckcr, QSPI_LCKCR_UNLOCK);
  94
  95         /* Write Enable */
  96         lut_base = SEQID_WREN * 4;
  97         qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_WREN) |
  98                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
  99         qspi_write32(&regs->lut[lut_base + 1], 0);
 100         qspi_write32(&regs->lut[lut_base + 2], 0);
 101         qspi_write32(&regs->lut[lut_base + 3], 0);
 102
 103         /* Fast Read */
 104         lut_base = SEQID_FAST_READ * 4;
 105         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 106                 qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_FAST_READ) |
 107                         PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 108                         PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 109         else
 110                 qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_FAST_READ_4B) |
 111                         PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 112                         PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 113         qspi_write32(&regs->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) |
 114                 INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
 115                 INSTR1(LUT_READ));
 116         qspi_write32(&regs->lut[lut_base + 2], 0);
 117         qspi_write32(&regs->lut[lut_base + 3], 0);
 118
 119         /* Read Status */
 120         lut_base = SEQID_RDSR * 4;
 121         qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_RDSR) |
 122                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 123                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 124         qspi_write32(&regs->lut[lut_base + 1], 0);
 125         qspi_write32(&regs->lut[lut_base + 2], 0);
 126         qspi_write32(&regs->lut[lut_base + 3], 0);
 127
 128         /* Erase a sector */
 129         lut_base = SEQID_SE * 4;
 130         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 131                 qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_SE) |
 132                         PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 133                         PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 134         else
 135                 qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_SE_4B) |
 136                         PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 137                         PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 138         qspi_write32(&regs->lut[lut_base + 1], 0);
 139         qspi_write32(&regs->lut[lut_base + 2], 0);
 140         qspi_write32(&regs->lut[lut_base + 3], 0);
 141
 142         /* Erase the whole chip */
 143         lut_base = SEQID_CHIP_ERASE * 4;
 144         qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_CHIP_ERASE) |
 145                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 146         qspi_write32(&regs->lut[lut_base + 1], 0);
 147         qspi_write32(&regs->lut[lut_base + 2], 0);
 148         qspi_write32(&regs->lut[lut_base + 3], 0);
 149
 150         /* Page Program */
 151         lut_base = SEQID_PP * 4;
 152         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 153                 qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_PP) |
 154                         PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 155                         PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 156         else
 157                 qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_PP_4B) |
 158                         PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 159                         PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 160         qspi_write32(&regs->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
 161                 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 162         qspi_write32(&regs->lut[lut_base + 2], 0);
 163         qspi_write32(&regs->lut[lut_base + 3], 0);
 164
 165         /* READ ID */
 166         lut_base = SEQID_RDID * 4;
 167         qspi_write32(&regs->lut[lut_base], OPRND0(OPCODE_RDID) |
 168                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
 169                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 170         qspi_write32(&regs->lut[lut_base + 1], 0);
 171         qspi_write32(&regs->lut[lut_base + 2], 0);
 172         qspi_write32(&regs->lut[lut_base + 3], 0);
 173
 174         /* Lock the LUT */
 175         qspi_write32(&regs->lutkey, LUT_KEY_VALUE);
 176         qspi_write32(&regs->lckcr, QSPI_LCKCR_LOCK);
 177 }
 178
 179 void spi_init()
 180 {
 181         /* do nothing */
 182 }
 183
 184 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 185                 unsigned int max_hz, unsigned int mode)
 186 {
 187         struct fsl_qspi *qspi;
 188         struct fsl_qspi_regs *regs;
 189         u32 reg_val, smpr_val;
 190         u32 total_size, seq_id;
 191
 192         if (bus >= ARRAY_SIZE(spi_bases))
 193                 return NULL;
 194
 195         qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
 196         if (!qspi)
 197                 return NULL;
 198
 199         qspi->reg_base = spi_bases[bus];
 200         qspi->amba_base = amba_bases[bus];
 201
 202         qspi->slave.max_write_size = TX_BUFFER_SIZE;
 203
 204         regs = (struct fsl_qspi_regs *)qspi->reg_base;
 205         qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
 206
 207         smpr_val = qspi_read32(&regs->smpr);
 208         qspi_write32(&regs->smpr, smpr_val & ~(QSPI_SMPR_FSDLY_MASK |
 209                 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK));
 210         qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK);
 211
 212         total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
 213         qspi_write32(&regs->sfa1ad, FSL_QSPI_FLASH_SIZE | qspi->amba_base);
 214         qspi_write32(&regs->sfa2ad, FSL_QSPI_FLASH_SIZE | qspi->amba_base);
 215         qspi_write32(&regs->sfb1ad, total_size | qspi->amba_base);
 216         qspi_write32(&regs->sfb2ad, total_size | qspi->amba_base);
 217
 218         qspi_set_lut(qspi);
 219
 220         smpr_val = qspi_read32(&regs->smpr);
 221         smpr_val &= ~QSPI_SMPR_DDRSMP_MASK;
 222         qspi_write32(&regs->smpr, smpr_val);
 223         qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK);
 224
 225         seq_id = 0;
 226         reg_val = qspi_read32(&regs->bfgencr);
 227         reg_val &= ~QSPI_BFGENCR_SEQID_MASK;
 228         reg_val |= (seq_id << QSPI_BFGENCR_SEQID_SHIFT);
 229         reg_val &= ~QSPI_BFGENCR_PAR_EN_MASK;
 230         qspi_write32(&regs->bfgencr, reg_val);
 231
 232         return &qspi->slave;
 233 }
 234
 235 void spi_free_slave(struct spi_slave *slave)
 236 {
 237         struct fsl_qspi *qspi = to_qspi_spi(slave);
 238
 239         free(qspi);
 240 }
 241
 242 int spi_claim_bus(struct spi_slave *slave)
 243 {
 244         return 0;
 245 }
 246
 247 static void qspi_op_rdid(struct fsl_qspi *qspi, u32 *rxbuf, u32 len)
 248 {
 249         struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
 250         u32 mcr_reg, rbsr_reg, data;
 251         int i, size;
 252
 253         mcr_reg = qspi_read32(&regs->mcr);
 254         qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 255                 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 256         qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 257
 258         qspi_write32(&regs->sfar, qspi->amba_base);
 259
 260         qspi_write32(&regs->ipcr, (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
 261         while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK)
 262                 ;
 263
 264         i = 0;
 265         size = len;
 266         while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
 267                 rbsr_reg = qspi_read32(&regs->rbsr);
 268                 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
 269                         data = qspi_read32(&regs->rbdr[i]);
 270                         data = qspi_endian_xchg(data);
 271                         memcpy(rxbuf, &data, 4);
 272                         rxbuf++;
 273                         size -= 4;
 274                         i++;
 275                 }
 276         }
 277
 278         qspi_write32(&regs->mcr, mcr_reg);
 279 }
 280
 281 static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, u32 len)
 282 {
 283         struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
 284         u32 mcr_reg, data;
 285         int i, size;
 286         u32 to_or_from;
 287
 288         mcr_reg = qspi_read32(&regs->mcr);
 289         qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 290                 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 291         qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 292
 293         to_or_from = qspi->sf_addr + qspi->amba_base;
 294
 295         while (len > 0) {
 296                 qspi_write32(&regs->sfar, to_or_from);
 297
 298                 size = (len > RX_BUFFER_SIZE) ?
 299                         RX_BUFFER_SIZE : len;
 300
 301                 qspi_write32(&regs->ipcr,
 302                         (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) | size);
 303                 while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK)
 304                         ;
 305
 306                 to_or_from += size;
 307                 len -= size;
 308
 309                 i = 0;
 310                 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
 311                         data = qspi_read32(&regs->rbdr[i]);
 312                         data = qspi_endian_xchg(data);
 313                         memcpy(rxbuf, &data, 4);
 314                         rxbuf++;
 315                         size -= 4;
 316                         i++;
 317                 }
 318                 qspi_write32(&regs->mcr, qspi_read32(&regs->mcr) |
 319                         QSPI_MCR_CLR_RXF_MASK);
 320         }
 321
 322         qspi_write32(&regs->mcr, mcr_reg);
 323 }
 324
 325 static void qspi_op_pp(struct fsl_qspi *qspi, u32 *txbuf, u32 len)
 326 {
 327         struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
 328         u32 mcr_reg, data, reg, status_reg;
 329         int i, size, tx_size;
 330         u32 to_or_from = 0;
 331
 332         mcr_reg = qspi_read32(&regs->mcr);
 333         qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 334                 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 335         qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 336
 337         status_reg = 0;
 338         while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
 339                 qspi_write32(&regs->ipcr,
 340                         (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 341                 while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK)
 342                         ;
 343
 344                 qspi_write32(&regs->ipcr,
 345                         (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
 346                 while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK)
 347                         ;
 348
 349                 reg = qspi_read32(&regs->rbsr);
 350                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 351                         status_reg = qspi_read32(&regs->rbdr[0]);
 352                         status_reg = qspi_endian_xchg(status_reg);
 353                 }
 354                 qspi_write32(&regs->mcr,
 355                         qspi_read32(&regs->mcr) | QSPI_MCR_CLR_RXF_MASK);
 356         }
 357
 358         to_or_from = qspi->sf_addr + qspi->amba_base;
 359         qspi_write32(&regs->sfar, to_or_from);
 360
 361         tx_size = (len > TX_BUFFER_SIZE) ?
 362                 TX_BUFFER_SIZE : len;
 363
 364         size = (tx_size + 3) / 4;
 365
 366         for (i = 0; i < size; i++) {
 367                 data = qspi_endian_xchg(*txbuf);
 368                 qspi_write32(&regs->tbdr, data);
 369                 txbuf++;
 370         }
 371
 372         qspi_write32(&regs->ipcr,
 373                 (SEQID_PP << QSPI_IPCR_SEQID_SHIFT) | tx_size);
 374         while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK)
 375                 ;
 376
 377         qspi_write32(&regs->mcr, mcr_reg);
 378 }
 379
 380 static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf)
 381 {
 382         struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
 383         u32 mcr_reg, reg, data;
 384
 385         mcr_reg = qspi_read32(&regs->mcr);
 386         qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 387                 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 388         qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 389
 390         qspi_write32(&regs->sfar, qspi->amba_base);
 391
 392         qspi_write32(&regs->ipcr,
 393                 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
 394         while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK)
 395                 ;
 396
 397         while (1) {
 398                 reg = qspi_read32(&regs->rbsr);
 399                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 400                         data = qspi_read32(&regs->rbdr[0]);
 401                         data = qspi_endian_xchg(data);
 402                         memcpy(rxbuf, &data, 4);
 403                         qspi_write32(&regs->mcr, qspi_read32(&regs->mcr) |
 404                                 QSPI_MCR_CLR_RXF_MASK);
 405                         break;
 406                 }
 407         }
 408
 409         qspi_write32(&regs->mcr, mcr_reg);
 410 }
 411
 412 static void qspi_op_se(struct fsl_qspi *qspi)
 413 {
 414         struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
 415         u32 mcr_reg;
 416         u32 to_or_from = 0;
 417
 418         mcr_reg = qspi_read32(&regs->mcr);
 419         qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 420                 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 421         qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 422
 423         to_or_from = qspi->sf_addr + qspi->amba_base;
 424         qspi_write32(&regs->sfar, to_or_from);
 425
 426         qspi_write32(&regs->ipcr,
 427                 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 428         while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK)
 429                 ;
 430
 431         qspi_write32(&regs->ipcr,
 432                 (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
 433         while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK)
 434                 ;
 435
 436         qspi_write32(&regs->mcr, mcr_reg);
 437 }
 438
 439 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 440                 const void *dout, void *din, unsigned long flags)
 441 {
 442         struct fsl_qspi *qspi = to_qspi_spi(slave);
 443         u32 bytes = DIV_ROUND_UP(bitlen, 8);
 444         static u32 pp_sfaddr;
 445         u32 txbuf;
 446
 447         if (dout) {
 448                 memcpy(&txbuf, dout, 4);
 449                 qspi->cur_seqid = *(u8 *)dout;
 450
 451                 if (flags == SPI_XFER_END) {
 452                         qspi->sf_addr = pp_sfaddr;
 453                         qspi_op_pp(qspi, (u32 *)dout, bytes);
 454                         return 0;
 455                 }
 456
 457                 if (qspi->cur_seqid == OPCODE_FAST_READ) {
 458                         qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 459                 } else if (qspi->cur_seqid == OPCODE_SE) {
 460                         qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 461                         qspi_op_se(qspi);
 462                 } else if (qspi->cur_seqid == OPCODE_PP) {
 463                         pp_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
 464                 }
 465         }
 466
 467         if (din) {
 468                 if (qspi->cur_seqid == OPCODE_FAST_READ)
 469                         qspi_op_read(qspi, din, bytes);
 470                 else if (qspi->cur_seqid == OPCODE_RDID)
 471                         qspi_op_rdid(qspi, din, bytes);
 472                 else if (qspi->cur_seqid == OPCODE_RDSR)
 473                         qspi_op_rdsr(qspi, din);
 474         }
 475
 476         return 0;
 477 }
 478
 479 void spi_release_bus(struct spi_slave *slave)
 480 {
 481         /* Nothing to do */
 482 }