drivers/tsi108_pci.c

   1 /*
   2  * (C) Copyright 2004 Tundra Semiconductor Corp.
   3  * Alex Bounine <alexandreb@tundra.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * PCI initialisation for the Tsi108 EMU board.
  26  */
  27
  28 #include <config.h>
  29
  30 #ifdef CONFIG_TSI108_PCI
  31
  32 #include <common.h>
  33 #include <pci.h>
  34 #include <asm/io.h>
  35 #include <tsi108.h>
  36
  37 struct pci_controller local_hose;
  38
  39 void tsi108_clear_pci_error(void)
  40 {
  41         u32 err_stat, err_addr, pci_stat;
  42
  43         /*
  44          * Quietly clear errors signalled as result of PCI/X configuration read
  45          * requests.
  46          */
  47         /* Read PB Error Log Registers */
  48         err_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE +
  49                                      TSI108_PB_REG_OFFSET + PB_ERRCS);
  50         err_addr = *(volatile u32 *)(CFG_TSI108_CSR_BASE +
  51                                      TSI108_PB_REG_OFFSET + PB_AERR);
  52         if (err_stat & PB_ERRCS_ES) {
  53                 /* Clear PCI/X bus errors if applicable */
  54                 if ((err_addr & 0xFF000000) == CFG_PCI_CFG_BASE) {
  55                         /* Clear error flag */
  56                         *(u32 *) (CFG_TSI108_CSR_BASE +
  57                                   TSI108_PB_REG_OFFSET + PB_ERRCS) =
  58                             PB_ERRCS_ES;
  59
  60                         /* Clear read error reported in PB_ISR */
  61                         *(u32 *) (CFG_TSI108_CSR_BASE +
  62                                   TSI108_PB_REG_OFFSET + PB_ISR) =
  63                             PB_ISR_PBS_RD_ERR;
  64
  65                 /* Clear errors reported by PCI CSR (Normally Master Abort) */
  66                         pci_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE +
  67                                                      TSI108_PCI_REG_OFFSET +
  68                                                      PCI_CSR);
  69                         *(volatile u32 *)(CFG_TSI108_CSR_BASE +
  70                                           TSI108_PCI_REG_OFFSET + PCI_CSR) =
  71                             pci_stat;
  72
  73                         *(volatile u32 *)(CFG_TSI108_CSR_BASE +
  74                                           TSI108_PCI_REG_OFFSET +
  75                                           PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR;
  76                 }
  77         }
  78
  79         return;
  80 }
  81
  82 unsigned int __get_pci_config_dword(u32 addr)
  83 {
  84         unsigned int retval;
  85
  86         __asm__ __volatile__("       lwbrx %0,0,%1\n"
  87                              "1:     eieio\n"
  88                              "2:\n"
  89                              ".section .fixup,\"ax\"\n"
  90                              "3:     li %0,-1\n"
  91                              "       b 2b\n"
  92                              ".section __ex_table,\"a\"\n"
  93                              "       .align 2\n"
  94                              "       .long 1b,3b\n"
  95                              ".text":"=r"(retval):"r"(addr));
  96
  97         return (retval);
  98 }
  99
 100 static int tsi108_read_config_dword(struct pci_controller *hose,
 101                                     pci_dev_t dev, int offset, u32 * value)
 102 {
 103         dev &= (CFG_PCI_CFG_SIZE - 1);
 104         dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc));
 105         *value = __get_pci_config_dword(dev);
 106         if (0xFFFFFFFF == *value)
 107                 tsi108_clear_pci_error();
 108         return 0;
 109 }
 110
 111 static int tsi108_write_config_dword(struct pci_controller *hose,
 112                                      pci_dev_t dev, int offset, u32 value)
 113 {
 114         dev &= (CFG_PCI_CFG_SIZE - 1);
 115         dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc));
 116
 117         out_le32((volatile unsigned *)dev, value);
 118
 119         return 0;
 120 }
 121
 122 void pci_init_board(void)
 123 {
 124         struct pci_controller *hose = (struct pci_controller *)&local_hose;
 125
 126         hose->first_busno = 0;
 127         hose->last_busno = 0xff;
 128
 129         pci_set_region(hose->regions + 0,
 130                        CFG_PCI_MEMORY_BUS,
 131                        CFG_PCI_MEMORY_PHYS,
 132                        CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY);
 133
 134         /* PCI memory space */
 135         pci_set_region(hose->regions + 1,
 136                        CFG_PCI_MEM_BUS,
 137                        CFG_PCI_MEM_PHYS, CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
 138
 139         /* PCI I/O space */
 140         pci_set_region(hose->regions + 2,
 141                        CFG_PCI_IO_BUS,
 142                        CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
 143
 144         hose->region_count = 3;
 145
 146         pci_set_ops(hose,
 147                     pci_hose_read_config_byte_via_dword,
 148                     pci_hose_read_config_word_via_dword,
 149                     tsi108_read_config_dword,
 150                     pci_hose_write_config_byte_via_dword,
 151                     pci_hose_write_config_word_via_dword,
 152                     tsi108_write_config_dword);
 153
 154         pci_register_hose(hose);
 155
 156         hose->last_busno = pci_hose_scan(hose);
 157
 158         debug("Done PCI initialization\n");
 159         return;
 160 }
 161
 162 #ifdef CONFIG_OF_FLAT_TREE
 163 void
 164 ft_pci_setup(void *blob, bd_t *bd)
 165 {
 166         u32 *p;
 167         int len;
 168
 169         p = (u32 *)ft_get_prop(blob, "/" OF_TSI "/pci@1000/bus-range", &len);
 170         if (p != NULL) {
 171                 p[0] = local_hose.first_busno;
 172                 p[1] = local_hose.last_busno;
 173         }
 174
 175 }
 176 #endif
 177
 178 #endif  /* CONFIG_TSI108_PCI */