drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
  10  * to uboot.
  11  *
  12  * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0
  15  */
  16
  17 #include <common.h>
  18 #include <malloc.h>
  19 #include <asm/dma-mapping.h>
  20 #include <usb/lin_gadget_compat.h>
  21 #include <linux/list.h>
  22
  23 #include <linux/usb/ch9.h>
  24 #include <linux/usb/gadget.h>
  25 #include <asm/arch/sys_proto.h>
  26
  27 #include "core.h"
  28 #include "gadget.h"
  29 #include "io.h"
  30
  31 #include "linux-compat.h"
  32
  33 /**
  34  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  35  * @dwc: pointer to our context structure
  36  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  37  *
  38  * Caller should take care of locking. This function will
  39  * return 0 on success or -EINVAL if wrong Test Selector
  40  * is passed
  41  */
  42 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  43 {
  44         u32             reg;
  45
  46         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  47         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  48
  49         switch (mode) {
  50         case TEST_J:
  51         case TEST_K:
  52         case TEST_SE0_NAK:
  53         case TEST_PACKET:
  54         case TEST_FORCE_EN:
  55                 reg |= mode << 1;
  56                 break;
  57         default:
  58                 return -EINVAL;
  59         }
  60
  61         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  62
  63         return 0;
  64 }
  65
  66 /**
  67  * dwc3_gadget_get_link_state - Gets current state of USB Link
  68  * @dwc: pointer to our context structure
  69  *
  70  * Caller should take care of locking. This function will
  71  * return the link state on success (>= 0) or -ETIMEDOUT.
  72  */
  73 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  74 {
  75         u32             reg;
  76
  77         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  78
  79         return DWC3_DSTS_USBLNKST(reg);
  80 }
  81
  82 /**
  83  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  84  * @dwc: pointer to our context structure
  85  * @state: the state to put link into
  86  *
  87  * Caller should take care of locking. This function will
  88  * return 0 on success or -ETIMEDOUT.
  89  */
  90 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  91 {
  92         int             retries = 10000;
  93         u32             reg;
  94
  95         /*
  96          * Wait until device controller is ready. Only applies to 1.94a and
  97          * later RTL.
  98          */
  99         if (dwc->revision >= DWC3_REVISION_194A) {
 100                 while (--retries) {
 101                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 102                         if (reg & DWC3_DSTS_DCNRD)
 103                                 udelay(5);
 104                         else
 105                                 break;
 106                 }
 107
 108                 if (retries <= 0)
 109                         return -ETIMEDOUT;
 110         }
 111
 112         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 113         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 114
 115         /* set requested state */
 116         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 117         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 118
 119         /*
 120          * The following code is racy when called from dwc3_gadget_wakeup,
 121          * and is not needed, at least on newer versions
 122          */
 123         if (dwc->revision >= DWC3_REVISION_194A)
 124                 return 0;
 125
 126         /* wait for a change in DSTS */
 127         retries = 10000;
 128         while (--retries) {
 129                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 130
 131                 if (DWC3_DSTS_USBLNKST(reg) == state)
 132                         return 0;
 133
 134                 udelay(5);
 135         }
 136
 137         dev_vdbg(dwc->dev, "link state change request timed out\n");
 138
 139         return -ETIMEDOUT;
 140 }
 141
 142 /**
 143  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 144  * @dwc: pointer to our context structure
 145  *
 146  * This function will a best effort FIFO allocation in order
 147  * to improve FIFO usage and throughput, while still allowing
 148  * us to enable as many endpoints as possible.
 149  *
 150  * Keep in mind that this operation will be highly dependent
 151  * on the configured size for RAM1 - which contains TxFifo -,
 152  * the amount of endpoints enabled on coreConsultant tool, and
 153  * the width of the Master Bus.
 154  *
 155  * In the ideal world, we would always be able to satisfy the
 156  * following equation:
 157  *
 158  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 159  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 160  *
 161  * Unfortunately, due to many variables that's not always the case.
 162  */
 163 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 164 {
 165         int             last_fifo_depth = 0;
 166         int             fifo_size;
 167         int             mdwidth;
 168         int             num;
 169
 170         if (!dwc->needs_fifo_resize)
 171                 return 0;
 172
 173         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 174
 175         /* MDWIDTH is represented in bits, we need it in bytes */
 176         mdwidth >>= 3;
 177
 178         /*
 179          * FIXME For now we will only allocate 1 wMaxPacketSize space
 180          * for each enabled endpoint, later patches will come to
 181          * improve this algorithm so that we better use the internal
 182          * FIFO space
 183          */
 184         for (num = 0; num < dwc->num_in_eps; num++) {
 185                 /* bit0 indicates direction; 1 means IN ep */
 186                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 187                 int             mult = 1;
 188                 int             tmp;
 189
 190                 if (!(dep->flags & DWC3_EP_ENABLED))
 191                         continue;
 192
 193                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 194                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 195                         mult = 3;
 196
 197                 /*
 198                  * REVISIT: the following assumes we will always have enough
 199                  * space available on the FIFO RAM for all possible use cases.
 200                  * Make sure that's true somehow and change FIFO allocation
 201                  * accordingly.
 202                  *
 203                  * If we have Bulk or Isochronous endpoints, we want
 204                  * them to be able to be very, very fast. So we're giving
 205                  * those endpoints a fifo_size which is enough for 3 full
 206                  * packets
 207                  */
 208                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 209                 tmp += mdwidth;
 210
 211                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 212
 213                 fifo_size |= (last_fifo_depth << 16);
 214
 215                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 216                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 217
 218                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 219
 220                 last_fifo_depth += (fifo_size & 0xffff);
 221         }
 222
 223         return 0;
 224 }
 225
 226 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 227                 int status)
 228 {
 229         struct dwc3                     *dwc = dep->dwc;
 230
 231         if (req->queued) {
 232                 dep->busy_slot++;
 233                 /*
 234                  * Skip LINK TRB. We can't use req->trb and check for
 235                  * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 236                  * just completed (not the LINK TRB).
 237                  */
 238                 if (((dep->busy_slot & DWC3_TRB_MASK) ==
 239                         DWC3_TRB_NUM- 1) &&
 240                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 241                         dep->busy_slot++;
 242                 req->queued = false;
 243         }
 244
 245         list_del(&req->list);
 246         req->trb = NULL;
 247         dwc3_flush_cache((int)req->request.dma, req->request.length);
 248
 249         if (req->request.status == -EINPROGRESS)
 250                 req->request.status = status;
 251
 252         if (dwc->ep0_bounced && dep->number == 0)
 253                 dwc->ep0_bounced = false;
 254         else
 255                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 256                                 req->direction);
 257
 258         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 259                         req, dep->name, req->request.actual,
 260                         req->request.length, status);
 261
 262         spin_unlock(&dwc->lock);
 263         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 264         spin_lock(&dwc->lock);
 265 }
 266
 267 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 268 {
 269         u32             timeout = 500;
 270         u32             reg;
 271
 272         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 273         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 274
 275         do {
 276                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 277                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 278                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 279                                         DWC3_DGCMD_STATUS(reg));
 280                         return 0;
 281                 }
 282
 283                 /*
 284                  * We can't sleep here, because it's also called from
 285                  * interrupt context.
 286                  */
 287                 timeout--;
 288                 if (!timeout)
 289                         return -ETIMEDOUT;
 290                 udelay(1);
 291         } while (1);
 292 }
 293
 294 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 295                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 296 {
 297         u32                     timeout = 500;
 298         u32                     reg;
 299
 300         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 301         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 302         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 303
 304         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 305         do {
 306                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 307                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 308                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 309                                         DWC3_DEPCMD_STATUS(reg));
 310                         return 0;
 311                 }
 312
 313                 /*
 314                  * We can't sleep here, because it is also called from
 315                  * interrupt context.
 316                  */
 317                 timeout--;
 318                 if (!timeout)
 319                         return -ETIMEDOUT;
 320
 321                 udelay(1);
 322         } while (1);
 323 }
 324
 325 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 326                 struct dwc3_trb *trb)
 327 {
 328         u32             offset = (char *) trb - (char *) dep->trb_pool;
 329
 330         return dep->trb_pool_dma + offset;
 331 }
 332
 333 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 334 {
 335         if (dep->trb_pool)
 336                 return 0;
 337
 338         if (dep->number == 0 || dep->number == 1)
 339                 return 0;
 340
 341         dep->trb_pool = dma_alloc_coherent(sizeof(struct dwc3_trb) *
 342                                            DWC3_TRB_NUM,
 343                                            (unsigned long *)&dep->trb_pool_dma);
 344         if (!dep->trb_pool) {
 345                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 346                                 dep->name);
 347                 return -ENOMEM;
 348         }
 349
 350         return 0;
 351 }
 352
 353 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 354 {
 355         dma_free_coherent(dep->trb_pool);
 356
 357         dep->trb_pool = NULL;
 358         dep->trb_pool_dma = 0;
 359 }
 360
 361 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 362 {
 363         struct dwc3_gadget_ep_cmd_params params;
 364         u32                     cmd;
 365
 366         memset(&params, 0x00, sizeof(params));
 367
 368         if (dep->number != 1) {
 369                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 370                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 371                 if (dep->number > 1) {
 372                         if (dwc->start_config_issued)
 373                                 return 0;
 374                         dwc->start_config_issued = true;
 375                         cmd |= DWC3_DEPCMD_PARAM(2);
 376                 }
 377
 378                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 379         }
 380
 381         return 0;
 382 }
 383
 384 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 385                 const struct usb_endpoint_descriptor *desc,
 386                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 387                 bool ignore, bool restore)
 388 {
 389         struct dwc3_gadget_ep_cmd_params params;
 390
 391         memset(&params, 0x00, sizeof(params));
 392
 393         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 394                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 395
 396         /* Burst size is only needed in SuperSpeed mode */
 397         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 398                 u32 burst = dep->endpoint.maxburst - 1;
 399
 400                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 401         }
 402
 403         if (ignore)
 404                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 405
 406         if (restore) {
 407                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 408                 params.param2 |= dep->saved_state;
 409         }
 410
 411         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 412                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 413
 414         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 415                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 416                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 417                 dep->stream_capable = true;
 418         }
 419
 420         if (!usb_endpoint_xfer_control(desc))
 421                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 422
 423         /*
 424          * We are doing 1:1 mapping for endpoints, meaning
 425          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 426          * so on. We consider the direction bit as part of the physical
 427          * endpoint number. So USB endpoint 0x81 is 0x03.
 428          */
 429         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 430
 431         /*
 432          * We must use the lower 16 TX FIFOs even though
 433          * HW might have more
 434          */
 435         if (dep->direction)
 436                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 437
 438         if (desc->bInterval) {
 439                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 440                 dep->interval = 1 << (desc->bInterval - 1);
 441         }
 442
 443         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 444                         DWC3_DEPCMD_SETEPCONFIG, &params);
 445 }
 446
 447 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 448 {
 449         struct dwc3_gadget_ep_cmd_params params;
 450
 451         memset(&params, 0x00, sizeof(params));
 452
 453         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 454
 455         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 456                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 457 }
 458
 459 /**
 460  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 461  * @dep: endpoint to be initialized
 462  * @desc: USB Endpoint Descriptor
 463  *
 464  * Caller should take care of locking
 465  */
 466 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 467                 const struct usb_endpoint_descriptor *desc,
 468                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 469                 bool ignore, bool restore)
 470 {
 471         struct dwc3             *dwc = dep->dwc;
 472         u32                     reg;
 473         int                     ret;
 474
 475         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 476
 477         if (!(dep->flags & DWC3_EP_ENABLED)) {
 478                 ret = dwc3_gadget_start_config(dwc, dep);
 479                 if (ret)
 480                         return ret;
 481         }
 482
 483         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 484                         restore);
 485         if (ret)
 486                 return ret;
 487
 488         if (!(dep->flags & DWC3_EP_ENABLED)) {
 489                 struct dwc3_trb *trb_st_hw;
 490                 struct dwc3_trb *trb_link;
 491
 492                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 493                 if (ret)
 494                         return ret;
 495
 496                 dep->endpoint.desc = desc;
 497                 dep->comp_desc = comp_desc;
 498                 dep->type = usb_endpoint_type(desc);
 499                 dep->flags |= DWC3_EP_ENABLED;
 500
 501                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 502                 reg |= DWC3_DALEPENA_EP(dep->number);
 503                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 504
 505                 if (!usb_endpoint_xfer_isoc(desc))
 506                         return 0;
 507
 508                 /* Link TRB for ISOC. The HWO bit is never reset */
 509                 trb_st_hw = &dep->trb_pool[0];
 510
 511                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 512                 memset(trb_link, 0, sizeof(*trb_link));
 513
 514                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 515                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 516                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 517                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 524 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 525 {
 526         struct dwc3_request             *req;
 527
 528         if (!list_empty(&dep->req_queued)) {
 529                 dwc3_stop_active_transfer(dwc, dep->number, true);
 530
 531                 /* - giveback all requests to gadget driver */
 532                 while (!list_empty(&dep->req_queued)) {
 533                         req = next_request(&dep->req_queued);
 534
 535                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 536                 }
 537         }
 538
 539         while (!list_empty(&dep->request_list)) {
 540                 req = next_request(&dep->request_list);
 541
 542                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 543         }
 544 }
 545
 546 /**
 547  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 548  * @dep: the endpoint to disable
 549  *
 550  * This function also removes requests which are currently processed ny the
 551  * hardware and those which are not yet scheduled.
 552  * Caller should take care of locking.
 553  */
 554 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 555 {
 556         struct dwc3             *dwc = dep->dwc;
 557         u32                     reg;
 558
 559         dwc3_remove_requests(dwc, dep);
 560
 561         /* make sure HW endpoint isn't stalled */
 562         if (dep->flags & DWC3_EP_STALL)
 563                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 564
 565         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 566         reg &= ~DWC3_DALEPENA_EP(dep->number);
 567         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 568
 569         dep->stream_capable = false;
 570         dep->endpoint.desc = NULL;
 571         dep->comp_desc = NULL;
 572         dep->type = 0;
 573         dep->flags = 0;
 574
 575         return 0;
 576 }
 577
 578 /* -------------------------------------------------------------------------- */
 579
 580 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 581                 const struct usb_endpoint_descriptor *desc)
 582 {
 583         return -EINVAL;
 584 }
 585
 586 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 587 {
 588         return -EINVAL;
 589 }
 590
 591 /* -------------------------------------------------------------------------- */
 592
 593 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 594                 const struct usb_endpoint_descriptor *desc)
 595 {
 596         struct dwc3_ep                  *dep;
 597         unsigned long                   flags;
 598         int                             ret;
 599
 600         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 601                 pr_debug("dwc3: invalid parameters\n");
 602                 return -EINVAL;
 603         }
 604
 605         if (!desc->wMaxPacketSize) {
 606                 pr_debug("dwc3: missing wMaxPacketSize\n");
 607                 return -EINVAL;
 608         }
 609
 610         dep = to_dwc3_ep(ep);
 611
 612         if (dep->flags & DWC3_EP_ENABLED) {
 613                 WARN(true, "%s is already enabled\n",
 614                                 dep->name);
 615                 return 0;
 616         }
 617
 618         switch (usb_endpoint_type(desc)) {
 619         case USB_ENDPOINT_XFER_CONTROL:
 620                 strlcat(dep->name, "-control", sizeof(dep->name));
 621                 break;
 622         case USB_ENDPOINT_XFER_ISOC:
 623                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 624                 break;
 625         case USB_ENDPOINT_XFER_BULK:
 626                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 627                 break;
 628         case USB_ENDPOINT_XFER_INT:
 629                 strlcat(dep->name, "-int", sizeof(dep->name));
 630                 break;
 631         default:
 632                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 633         }
 634
 635         spin_lock_irqsave(&dwc->lock, flags);
 636         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 637         spin_unlock_irqrestore(&dwc->lock, flags);
 638
 639         return ret;
 640 }
 641
 642 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 643 {
 644         struct dwc3_ep                  *dep;
 645         unsigned long                   flags;
 646         int                             ret;
 647
 648         if (!ep) {
 649                 pr_debug("dwc3: invalid parameters\n");
 650                 return -EINVAL;
 651         }
 652
 653         dep = to_dwc3_ep(ep);
 654
 655         if (!(dep->flags & DWC3_EP_ENABLED)) {
 656                 WARN(true, "%s is already disabled\n",
 657                                 dep->name);
 658                 return 0;
 659         }
 660
 661         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 662                         dep->number >> 1,
 663                         (dep->number & 1) ? "in" : "out");
 664
 665         spin_lock_irqsave(&dwc->lock, flags);
 666         ret = __dwc3_gadget_ep_disable(dep);
 667         spin_unlock_irqrestore(&dwc->lock, flags);
 668
 669         return ret;
 670 }
 671
 672 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 673         gfp_t gfp_flags)
 674 {
 675         struct dwc3_request             *req;
 676         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 677
 678         req = kzalloc(sizeof(*req), gfp_flags);
 679         if (!req)
 680                 return NULL;
 681
 682         req->epnum      = dep->number;
 683         req->dep        = dep;
 684
 685         return &req->request;
 686 }
 687
 688 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 689                 struct usb_request *request)
 690 {
 691         struct dwc3_request             *req = to_dwc3_request(request);
 692
 693         kfree(req);
 694 }
 695
 696 /**
 697  * dwc3_prepare_one_trb - setup one TRB from one request
 698  * @dep: endpoint for which this request is prepared
 699  * @req: dwc3_request pointer
 700  */
 701 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 702                 struct dwc3_request *req, dma_addr_t dma,
 703                 unsigned length, unsigned last, unsigned chain, unsigned node)
 704 {
 705         struct dwc3_trb         *trb;
 706
 707         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 708                         dep->name, req, (unsigned long long) dma,
 709                         length, last ? " last" : "",
 710                         chain ? " chain" : "");
 711
 712
 713         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 714
 715         if (!req->trb) {
 716                 dwc3_gadget_move_request_queued(req);
 717                 req->trb = trb;
 718                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 719                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 720         }
 721
 722         dep->free_slot++;
 723         /* Skip the LINK-TRB on ISOC */
 724         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 725                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 726                 dep->free_slot++;
 727
 728         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 729         trb->bpl = lower_32_bits(dma);
 730         trb->bph = upper_32_bits(dma);
 731
 732         switch (usb_endpoint_type(dep->endpoint.desc)) {
 733         case USB_ENDPOINT_XFER_CONTROL:
 734                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 735                 break;
 736
 737         case USB_ENDPOINT_XFER_ISOC:
 738                 if (!node)
 739                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 740                 else
 741                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 742                 break;
 743
 744         case USB_ENDPOINT_XFER_BULK:
 745         case USB_ENDPOINT_XFER_INT:
 746                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 747                 break;
 748         default:
 749                 /*
 750                  * This is only possible with faulty memory because we
 751                  * checked it already :)
 752                  */
 753                 BUG();
 754         }
 755
 756         if (!req->request.no_interrupt && !chain)
 757                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 758
 759         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 760                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 761                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 762         } else if (last) {
 763                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 764         }
 765
 766         if (chain)
 767                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 768
 769         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 770                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 771
 772         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 773
 774         dwc3_flush_cache((int)dma, length);
 775         dwc3_flush_cache((int)trb, sizeof(*trb));
 776 }
 777
 778 /*
 779  * dwc3_prepare_trbs - setup TRBs from requests
 780  * @dep: endpoint for which requests are being prepared
 781  * @starting: true if the endpoint is idle and no requests are queued.
 782  *
 783  * The function goes through the requests list and sets up TRBs for the
 784  * transfers. The function returns once there are no more TRBs available or
 785  * it runs out of requests.
 786  */
 787 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 788 {
 789         struct dwc3_request     *req, *n;
 790         u32                     trbs_left;
 791         u32                     max;
 792         unsigned int            last_one = 0;
 793
 794         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 795
 796         /* the first request must not be queued */
 797         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 798
 799         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 800         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 801                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 802                 if (trbs_left > max)
 803                         trbs_left = max;
 804         }
 805
 806         /*
 807          * If busy & slot are equal than it is either full or empty. If we are
 808          * starting to process requests then we are empty. Otherwise we are
 809          * full and don't do anything
 810          */
 811         if (!trbs_left) {
 812                 if (!starting)
 813                         return;
 814                 trbs_left = DWC3_TRB_NUM;
 815                 /*
 816                  * In case we start from scratch, we queue the ISOC requests
 817                  * starting from slot 1. This is done because we use ring
 818                  * buffer and have no LST bit to stop us. Instead, we place
 819                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 820                  * after the first request so we start at slot 1 and have
 821                  * 7 requests proceed before we hit the first IOC.
 822                  * Other transfer types don't use the ring buffer and are
 823                  * processed from the first TRB until the last one. Since we
 824                  * don't wrap around we have to start at the beginning.
 825                  */
 826                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 827                         dep->busy_slot = 1;
 828                         dep->free_slot = 1;
 829                 } else {
 830                         dep->busy_slot = 0;
 831                         dep->free_slot = 0;
 832                 }
 833         }
 834
 835         /* The last TRB is a link TRB, not used for xfer */
 836         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 837                 return;
 838
 839         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 840                 unsigned        length;
 841                 dma_addr_t      dma;
 842                 last_one = false;
 843
 844                 dma = req->request.dma;
 845                 length = req->request.length;
 846                 trbs_left--;
 847
 848                 if (!trbs_left)
 849                         last_one = 1;
 850
 851                 /* Is this the last request? */
 852                 if (list_is_last(&req->list, &dep->request_list))
 853                         last_one = 1;
 854
 855                 dwc3_prepare_one_trb(dep, req, dma, length,
 856                                 last_one, false, 0);
 857
 858                 if (last_one)
 859                         break;
 860         }
 861 }
 862
 863 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 864                 int start_new)
 865 {
 866         struct dwc3_gadget_ep_cmd_params params;
 867         struct dwc3_request             *req;
 868         struct dwc3                     *dwc = dep->dwc;
 869         int                             ret;
 870         u32                             cmd;
 871
 872         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 873                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 874                 return -EBUSY;
 875         }
 876         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 877
 878         /*
 879          * If we are getting here after a short-out-packet we don't enqueue any
 880          * new requests as we try to set the IOC bit only on the last request.
 881          */
 882         if (start_new) {
 883                 if (list_empty(&dep->req_queued))
 884                         dwc3_prepare_trbs(dep, start_new);
 885
 886                 /* req points to the first request which will be sent */
 887                 req = next_request(&dep->req_queued);
 888         } else {
 889                 dwc3_prepare_trbs(dep, start_new);
 890
 891                 /*
 892                  * req points to the first request where HWO changed from 0 to 1
 893                  */
 894                 req = next_request(&dep->req_queued);
 895         }
 896         if (!req) {
 897                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 898                 return 0;
 899         }
 900
 901         memset(&params, 0, sizeof(params));
 902
 903         if (start_new) {
 904                 params.param0 = upper_32_bits(req->trb_dma);
 905                 params.param1 = lower_32_bits(req->trb_dma);
 906                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 907         } else {
 908                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 909         }
 910
 911         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 912         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 913         if (ret < 0) {
 914                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 915
 916                 /*
 917                  * FIXME we need to iterate over the list of requests
 918                  * here and stop, unmap, free and del each of the linked
 919                  * requests instead of what we do now.
 920                  */
 921                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 922                                 req->direction);
 923                 list_del(&req->list);
 924                 return ret;
 925         }
 926
 927         dep->flags |= DWC3_EP_BUSY;
 928
 929         if (start_new) {
 930                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 931                                 dep->number);
 932                 WARN_ON_ONCE(!dep->resource_index);
 933         }
 934
 935         return 0;
 936 }
 937
 938 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
 939                 struct dwc3_ep *dep, u32 cur_uf)
 940 {
 941         u32 uf;
 942
 943         if (list_empty(&dep->request_list)) {
 944                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
 945                         dep->name);
 946                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 947                 return;
 948         }
 949
 950         /* 4 micro frames in the future */
 951         uf = cur_uf + dep->interval * 4;
 952
 953         __dwc3_gadget_kick_transfer(dep, uf, 1);
 954 }
 955
 956 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
 957                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
 958 {
 959         u32 cur_uf, mask;
 960
 961         mask = ~(dep->interval - 1);
 962         cur_uf = event->parameters & mask;
 963
 964         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
 965 }
 966
 967 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
 968 {
 969         struct dwc3             *dwc = dep->dwc;
 970         int                     ret;
 971
 972         req->request.actual     = 0;
 973         req->request.status     = -EINPROGRESS;
 974         req->direction          = dep->direction;
 975         req->epnum              = dep->number;
 976
 977         /*
 978          * DWC3 hangs on OUT requests smaller than maxpacket size,
 979          * so HACK the request length
 980          */
 981         if (dep->direction == 0 &&
 982             req->request.length < dep->endpoint.maxpacket)
 983                 req->request.length = dep->endpoint.maxpacket;
 984
 985         /*
 986          * We only add to our list of requests now and
 987          * start consuming the list once we get XferNotReady
 988          * IRQ.
 989          *
 990          * That way, we avoid doing anything that we don't need
 991          * to do now and defer it until the point we receive a
 992          * particular token from the Host side.
 993          *
 994          * This will also avoid Host cancelling URBs due to too
 995          * many NAKs.
 996          */
 997         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 998                         dep->direction);
 999         if (ret)
1000                 return ret;
1001
1002         list_add_tail(&req->list, &dep->request_list);
1003
1004         /*
1005          * There are a few special cases:
1006          *
1007          * 1. XferNotReady with empty list of requests. We need to kick the
1008          *    transfer here in that situation, otherwise we will be NAKing
1009          *    forever. If we get XferNotReady before gadget driver has a
1010          *    chance to queue a request, we will ACK the IRQ but won't be
1011          *    able to receive the data until the next request is queued.
1012          *    The following code is handling exactly that.
1013          *
1014          */
1015         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1016                 /*
1017                  * If xfernotready is already elapsed and it is a case
1018                  * of isoc transfer, then issue END TRANSFER, so that
1019                  * you can receive xfernotready again and can have
1020                  * notion of current microframe.
1021                  */
1022                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1023                         if (list_empty(&dep->req_queued)) {
1024                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1025                                 dep->flags = DWC3_EP_ENABLED;
1026                         }
1027                         return 0;
1028                 }
1029
1030                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1031                 if (ret && ret != -EBUSY)
1032                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1033                                         dep->name);
1034                 return ret;
1035         }
1036
1037         /*
1038          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1039          *    kick the transfer here after queuing a request, otherwise the
1040          *    core may not see the modified TRB(s).
1041          */
1042         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1043                         (dep->flags & DWC3_EP_BUSY) &&
1044                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1045                 WARN_ON_ONCE(!dep->resource_index);
1046                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1047                                 false);
1048                 if (ret && ret != -EBUSY)
1049                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1050                                         dep->name);
1051                 return ret;
1052         }
1053
1054         /*
1055          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1056          * right away, otherwise host will not know we have streams to be
1057          * handled.
1058          */
1059         if (dep->stream_capable) {
1060                 int     ret;
1061
1062                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1063                 if (ret && ret != -EBUSY) {
1064                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1065                                         dep->name);
1066                 }
1067         }
1068
1069         return 0;
1070 }
1071
1072 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1073         gfp_t gfp_flags)
1074 {
1075         struct dwc3_request             *req = to_dwc3_request(request);
1076         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1077
1078         unsigned long                   flags;
1079
1080         int                             ret;
1081
1082         spin_lock_irqsave(&dwc->lock, flags);
1083         if (!dep->endpoint.desc) {
1084                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1085                                 request, ep->name);
1086                 ret = -ESHUTDOWN;
1087                 goto out;
1088         }
1089
1090         if (req->dep != dep) {
1091                 WARN(true, "request %p belongs to '%s'\n",
1092                                 request, req->dep->name);
1093                 ret = -EINVAL;
1094                 goto out;
1095         }
1096
1097         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1098                         request, ep->name, request->length);
1099
1100         ret = __dwc3_gadget_ep_queue(dep, req);
1101
1102 out:
1103         spin_unlock_irqrestore(&dwc->lock, flags);
1104
1105         return ret;
1106 }
1107
1108 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1109                 struct usb_request *request)
1110 {
1111         struct dwc3_request             *req = to_dwc3_request(request);
1112         struct dwc3_request             *r = NULL;
1113
1114         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1115         struct dwc3                     *dwc = dep->dwc;
1116
1117         unsigned long                   flags;
1118         int                             ret = 0;
1119
1120         spin_lock_irqsave(&dwc->lock, flags);
1121
1122         list_for_each_entry(r, &dep->request_list, list) {
1123                 if (r == req)
1124                         break;
1125         }
1126
1127         if (r != req) {
1128                 list_for_each_entry(r, &dep->req_queued, list) {
1129                         if (r == req)
1130                                 break;
1131                 }
1132                 if (r == req) {
1133                         /* wait until it is processed */
1134                         dwc3_stop_active_transfer(dwc, dep->number, true);
1135                         goto out1;
1136                 }
1137                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1138                                 request, ep->name);
1139                 ret = -EINVAL;
1140                 goto out0;
1141         }
1142
1143 out1:
1144         /* giveback the request */
1145         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1146
1147 out0:
1148         spin_unlock_irqrestore(&dwc->lock, flags);
1149
1150         return ret;
1151 }
1152
1153 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1154 {
1155         struct dwc3_gadget_ep_cmd_params        params;
1156         struct dwc3                             *dwc = dep->dwc;
1157         int                                     ret;
1158
1159         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1160                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1161                 return -EINVAL;
1162         }
1163
1164         memset(&params, 0x00, sizeof(params));
1165
1166         if (value) {
1167                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1168                                 (!list_empty(&dep->req_queued) ||
1169                                  !list_empty(&dep->request_list)))) {
1170                         dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1171                                         dep->name);
1172                         return -EAGAIN;
1173                 }
1174
1175                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1176                         DWC3_DEPCMD_SETSTALL, &params);
1177                 if (ret)
1178                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1179                                         dep->name);
1180                 else
1181                         dep->flags |= DWC3_EP_STALL;
1182         } else {
1183                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1184                         DWC3_DEPCMD_CLEARSTALL, &params);
1185                 if (ret)
1186                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1187                                         dep->name);
1188                 else
1189                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1190         }
1191
1192         return ret;
1193 }
1194
1195 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1196 {
1197         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1198
1199         unsigned long                   flags;
1200
1201         int                             ret;
1202
1203         spin_lock_irqsave(&dwc->lock, flags);
1204         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1205         spin_unlock_irqrestore(&dwc->lock, flags);
1206
1207         return ret;
1208 }
1209
1210 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1211 {
1212         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1213         unsigned long                   flags;
1214         int                             ret;
1215
1216         spin_lock_irqsave(&dwc->lock, flags);
1217         dep->flags |= DWC3_EP_WEDGE;
1218
1219         if (dep->number == 0 || dep->number == 1)
1220                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1221         else
1222                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1223         spin_unlock_irqrestore(&dwc->lock, flags);
1224
1225         return ret;
1226 }
1227
1228 /* -------------------------------------------------------------------------- */
1229
1230 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1231         .bLength        = USB_DT_ENDPOINT_SIZE,
1232         .bDescriptorType = USB_DT_ENDPOINT,
1233         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1234 };
1235
1236 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1237         .enable         = dwc3_gadget_ep0_enable,
1238         .disable        = dwc3_gadget_ep0_disable,
1239         .alloc_request  = dwc3_gadget_ep_alloc_request,
1240         .free_request   = dwc3_gadget_ep_free_request,
1241         .queue          = dwc3_gadget_ep0_queue,
1242         .dequeue        = dwc3_gadget_ep_dequeue,
1243         .set_halt       = dwc3_gadget_ep0_set_halt,
1244         .set_wedge      = dwc3_gadget_ep_set_wedge,
1245 };
1246
1247 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1248         .enable         = dwc3_gadget_ep_enable,
1249         .disable        = dwc3_gadget_ep_disable,
1250         .alloc_request  = dwc3_gadget_ep_alloc_request,
1251         .free_request   = dwc3_gadget_ep_free_request,
1252         .queue          = dwc3_gadget_ep_queue,
1253         .dequeue        = dwc3_gadget_ep_dequeue,
1254         .set_halt       = dwc3_gadget_ep_set_halt,
1255         .set_wedge      = dwc3_gadget_ep_set_wedge,
1256 };
1257
1258 /* -------------------------------------------------------------------------- */
1259
1260 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1261 {
1262         struct dwc3             *dwc = gadget_to_dwc(g);
1263         u32                     reg;
1264
1265         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1266         return DWC3_DSTS_SOFFN(reg);
1267 }
1268
1269 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1270 {
1271         struct dwc3             *dwc = gadget_to_dwc(g);
1272
1273         unsigned long           timeout;
1274         unsigned long           flags;
1275
1276         u32                     reg;
1277
1278         int                     ret = 0;
1279
1280         u8                      link_state;
1281         u8                      speed;
1282
1283         spin_lock_irqsave(&dwc->lock, flags);
1284
1285         /*
1286          * According to the Databook Remote wakeup request should
1287          * be issued only when the device is in early suspend state.
1288          *
1289          * We can check that via USB Link State bits in DSTS register.
1290          */
1291         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1292
1293         speed = reg & DWC3_DSTS_CONNECTSPD;
1294         if (speed == DWC3_DSTS_SUPERSPEED) {
1295                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1296                 ret = -EINVAL;
1297                 goto out;
1298         }
1299
1300         link_state = DWC3_DSTS_USBLNKST(reg);
1301
1302         switch (link_state) {
1303         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1304         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1305                 break;
1306         default:
1307                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1308                                 link_state);
1309                 ret = -EINVAL;
1310                 goto out;
1311         }
1312
1313         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1314         if (ret < 0) {
1315                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1316                 goto out;
1317         }
1318
1319         /* Recent versions do this automatically */
1320         if (dwc->revision < DWC3_REVISION_194A) {
1321                 /* write zeroes to Link Change Request */
1322                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1323                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1324                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1325         }
1326
1327         /* poll until Link State changes to ON */
1328         timeout = 1000;
1329
1330         while (timeout--) {
1331                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1332
1333                 /* in HS, means ON */
1334                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1335                         break;
1336         }
1337
1338         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1339                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1340                 ret = -EINVAL;
1341         }
1342
1343 out:
1344         spin_unlock_irqrestore(&dwc->lock, flags);
1345
1346         return ret;
1347 }
1348
1349 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1350                 int is_selfpowered)
1351 {
1352         struct dwc3             *dwc = gadget_to_dwc(g);
1353         unsigned long           flags;
1354
1355         spin_lock_irqsave(&dwc->lock, flags);
1356         dwc->is_selfpowered = !!is_selfpowered;
1357         spin_unlock_irqrestore(&dwc->lock, flags);
1358
1359         return 0;
1360 }
1361
1362 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1363 {
1364         u32                     reg;
1365         u32                     timeout = 500;
1366
1367         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1368         if (is_on) {
1369                 if (dwc->revision <= DWC3_REVISION_187A) {
1370                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1371                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1372                 }
1373
1374                 if (dwc->revision >= DWC3_REVISION_194A)
1375                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1376                 reg |= DWC3_DCTL_RUN_STOP;
1377
1378                 if (dwc->has_hibernation)
1379                         reg |= DWC3_DCTL_KEEP_CONNECT;
1380
1381                 dwc->pullups_connected = true;
1382         } else {
1383                 reg &= ~DWC3_DCTL_RUN_STOP;
1384
1385                 if (dwc->has_hibernation && !suspend)
1386                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1387
1388                 dwc->pullups_connected = false;
1389         }
1390
1391         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1392
1393         do {
1394                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1395                 if (is_on) {
1396                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1397                                 break;
1398                 } else {
1399                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1400                                 break;
1401                 }
1402                 timeout--;
1403                 if (!timeout)
1404                         return -ETIMEDOUT;
1405                 udelay(1);
1406         } while (1);
1407
1408         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1409                         dwc->gadget_driver
1410                         ? dwc->gadget_driver->function : "no-function",
1411                         is_on ? "connect" : "disconnect");
1412
1413         return 0;
1414 }
1415
1416 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1417 {
1418         struct dwc3             *dwc = gadget_to_dwc(g);
1419         unsigned long           flags;
1420         int                     ret;
1421
1422         is_on = !!is_on;
1423
1424         spin_lock_irqsave(&dwc->lock, flags);
1425         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1426         spin_unlock_irqrestore(&dwc->lock, flags);
1427
1428         return ret;
1429 }
1430
1431 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1432 {
1433         u32                     reg;
1434
1435         /* Enable all but Start and End of Frame IRQs */
1436         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1437                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1438                         DWC3_DEVTEN_CMDCMPLTEN |
1439                         DWC3_DEVTEN_ERRTICERREN |
1440                         DWC3_DEVTEN_WKUPEVTEN |
1441                         DWC3_DEVTEN_ULSTCNGEN |
1442                         DWC3_DEVTEN_CONNECTDONEEN |
1443                         DWC3_DEVTEN_USBRSTEN |
1444                         DWC3_DEVTEN_DISCONNEVTEN);
1445
1446         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1447 }
1448
1449 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1450 {
1451         /* mask all interrupts */
1452         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1453 }
1454
1455 static int dwc3_gadget_start(struct usb_gadget *g,
1456                 struct usb_gadget_driver *driver)
1457 {
1458         struct dwc3             *dwc = gadget_to_dwc(g);
1459         struct dwc3_ep          *dep;
1460         unsigned long           flags;
1461         int                     ret = 0;
1462         u32                     reg;
1463
1464         spin_lock_irqsave(&dwc->lock, flags);
1465
1466         if (dwc->gadget_driver) {
1467                 dev_err(dwc->dev, "%s is already bound to %s\n",
1468                                 dwc->gadget.name,
1469                                 dwc->gadget_driver->function);
1470                 ret = -EBUSY;
1471                 goto err1;
1472         }
1473
1474         dwc->gadget_driver      = driver;
1475
1476         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1477         reg &= ~(DWC3_DCFG_SPEED_MASK);
1478
1479         /**
1480          * WORKAROUND: DWC3 revision < 2.20a have an issue
1481          * which would cause metastability state on Run/Stop
1482          * bit if we try to force the IP to USB2-only mode.
1483          *
1484          * Because of that, we cannot configure the IP to any
1485          * speed other than the SuperSpeed
1486          *
1487          * Refers to:
1488          *
1489          * STAR#9000525659: Clock Domain Crossing on DCTL in
1490          * USB 2.0 Mode
1491          */
1492         if (dwc->revision < DWC3_REVISION_220A) {
1493                 reg |= DWC3_DCFG_SUPERSPEED;
1494         } else {
1495                 switch (dwc->maximum_speed) {
1496                 case USB_SPEED_LOW:
1497                         reg |= DWC3_DSTS_LOWSPEED;
1498                         break;
1499                 case USB_SPEED_FULL:
1500                         reg |= DWC3_DSTS_FULLSPEED1;
1501                         break;
1502                 case USB_SPEED_HIGH:
1503                         reg |= DWC3_DSTS_HIGHSPEED;
1504                         break;
1505                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1506                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1507                 default:
1508                         reg |= DWC3_DSTS_SUPERSPEED;
1509                 }
1510         }
1511         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1512
1513         dwc->start_config_issued = false;
1514
1515         /* Start with SuperSpeed Default */
1516         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1517
1518         dep = dwc->eps[0];
1519         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1520                         false);
1521         if (ret) {
1522                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1523                 goto err2;
1524         }
1525
1526         dep = dwc->eps[1];
1527         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1528                         false);
1529         if (ret) {
1530                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1531                 goto err3;
1532         }
1533
1534         /* begin to receive SETUP packets */
1535         dwc->ep0state = EP0_SETUP_PHASE;
1536         dwc3_ep0_out_start(dwc);
1537
1538         dwc3_gadget_enable_irq(dwc);
1539
1540         spin_unlock_irqrestore(&dwc->lock, flags);
1541
1542         return 0;
1543
1544 err3:
1545         __dwc3_gadget_ep_disable(dwc->eps[0]);
1546
1547 err2:
1548         dwc->gadget_driver = NULL;
1549
1550 err1:
1551         spin_unlock_irqrestore(&dwc->lock, flags);
1552
1553         return ret;
1554 }
1555
1556 static int dwc3_gadget_stop(struct usb_gadget *g)
1557 {
1558         struct dwc3             *dwc = gadget_to_dwc(g);
1559         unsigned long           flags;
1560
1561         spin_lock_irqsave(&dwc->lock, flags);
1562
1563         dwc3_gadget_disable_irq(dwc);
1564         __dwc3_gadget_ep_disable(dwc->eps[0]);
1565         __dwc3_gadget_ep_disable(dwc->eps[1]);
1566
1567         dwc->gadget_driver      = NULL;
1568
1569         spin_unlock_irqrestore(&dwc->lock, flags);
1570
1571         return 0;
1572 }
1573
1574 static const struct usb_gadget_ops dwc3_gadget_ops = {
1575         .get_frame              = dwc3_gadget_get_frame,
1576         .wakeup                 = dwc3_gadget_wakeup,
1577         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1578         .pullup                 = dwc3_gadget_pullup,
1579         .udc_start              = dwc3_gadget_start,
1580         .udc_stop               = dwc3_gadget_stop,
1581 };
1582
1583 /* -------------------------------------------------------------------------- */
1584
1585 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1586                 u8 num, u32 direction)
1587 {
1588         struct dwc3_ep                  *dep;
1589         u8                              i;
1590
1591         for (i = 0; i < num; i++) {
1592                 u8 epnum = (i << 1) | (!!direction);
1593
1594                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1595                 if (!dep)
1596                         return -ENOMEM;
1597
1598                 dep->dwc = dwc;
1599                 dep->number = epnum;
1600                 dep->direction = !!direction;
1601                 dwc->eps[epnum] = dep;
1602
1603                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1604                                 (epnum & 1) ? "in" : "out");
1605
1606                 dep->endpoint.name = dep->name;
1607
1608                 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1609
1610                 if (epnum == 0 || epnum == 1) {
1611                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1612                         dep->endpoint.maxburst = 1;
1613                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1614                         if (!epnum)
1615                                 dwc->gadget.ep0 = &dep->endpoint;
1616                 } else {
1617                         int             ret;
1618
1619                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1620                         dep->endpoint.max_streams = 15;
1621                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1622                         list_add_tail(&dep->endpoint.ep_list,
1623                                         &dwc->gadget.ep_list);
1624
1625                         ret = dwc3_alloc_trb_pool(dep);
1626                         if (ret)
1627                                 return ret;
1628                 }
1629
1630                 INIT_LIST_HEAD(&dep->request_list);
1631                 INIT_LIST_HEAD(&dep->req_queued);
1632         }
1633
1634         return 0;
1635 }
1636
1637 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1638 {
1639         int                             ret;
1640
1641         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1642
1643         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1644         if (ret < 0) {
1645                 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1646                 return ret;
1647         }
1648
1649         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1650         if (ret < 0) {
1651                 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1652                 return ret;
1653         }
1654
1655         return 0;
1656 }
1657
1658 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1659 {
1660         struct dwc3_ep                  *dep;
1661         u8                              epnum;
1662
1663         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1664                 dep = dwc->eps[epnum];
1665                 if (!dep)
1666                         continue;
1667                 /*
1668                  * Physical endpoints 0 and 1 are special; they form the
1669                  * bi-directional USB endpoint 0.
1670                  *
1671                  * For those two physical endpoints, we don't allocate a TRB
1672                  * pool nor do we add them the endpoints list. Due to that, we
1673                  * shouldn't do these two operations otherwise we would end up
1674                  * with all sorts of bugs when removing dwc3.ko.
1675                  */
1676                 if (epnum != 0 && epnum != 1) {
1677                         dwc3_free_trb_pool(dep);
1678                         list_del(&dep->endpoint.ep_list);
1679                 }
1680
1681                 kfree(dep);
1682         }
1683 }
1684
1685 /* -------------------------------------------------------------------------- */
1686
1687 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1688                 struct dwc3_request *req, struct dwc3_trb *trb,
1689                 const struct dwc3_event_depevt *event, int status)
1690 {
1691         unsigned int            count;
1692         unsigned int            s_pkt = 0;
1693         unsigned int            trb_status;
1694
1695         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1696                 /*
1697                  * We continue despite the error. There is not much we
1698                  * can do. If we don't clean it up we loop forever. If
1699                  * we skip the TRB then it gets overwritten after a
1700                  * while since we use them in a ring buffer. A BUG()
1701                  * would help. Lets hope that if this occurs, someone
1702                  * fixes the root cause instead of looking away :)
1703                  */
1704                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1705                                 dep->name, trb);
1706         count = trb->size & DWC3_TRB_SIZE_MASK;
1707
1708         if (dep->direction) {
1709                 if (count) {
1710                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1711                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1712                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1713                                                 dep->name);
1714                                 /*
1715                                  * If missed isoc occurred and there is
1716                                  * no request queued then issue END
1717                                  * TRANSFER, so that core generates
1718                                  * next xfernotready and we will issue
1719                                  * a fresh START TRANSFER.
1720                                  * If there are still queued request
1721                                  * then wait, do not issue either END
1722                                  * or UPDATE TRANSFER, just attach next
1723                                  * request in request_list during
1724                                  * giveback.If any future queued request
1725                                  * is successfully transferred then we
1726                                  * will issue UPDATE TRANSFER for all
1727                                  * request in the request_list.
1728                                  */
1729                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1730                         } else {
1731                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1732                                                 dep->name);
1733                                 status = -ECONNRESET;
1734                         }
1735                 } else {
1736                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1737                 }
1738         } else {
1739                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1740                         s_pkt = 1;
1741         }
1742
1743         /*
1744          * We assume here we will always receive the entire data block
1745          * which we should receive. Meaning, if we program RX to
1746          * receive 4K but we receive only 2K, we assume that's all we
1747          * should receive and we simply bounce the request back to the
1748          * gadget driver for further processing.
1749          */
1750         req->request.actual += req->request.length - count;
1751         if (s_pkt)
1752                 return 1;
1753         if ((event->status & DEPEVT_STATUS_LST) &&
1754                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1755                                 DWC3_TRB_CTRL_HWO)))
1756                 return 1;
1757         if ((event->status & DEPEVT_STATUS_IOC) &&
1758                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1759                 return 1;
1760         return 0;
1761 }
1762
1763 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1764                 const struct dwc3_event_depevt *event, int status)
1765 {
1766         struct dwc3_request     *req;
1767         struct dwc3_trb         *trb;
1768         unsigned int            slot;
1769         int                     ret;
1770
1771         do {
1772                 req = next_request(&dep->req_queued);
1773                 if (!req) {
1774                         WARN_ON_ONCE(1);
1775                         return 1;
1776                 }
1777
1778                 slot = req->start_slot;
1779                 if ((slot == DWC3_TRB_NUM - 1) &&
1780                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
1781                         slot++;
1782                 slot %= DWC3_TRB_NUM;
1783                 trb = &dep->trb_pool[slot];
1784
1785                 dwc3_flush_cache((int)trb, sizeof(*trb));
1786                 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1787                                 event, status);
1788                 if (ret)
1789                         break;
1790
1791                 dwc3_gadget_giveback(dep, req, status);
1792
1793                 if (ret)
1794                         break;
1795         } while (1);
1796
1797         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1798                         list_empty(&dep->req_queued)) {
1799                 if (list_empty(&dep->request_list)) {
1800                         /*
1801                          * If there is no entry in request list then do
1802                          * not issue END TRANSFER now. Just set PENDING
1803                          * flag, so that END TRANSFER is issued when an
1804                          * entry is added into request list.
1805                          */
1806                         dep->flags = DWC3_EP_PENDING_REQUEST;
1807                 } else {
1808                         dwc3_stop_active_transfer(dwc, dep->number, true);
1809                         dep->flags = DWC3_EP_ENABLED;
1810                 }
1811                 return 1;
1812         }
1813
1814         return 1;
1815 }
1816
1817 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1818                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1819 {
1820         unsigned                status = 0;
1821         int                     clean_busy;
1822
1823         if (event->status & DEPEVT_STATUS_BUSERR)
1824                 status = -ECONNRESET;
1825
1826         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1827         if (clean_busy)
1828                 dep->flags &= ~DWC3_EP_BUSY;
1829
1830         /*
1831          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1832          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1833          */
1834         if (dwc->revision < DWC3_REVISION_183A) {
1835                 u32             reg;
1836                 int             i;
1837
1838                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1839                         dep = dwc->eps[i];
1840
1841                         if (!(dep->flags & DWC3_EP_ENABLED))
1842                                 continue;
1843
1844                         if (!list_empty(&dep->req_queued))
1845                                 return;
1846                 }
1847
1848                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1849                 reg |= dwc->u1u2;
1850                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1851
1852                 dwc->u1u2 = 0;
1853         }
1854 }
1855
1856 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1857                 const struct dwc3_event_depevt *event)
1858 {
1859         struct dwc3_ep          *dep;
1860         u8                      epnum = event->endpoint_number;
1861
1862         dep = dwc->eps[epnum];
1863
1864         if (!(dep->flags & DWC3_EP_ENABLED))
1865                 return;
1866
1867         if (epnum == 0 || epnum == 1) {
1868                 dwc3_ep0_interrupt(dwc, event);
1869                 return;
1870         }
1871
1872         switch (event->endpoint_event) {
1873         case DWC3_DEPEVT_XFERCOMPLETE:
1874                 dep->resource_index = 0;
1875
1876                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1877                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1878                                         dep->name);
1879                         return;
1880                 }
1881
1882                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1883                 break;
1884         case DWC3_DEPEVT_XFERINPROGRESS:
1885                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1886                 break;
1887         case DWC3_DEPEVT_XFERNOTREADY:
1888                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1889                         dwc3_gadget_start_isoc(dwc, dep, event);
1890                 } else {
1891                         int ret;
1892
1893                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1894                                         dep->name, event->status &
1895                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1896                                         ? "Transfer Active"
1897                                         : "Transfer Not Active");
1898
1899                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1900                         if (!ret || ret == -EBUSY)
1901                                 return;
1902
1903                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1904                                         dep->name);
1905                 }
1906
1907                 break;
1908         case DWC3_DEPEVT_STREAMEVT:
1909                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1910                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1911                                         dep->name);
1912                         return;
1913                 }
1914
1915                 switch (event->status) {
1916                 case DEPEVT_STREAMEVT_FOUND:
1917                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1918                                         event->parameters);
1919
1920                         break;
1921                 case DEPEVT_STREAMEVT_NOTFOUND:
1922                         /* FALLTHROUGH */
1923                 default:
1924                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1925                 }
1926                 break;
1927         case DWC3_DEPEVT_RXTXFIFOEVT:
1928                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1929                 break;
1930         case DWC3_DEPEVT_EPCMDCMPLT:
1931                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1932                 break;
1933         }
1934 }
1935
1936 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1937 {
1938         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1939                 spin_unlock(&dwc->lock);
1940                 dwc->gadget_driver->disconnect(&dwc->gadget);
1941                 spin_lock(&dwc->lock);
1942         }
1943 }
1944
1945 static void dwc3_suspend_gadget(struct dwc3 *dwc)
1946 {
1947         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
1948                 spin_unlock(&dwc->lock);
1949                 dwc->gadget_driver->suspend(&dwc->gadget);
1950                 spin_lock(&dwc->lock);
1951         }
1952 }
1953
1954 static void dwc3_resume_gadget(struct dwc3 *dwc)
1955 {
1956         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
1957                 spin_unlock(&dwc->lock);
1958                 dwc->gadget_driver->resume(&dwc->gadget);
1959         }
1960 }
1961
1962 static void dwc3_reset_gadget(struct dwc3 *dwc)
1963 {
1964         if (!dwc->gadget_driver)
1965                 return;
1966
1967         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
1968                 spin_unlock(&dwc->lock);
1969                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
1970                 spin_lock(&dwc->lock);
1971         }
1972 }
1973
1974 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
1975 {
1976         struct dwc3_ep *dep;
1977         struct dwc3_gadget_ep_cmd_params params;
1978         u32 cmd;
1979         int ret;
1980
1981         dep = dwc->eps[epnum];
1982
1983         if (!dep->resource_index)
1984                 return;
1985
1986         /*
1987          * NOTICE: We are violating what the Databook says about the
1988          * EndTransfer command. Ideally we would _always_ wait for the
1989          * EndTransfer Command Completion IRQ, but that's causing too
1990          * much trouble synchronizing between us and gadget driver.
1991          *
1992          * We have discussed this with the IP Provider and it was
1993          * suggested to giveback all requests here, but give HW some
1994          * extra time to synchronize with the interconnect. We're using
1995          * an arbitraty 100us delay for that.
1996          *
1997          * Note also that a similar handling was tested by Synopsys
1998          * (thanks a lot Paul) and nothing bad has come out of it.
1999          * In short, what we're doing is:
2000          *
2001          * - Issue EndTransfer WITH CMDIOC bit set
2002          * - Wait 100us
2003          */
2004
2005         cmd = DWC3_DEPCMD_ENDTRANSFER;
2006         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2007         cmd |= DWC3_DEPCMD_CMDIOC;
2008         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2009         memset(&params, 0, sizeof(params));
2010         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2011         WARN_ON_ONCE(ret);
2012         dep->resource_index = 0;
2013         dep->flags &= ~DWC3_EP_BUSY;
2014         udelay(100);
2015 }
2016
2017 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2018 {
2019         u32 epnum;
2020
2021         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2022                 struct dwc3_ep *dep;
2023
2024                 dep = dwc->eps[epnum];
2025                 if (!dep)
2026                         continue;
2027
2028                 if (!(dep->flags & DWC3_EP_ENABLED))
2029                         continue;
2030
2031                 dwc3_remove_requests(dwc, dep);
2032         }
2033 }
2034
2035 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2036 {
2037         u32 epnum;
2038
2039         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2040                 struct dwc3_ep *dep;
2041                 struct dwc3_gadget_ep_cmd_params params;
2042                 int ret;
2043
2044                 dep = dwc->eps[epnum];
2045                 if (!dep)
2046                         continue;
2047
2048                 if (!(dep->flags & DWC3_EP_STALL))
2049                         continue;
2050
2051                 dep->flags &= ~DWC3_EP_STALL;
2052
2053                 memset(&params, 0, sizeof(params));
2054                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2055                                 DWC3_DEPCMD_CLEARSTALL, &params);
2056                 WARN_ON_ONCE(ret);
2057         }
2058 }
2059
2060 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2061 {
2062         int                     reg;
2063
2064         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2065         reg &= ~DWC3_DCTL_INITU1ENA;
2066         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2067
2068         reg &= ~DWC3_DCTL_INITU2ENA;
2069         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2070
2071         dwc3_disconnect_gadget(dwc);
2072         dwc->start_config_issued = false;
2073
2074         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2075         dwc->setup_packet_pending = false;
2076         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2077 }
2078
2079 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2080 {
2081         u32                     reg;
2082
2083         /*
2084          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2085          * would cause a missing Disconnect Event if there's a
2086          * pending Setup Packet in the FIFO.
2087          *
2088          * There's no suggested workaround on the official Bug
2089          * report, which states that "unless the driver/application
2090          * is doing any special handling of a disconnect event,
2091          * there is no functional issue".
2092          *
2093          * Unfortunately, it turns out that we _do_ some special
2094          * handling of a disconnect event, namely complete all
2095          * pending transfers, notify gadget driver of the
2096          * disconnection, and so on.
2097          *
2098          * Our suggested workaround is to follow the Disconnect
2099          * Event steps here, instead, based on a setup_packet_pending
2100          * flag. Such flag gets set whenever we have a XferNotReady
2101          * event on EP0 and gets cleared on XferComplete for the
2102          * same endpoint.
2103          *
2104          * Refers to:
2105          *
2106          * STAR#9000466709: RTL: Device : Disconnect event not
2107          * generated if setup packet pending in FIFO
2108          */
2109         if (dwc->revision < DWC3_REVISION_188A) {
2110                 if (dwc->setup_packet_pending)
2111                         dwc3_gadget_disconnect_interrupt(dwc);
2112         }
2113
2114         dwc3_reset_gadget(dwc);
2115
2116         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2117         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2118         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2119         dwc->test_mode = false;
2120
2121         dwc3_stop_active_transfers(dwc);
2122         dwc3_clear_stall_all_ep(dwc);
2123         dwc->start_config_issued = false;
2124
2125         /* Reset device address to zero */
2126         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2127         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2128         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2129 }
2130
2131 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2132 {
2133         u32 reg;
2134         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2135
2136         /*
2137          * We change the clock only at SS but I dunno why I would want to do
2138          * this. Maybe it becomes part of the power saving plan.
2139          */
2140
2141         if (speed != DWC3_DSTS_SUPERSPEED)
2142                 return;
2143
2144         /*
2145          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2146          * each time on Connect Done.
2147          */
2148         if (!usb30_clock)
2149                 return;
2150
2151         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2152         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2153         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2154 }
2155
2156 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2157 {
2158         struct dwc3_ep          *dep;
2159         int                     ret;
2160         u32                     reg;
2161         u8                      speed;
2162
2163         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2164         speed = reg & DWC3_DSTS_CONNECTSPD;
2165         dwc->speed = speed;
2166
2167         dwc3_update_ram_clk_sel(dwc, speed);
2168
2169         switch (speed) {
2170         case DWC3_DCFG_SUPERSPEED:
2171                 /*
2172                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2173                  * would cause a missing USB3 Reset event.
2174                  *
2175                  * In such situations, we should force a USB3 Reset
2176                  * event by calling our dwc3_gadget_reset_interrupt()
2177                  * routine.
2178                  *
2179                  * Refers to:
2180                  *
2181                  * STAR#9000483510: RTL: SS : USB3 reset event may
2182                  * not be generated always when the link enters poll
2183                  */
2184                 if (dwc->revision < DWC3_REVISION_190A)
2185                         dwc3_gadget_reset_interrupt(dwc);
2186
2187                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2188                 dwc->gadget.ep0->maxpacket = 512;
2189                 dwc->gadget.speed = USB_SPEED_SUPER;
2190                 break;
2191         case DWC3_DCFG_HIGHSPEED:
2192                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2193                 dwc->gadget.ep0->maxpacket = 64;
2194                 dwc->gadget.speed = USB_SPEED_HIGH;
2195                 break;
2196         case DWC3_DCFG_FULLSPEED2:
2197         case DWC3_DCFG_FULLSPEED1:
2198                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2199                 dwc->gadget.ep0->maxpacket = 64;
2200                 dwc->gadget.speed = USB_SPEED_FULL;
2201                 break;
2202         case DWC3_DCFG_LOWSPEED:
2203                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2204                 dwc->gadget.ep0->maxpacket = 8;
2205                 dwc->gadget.speed = USB_SPEED_LOW;
2206                 break;
2207         }
2208
2209         /* Enable USB2 LPM Capability */
2210
2211         if ((dwc->revision > DWC3_REVISION_194A)
2212                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2213                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2214                 reg |= DWC3_DCFG_LPM_CAP;
2215                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2216
2217                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2218                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2219
2220                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2221
2222                 /*
2223                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2224                  * DCFG.LPMCap is set, core responses with an ACK and the
2225                  * BESL value in the LPM token is less than or equal to LPM
2226                  * NYET threshold.
2227                  */
2228                 if (dwc->revision < DWC3_REVISION_240A  && dwc->has_lpm_erratum)
2229                         WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2230
2231                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2232                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2233
2234                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2235         } else {
2236                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2237                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2238                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2239         }
2240
2241         dep = dwc->eps[0];
2242         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2243                         false);
2244         if (ret) {
2245                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2246                 return;
2247         }
2248
2249         dep = dwc->eps[1];
2250         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2251                         false);
2252         if (ret) {
2253                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2254                 return;
2255         }
2256
2257         /*
2258          * Configure PHY via GUSB3PIPECTLn if required.
2259          *
2260          * Update GTXFIFOSIZn
2261          *
2262          * In both cases reset values should be sufficient.
2263          */
2264 }
2265
2266 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2267 {
2268         /*
2269          * TODO take core out of low power mode when that's
2270          * implemented.
2271          */
2272
2273         dwc->gadget_driver->resume(&dwc->gadget);
2274 }
2275
2276 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2277                 unsigned int evtinfo)
2278 {
2279         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2280         unsigned int            pwropt;
2281
2282         /*
2283          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2284          * Hibernation mode enabled which would show up when device detects
2285          * host-initiated U3 exit.
2286          *
2287          * In that case, device will generate a Link State Change Interrupt
2288          * from U3 to RESUME which is only necessary if Hibernation is
2289          * configured in.
2290          *
2291          * There are no functional changes due to such spurious event and we
2292          * just need to ignore it.
2293          *
2294          * Refers to:
2295          *
2296          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2297          * operational mode
2298          */
2299         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2300         if ((dwc->revision < DWC3_REVISION_250A) &&
2301                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2302                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2303                                 (next == DWC3_LINK_STATE_RESUME)) {
2304                         dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2305                         return;
2306                 }
2307         }
2308
2309         /*
2310          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2311          * on the link partner, the USB session might do multiple entry/exit
2312          * of low power states before a transfer takes place.
2313          *
2314          * Due to this problem, we might experience lower throughput. The
2315          * suggested workaround is to disable DCTL[12:9] bits if we're
2316          * transitioning from U1/U2 to U0 and enable those bits again
2317          * after a transfer completes and there are no pending transfers
2318          * on any of the enabled endpoints.
2319          *
2320          * This is the first half of that workaround.
2321          *
2322          * Refers to:
2323          *
2324          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2325          * core send LGO_Ux entering U0
2326          */
2327         if (dwc->revision < DWC3_REVISION_183A) {
2328                 if (next == DWC3_LINK_STATE_U0) {
2329                         u32     u1u2;
2330                         u32     reg;
2331
2332                         switch (dwc->link_state) {
2333                         case DWC3_LINK_STATE_U1:
2334                         case DWC3_LINK_STATE_U2:
2335                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2336                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2337                                                 | DWC3_DCTL_ACCEPTU2ENA
2338                                                 | DWC3_DCTL_INITU1ENA
2339                                                 | DWC3_DCTL_ACCEPTU1ENA);
2340
2341                                 if (!dwc->u1u2)
2342                                         dwc->u1u2 = reg & u1u2;
2343
2344                                 reg &= ~u1u2;
2345
2346                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2347                                 break;
2348                         default:
2349                                 /* do nothing */
2350                                 break;
2351                         }
2352                 }
2353         }
2354
2355         switch (next) {
2356         case DWC3_LINK_STATE_U1:
2357                 if (dwc->speed == USB_SPEED_SUPER)
2358                         dwc3_suspend_gadget(dwc);
2359                 break;
2360         case DWC3_LINK_STATE_U2:
2361         case DWC3_LINK_STATE_U3:
2362                 dwc3_suspend_gadget(dwc);
2363                 break;
2364         case DWC3_LINK_STATE_RESUME:
2365                 dwc3_resume_gadget(dwc);
2366                 break;
2367         default:
2368                 /* do nothing */
2369                 break;
2370         }
2371
2372         dwc->link_state = next;
2373 }
2374
2375 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2376                 unsigned int evtinfo)
2377 {
2378         unsigned int is_ss = evtinfo & (1UL << 4);
2379
2380         /**
2381          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2382          * have a known issue which can cause USB CV TD.9.23 to fail
2383          * randomly.
2384          *
2385          * Because of this issue, core could generate bogus hibernation
2386          * events which SW needs to ignore.
2387          *
2388          * Refers to:
2389          *
2390          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2391          * Device Fallback from SuperSpeed
2392          */
2393         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2394                 return;
2395
2396         /* enter hibernation here */
2397 }
2398
2399 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2400                 const struct dwc3_event_devt *event)
2401 {
2402         switch (event->type) {
2403         case DWC3_DEVICE_EVENT_DISCONNECT:
2404                 dwc3_gadget_disconnect_interrupt(dwc);
2405                 break;
2406         case DWC3_DEVICE_EVENT_RESET:
2407                 dwc3_gadget_reset_interrupt(dwc);
2408                 break;
2409         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2410                 dwc3_gadget_conndone_interrupt(dwc);
2411                 break;
2412         case DWC3_DEVICE_EVENT_WAKEUP:
2413                 dwc3_gadget_wakeup_interrupt(dwc);
2414                 break;
2415         case DWC3_DEVICE_EVENT_HIBER_REQ:
2416                 if (!dwc->has_hibernation) {
2417                         WARN(1 ,"unexpected hibernation event\n");
2418                         break;
2419                 }
2420                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2421                 break;
2422         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2423                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2424                 break;
2425         case DWC3_DEVICE_EVENT_EOPF:
2426                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2427                 break;
2428         case DWC3_DEVICE_EVENT_SOF:
2429                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2430                 break;
2431         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2432                 dev_vdbg(dwc->dev, "Erratic Error\n");
2433                 break;
2434         case DWC3_DEVICE_EVENT_CMD_CMPL:
2435                 dev_vdbg(dwc->dev, "Command Complete\n");
2436                 break;
2437         case DWC3_DEVICE_EVENT_OVERFLOW:
2438                 dev_vdbg(dwc->dev, "Overflow\n");
2439                 break;
2440         default:
2441                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2442         }
2443 }
2444
2445 static void dwc3_process_event_entry(struct dwc3 *dwc,
2446                 const union dwc3_event *event)
2447 {
2448         /* Endpoint IRQ, handle it and return early */
2449         if (event->type.is_devspec == 0) {
2450                 /* depevt */
2451                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2452         }
2453
2454         switch (event->type.type) {
2455         case DWC3_EVENT_TYPE_DEV:
2456                 dwc3_gadget_interrupt(dwc, &event->devt);
2457                 break;
2458         /* REVISIT what to do with Carkit and I2C events ? */
2459         default:
2460                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2461         }
2462 }
2463
2464 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2465 {
2466         struct dwc3_event_buffer *evt;
2467         irqreturn_t ret = IRQ_NONE;
2468         int left;
2469         u32 reg;
2470
2471         evt = dwc->ev_buffs[buf];
2472         left = evt->count;
2473
2474         if (!(evt->flags & DWC3_EVENT_PENDING))
2475                 return IRQ_NONE;
2476
2477         while (left > 0) {
2478                 union dwc3_event event;
2479
2480                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2481
2482                 dwc3_process_event_entry(dwc, &event);
2483
2484                 /*
2485                  * FIXME we wrap around correctly to the next entry as
2486                  * almost all entries are 4 bytes in size. There is one
2487                  * entry which has 12 bytes which is a regular entry
2488                  * followed by 8 bytes data. ATM I don't know how
2489                  * things are organized if we get next to the a
2490                  * boundary so I worry about that once we try to handle
2491                  * that.
2492                  */
2493                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2494                 left -= 4;
2495
2496                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2497         }
2498
2499         evt->count = 0;
2500         evt->flags &= ~DWC3_EVENT_PENDING;
2501         ret = IRQ_HANDLED;
2502
2503         /* Unmask interrupt */
2504         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2505         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2506         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2507
2508         return ret;
2509 }
2510
2511 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2512 {
2513         struct dwc3 *dwc = _dwc;
2514         unsigned long flags;
2515         irqreturn_t ret = IRQ_NONE;
2516         int i;
2517
2518         spin_lock_irqsave(&dwc->lock, flags);
2519
2520         for (i = 0; i < dwc->num_event_buffers; i++)
2521                 ret |= dwc3_process_event_buf(dwc, i);
2522
2523         spin_unlock_irqrestore(&dwc->lock, flags);
2524
2525         return ret;
2526 }
2527
2528 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2529 {
2530         struct dwc3_event_buffer *evt;
2531         u32 count;
2532         u32 reg;
2533
2534         evt = dwc->ev_buffs[buf];
2535
2536         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2537         count &= DWC3_GEVNTCOUNT_MASK;
2538         if (!count)
2539                 return IRQ_NONE;
2540
2541         evt->count = count;
2542         evt->flags |= DWC3_EVENT_PENDING;
2543
2544         /* Mask interrupt */
2545         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2546         reg |= DWC3_GEVNTSIZ_INTMASK;
2547         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2548
2549         return IRQ_WAKE_THREAD;
2550 }
2551
2552 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2553 {
2554         struct dwc3                     *dwc = _dwc;
2555         int                             i;
2556         irqreturn_t                     ret = IRQ_NONE;
2557
2558         spin_lock(&dwc->lock);
2559
2560         for (i = 0; i < dwc->num_event_buffers; i++) {
2561                 irqreturn_t status;
2562
2563                 status = dwc3_check_event_buf(dwc, i);
2564                 if (status == IRQ_WAKE_THREAD)
2565                         ret = status;
2566         }
2567
2568         spin_unlock(&dwc->lock);
2569
2570         return ret;
2571 }
2572
2573 /**
2574  * dwc3_gadget_init - Initializes gadget related registers
2575  * @dwc: pointer to our controller context structure
2576  *
2577  * Returns 0 on success otherwise negative errno.
2578  */
2579 int dwc3_gadget_init(struct dwc3 *dwc)
2580 {
2581         int                                     ret;
2582
2583         dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
2584                                         (unsigned long *)&dwc->ctrl_req_addr);
2585         if (!dwc->ctrl_req) {
2586                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2587                 ret = -ENOMEM;
2588                 goto err0;
2589         }
2590
2591         dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb) * 2,
2592                                           (unsigned long *)&dwc->ep0_trb_addr);
2593         if (!dwc->ep0_trb) {
2594                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2595                 ret = -ENOMEM;
2596                 goto err1;
2597         }
2598
2599         dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
2600                                   DWC3_EP0_BOUNCE_SIZE);
2601         if (!dwc->setup_buf) {
2602                 ret = -ENOMEM;
2603                 goto err2;
2604         }
2605
2606         dwc->ep0_bounce = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
2607                                         (unsigned long *)&dwc->ep0_bounce_addr);
2608         if (!dwc->ep0_bounce) {
2609                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2610                 ret = -ENOMEM;
2611                 goto err3;
2612         }
2613
2614         dwc->gadget.ops                 = &dwc3_gadget_ops;
2615         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2616         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2617         dwc->gadget.name                = "dwc3-gadget";
2618
2619         /*
2620          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2621          * on ep out.
2622          */
2623         dwc->gadget.quirk_ep_out_aligned_size = true;
2624
2625         /*
2626          * REVISIT: Here we should clear all pending IRQs to be
2627          * sure we're starting from a well known location.
2628          */
2629
2630         ret = dwc3_gadget_init_endpoints(dwc);
2631         if (ret)
2632                 goto err4;
2633
2634         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2635         if (ret) {
2636                 dev_err(dwc->dev, "failed to register udc\n");
2637                 goto err4;
2638         }
2639
2640         return 0;
2641
2642 err4:
2643         dwc3_gadget_free_endpoints(dwc);
2644         dma_free_coherent(dwc->ep0_bounce);
2645
2646 err3:
2647         kfree(dwc->setup_buf);
2648
2649 err2:
2650         dma_free_coherent(dwc->ep0_trb);
2651
2652 err1:
2653         dma_free_coherent(dwc->ctrl_req);
2654
2655 err0:
2656         return ret;
2657 }
2658
2659 /* -------------------------------------------------------------------------- */
2660
2661 void dwc3_gadget_exit(struct dwc3 *dwc)
2662 {
2663         usb_del_gadget_udc(&dwc->gadget);
2664
2665         dwc3_gadget_free_endpoints(dwc);
2666
2667         dma_free_coherent(dwc->ep0_bounce);
2668
2669         kfree(dwc->setup_buf);
2670
2671         dma_free_coherent(dwc->ep0_trb);
2672
2673         dma_free_coherent(dwc->ctrl_req);
2674 }
2675
2676 /**
2677  * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
2678  * @dwc: struct dwce *
2679  *
2680  * Handles ep0 and gadget interrupt
2681  *
2682  * Should be called from dwc3 core.
2683  */
2684 void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
2685 {
2686         dwc3_interrupt(0, dwc);
2687         dwc3_thread_interrupt(0, dwc);
2688 }