drivers/usb/gadget/pxa25x_udc.c

   1 /*
   2  * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
   3  *
   4  * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
   5  * Copyright (C) 2003 Robert Schwebel, Pengutronix
   6  * Copyright (C) 2003 Benedikt Spranger, Pengutronix
   7  * Copyright (C) 2003 David Brownell
   8  * Copyright (C) 2003 Joshua Wise
   9  * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  *
  13  * MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
  14  */
  15
  16 #define CONFIG_USB_PXA25X_SMALL
  17 #define DRIVER_NAME "pxa25x_udc_linux"
  18 #define ARCH_HAS_PREFETCH
  19
  20 #include <common.h>
  21 #include <errno.h>
  22 #include <asm/byteorder.h>
  23 #include <asm/system.h>
  24 #include <asm/mach-types.h>
  25 #include <asm/unaligned.h>
  26 #include <linux/compat.h>
  27 #include <malloc.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/pxa.h>
  30
  31 #include <linux/usb/ch9.h>
  32 #include <linux/usb/gadget.h>
  33 #include <usb/lin_gadget_compat.h>
  34 #include <asm/arch/pxa-regs.h>
  35
  36 #include "pxa25x_udc.h"
  37
  38 /*
  39  * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
  40  * series processors.  The UDC for the IXP 4xx series is very similar.
  41  * There are fifteen endpoints, in addition to ep0.
  42  *
  43  * Such controller drivers work with a gadget driver.  The gadget driver
  44  * returns descriptors, implements configuration and data protocols used
  45  * by the host to interact with this device, and allocates endpoints to
  46  * the different protocol interfaces.  The controller driver virtualizes
  47  * usb hardware so that the gadget drivers will be more portable.
  48  *
  49  * This UDC hardware wants to implement a bit too much USB protocol, so
  50  * it constrains the sorts of USB configuration change events that work.
  51  * The errata for these chips are misleading; some "fixed" bugs from
  52  * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
  53  *
  54  * Note that the UDC hardware supports DMA (except on IXP) but that's
  55  * not used here.  IN-DMA (to host) is simple enough, when the data is
  56  * suitably aligned (16 bytes) ... the network stack doesn't do that,
  57  * other software can.  OUT-DMA is buggy in most chip versions, as well
  58  * as poorly designed (data toggle not automatic).  So this driver won't
  59  * bother using DMA.  (Mostly-working IN-DMA support was available in
  60  * kernels before 2.6.23, but was never enabled or well tested.)
  61  */
  62
  63 #define DRIVER_VERSION  "18-August-2012"
  64 #define DRIVER_DESC     "PXA 25x USB Device Controller driver"
  65
  66 static const char driver_name[] = "pxa25x_udc";
  67 static const char ep0name[] = "ep0";
  68
  69 /* Watchdog */
  70 static inline void start_watchdog(struct pxa25x_udc *udc)
  71 {
  72         debug("Started watchdog\n");
  73         udc->watchdog.base = get_timer(0);
  74         udc->watchdog.running = 1;
  75 }
  76
  77 static inline void stop_watchdog(struct pxa25x_udc *udc)
  78 {
  79         udc->watchdog.running = 0;
  80         debug("Stopped watchdog\n");
  81 }
  82
  83 static inline void test_watchdog(struct pxa25x_udc *udc)
  84 {
  85         if (!udc->watchdog.running)
  86                 return;
  87
  88         debug("watchdog %ld %ld\n", get_timer(udc->watchdog.base),
  89                 udc->watchdog.period);
  90
  91         if (get_timer(udc->watchdog.base) >= udc->watchdog.period) {
  92                 stop_watchdog(udc);
  93                 udc->watchdog.function(udc);
  94         }
  95 }
  96
  97 static void udc_watchdog(struct pxa25x_udc *dev)
  98 {
  99         uint32_t udccs0 = readl(&dev->regs->udccs[0]);
 100
 101         debug("Fired up udc_watchdog\n");
 102
 103         local_irq_disable();
 104         if (dev->ep0state == EP0_STALL
 105                         && (udccs0 & UDCCS0_FST) == 0
 106                         && (udccs0 & UDCCS0_SST) == 0) {
 107                 writel(UDCCS0_FST|UDCCS0_FTF, &dev->regs->udccs[0]);
 108                 debug("ep0 re-stall\n");
 109                 start_watchdog(dev);
 110         }
 111         local_irq_enable();
 112 }
 113
 114 #ifdef DEBUG
 115
 116 static const char * const state_name[] = {
 117         "EP0_IDLE",
 118         "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
 119         "EP0_END_XFER", "EP0_STALL"
 120 };
 121
 122 static void
 123 dump_udccr(const char *label)
 124 {
 125         u32 udccr = readl(&UDC_REGS->udccr);
 126         debug("%s %02X =%s%s%s%s%s%s%s%s\n",
 127                 label, udccr,
 128                 (udccr & UDCCR_REM) ? " rem" : "",
 129                 (udccr & UDCCR_RSTIR) ? " rstir" : "",
 130                 (udccr & UDCCR_SRM) ? " srm" : "",
 131                 (udccr & UDCCR_SUSIR) ? " susir" : "",
 132                 (udccr & UDCCR_RESIR) ? " resir" : "",
 133                 (udccr & UDCCR_RSM) ? " rsm" : "",
 134                 (udccr & UDCCR_UDA) ? " uda" : "",
 135                 (udccr & UDCCR_UDE) ? " ude" : "");
 136 }
 137
 138 static void
 139 dump_udccs0(const char *label)
 140 {
 141         u32 udccs0 = readl(&UDC_REGS->udccs[0]);
 142
 143         debug("%s %s %02X =%s%s%s%s%s%s%s%s\n",
 144                 label, state_name[the_controller->ep0state], udccs0,
 145                 (udccs0 & UDCCS0_SA) ? " sa" : "",
 146                 (udccs0 & UDCCS0_RNE) ? " rne" : "",
 147                 (udccs0 & UDCCS0_FST) ? " fst" : "",
 148                 (udccs0 & UDCCS0_SST) ? " sst" : "",
 149                 (udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
 150                 (udccs0 & UDCCS0_FTF) ? " ftf" : "",
 151                 (udccs0 & UDCCS0_IPR) ? " ipr" : "",
 152                 (udccs0 & UDCCS0_OPR) ? " opr" : "");
 153 }
 154
 155 static void
 156 dump_state(struct pxa25x_udc *dev)
 157 {
 158         u32 tmp;
 159         unsigned i;
 160
 161         debug("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
 162                 state_name[dev->ep0state],
 163                 readl(&UDC_REGS->uicr1), readl(&UDC_REGS->uicr0),
 164                 readl(&UDC_REGS->usir1), readl(&UDC_REGS->usir0),
 165                 readl(&UDC_REGS->ufnrh), readl(&UDC_REGS->ufnrl));
 166         dump_udccr("udccr");
 167         if (dev->has_cfr) {
 168                 tmp = readl(&UDC_REGS->udccfr);
 169                 debug("udccfr %02X =%s%s\n", tmp,
 170                         (tmp & UDCCFR_AREN) ? " aren" : "",
 171                         (tmp & UDCCFR_ACM) ? " acm" : "");
 172         }
 173
 174         if (!dev->driver) {
 175                 debug("no gadget driver bound\n");
 176                 return;
 177         } else
 178                 debug("ep0 driver '%s'\n", "ether");
 179
 180         dump_udccs0("udccs0");
 181         debug("ep0 IN %lu/%lu, OUT %lu/%lu\n",
 182                 dev->stats.write.bytes, dev->stats.write.ops,
 183                 dev->stats.read.bytes, dev->stats.read.ops);
 184
 185         for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
 186                 if (dev->ep[i].desc == NULL)
 187                         continue;
 188                 debug("udccs%d = %02x\n", i, *dev->ep->reg_udccs);
 189         }
 190 }
 191
 192 #else /* DEBUG */
 193
 194 static inline void dump_udccr(const char *label) { }
 195 static inline void dump_udccs0(const char *label) { }
 196 static inline void dump_state(struct pxa25x_udc *dev) { }
 197
 198 #endif /* DEBUG */
 199
 200 /*
 201  * ---------------------------------------------------------------------------
 202  *      endpoint related parts of the api to the usb controller hardware,
 203  *      used by gadget driver; and the inner talker-to-hardware core.
 204  * ---------------------------------------------------------------------------
 205  */
 206
 207 static void pxa25x_ep_fifo_flush(struct usb_ep *ep);
 208 static void nuke(struct pxa25x_ep *, int status);
 209
 210 /* one GPIO should control a D+ pullup, so host sees this device (or not) */
 211 static void pullup_off(void)
 212 {
 213         struct pxa2xx_udc_mach_info *mach = the_controller->mach;
 214
 215         if (mach->udc_command)
 216                 mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
 217 }
 218
 219 static void pullup_on(void)
 220 {
 221         struct pxa2xx_udc_mach_info *mach = the_controller->mach;
 222
 223         if (mach->udc_command)
 224                 mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
 225 }
 226
 227 static void pio_irq_enable(int bEndpointAddress)
 228 {
 229         bEndpointAddress &= 0xf;
 230         if (bEndpointAddress < 8) {
 231                 clrbits_le32(&the_controller->regs->uicr0,
 232                         1 << bEndpointAddress);
 233         } else {
 234                 bEndpointAddress -= 8;
 235                 clrbits_le32(&the_controller->regs->uicr1,
 236                         1 << bEndpointAddress);
 237         }
 238 }
 239
 240 static void pio_irq_disable(int bEndpointAddress)
 241 {
 242         bEndpointAddress &= 0xf;
 243         if (bEndpointAddress < 8) {
 244                 setbits_le32(&the_controller->regs->uicr0,
 245                         1 << bEndpointAddress);
 246         } else {
 247                 bEndpointAddress -= 8;
 248                 setbits_le32(&the_controller->regs->uicr1,
 249                         1 << bEndpointAddress);
 250         }
 251 }
 252
 253 static inline void udc_set_mask_UDCCR(int mask)
 254 {
 255         /*
 256          * The UDCCR reg contains mask and interrupt status bits,
 257          * so using '|=' isn't safe as it may ack an interrupt.
 258          */
 259         const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
 260
 261         mask &= mask_bits;
 262         clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
 263 }
 264
 265 static inline void udc_clear_mask_UDCCR(int mask)
 266 {
 267         const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
 268
 269         mask = ~mask & mask_bits;
 270         clrbits_le32(&the_controller->regs->udccr, ~mask);
 271 }
 272
 273 static inline void udc_ack_int_UDCCR(int mask)
 274 {
 275         const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
 276
 277         mask &= ~mask_bits;
 278         clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
 279 }
 280
 281 /*
 282  * endpoint enable/disable
 283  *
 284  * we need to verify the descriptors used to enable endpoints.  since pxa25x
 285  * endpoint configurations are fixed, and are pretty much always enabled,
 286  * there's not a lot to manage here.
 287  *
 288  * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
 289  * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
 290  * for a single interface (with only the default altsetting) and for gadget
 291  * drivers that don't halt endpoints (not reset by set_interface).  that also
 292  * means that if you use ISO, you must violate the USB spec rule that all
 293  * iso endpoints must be in non-default altsettings.
 294  */
 295 static int pxa25x_ep_enable(struct usb_ep *_ep,
 296                 const struct usb_endpoint_descriptor *desc)
 297 {
 298         struct pxa25x_ep *ep;
 299         struct pxa25x_udc *dev;
 300
 301         ep = container_of(_ep, struct pxa25x_ep, ep);
 302         if (!_ep || !desc || ep->desc || _ep->name == ep0name
 303                         || desc->bDescriptorType != USB_DT_ENDPOINT
 304                         || ep->bEndpointAddress != desc->bEndpointAddress
 305                         || ep->fifo_size <
 306                            le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
 307                 printf("%s, bad ep or descriptor\n", __func__);
 308                 return -EINVAL;
 309         }
 310
 311         /* xfer types must match, except that interrupt ~= bulk */
 312         if (ep->bmAttributes != desc->bmAttributes
 313                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 314                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 315                 printf("%s, %s type mismatch\n", __func__, _ep->name);
 316                 return -EINVAL;
 317         }
 318
 319         /* hardware _could_ do smaller, but driver doesn't */
 320         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 321                         && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))
 322                                                 != BULK_FIFO_SIZE)
 323                         || !get_unaligned(&desc->wMaxPacketSize)) {
 324                 printf("%s, bad %s maxpacket\n", __func__, _ep->name);
 325                 return -ERANGE;
 326         }
 327
 328         dev = ep->dev;
 329         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
 330                 printf("%s, bogus device state\n", __func__);
 331                 return -ESHUTDOWN;
 332         }
 333
 334         ep->desc = desc;
 335         ep->stopped = 0;
 336         ep->pio_irqs = 0;
 337         ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
 338
 339         /* flush fifo (mostly for OUT buffers) */
 340         pxa25x_ep_fifo_flush(_ep);
 341
 342         /* ... reset halt state too, if we could ... */
 343
 344         debug("enabled %s\n", _ep->name);
 345         return 0;
 346 }
 347
 348 static int pxa25x_ep_disable(struct usb_ep *_ep)
 349 {
 350         struct pxa25x_ep *ep;
 351         unsigned long flags;
 352
 353         ep = container_of(_ep, struct pxa25x_ep, ep);
 354         if (!_ep || !ep->desc) {
 355                 printf("%s, %s not enabled\n", __func__,
 356                         _ep ? ep->ep.name : NULL);
 357                 return -EINVAL;
 358         }
 359         local_irq_save(flags);
 360
 361         nuke(ep, -ESHUTDOWN);
 362
 363         /* flush fifo (mostly for IN buffers) */
 364         pxa25x_ep_fifo_flush(_ep);
 365
 366         ep->desc = NULL;
 367         ep->stopped = 1;
 368
 369         local_irq_restore(flags);
 370         debug("%s disabled\n", _ep->name);
 371         return 0;
 372 }
 373
 374 /*-------------------------------------------------------------------------*/
 375
 376 /*
 377  * for the pxa25x, these can just wrap kmalloc/kfree.  gadget drivers
 378  * must still pass correctly initialized endpoints, since other controller
 379  * drivers may care about how it's currently set up (dma issues etc).
 380  */
 381
 382 /*
 383  *      pxa25x_ep_alloc_request - allocate a request data structure
 384  */
 385 static struct usb_request *
 386 pxa25x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 387 {
 388         struct pxa25x_request *req;
 389
 390         req = kzalloc(sizeof(*req), gfp_flags);
 391         if (!req)
 392                 return NULL;
 393
 394         INIT_LIST_HEAD(&req->queue);
 395         return &req->req;
 396 }
 397
 398
 399 /*
 400  *      pxa25x_ep_free_request - deallocate a request data structure
 401  */
 402 static void
 403 pxa25x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
 404 {
 405         struct pxa25x_request   *req;
 406
 407         req = container_of(_req, struct pxa25x_request, req);
 408         WARN_ON(!list_empty(&req->queue));
 409         kfree(req);
 410 }
 411
 412 /*-------------------------------------------------------------------------*/
 413
 414 /*
 415  *      done - retire a request; caller blocked irqs
 416  */
 417 static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
 418 {
 419         unsigned stopped = ep->stopped;
 420
 421         list_del_init(&req->queue);
 422
 423         if (likely(req->req.status == -EINPROGRESS))
 424                 req->req.status = status;
 425         else
 426                 status = req->req.status;
 427
 428         if (status && status != -ESHUTDOWN)
 429                 debug("complete %s req %p stat %d len %u/%u\n",
 430                         ep->ep.name, &req->req, status,
 431                         req->req.actual, req->req.length);
 432
 433         /* don't modify queue heads during completion callback */
 434         ep->stopped = 1;
 435         req->req.complete(&ep->ep, &req->req);
 436         ep->stopped = stopped;
 437 }
 438
 439
 440 static inline void ep0_idle(struct pxa25x_udc *dev)
 441 {
 442         dev->ep0state = EP0_IDLE;
 443 }
 444
 445 static int
 446 write_packet(u32 *uddr, struct pxa25x_request *req, unsigned max)
 447 {
 448         u8 *buf;
 449         unsigned length, count;
 450
 451         debug("%s(): uddr %p\n", __func__, uddr);
 452
 453         buf = req->req.buf + req->req.actual;
 454         prefetch(buf);
 455
 456         /* how big will this packet be? */
 457         length = min(req->req.length - req->req.actual, max);
 458         req->req.actual += length;
 459
 460         count = length;
 461         while (likely(count--))
 462                 writeb(*buf++, uddr);
 463
 464         return length;
 465 }
 466
 467 /*
 468  * write to an IN endpoint fifo, as many packets as possible.
 469  * irqs will use this to write the rest later.
 470  * caller guarantees at least one packet buffer is ready (or a zlp).
 471  */
 472 static int
 473 write_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
 474 {
 475         unsigned max;
 476
 477         max = le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize));
 478         do {
 479                 unsigned count;
 480                 int is_last, is_short;
 481
 482                 count = write_packet(ep->reg_uddr, req, max);
 483
 484                 /* last packet is usually short (or a zlp) */
 485                 if (unlikely(count != max))
 486                         is_last = is_short = 1;
 487                 else {
 488                         if (likely(req->req.length != req->req.actual)
 489                                         || req->req.zero)
 490                                 is_last = 0;
 491                         else
 492                                 is_last = 1;
 493                         /* interrupt/iso maxpacket may not fill the fifo */
 494                         is_short = unlikely(max < ep->fifo_size);
 495                 }
 496
 497                 debug_cond(NOISY, "wrote %s %d bytes%s%s %d left %p\n",
 498                         ep->ep.name, count,
 499                         is_last ? "/L" : "", is_short ? "/S" : "",
 500                         req->req.length - req->req.actual, req);
 501
 502                 /*
 503                  * let loose that packet. maybe try writing another one,
 504                  * double buffering might work.  TSP, TPC, and TFS
 505                  * bit values are the same for all normal IN endpoints.
 506                  */
 507                 writel(UDCCS_BI_TPC, ep->reg_udccs);
 508                 if (is_short)
 509                         writel(UDCCS_BI_TSP, ep->reg_udccs);
 510
 511                 /* requests complete when all IN data is in the FIFO */
 512                 if (is_last) {
 513                         done(ep, req, 0);
 514                         if (list_empty(&ep->queue))
 515                                 pio_irq_disable(ep->bEndpointAddress);
 516                         return 1;
 517                 }
 518
 519                 /*
 520                  * TODO experiment: how robust can fifo mode tweaking be?
 521                  * double buffering is off in the default fifo mode, which
 522                  * prevents TFS from being set here.
 523                  */
 524
 525         } while (readl(ep->reg_udccs) & UDCCS_BI_TFS);
 526         return 0;
 527 }
 528
 529 /*
 530  * caller asserts req->pending (ep0 irq status nyet cleared); starts
 531  * ep0 data stage.  these chips want very simple state transitions.
 532  */
 533 static inline
 534 void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
 535 {
 536         writel(flags|UDCCS0_SA|UDCCS0_OPR, &dev->regs->udccs[0]);
 537         writel(USIR0_IR0, &dev->regs->usir0);
 538         dev->req_pending = 0;
 539         debug_cond(NOISY, "%s() %s, udccs0: %02x/%02x usir: %X.%X\n",
 540                 __func__, tag, readl(&dev->regs->udccs[0]), flags,
 541                 readl(&dev->regs->usir1), readl(&dev->regs->usir0));
 542 }
 543
 544 static int
 545 write_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
 546 {
 547         unsigned count;
 548         int is_short;
 549
 550         count = write_packet(&ep->dev->regs->uddr0, req, EP0_FIFO_SIZE);
 551         ep->dev->stats.write.bytes += count;
 552
 553         /* last packet "must be" short (or a zlp) */
 554         is_short = (count != EP0_FIFO_SIZE);
 555
 556         debug_cond(NOISY, "ep0in %d bytes %d left %p\n", count,
 557                 req->req.length - req->req.actual, req);
 558
 559         if (unlikely(is_short)) {
 560                 if (ep->dev->req_pending)
 561                         ep0start(ep->dev, UDCCS0_IPR, "short IN");
 562                 else
 563                         writel(UDCCS0_IPR, &ep->dev->regs->udccs[0]);
 564
 565                 count = req->req.length;
 566                 done(ep, req, 0);
 567                 ep0_idle(ep->dev);
 568
 569                 /*
 570                  * This seems to get rid of lost status irqs in some cases:
 571                  * host responds quickly, or next request involves config
 572                  * change automagic, or should have been hidden, or ...
 573                  *
 574                  * FIXME get rid of all udelays possible...
 575                  */
 576                 if (count >= EP0_FIFO_SIZE) {
 577                         count = 100;
 578                         do {
 579                                 if ((readl(&ep->dev->regs->udccs[0]) &
 580                                      UDCCS0_OPR) != 0) {
 581                                         /* clear OPR, generate ack */
 582                                         writel(UDCCS0_OPR,
 583                                                 &ep->dev->regs->udccs[0]);
 584                                         break;
 585                                 }
 586                                 count--;
 587                                 udelay(1);
 588                         } while (count);
 589                 }
 590         } else if (ep->dev->req_pending)
 591                 ep0start(ep->dev, 0, "IN");
 592
 593         return is_short;
 594 }
 595
 596
 597 /*
 598  * read_fifo -  unload packet(s) from the fifo we use for usb OUT
 599  * transfers and put them into the request.  caller should have made
 600  * sure there's at least one packet ready.
 601  *
 602  * returns true if the request completed because of short packet or the
 603  * request buffer having filled (and maybe overran till end-of-packet).
 604  */
 605 static int
 606 read_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
 607 {
 608         u32 udccs;
 609         u8 *buf;
 610         unsigned bufferspace, count, is_short;
 611
 612         for (;;) {
 613                 /*
 614                  * make sure there's a packet in the FIFO.
 615                  * UDCCS_{BO,IO}_RPC are all the same bit value.
 616                  * UDCCS_{BO,IO}_RNE are all the same bit value.
 617                  */
 618                 udccs = readl(ep->reg_udccs);
 619                 if (unlikely((udccs & UDCCS_BO_RPC) == 0))
 620                         break;
 621                 buf = req->req.buf + req->req.actual;
 622                 prefetchw(buf);
 623                 bufferspace = req->req.length - req->req.actual;
 624
 625                 /* read all bytes from this packet */
 626                 if (likely(udccs & UDCCS_BO_RNE)) {
 627                         count = 1 + (0x0ff & readl(ep->reg_ubcr));
 628                         req->req.actual += min(count, bufferspace);
 629                 } else /* zlp */
 630                         count = 0;
 631                 is_short = (count < ep->ep.maxpacket);
 632                 debug_cond(NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
 633                         ep->ep.name, udccs, count,
 634                         is_short ? "/S" : "",
 635                         req, req->req.actual, req->req.length);
 636                 while (likely(count-- != 0)) {
 637                         u8 byte = readb(ep->reg_uddr);
 638
 639                         if (unlikely(bufferspace == 0)) {
 640                                 /*
 641                                  * this happens when the driver's buffer
 642                                  * is smaller than what the host sent.
 643                                  * discard the extra data.
 644                                  */
 645                                 if (req->req.status != -EOVERFLOW)
 646                                         printf("%s overflow %d\n",
 647                                                 ep->ep.name, count);
 648                                 req->req.status = -EOVERFLOW;
 649                         } else {
 650                                 *buf++ = byte;
 651                                 bufferspace--;
 652                         }
 653                 }
 654                 writel(UDCCS_BO_RPC, ep->reg_udccs);
 655                 /* RPC/RSP/RNE could now reflect the other packet buffer */
 656
 657                 /* iso is one request per packet */
 658                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 659                         if (udccs & UDCCS_IO_ROF)
 660                                 req->req.status = -EHOSTUNREACH;
 661                         /* more like "is_done" */
 662                         is_short = 1;
 663                 }
 664
 665                 /* completion */
 666                 if (is_short || req->req.actual == req->req.length) {
 667                         done(ep, req, 0);
 668                         if (list_empty(&ep->queue))
 669                                 pio_irq_disable(ep->bEndpointAddress);
 670                         return 1;
 671                 }
 672
 673                 /* finished that packet.  the next one may be waiting... */
 674         }
 675         return 0;
 676 }
 677
 678 /*
 679  * special ep0 version of the above.  no UBCR0 or double buffering; status
 680  * handshaking is magic.  most device protocols don't need control-OUT.
 681  * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
 682  * protocols do use them.
 683  */
 684 static int
 685 read_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
 686 {
 687         u8 *buf, byte;
 688         unsigned bufferspace;
 689
 690         buf = req->req.buf + req->req.actual;
 691         bufferspace = req->req.length - req->req.actual;
 692
 693         while (readl(&ep->dev->regs->udccs[0]) & UDCCS0_RNE) {
 694                 byte = (u8)readb(&ep->dev->regs->uddr0);
 695
 696                 if (unlikely(bufferspace == 0)) {
 697                         /*
 698                          * this happens when the driver's buffer
 699                          * is smaller than what the host sent.
 700                          * discard the extra data.
 701                          */
 702                         if (req->req.status != -EOVERFLOW)
 703                                 printf("%s overflow\n", ep->ep.name);
 704                         req->req.status = -EOVERFLOW;
 705                 } else {
 706                         *buf++ = byte;
 707                         req->req.actual++;
 708                         bufferspace--;
 709                 }
 710         }
 711
 712         writel(UDCCS0_OPR | UDCCS0_IPR, &ep->dev->regs->udccs[0]);
 713
 714         /* completion */
 715         if (req->req.actual >= req->req.length)
 716                 return 1;
 717
 718         /* finished that packet.  the next one may be waiting... */
 719         return 0;
 720 }
 721
 722 /*-------------------------------------------------------------------------*/
 723
 724 static int
 725 pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 726 {
 727         struct pxa25x_request *req;
 728         struct pxa25x_ep *ep;
 729         struct pxa25x_udc *dev;
 730         unsigned long flags;
 731
 732         req = container_of(_req, struct pxa25x_request, req);
 733         if (unlikely(!_req || !_req->complete || !_req->buf
 734                         || !list_empty(&req->queue))) {
 735                 printf("%s, bad params\n", __func__);
 736                 return -EINVAL;
 737         }
 738
 739         ep = container_of(_ep, struct pxa25x_ep, ep);
 740         if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 741                 printf("%s, bad ep\n", __func__);
 742                 return -EINVAL;
 743         }
 744
 745         dev = ep->dev;
 746         if (unlikely(!dev->driver
 747                         || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 748                 printf("%s, bogus device state\n", __func__);
 749                 return -ESHUTDOWN;
 750         }
 751
 752         /*
 753          * iso is always one packet per request, that's the only way
 754          * we can report per-packet status.  that also helps with dma.
 755          */
 756         if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
 757                         && req->req.length >
 758                         le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize))))
 759                 return -EMSGSIZE;
 760
 761         debug_cond(NOISY, "%s queue req %p, len %d buf %p\n",
 762                 _ep->name, _req, _req->length, _req->buf);
 763
 764         local_irq_save(flags);
 765
 766         _req->status = -EINPROGRESS;
 767         _req->actual = 0;
 768
 769         /* kickstart this i/o queue? */
 770         if (list_empty(&ep->queue) && !ep->stopped) {
 771                 if (ep->desc == NULL/* ep0 */) {
 772                         unsigned length = _req->length;
 773
 774                         switch (dev->ep0state) {
 775                         case EP0_IN_DATA_PHASE:
 776                                 dev->stats.write.ops++;
 777                                 if (write_ep0_fifo(ep, req))
 778                                         req = NULL;
 779                                 break;
 780
 781                         case EP0_OUT_DATA_PHASE:
 782                                 dev->stats.read.ops++;
 783                                 /* messy ... */
 784                                 if (dev->req_config) {
 785                                         debug("ep0 config ack%s\n",
 786                                                 dev->has_cfr ?  "" : " raced");
 787                                         if (dev->has_cfr)
 788                                                 writel(UDCCFR_AREN|UDCCFR_ACM
 789                                                         |UDCCFR_MB1,
 790                                                         &ep->dev->regs->udccfr);
 791                                         done(ep, req, 0);
 792                                         dev->ep0state = EP0_END_XFER;
 793                                         local_irq_restore(flags);
 794                                         return 0;
 795                                 }
 796                                 if (dev->req_pending)
 797                                         ep0start(dev, UDCCS0_IPR, "OUT");
 798                                 if (length == 0 ||
 799                                                 ((readl(
 800                                                 &ep->dev->regs->udccs[0])
 801                                                 & UDCCS0_RNE) != 0
 802                                                 && read_ep0_fifo(ep, req))) {
 803                                         ep0_idle(dev);
 804                                         done(ep, req, 0);
 805                                         req = NULL;
 806                                 }
 807                                 break;
 808
 809                         default:
 810                                 printf("ep0 i/o, odd state %d\n",
 811                                         dev->ep0state);
 812                                 local_irq_restore(flags);
 813                                 return -EL2HLT;
 814                         }
 815                 /* can the FIFO can satisfy the request immediately? */
 816                 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
 817                         if ((readl(ep->reg_udccs) & UDCCS_BI_TFS) != 0
 818                                         && write_fifo(ep, req))
 819                                 req = NULL;
 820                 } else if ((readl(ep->reg_udccs) & UDCCS_BO_RFS) != 0
 821                                 && read_fifo(ep, req)) {
 822                         req = NULL;
 823                 }
 824
 825                 if (likely(req && ep->desc))
 826                         pio_irq_enable(ep->bEndpointAddress);
 827         }
 828
 829         /* pio or dma irq handler advances the queue. */
 830         if (likely(req != NULL))
 831                 list_add_tail(&req->queue, &ep->queue);
 832         local_irq_restore(flags);
 833
 834         return 0;
 835 }
 836
 837
 838 /*
 839  *      nuke - dequeue ALL requests
 840  */
 841 static void nuke(struct pxa25x_ep *ep, int status)
 842 {
 843         struct pxa25x_request *req;
 844
 845         /* called with irqs blocked */
 846         while (!list_empty(&ep->queue)) {
 847                 req = list_entry(ep->queue.next,
 848                                 struct pxa25x_request,
 849                                 queue);
 850                 done(ep, req, status);
 851         }
 852         if (ep->desc)
 853                 pio_irq_disable(ep->bEndpointAddress);
 854 }
 855
 856
 857 /* dequeue JUST ONE request */
 858 static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 859 {
 860         struct pxa25x_ep *ep;
 861         struct pxa25x_request *req;
 862         unsigned long flags;
 863
 864         ep = container_of(_ep, struct pxa25x_ep, ep);
 865         if (!_ep || ep->ep.name == ep0name)
 866                 return -EINVAL;
 867
 868         local_irq_save(flags);
 869
 870         /* make sure it's actually queued on this endpoint */
 871         list_for_each_entry(req, &ep->queue, queue) {
 872                 if (&req->req == _req)
 873                         break;
 874         }
 875         if (&req->req != _req) {
 876                 local_irq_restore(flags);
 877                 return -EINVAL;
 878         }
 879
 880         done(ep, req, -ECONNRESET);
 881
 882         local_irq_restore(flags);
 883         return 0;
 884 }
 885
 886 /*-------------------------------------------------------------------------*/
 887
 888 static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
 889 {
 890         struct pxa25x_ep *ep;
 891         unsigned long flags;
 892
 893         ep = container_of(_ep, struct pxa25x_ep, ep);
 894         if (unlikely(!_ep
 895                         || (!ep->desc && ep->ep.name != ep0name))
 896                         || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 897                 printf("%s, bad ep\n", __func__);
 898                 return -EINVAL;
 899         }
 900         if (value == 0) {
 901                 /*
 902                  * this path (reset toggle+halt) is needed to implement
 903                  * SET_INTERFACE on normal hardware.  but it can't be
 904                  * done from software on the PXA UDC, and the hardware
 905                  * forgets to do it as part of SET_INTERFACE automagic.
 906                  */
 907                 printf("only host can clear %s halt\n", _ep->name);
 908                 return -EROFS;
 909         }
 910
 911         local_irq_save(flags);
 912
 913         if ((ep->bEndpointAddress & USB_DIR_IN) != 0
 914                         && ((readl(ep->reg_udccs) & UDCCS_BI_TFS) == 0
 915                            || !list_empty(&ep->queue))) {
 916                 local_irq_restore(flags);
 917                 return -EAGAIN;
 918         }
 919
 920         /* FST bit is the same for control, bulk in, bulk out, interrupt in */
 921         writel(UDCCS_BI_FST|UDCCS_BI_FTF, ep->reg_udccs);
 922
 923         /* ep0 needs special care */
 924         if (!ep->desc) {
 925                 start_watchdog(ep->dev);
 926                 ep->dev->req_pending = 0;
 927                 ep->dev->ep0state = EP0_STALL;
 928
 929         /* and bulk/intr endpoints like dropping stalls too */
 930         } else {
 931                 unsigned i;
 932                 for (i = 0; i < 1000; i += 20) {
 933                         if (readl(ep->reg_udccs) & UDCCS_BI_SST)
 934                                 break;
 935                         udelay(20);
 936                 }
 937         }
 938         local_irq_restore(flags);
 939
 940         debug("%s halt\n", _ep->name);
 941         return 0;
 942 }
 943
 944 static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
 945 {
 946         struct pxa25x_ep        *ep;
 947
 948         ep = container_of(_ep, struct pxa25x_ep, ep);
 949         if (!_ep) {
 950                 printf("%s, bad ep\n", __func__);
 951                 return -ENODEV;
 952         }
 953         /* pxa can't report unclaimed bytes from IN fifos */
 954         if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
 955                 return -EOPNOTSUPP;
 956         if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
 957                         || (readl(ep->reg_udccs) & UDCCS_BO_RFS) == 0)
 958                 return 0;
 959         else
 960                 return (readl(ep->reg_ubcr) & 0xfff) + 1;
 961 }
 962
 963 static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
 964 {
 965         struct pxa25x_ep        *ep;
 966
 967         ep = container_of(_ep, struct pxa25x_ep, ep);
 968         if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
 969                 printf("%s, bad ep\n", __func__);
 970                 return;
 971         }
 972
 973         /* toggle and halt bits stay unchanged */
 974
 975         /* for OUT, just read and discard the FIFO contents. */
 976         if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
 977                 while (((readl(ep->reg_udccs)) & UDCCS_BO_RNE) != 0)
 978                         (void)readb(ep->reg_uddr);
 979                 return;
 980         }
 981
 982         /* most IN status is the same, but ISO can't stall */
 983         writel(UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
 984                 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
 985                         ? 0 : UDCCS_BI_SST), ep->reg_udccs);
 986 }
 987
 988
 989 static struct usb_ep_ops pxa25x_ep_ops = {
 990         .enable         = pxa25x_ep_enable,
 991         .disable        = pxa25x_ep_disable,
 992
 993         .alloc_request  = pxa25x_ep_alloc_request,
 994         .free_request   = pxa25x_ep_free_request,
 995
 996         .queue          = pxa25x_ep_queue,
 997         .dequeue        = pxa25x_ep_dequeue,
 998
 999         .set_halt       = pxa25x_ep_set_halt,
1000         .fifo_status    = pxa25x_ep_fifo_status,
1001         .fifo_flush     = pxa25x_ep_fifo_flush,
1002 };
1003
1004
1005 /* ---------------------------------------------------------------------------
1006  *      device-scoped parts of the api to the usb controller hardware
1007  * ---------------------------------------------------------------------------
1008  */
1009
1010 static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
1011 {
1012         return ((readl(&the_controller->regs->ufnrh) & 0x07) << 8) |
1013                 (readl(&the_controller->regs->ufnrl) & 0xff);
1014 }
1015
1016 static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
1017 {
1018         /* host may not have enabled remote wakeup */
1019         if ((readl(&the_controller->regs->udccs[0]) & UDCCS0_DRWF) == 0)
1020                 return -EHOSTUNREACH;
1021         udc_set_mask_UDCCR(UDCCR_RSM);
1022         return 0;
1023 }
1024
1025 static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
1026 static void udc_enable(struct pxa25x_udc *);
1027 static void udc_disable(struct pxa25x_udc *);
1028
1029 /*
1030  * We disable the UDC -- and its 48 MHz clock -- whenever it's not
1031  * in active use.
1032  */
1033 static int pullup(struct pxa25x_udc *udc)
1034 {
1035         if (udc->pullup)
1036                 pullup_on();
1037         else
1038                 pullup_off();
1039
1040
1041         int is_active = udc->pullup;
1042         if (is_active) {
1043                 if (!udc->active) {
1044                         udc->active = 1;
1045                         udc_enable(udc);
1046                 }
1047         } else {
1048                 if (udc->active) {
1049                         if (udc->gadget.speed != USB_SPEED_UNKNOWN)
1050                                 stop_activity(udc, udc->driver);
1051                         udc_disable(udc);
1052                         udc->active = 0;
1053                 }
1054
1055         }
1056         return 0;
1057 }
1058
1059 /* VBUS reporting logically comes from a transceiver */
1060 static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1061 {
1062         struct pxa25x_udc *udc;
1063
1064         udc = container_of(_gadget, struct pxa25x_udc, gadget);
1065         printf("vbus %s\n", is_active ? "supplied" : "inactive");
1066         pullup(udc);
1067         return 0;
1068 }
1069
1070 /* drivers may have software control over D+ pullup */
1071 static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
1072 {
1073         struct pxa25x_udc       *udc;
1074
1075         udc = container_of(_gadget, struct pxa25x_udc, gadget);
1076
1077         /* not all boards support pullup control */
1078         if (!udc->mach->udc_command)
1079                 return -EOPNOTSUPP;
1080
1081         udc->pullup = (is_active != 0);
1082         pullup(udc);
1083         return 0;
1084 }
1085
1086 /*
1087  * boards may consume current from VBUS, up to 100-500mA based on config.
1088  * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs
1089  * violate USB specs.
1090  */
1091 static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1092 {
1093         return -EOPNOTSUPP;
1094 }
1095
1096 static const struct usb_gadget_ops pxa25x_udc_ops = {
1097         .get_frame      = pxa25x_udc_get_frame,
1098         .wakeup         = pxa25x_udc_wakeup,
1099         .vbus_session   = pxa25x_udc_vbus_session,
1100         .pullup         = pxa25x_udc_pullup,
1101         .vbus_draw      = pxa25x_udc_vbus_draw,
1102 };
1103
1104 /*-------------------------------------------------------------------------*/
1105
1106 /*
1107  *      udc_disable - disable USB device controller
1108  */
1109 static void udc_disable(struct pxa25x_udc *dev)
1110 {
1111         /* block all irqs */
1112         udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1113         writel(0xff, &dev->regs->uicr0);
1114         writel(0xff, &dev->regs->uicr1);
1115         writel(UFNRH_SIM, &dev->regs->ufnrh);
1116
1117         /* if hardware supports it, disconnect from usb */
1118         pullup_off();
1119
1120         udc_clear_mask_UDCCR(UDCCR_UDE);
1121
1122         ep0_idle(dev);
1123         dev->gadget.speed = USB_SPEED_UNKNOWN;
1124 }
1125
1126 /*
1127  *      udc_reinit - initialize software state
1128  */
1129 static void udc_reinit(struct pxa25x_udc *dev)
1130 {
1131         u32 i;
1132
1133         /* device/ep0 records init */
1134         INIT_LIST_HEAD(&dev->gadget.ep_list);
1135         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1136         dev->ep0state = EP0_IDLE;
1137
1138         /* basic endpoint records init */
1139         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1140                 struct pxa25x_ep *ep = &dev->ep[i];
1141
1142                 if (i != 0)
1143                         list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
1144
1145                 ep->desc = NULL;
1146                 ep->stopped = 0;
1147                 INIT_LIST_HEAD(&ep->queue);
1148                 ep->pio_irqs = 0;
1149         }
1150
1151         /* the rest was statically initialized, and is read-only */
1152 }
1153
1154 /*
1155  * until it's enabled, this UDC should be completely invisible
1156  * to any USB host.
1157  */
1158 static void udc_enable(struct pxa25x_udc *dev)
1159 {
1160         debug("udc: enabling udc\n");
1161
1162         udc_clear_mask_UDCCR(UDCCR_UDE);
1163
1164         /*
1165          * Try to clear these bits before we enable the udc.
1166          * Do not touch reset ack bit, we would take care of it in
1167          * interrupt handle routine
1168          */
1169         udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RESIR);
1170
1171         ep0_idle(dev);
1172         dev->gadget.speed = USB_SPEED_UNKNOWN;
1173         dev->stats.irqs = 0;
1174
1175         /*
1176          * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1177          * - enable UDC
1178          * - if RESET is already in progress, ack interrupt
1179          * - unmask reset interrupt
1180          */
1181         udc_set_mask_UDCCR(UDCCR_UDE);
1182         if (!(readl(&dev->regs->udccr) & UDCCR_UDA))
1183                 udc_ack_int_UDCCR(UDCCR_RSTIR);
1184
1185         if (dev->has_cfr /* UDC_RES2 is defined */) {
1186                 /*
1187                  * pxa255 (a0+) can avoid a set_config race that could
1188                  * prevent gadget drivers from configuring correctly
1189                  */
1190                 writel(UDCCFR_ACM | UDCCFR_MB1, &dev->regs->udccfr);
1191         }
1192
1193         /* enable suspend/resume and reset irqs */
1194         udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1195
1196         /* enable ep0 irqs */
1197         clrbits_le32(&dev->regs->uicr0, UICR0_IM0);
1198
1199         /* if hardware supports it, pullup D+ and wait for reset */
1200         pullup_on();
1201 }
1202
1203 static inline void clear_ep_state(struct pxa25x_udc *dev)
1204 {
1205         unsigned i;
1206
1207         /*
1208          * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1209          * fifos, and pending transactions mustn't be continued in any case.
1210          */
1211         for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1212                 nuke(&dev->ep[i], -ECONNABORTED);
1213 }
1214
1215 static void handle_ep0(struct pxa25x_udc *dev)
1216 {
1217         u32 udccs0 = readl(&dev->regs->udccs[0]);
1218         struct pxa25x_ep *ep = &dev->ep[0];
1219         struct pxa25x_request *req;
1220         union {
1221                 struct usb_ctrlrequest  r;
1222                 u8                      raw[8];
1223                 u32                     word[2];
1224         } u;
1225
1226         if (list_empty(&ep->queue))
1227                 req = NULL;
1228         else
1229                 req = list_entry(ep->queue.next, struct pxa25x_request, queue);
1230
1231         /* clear stall status */
1232         if (udccs0 & UDCCS0_SST) {
1233                 nuke(ep, -EPIPE);
1234                 writel(UDCCS0_SST, &dev->regs->udccs[0]);
1235                 stop_watchdog(dev);
1236                 ep0_idle(dev);
1237         }
1238
1239         /* previous request unfinished?  non-error iff back-to-back ... */
1240         if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1241                 nuke(ep, 0);
1242                 stop_watchdog(dev);
1243                 ep0_idle(dev);
1244         }
1245
1246         switch (dev->ep0state) {
1247         case EP0_IDLE:
1248                 /* late-breaking status? */
1249                 udccs0 = readl(&dev->regs->udccs[0]);
1250
1251                 /* start control request? */
1252                 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1253                                 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1254                         int i;
1255
1256                         nuke(ep, -EPROTO);
1257
1258                         /* read SETUP packet */
1259                         for (i = 0; i < 8; i++) {
1260                                 if (unlikely(!(readl(&dev->regs->udccs[0]) &
1261                                                 UDCCS0_RNE))) {
1262 bad_setup:
1263                                         debug("SETUP %d!\n", i);
1264                                         goto stall;
1265                                 }
1266                                 u.raw[i] = (u8)readb(&dev->regs->uddr0);
1267                         }
1268                         if (unlikely((readl(&dev->regs->udccs[0]) &
1269                                         UDCCS0_RNE) != 0))
1270                                 goto bad_setup;
1271
1272 got_setup:
1273                         debug("SETUP %02x.%02x v%04x i%04x l%04x\n",
1274                                 u.r.bRequestType, u.r.bRequest,
1275                                 le16_to_cpu(u.r.wValue),
1276                                 le16_to_cpu(u.r.wIndex),
1277                                 le16_to_cpu(u.r.wLength));
1278
1279                         /* cope with automagic for some standard requests. */
1280                         dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1281                                                 == USB_TYPE_STANDARD;
1282                         dev->req_config = 0;
1283                         dev->req_pending = 1;
1284                         switch (u.r.bRequest) {
1285                         /* hardware restricts gadget drivers here! */
1286                         case USB_REQ_SET_CONFIGURATION:
1287                                 debug("GOT SET_CONFIGURATION\n");
1288                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1289                                         /*
1290                                          * reflect hardware's automagic
1291                                          * up to the gadget driver.
1292                                          */
1293 config_change:
1294                                         dev->req_config = 1;
1295                                         clear_ep_state(dev);
1296                                         /*
1297                                          * if !has_cfr, there's no synch
1298                                          * else use AREN (later) not SA|OPR
1299                                          * USIR0_IR0 acts edge sensitive
1300                                          */
1301                                 }
1302                                 break;
1303                         /* ... and here, even more ... */
1304                         case USB_REQ_SET_INTERFACE:
1305                                 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1306                                         /*
1307                                          * udc hardware is broken by design:
1308                                          *  - altsetting may only be zero;
1309                                          *  - hw resets all interfaces' eps;
1310                                          *  - ep reset doesn't include halt(?).
1311                                          */
1312                                         printf("broken set_interface (%d/%d)\n",
1313                                                 le16_to_cpu(u.r.wIndex),
1314                                                 le16_to_cpu(u.r.wValue));
1315                                         goto config_change;
1316                                 }
1317                                 break;
1318                         /* hardware was supposed to hide this */
1319                         case USB_REQ_SET_ADDRESS:
1320                                 debug("GOT SET ADDRESS\n");
1321                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1322                                         ep0start(dev, 0, "address");
1323                                         return;
1324                                 }
1325                                 break;
1326                         }
1327
1328                         if (u.r.bRequestType & USB_DIR_IN)
1329                                 dev->ep0state = EP0_IN_DATA_PHASE;
1330                         else
1331                                 dev->ep0state = EP0_OUT_DATA_PHASE;
1332
1333                         i = dev->driver->setup(&dev->gadget, &u.r);
1334                         if (i < 0) {
1335                                 /* hardware automagic preventing STALL... */
1336                                 if (dev->req_config) {
1337                                         /*
1338                                          * hardware sometimes neglects to tell
1339                                          * tell us about config change events,
1340                                          * so later ones may fail...
1341                                          */
1342                                         printf("config change %02x fail %d?\n",
1343                                                 u.r.bRequest, i);
1344                                         return;
1345                                         /*
1346                                          * TODO experiment:  if has_cfr,
1347                                          * hardware didn't ACK; maybe we
1348                                          * could actually STALL!
1349                                          */
1350                                 }
1351                                 if (0) {
1352 stall:
1353                                         /* uninitialized when goto stall */
1354                                         i = 0;
1355                                 }
1356                                 debug("protocol STALL, "
1357                                         "%02x err %d\n",
1358                                         readl(&dev->regs->udccs[0]), i);
1359
1360                                 /*
1361                                  * the watchdog timer helps deal with cases
1362                                  * where udc seems to clear FST wrongly, and
1363                                  * then NAKs instead of STALLing.
1364                                  */
1365                                 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1366                                 start_watchdog(dev);
1367                                 dev->ep0state = EP0_STALL;
1368
1369                         /* deferred i/o == no response yet */
1370                         } else if (dev->req_pending) {
1371                                 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1372                                                 || dev->req_std || u.r.wLength))
1373                                         ep0start(dev, 0, "defer");
1374                                 else
1375                                         ep0start(dev, UDCCS0_IPR, "defer/IPR");
1376                         }
1377
1378                         /* expect at least one data or status stage irq */
1379                         return;
1380
1381                 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1382                                 == (UDCCS0_OPR|UDCCS0_SA))) {
1383                         unsigned i;
1384
1385                         /*
1386                          * pxa210/250 erratum 131 for B0/B1 says RNE lies.
1387                          * still observed on a pxa255 a0.
1388                          */
1389                         debug("e131\n");
1390                         nuke(ep, -EPROTO);
1391
1392                         /* read SETUP data, but don't trust it too much */
1393                         for (i = 0; i < 8; i++)
1394                                 u.raw[i] = (u8)readb(&dev->regs->uddr0);
1395                         if ((u.r.bRequestType & USB_RECIP_MASK)
1396                                         > USB_RECIP_OTHER)
1397                                 goto stall;
1398                         if (u.word[0] == 0 && u.word[1] == 0)
1399                                 goto stall;
1400                         goto got_setup;
1401                 } else {
1402                         /*
1403                          * some random early IRQ:
1404                          * - we acked FST
1405                          * - IPR cleared
1406                          * - OPR got set, without SA (likely status stage)
1407                          */
1408                         debug("random IRQ %X %X\n", udccs0,
1409                                 readl(&dev->regs->udccs[0]));
1410                         writel(udccs0 & (UDCCS0_SA|UDCCS0_OPR),
1411                                 &dev->regs->udccs[0]);
1412                 }
1413                 break;
1414         case EP0_IN_DATA_PHASE:                 /* GET_DESCRIPTOR etc */
1415                 if (udccs0 & UDCCS0_OPR) {
1416                         debug("ep0in premature status\n");
1417                         if (req)
1418                                 done(ep, req, 0);
1419                         ep0_idle(dev);
1420                 } else /* irq was IPR clearing */ {
1421                         if (req) {
1422                                 debug("next ep0 in packet\n");
1423                                 /* this IN packet might finish the request */
1424                                 (void) write_ep0_fifo(ep, req);
1425                         } /* else IN token before response was written */
1426                 }
1427                 break;
1428         case EP0_OUT_DATA_PHASE:                /* SET_DESCRIPTOR etc */
1429                 if (udccs0 & UDCCS0_OPR) {
1430                         if (req) {
1431                                 /* this OUT packet might finish the request */
1432                                 if (read_ep0_fifo(ep, req))
1433                                         done(ep, req, 0);
1434                                 /* else more OUT packets expected */
1435                         } /* else OUT token before read was issued */
1436                 } else /* irq was IPR clearing */ {
1437                         debug("ep0out premature status\n");
1438                         if (req)
1439                                 done(ep, req, 0);
1440                         ep0_idle(dev);
1441                 }
1442                 break;
1443         case EP0_END_XFER:
1444                 if (req)
1445                         done(ep, req, 0);
1446                 /*
1447                  * ack control-IN status (maybe in-zlp was skipped)
1448                  * also appears after some config change events.
1449                  */
1450                 if (udccs0 & UDCCS0_OPR)
1451                         writel(UDCCS0_OPR, &dev->regs->udccs[0]);
1452                 ep0_idle(dev);
1453                 break;
1454         case EP0_STALL:
1455                 writel(UDCCS0_FST, &dev->regs->udccs[0]);
1456                 break;
1457         }
1458
1459         writel(USIR0_IR0, &dev->regs->usir0);
1460 }
1461
1462 static void handle_ep(struct pxa25x_ep *ep)
1463 {
1464         struct pxa25x_request   *req;
1465         int                     is_in = ep->bEndpointAddress & USB_DIR_IN;
1466         int                     completed;
1467         u32                     udccs, tmp;
1468
1469         do {
1470                 completed = 0;
1471                 if (likely(!list_empty(&ep->queue)))
1472                         req = list_entry(ep->queue.next,
1473                                         struct pxa25x_request, queue);
1474                 else
1475                         req = NULL;
1476
1477                 /* TODO check FST handling */
1478
1479                 udccs = readl(ep->reg_udccs);
1480                 if (unlikely(is_in)) {  /* irq from TPC, SST, or (ISO) TUR */
1481                         tmp = UDCCS_BI_TUR;
1482                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1483                                 tmp |= UDCCS_BI_SST;
1484                         tmp &= udccs;
1485                         if (likely(tmp))
1486                                 writel(tmp, ep->reg_udccs);
1487                         if (req && likely((udccs & UDCCS_BI_TFS) != 0))
1488                                 completed = write_fifo(ep, req);
1489
1490                 } else {        /* irq from RPC (or for ISO, ROF) */
1491                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1492                                 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1493                         else
1494                                 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1495                         tmp &= udccs;
1496                         if (likely(tmp))
1497                                 writel(tmp, ep->reg_udccs);
1498
1499                         /* fifos can hold packets, ready for reading... */
1500                         if (likely(req))
1501                                 completed = read_fifo(ep, req);
1502                         else
1503                                 pio_irq_disable(ep->bEndpointAddress);
1504                 }
1505                 ep->pio_irqs++;
1506         } while (completed);
1507 }
1508
1509 /*
1510  *      pxa25x_udc_irq - interrupt handler
1511  *
1512  * avoid delays in ep0 processing. the control handshaking isn't always
1513  * under software control (pxa250c0 and the pxa255 are better), and delays
1514  * could cause usb protocol errors.
1515  */
1516 static struct pxa25x_udc memory;
1517 static int
1518 pxa25x_udc_irq(void)
1519 {
1520         struct pxa25x_udc *dev = &memory;
1521         int handled;
1522
1523         test_watchdog(dev);
1524
1525         dev->stats.irqs++;
1526         do {
1527                 u32 udccr = readl(&dev->regs->udccr);
1528
1529                 handled = 0;
1530
1531                 /* SUSpend Interrupt Request */
1532                 if (unlikely(udccr & UDCCR_SUSIR)) {
1533                         udc_ack_int_UDCCR(UDCCR_SUSIR);
1534                         handled = 1;
1535                         debug("USB suspend\n");
1536
1537                         if (dev->gadget.speed != USB_SPEED_UNKNOWN
1538                                         && dev->driver
1539                                         && dev->driver->suspend)
1540                                 dev->driver->suspend(&dev->gadget);
1541                         ep0_idle(dev);
1542                 }
1543
1544                 /* RESume Interrupt Request */
1545                 if (unlikely(udccr & UDCCR_RESIR)) {
1546                         udc_ack_int_UDCCR(UDCCR_RESIR);
1547                         handled = 1;
1548                         debug("USB resume\n");
1549
1550                         if (dev->gadget.speed != USB_SPEED_UNKNOWN
1551                                         && dev->driver
1552                                         && dev->driver->resume)
1553                                 dev->driver->resume(&dev->gadget);
1554                 }
1555
1556                 /* ReSeT Interrupt Request - USB reset */
1557                 if (unlikely(udccr & UDCCR_RSTIR)) {
1558                         udc_ack_int_UDCCR(UDCCR_RSTIR);
1559                         handled = 1;
1560
1561                         if ((readl(&dev->regs->udccr) & UDCCR_UDA) == 0) {
1562                                 debug("USB reset start\n");
1563
1564                                 /*
1565                                  * reset driver and endpoints,
1566                                  * in case that's not yet done
1567                                  */
1568                                 stop_activity(dev, dev->driver);
1569
1570                         } else {
1571                                 debug("USB reset end\n");
1572                                 dev->gadget.speed = USB_SPEED_FULL;
1573                                 memset(&dev->stats, 0, sizeof dev->stats);
1574                                 /* driver and endpoints are still reset */
1575                         }
1576
1577                 } else {
1578                         u32 uicr0 = readl(&dev->regs->uicr0);
1579                         u32 uicr1 = readl(&dev->regs->uicr1);
1580                         u32 usir0 = readl(&dev->regs->usir0);
1581                         u32 usir1 = readl(&dev->regs->usir1);
1582
1583                         usir0 = usir0 & ~uicr0;
1584                         usir1 = usir1 & ~uicr1;
1585                         int i;
1586
1587                         if (unlikely(!usir0 && !usir1))
1588                                 continue;
1589
1590                         debug_cond(NOISY, "irq %02x.%02x\n", usir1, usir0);
1591
1592                         /* control traffic */
1593                         if (usir0 & USIR0_IR0) {
1594                                 dev->ep[0].pio_irqs++;
1595                                 handle_ep0(dev);
1596                                 handled = 1;
1597                         }
1598
1599                         /* endpoint data transfers */
1600                         for (i = 0; i < 8; i++) {
1601                                 u32     tmp = 1 << i;
1602
1603                                 if (i && (usir0 & tmp)) {
1604                                         handle_ep(&dev->ep[i]);
1605                                         setbits_le32(&dev->regs->usir0, tmp);
1606                                         handled = 1;
1607                                 }
1608 #ifndef CONFIG_USB_PXA25X_SMALL
1609                                 if (usir1 & tmp) {
1610                                         handle_ep(&dev->ep[i+8]);
1611                                         setbits_le32(&dev->regs->usir1, tmp);
1612                                         handled = 1;
1613                                 }
1614 #endif
1615                         }
1616                 }
1617
1618                 /* we could also ask for 1 msec SOF (SIR) interrupts */
1619
1620         } while (handled);
1621         return IRQ_HANDLED;
1622 }
1623
1624 /*-------------------------------------------------------------------------*/
1625
1626 /*
1627  * this uses load-time allocation and initialization (instead of
1628  * doing it at run-time) to save code, eliminate fault paths, and
1629  * be more obviously correct.
1630  */
1631 static struct pxa25x_udc memory = {
1632         .regs = UDC_REGS,
1633
1634         .gadget = {
1635                 .ops            = &pxa25x_udc_ops,
1636                 .ep0            = &memory.ep[0].ep,
1637                 .name           = driver_name,
1638         },
1639
1640         /* control endpoint */
1641         .ep[0] = {
1642                 .ep = {
1643                         .name           = ep0name,
1644                         .ops            = &pxa25x_ep_ops,
1645                         .maxpacket      = EP0_FIFO_SIZE,
1646                 },
1647                 .dev            = &memory,
1648                 .reg_udccs      = &UDC_REGS->udccs[0],
1649                 .reg_uddr       = &UDC_REGS->uddr0,
1650         },
1651
1652         /* first group of endpoints */
1653         .ep[1] = {
1654                 .ep = {
1655                         .name           = "ep1in-bulk",
1656                         .ops            = &pxa25x_ep_ops,
1657                         .maxpacket      = BULK_FIFO_SIZE,
1658                 },
1659                 .dev            = &memory,
1660                 .fifo_size      = BULK_FIFO_SIZE,
1661                 .bEndpointAddress = USB_DIR_IN | 1,
1662                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1663                 .reg_udccs      = &UDC_REGS->udccs[1],
1664                 .reg_uddr       = &UDC_REGS->uddr1,
1665         },
1666         .ep[2] = {
1667                 .ep = {
1668                         .name           = "ep2out-bulk",
1669                         .ops            = &pxa25x_ep_ops,
1670                         .maxpacket      = BULK_FIFO_SIZE,
1671                 },
1672                 .dev            = &memory,
1673                 .fifo_size      = BULK_FIFO_SIZE,
1674                 .bEndpointAddress = 2,
1675                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1676                 .reg_udccs      = &UDC_REGS->udccs[2],
1677                 .reg_ubcr       = &UDC_REGS->ubcr2,
1678                 .reg_uddr       = &UDC_REGS->uddr2,
1679         },
1680 #ifndef CONFIG_USB_PXA25X_SMALL
1681         .ep[3] = {
1682                 .ep = {
1683                         .name           = "ep3in-iso",
1684                         .ops            = &pxa25x_ep_ops,
1685                         .maxpacket      = ISO_FIFO_SIZE,
1686                 },
1687                 .dev            = &memory,
1688                 .fifo_size      = ISO_FIFO_SIZE,
1689                 .bEndpointAddress = USB_DIR_IN | 3,
1690                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1691                 .reg_udccs      = &UDC_REGS->udccs[3],
1692                 .reg_uddr       = &UDC_REGS->uddr3,
1693         },
1694         .ep[4] = {
1695                 .ep = {
1696                         .name           = "ep4out-iso",
1697                         .ops            = &pxa25x_ep_ops,
1698                         .maxpacket      = ISO_FIFO_SIZE,
1699                 },
1700                 .dev            = &memory,
1701                 .fifo_size      = ISO_FIFO_SIZE,
1702                 .bEndpointAddress = 4,
1703                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1704                 .reg_udccs      = &UDC_REGS->udccs[4],
1705                 .reg_ubcr       = &UDC_REGS->ubcr4,
1706                 .reg_uddr       = &UDC_REGS->uddr4,
1707         },
1708         .ep[5] = {
1709                 .ep = {
1710                         .name           = "ep5in-int",
1711                         .ops            = &pxa25x_ep_ops,
1712                         .maxpacket      = INT_FIFO_SIZE,
1713                 },
1714                 .dev            = &memory,
1715                 .fifo_size      = INT_FIFO_SIZE,
1716                 .bEndpointAddress = USB_DIR_IN | 5,
1717                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
1718                 .reg_udccs      = &UDC_REGS->udccs[5],
1719                 .reg_uddr       = &UDC_REGS->uddr5,
1720         },
1721
1722         /* second group of endpoints */
1723         .ep[6] = {
1724                 .ep = {
1725                         .name           = "ep6in-bulk",
1726                         .ops            = &pxa25x_ep_ops,
1727                         .maxpacket      = BULK_FIFO_SIZE,
1728                 },
1729                 .dev            = &memory,
1730                 .fifo_size      = BULK_FIFO_SIZE,
1731                 .bEndpointAddress = USB_DIR_IN | 6,
1732                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1733                 .reg_udccs      = &UDC_REGS->udccs[6],
1734                 .reg_uddr       = &UDC_REGS->uddr6,
1735         },
1736         .ep[7] = {
1737                 .ep = {
1738                         .name           = "ep7out-bulk",
1739                         .ops            = &pxa25x_ep_ops,
1740                         .maxpacket      = BULK_FIFO_SIZE,
1741                 },
1742                 .dev            = &memory,
1743                 .fifo_size      = BULK_FIFO_SIZE,
1744                 .bEndpointAddress = 7,
1745                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1746                 .reg_udccs      = &UDC_REGS->udccs[7],
1747                 .reg_ubcr       = &UDC_REGS->ubcr7,
1748                 .reg_uddr       = &UDC_REGS->uddr7,
1749         },
1750         .ep[8] = {
1751                 .ep = {
1752                         .name           = "ep8in-iso",
1753                         .ops            = &pxa25x_ep_ops,
1754                         .maxpacket      = ISO_FIFO_SIZE,
1755                 },
1756                 .dev            = &memory,
1757                 .fifo_size      = ISO_FIFO_SIZE,
1758                 .bEndpointAddress = USB_DIR_IN | 8,
1759                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1760                 .reg_udccs      = &UDC_REGS->udccs[8],
1761                 .reg_uddr       = &UDC_REGS->uddr8,
1762         },
1763         .ep[9] = {
1764                 .ep = {
1765                         .name           = "ep9out-iso",
1766                         .ops            = &pxa25x_ep_ops,
1767                         .maxpacket      = ISO_FIFO_SIZE,
1768                 },
1769                 .dev            = &memory,
1770                 .fifo_size      = ISO_FIFO_SIZE,
1771                 .bEndpointAddress = 9,
1772                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1773                 .reg_udccs      = &UDC_REGS->udccs[9],
1774                 .reg_ubcr       = &UDC_REGS->ubcr9,
1775                 .reg_uddr       = &UDC_REGS->uddr9,
1776         },
1777         .ep[10] = {
1778                 .ep = {
1779                         .name           = "ep10in-int",
1780                         .ops            = &pxa25x_ep_ops,
1781                         .maxpacket      = INT_FIFO_SIZE,
1782                 },
1783                 .dev            = &memory,
1784                 .fifo_size      = INT_FIFO_SIZE,
1785                 .bEndpointAddress = USB_DIR_IN | 10,
1786                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
1787                 .reg_udccs      = &UDC_REGS->udccs[10],
1788                 .reg_uddr       = &UDC_REGS->uddr10,
1789         },
1790
1791         /* third group of endpoints */
1792         .ep[11] = {
1793                 .ep = {
1794                         .name           = "ep11in-bulk",
1795                         .ops            = &pxa25x_ep_ops,
1796                         .maxpacket      = BULK_FIFO_SIZE,
1797                 },
1798                 .dev            = &memory,
1799                 .fifo_size      = BULK_FIFO_SIZE,
1800                 .bEndpointAddress = USB_DIR_IN | 11,
1801                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1802                 .reg_udccs      = &UDC_REGS->udccs[11],
1803                 .reg_uddr       = &UDC_REGS->uddr11,
1804         },
1805         .ep[12] = {
1806                 .ep = {
1807                         .name           = "ep12out-bulk",
1808                         .ops            = &pxa25x_ep_ops,
1809                         .maxpacket      = BULK_FIFO_SIZE,
1810                 },
1811                 .dev            = &memory,
1812                 .fifo_size      = BULK_FIFO_SIZE,
1813                 .bEndpointAddress = 12,
1814                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1815                 .reg_udccs      = &UDC_REGS->udccs[12],
1816                 .reg_ubcr       = &UDC_REGS->ubcr12,
1817                 .reg_uddr       = &UDC_REGS->uddr12,
1818         },
1819         .ep[13] = {
1820                 .ep = {
1821                         .name           = "ep13in-iso",
1822                         .ops            = &pxa25x_ep_ops,
1823                         .maxpacket      = ISO_FIFO_SIZE,
1824                 },
1825                 .dev            = &memory,
1826                 .fifo_size      = ISO_FIFO_SIZE,
1827                 .bEndpointAddress = USB_DIR_IN | 13,
1828                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1829                 .reg_udccs      = &UDC_REGS->udccs[13],
1830                 .reg_uddr       = &UDC_REGS->uddr13,
1831         },
1832         .ep[14] = {
1833                 .ep = {
1834                         .name           = "ep14out-iso",
1835                         .ops            = &pxa25x_ep_ops,
1836                         .maxpacket      = ISO_FIFO_SIZE,
1837                 },
1838                 .dev            = &memory,
1839                 .fifo_size      = ISO_FIFO_SIZE,
1840                 .bEndpointAddress = 14,
1841                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1842                 .reg_udccs      = &UDC_REGS->udccs[14],
1843                 .reg_ubcr       = &UDC_REGS->ubcr14,
1844                 .reg_uddr       = &UDC_REGS->uddr14,
1845         },
1846         .ep[15] = {
1847                 .ep = {
1848                         .name           = "ep15in-int",
1849                         .ops            = &pxa25x_ep_ops,
1850                         .maxpacket      = INT_FIFO_SIZE,
1851                 },
1852                 .dev            = &memory,
1853                 .fifo_size      = INT_FIFO_SIZE,
1854                 .bEndpointAddress = USB_DIR_IN | 15,
1855                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
1856                 .reg_udccs      = &UDC_REGS->udccs[15],
1857                 .reg_uddr       = &UDC_REGS->uddr15,
1858         },
1859 #endif /* !CONFIG_USB_PXA25X_SMALL */
1860 };
1861
1862 static void udc_command(int cmd)
1863 {
1864         switch (cmd) {
1865         case PXA2XX_UDC_CMD_CONNECT:
1866                 setbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
1867                         GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
1868
1869                 /* enable pullup */
1870                 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
1871                         GPCR(CONFIG_USB_DEV_PULLUP_GPIO));
1872
1873                 debug("Connected to USB\n");
1874                 break;
1875
1876         case PXA2XX_UDC_CMD_DISCONNECT:
1877                 /* disable pullup resistor */
1878                 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
1879                         GPSR(CONFIG_USB_DEV_PULLUP_GPIO));
1880
1881                 /* setup pin as input, line will float */
1882                 clrbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
1883                         GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
1884
1885                 debug("Disconnected from USB\n");
1886                 break;
1887         }
1888 }
1889
1890 static struct pxa2xx_udc_mach_info mach_info = {
1891         .udc_command = udc_command,
1892 };
1893
1894 /*
1895  * when a driver is successfully registered, it will receive
1896  * control requests including set_configuration(), which enables
1897  * non-control requests.  then usb traffic follows until a
1898  * disconnect is reported.  then a host may connect again, or
1899  * the driver might get unbound.
1900  */
1901 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1902 {
1903         struct pxa25x_udc *dev = &memory;
1904         int retval;
1905         uint32_t chiprev;
1906
1907         if (!driver
1908                         || driver->speed < USB_SPEED_FULL
1909                         || !driver->disconnect
1910                         || !driver->setup)
1911                 return -EINVAL;
1912         if (!dev)
1913                 return -ENODEV;
1914         if (dev->driver)
1915                 return -EBUSY;
1916
1917         /* Enable clock for usb controller */
1918         setbits_le32(CKEN, CKEN11_USB);
1919
1920         /* first hook up the driver ... */
1921         dev->driver = driver;
1922         dev->pullup = 1;
1923
1924         /* trigger chiprev-specific logic */
1925         switch ((chiprev = pxa_get_cpu_revision())) {
1926         case PXA255_A0:
1927                 dev->has_cfr = 1;
1928                 break;
1929         case PXA250_A0:
1930         case PXA250_A1:
1931                 /* A0/A1 "not released"; ep 13, 15 unusable */
1932                 /* fall through */
1933         case PXA250_B2: case PXA210_B2:
1934         case PXA250_B1: case PXA210_B1:
1935         case PXA250_B0: case PXA210_B0:
1936                 /* OUT-DMA is broken ... */
1937                 /* fall through */
1938         case PXA250_C0: case PXA210_C0:
1939                 break;
1940         default:
1941                 printf("%s: unrecognized processor: %08x\n",
1942                         DRIVER_NAME, chiprev);
1943                 return -ENODEV;
1944         }
1945
1946         the_controller = dev;
1947
1948         /* prepare watchdog timer */
1949         dev->watchdog.running = 0;
1950         dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */
1951         dev->watchdog.function = udc_watchdog;
1952
1953         udc_disable(dev);
1954         udc_reinit(dev);
1955
1956         dev->mach = &mach_info;
1957
1958         dev->gadget.name = "pxa2xx_udc";
1959         retval = driver->bind(&dev->gadget);
1960         if (retval) {
1961                 printf("bind to driver %s --> error %d\n",
1962                                 DRIVER_NAME, retval);
1963                 dev->driver = NULL;
1964                 return retval;
1965         }
1966
1967         /*
1968          * ... then enable host detection and ep0; and we're ready
1969          * for set_configuration as well as eventual disconnect.
1970          */
1971         printf("registered gadget driver '%s'\n", DRIVER_NAME);
1972
1973         pullup(dev);
1974         dump_state(dev);
1975         return 0;
1976 }
1977
1978 static void
1979 stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
1980 {
1981         int i;
1982
1983         /* don't disconnect drivers more than once */
1984         if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1985                 driver = NULL;
1986         dev->gadget.speed = USB_SPEED_UNKNOWN;
1987
1988         /* prevent new request submissions, kill any outstanding requests  */
1989         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1990                 struct pxa25x_ep *ep = &dev->ep[i];
1991
1992                 ep->stopped = 1;
1993                 nuke(ep, -ESHUTDOWN);
1994         }
1995         stop_watchdog(dev);
1996
1997         /* report disconnect; the driver is already quiesced */
1998         if (driver)
1999                 driver->disconnect(&dev->gadget);
2000
2001         /* re-init driver-visible data structures */
2002         udc_reinit(dev);
2003 }
2004
2005 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2006 {
2007         struct pxa25x_udc       *dev = the_controller;
2008
2009         if (!dev)
2010                 return -ENODEV;
2011         if (!driver || driver != dev->driver || !driver->unbind)
2012                 return -EINVAL;
2013
2014         local_irq_disable();
2015         dev->pullup = 0;
2016         pullup(dev);
2017         stop_activity(dev, driver);
2018         local_irq_enable();
2019
2020         driver->unbind(&dev->gadget);
2021         dev->driver = NULL;
2022
2023         printf("unregistered gadget driver '%s'\n", DRIVER_NAME);
2024         dump_state(dev);
2025
2026         the_controller = NULL;
2027
2028         clrbits_le32(CKEN, CKEN11_USB);
2029
2030         return 0;
2031 }
2032
2033 extern void udc_disconnect(void)
2034 {
2035         setbits_le32(CKEN, CKEN11_USB);
2036         udc_clear_mask_UDCCR(UDCCR_UDE);
2037         udc_command(PXA2XX_UDC_CMD_DISCONNECT);
2038         clrbits_le32(CKEN, CKEN11_USB);
2039 }
2040
2041 /*-------------------------------------------------------------------------*/
2042
2043 extern int
2044 usb_gadget_handle_interrupts(void)
2045 {
2046         return pxa25x_udc_irq();
2047 }